INTEGRATED FAN-OUT PACKAGE AND PROCEDURE

Abstract

Device (300) comprising: a first redistribution structure (100, 200) coupled to a conductive element (101, 201) of a substrate (102, 202), the first redistribution structure comprising: a first conductive layer (106, 108, 206, 208), a first insulating layer (112, 212) over the first conductive layer (106, 108, 206, 208), the first insulating layer comprising a first filler-free insulating material, a second conductive layer (116, 118, 216, 218) over the first insulating layer (112, 212), the second conductive layer being coupled to the first conductive layer (106, 108, 206, 208), and a second insulating layer (122, 222) above the second conductive layer (116, 118, 216, 218), wherein the second insulating layer comprises a second filler-free insulating material;and wherein the device (300) further comprises: a conductive connector (160, 260, 396) electrically coupled to the first redistribution structure (100, 200); an encapsulated die (350), wherein the substrate (102, 202) is a support (302, 402), and the substrate (102, 202) is arranged between the first redistribution structure (100, 200) and the encapsulated die; and a second redistribution structure (322), wherein the second redistribution structure and the support (302, 402) are arranged on opposite sides of the encapsulated die (350), and the encapsulated die is electrically connected to the first redistribution structure (100, 200) via the second redistribution structure; and wherein an active side of the encapsulated die (350) faces the second redistribution structure (322).

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 091,966, filed on October 15, 2020, which is incorporated by reference into the present application. BACKGROUND

[0002] The semiconductor industry has grown rapidly due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have resulted from iteratively reducing the minimum feature size, allowing more components to be integrated into a given area. As the need for miniaturized electronic components has increased, so too has the demand for smaller and more innovative packaging techniques for semiconductor dies. One example of such a packaging system is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and component density.PoP technology generally enables the production of semiconductor devices with improved functionalities and a small footprint on a printed circuit board (PCB). List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1 to Fig. Figure 19 illustrates intermediate processes in the formation of a redistribution structure in accordance with some embodiments. Fig. 20 to Fig. Figure 30 illustrates intermediate processes in the formation of a redistribution structure in accordance with some embodiments. Fig. 31 to Fig. Figure 37 illustrates intermediate processes in the formation of a component stack in accordance with some embodiments. Fig. Figure 38 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments. Fig. 39 to Fig. 53 illustrate intermediate processes in the formation of a component stack in accordance with some embodiments. Fig. 54 to Fig. 59 illustrate intermediate processes in the formation of a component stack in accordance with some embodiments. Fig. 60 and Fig. Figure 61 illustrates component packages in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various discussed embodiments and / or configurations.

[0005] Furthermore, spatially relating terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein to facilitate description of the relationship of one element or feature to another, as illustrated in the figures. These spatially relating terms are intended to encompass different orientations of the component in use or operation, in addition to the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relating descriptors used herein may be interpreted accordingly.

[0006] In accordance with some embodiments, redistribution structures are disclosed which are fabricated from filler-free insulating layers with shrinkage rates to achieve a top profile that is wavy, but within tolerances to avoid the need for a flattening process, such as planarization, of the insulating layers between each successive deposition of the redistribution structure layers. As a result, the redistribution structures are easier to fabricate, and the insulating layers can advantageously be made thin. Furthermore, the first metallization structure of the redistribution structure can be fabricated with a relatively thicker metal to provide increased signal output and less attenuation. Some embodiments may incorporate a ceramic support, such as…An aluminum oxide support is used for good heat dissipation and electrical insulation properties. An embedded die can be used for additional functionality in the redistribution structure.

[0007] In Fig. 1 to Fig. 19 is a redistribution structure 100 (see Fig. 19) formed over a substrate 102. Briefly on Fig. 19 Referring to this, the redistribution structure 100 serves to electrically couple conductive elements 101 in the substrate 102 to other conductive elements 101 in the substrate 102 and to conductive connectors 160. The redistribution structure 100 comprises insulating layers 112, 122, 132, 142, and 152 and metallization structures containing conductive layers 108, 118, 128, 138, and 148. The metallization structures can also be referred to as redistribution layers or redistribution lines. The redistribution structure 100 is shown as an example with five layers of metallization structures. A greater or lesser number of dielectric layers and metallization structures can be formed in the redistribution structure 100. If fewer dielectric layers and metallization structures are to be formed, the steps and processes discussed below can be omitted.If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below can be repeated.

[0008] Fig. Figure 1 illustrates a cross-sectional view of a substrate 102 of a semiconductor device. In some embodiments, the semiconductor device is a device wafer comprising active and / or passive components. In some embodiments, the substrate 102 and the semiconductor device can be separated to form multiple chips / dies, as shown in the illustrated view of Fig. 1. This may be one of such dies. In some embodiments, the substrate 102 may correspond to an interposer wafer which is free of active components and may contain passive components. In some embodiments, the substrate 102 may correspond to a package substrate strip which is either a coreless package substrate or a cored package substrate with a core therein. In some embodiments, the substrate 102 may correspond to a component wafer which is singulated in subsequent processes. The embodiments of the redistribution structure of the present disclosure may also be applied to interposer wafers, package substrates, packages, or the like.

[0009] In some embodiments, the substrate can support 102 logic dies (e.g., central processing units (CPUs), graphics processing units (GPUs), systems-on-chips (SoCs), application processors (APs), microcontrollers, application-specific integrated circuit dies (ASIC dies), or the like), memory dies (e.g., dynamic random access memory dies (DRAM dies), static random access memory dies (SRAM dies), high-bandwidth memory dies (HBM dies), or the like), power management dies (e.g., integrated power management circuit dies (PMIC dies)), high-frequency dies (RF dies), sensor dies, microelectromechanical system dies (MEMS dies), signal processing dies (e.g., digital signal processing dies (DSP dies), or the like). Frontend dies (e.g., analog frontend dies (AFE dies)), the like, or a combination thereof.

[0010] In some embodiments, the substrate 102 may be a semiconductor substrate and may include elements formed on a top surface of the substrate 102. In such embodiments, the substrate 102 may be a solid semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 102 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 102 may include silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Shallow trench isolation regions (STI regions) (not illustrated separately) may be formed in substrate 102 to isolate active regions within the substrate 102. Contacts (not illustrated separately) can be configured to extend into or through the substrate 102 (e.g. vias) and can be used to electrically couple features on opposite sides of the substrate 102.

[0011] In some embodiments, the substrate 102 has integrated circuit components which are formed on the uppermost surface of the semiconductor substrate 102 and connected to the conductive elements 101 of Fig. 19 are coupled. The integrated circuit components can comprise complementary metal-oxide-semiconductor transistors (CMOS transistors), resistors, capacitors, diodes, and the like. The details of the integrated circuit components are not illustrated herein. In some embodiments, the substrate 102 is used to form interposers (which are free of active components), and the substrate 102 can be a semiconductor substrate or a dielectric substrate.

[0012] A seed layer 106 is formed over the substrate 102. The seed layer 106 can be formed from any suitable material by a suitable process. In some embodiments, the seed layer can contain copper, aluminum, platinum, gold, palladium, titanium, tungsten, cobalt, the like, and combinations thereof, and can be deposited by sputtering, a CVD process, a PVD process, the like, or combinations thereof. The seed layer 106 can be deposited to a thickness between 0.2 µm and 0.6 µm, or any suitable thickness.

[0013] In Fig. 2. A mask layer 107 is formed on the seed layer 106 and structured to expose sections of the seed layer 106. The mask layer 107 can be formed from a photosensitive material and structured using acceptable photolithography techniques. In some embodiments, the mask layer 107 can be the bottom layer of a two-layer or three-layer photomask, wherein an upper layer of the mask is structured by photolithography and underlying layers, including the mask layer 107, are subsequently structured by etching. In some embodiments, double structuring or multiple structuring processes can be used.In general, dual- or multi-structuring processes combine photolithography and self-aligning processes, thereby enabling the creation of structures with, for example, smaller spacing than can otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate 102 and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then become the mask layer 107.

[0014] In Fig. 3. The conductive layer 108 is deposited on the exposed portions of the seed layer 106. In some embodiments, the conductive layer 108 is relatively thick, for example, compared to the thickness of the dielectric layer that separates the conductive layer 108 from another conductive layer formed in a subsequent process (described below). The conductive layer 108 is also thick relative to subsequent metal conductors and can be used for routing signals with less signal loss, for example, in the case of radio or analog signals. In some embodiments, the thickness of the combination of the seed layer 106 and the conductive layer 108 can be between about 10 µm and about 60 µm, although other thicknesses are also considered and can be used.The conductive layer 108 can be formed from any suitable conductive material, including, for example, Co, Cu, Al, Ti, Ta, W, TiN, TaN, the like, or combinations thereof. The conductive layer 108 can be formed using any suitable technique, including PVD, ALD, CVD, variants thereof, the like, or combinations thereof. The conductive layer 108 is a first metallization layer of a redistribution structure.

[0015] Further referring to Fig. 3. The mask layer 107 is removed by a back-etching or ashing technique. Any material of the conductive layer 108 that may be lying on top of the mask layer 107 is removed when the mask layer 107 is removed. Next, exposed portions of the seed layer 106 are removed by an etching technique using a suitable etchant that is selective for the material of the seed layer 106.

[0016] In Fig. 4 An insulating material 111 is deposited over the conductive layer 108. Fig. Figure 4 illustrates insulating material 111 shortly after deposition, i.e., before curing. Insulating material 111 may be a lacquer-like insulating material rather than a dry insulating material. Insulating material 111 may simply be a resin, i.e., the resin may be free of filler material. For example, insulating material 111 may be a type of polymer known as an additive polymer, such as an epoxy, bismaleimide (BMI), polyphenylene oxide (PPO), cyanate ester, acrylate, the like, or combinations thereof. The molecular weight of the insulating material may be less than 50,000 g / mol, such as between approximately 25,000 g / mol and 50,000 g / mol. The solids content of the resin may be greater than 40%, such as between approximately 40% and approximately 60%. The shrinkage rate of the insulating material 111 can be between approximately 95-99%, or in other words, the thickness of the final cured insulating material 112 (see Fig. 5) is 95-99% of the thickness of the uncured insulating material 111, or in other words, the shrinkage is very low (between 1% and 5%). The insulating material 111 can be deposited using any technique, such as rotational coating, screen printing, spray coating, the like, or combinations thereof. An SAP process can also be used, an example of which is further described below, in which the subsequently formed via and conductive layer are processed simultaneously. Due to the deposition technique, the top surface of the insulating material 111 may exhibit a high degree of planarity, i.e., be flat, shortly after deposition, as shown, for example, in Fig. Figure 4 illustrates this. Thus, the thickness of the insulating material 111 varies due to the underlying conductive layer 108, being thicker between elements of the conductive layer 108 (e.g., thickness 111t1) and thinner over elements of the conductive layer 108 (e.g., thickness 111t2).

[0017] The insulating material 111 can be deposited to a thickness 111t1 between approximately 12 µm and approximately 120 µm (or a thickness 111t2 between approximately 2 µm and approximately 60 µm, or less than the thickness of the combination of the seed layer 106 and the conductive layer 108, such as between 30% and 100% or between 30% and 70% of the thickness of the combination of the seed layer 106 and the conductive layer 108). Because the shrinkage rate of the insulating material 111 is only 95% to 99%, when the insulating material 111 shrinks, the differences in thickness due to the conductive layer 108 are minimal. Therefore, when the insulating material 111 shrinks after application, the combination of the shrinkage rate, the filler-free design, the molecular weight and the solids content ensures that only small voids appear in the upper surface, which correspond to areas where the structure of the conductive layer 108 is sparse.Because the insulating material 111 has an additional polymerization, there are no additional by-products to be removed during curing, and little to no weight loss of the insulating material 111 is observed.

[0018] Referring to Fig. 5. After the insulating material 111 has shrunk into its final form as the insulating layer 112, the thickness 112t1 of the insulating material between elements of the conductive layer 108, from the underlying substrate 102 to the upper surface of the insulating layer 112, can be between approximately 12 µm and approximately 114 µm. The thickness d1 (or 112t2) of the insulating material above the conductive layer 108 can be between approximately 2 µm and approximately 57 µm. In other words, the thickness d1 of the insulating layer 112 can be between approximately 25% and 100% of the combined thickness of the conductive layer 108 and seed layer 106, such as between approximately 30% and 60%. In some embodiments, the thickness d1 of the insulating layer 112 can be less than half the thickness of the combined conductive layer 108 and seed layer 106.The relatively thin insulating layer 112 over the thick conductive metal layer 108 reduces transmission loss and increases energy efficiency. The illustrated process advantageously produces an insulating layer 112 that is thinner than the thickness of the underlying metallization (seed layer 106 and conductive layer 108) without the need for any additional planarization processes.

[0019] Where the insulating layer 112 fills the spaces laterally surrounding the conductive layer 108, when the film of insulating material 111 shrinks into its final shape within the insulating layer 112, recesses ri can form in the upper surface of the insulating layer 112 due to the different thicknesses of the insulating layer 112 over elements of the conductive layer 108 compared to between elements of the conductive layer 108. The recesses ri can have a depth d2, which is determined by the differences in thicknesses 111t1 and 111t2. This difference can be attributed to the metallization structure (conductive layer 108 and seed layer 106). Therefore, the depth d2 is approximately the thickness of the metallization structure multiplied by the shrinkage rate. Thus, the recesses ri can have a depth d2 between 1% and 5% of the thickness of the combined conductive layer 108 and seed layer 106, such as e.g.between 0.1 µm and approximately 3 µm. Taking into account the thickness d1, since this refers to the conductive layer 108 and the seed layer 106, the recesses ri also lie between 1% and 5% of the thickness d1.

[0020] Because the recesses ri are only between 1% and 5% of the thickness d1, a planarization process can be omitted, saving time and resources. This results in an upper surface of the insulating layer 112 that may exhibit slight waviness due to the recesses ri. Furthermore, if planarization were performed, traces would be left behind as a result of the planarization process. However, in the present embodiments, there are no planarization traces on the insulating layer 112 (and subsequent insulating layers).When subsequent conductive and insulating layers are formed, these voids ri can be transferred to the subsequent layers to some extent; however, the transfer for each subsequent layer may be less than that of the preceding layer because, in general, only a fraction of the void depth d2 is transferred. For example, as stated above, the void depth d2 is between 1% and 5% of the thickness of the combined conductive layer 108 and seed layer 106. In a subsequent insulating layer, the transfer is reduced by a similar amount, depending on the material of the next insulating layer, so that any transfer of voids r1 may only be about 1% to 35% of the void depth d2. In principle, acceptable planarity of the subsequent layers can be maintained without the need for planarization steps.Acceptable planarity allows for the reliable execution of subsequent photolithography techniques, e.g., without focus errors that can result from topography problems.

[0021] In Fig. 6. After the insulating layer 112 has been formed, the insulating layer 112 is then photostructured using an acceptable photolithography technique, such as exposure, development and curing, to form the openings 114 in the insulating layer 112 to expose sections of the conductive layer 108. Although the openings 114 are illustrated as conical, the openings 114 can also be rectangular, i.e., have vertical sidewalls.

[0022] In Fig. 7. A metallization structure is formed which includes conductive elements, such as the seed layer 116 and the conductive layer 118, which extend along the main surface of the insulating layer 112 and through the insulating layer 112 to establish physical and electrical coupling to the conductive layer 108. As an example of forming the metallization structure, the seed layer 116 is formed above the insulating layer 112 and in the openings 114 that extend through the insulating layer 112. In some embodiments, the seed layer 116 is a metal layer, which may be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer 116 includes a titanium layer and a copper layer above the titanium layer.The seed layer 116 can be formed, for example, by PVD or similar processes. A photoresist is then applied to the seed layer 116 and structured. The photoresist can be formed by rotational coating or similar processes and can be exposed to light for structuring. The structure of the photoresist corresponds to the metallization structure of the conductive layer 118. The structuring creates openings through the photoresist to expose the seed layer. The conductive layer 118 is then formed in the openings of the photoresist and on the exposed sections of the seed layer 116. The conductive layer 118 can be formed by plating, such as electroplating or electroless plating, or similar processes. The conductive layer 118 can contain a metal such as copper, titanium, tungsten, aluminum, or similar materials.The combination of the conductive layer 118 and underlying sections of the seed layer 116 forms the metallization structure. The photoresist and sections of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using oxygen plasma or the like. After the photoresist has been removed, exposed sections of the seed layer are removed, for example, by using an acceptable etching process, such as wet or dry etching.

[0023] The thickness d3 of the combined seed layer 116 and conductive layer 118 can be between 15% and 30% of the thickness of the conductive layer 108. In other words, the thickness d3 of the subsequent metallization structures can be much thinner than the thickness of the first metallization structures of the redistribution structure 100. In some embodiments, the conductive layer 118 can be used to route signals that are not as sensitive to attenuation as the signals routed in the conductive layer 108. The reduced thickness of the conductive layer 118 compared to the conductive layer 108 helps to reduce the overall device thickness and to control heat dissipation. The reduced thickness of the conductive layer 118 also helps to maintain good planarity in the subsequently formed insulating layer without the need for a planarization process, such as the one described below.In some embodiments, the thickness d3 of the combined seed layer 116 and conductive layer 118 can be between approximately 3 µm and approximately 8 µm. The seed layer 116 and the conductive layer 118 follow the shape of the openings 114, causing a portion of the conductive layer 118 to have an upper surface in the openings 114, which extends into the openings 114 by a distance d4 to approximately half the thickness of the insulating layer 112 above the conductive layer 108. In some embodiments, the distance d4 can be greater than the thickness d3, for example, between 0 and (d3 + (d1) / 2). In other embodiments, the distance d4 can be less than the thickness d3.

[0024] In Fig. In Figure 8, an insulating layer 122 is deposited over the conductive layer 118 and over sections of the insulating layer 112. In some embodiments, the insulating layer 122 can be an additive polymer, such as that used in the insulating layer 112, and can be formed using the same materials and processes as those discussed above with reference to the insulating layer 112, although the material composition of the insulating layer 122 may be the same as or different from that of the insulating layer 112. In other embodiments, the insulating layer 122 can be a different type of polymer, such as a condensation polymer. The insulating layer 122 can be a lacquer-like insulating material rather than a dry insulating material. The material can simply be a resin, i.e., the resin can be free of filler material.For example, the material can be a condensation polymer, such as a polyimide, polybenzoxazole (PBO), nylon, the like, or combinations thereof. The molecular weight of the insulating layer 122 material can be less than 25,000 g / mol, for example, between approximately 10,000 g / mol and 25,000 g / mol. The solids content of the resin can be greater than 45%, for example, between approximately 45% and approximately 60%. The shrinkage rate of the insulating layer 122 material can be between approximately 65% ​​and 80%, for example, between 68% and 75%. In other words, the insulating layer 122 can lose 20% to 35% of its thickness during curing from the freshly deposited to the cured state. The insulating layer 122 can be deposited using any technique, such as rotary coating, screen printing, spray coating, the like or combinations thereof.Due to the deposition technique, the upper surface of the insulating material of the insulating layer 122 can exhibit a high degree of planarity, i.e., be flat, shortly after deposition. Thus, the thickness of the insulating material varies due to the underlying conductive layer 118 and the recesses ri, being thicker between elements of the conductive layer 118 and thinner over elements of the conductive layer 118.

[0025] The insulating layer 122 can be deposited to a thickness between approximately 7 µm and approximately 25 µm. Because the shrinkage rate of the insulating layer 122 material is relatively high, the combination of the shrinkage rate, the filler-free design, the molecular weight, and the solids content tends to transfer attenuated versions of the underlying dimples and bumps to form a wavy top surface of the insulating layer 122, as the insulating layer 122 shrinks after deposition. These attenuated protrusions protrude at a rate of approximately one to three or one to four, or in other words, for every 3 µm to 4 µm of variation, approximately 1 µm is transferred to the surface of the insulating layer 122 (plus / minus 50%). For example, the underlying features, such asThe conductive layer 118 and / or the recesses ri are transferred to the upper surface of the insulating layer 122. In other words, although the insulating material of the insulating layer 122 may be planar shortly after deposition, the insulating layer 122 may have an upper surface after curing that is to some extent conformed to the features of the underlying material. However, the insulating layer 122 is relatively thin, e.g., compared to the thickness of the conductive layer 118. Therefore, it would be difficult to reliably flatten the upper surface of the insulating layer 122, for example, by planarization. Thus, instead of planarizing the upper surface of the insulating layer 122, as noted in the subsequent processes described below, the subsequent metallization structures are formed directly on the corrugated upper surface of the insulating layer 122.

[0026] After the insulating material of the insulating layer 122 has shrunk into its final shape as the insulating layer 122, the thickness d5 of the insulating layer 122 above the conductive layer 118 can be between approximately 5 µm and approximately 7 µm. The illustrated process advantageously produces the insulating layer 122, which has 100% to 200% of the thickness of the underlying metallization (seed layer 116 and conductive layer 118), without the need for any additional planarization processes. Sections of the insulating layer 122 can extend into depressions in the conductive layer 118 according to distances d4 (see Figure 1). Fig. 7), and as a result, in some embodiments the lowest surface of the insulating layer 122 may extend deeper than an upper surface of the insulating layer 112.

[0027] Where the insulating layer 122 fills the spaces that laterally surround the conductive layer 118, recesses r2 can be formed in the upper surface of the insulating layer 122. Similarly, where the insulating layer 122 fills the depression in the upper surface of the conductive layer 118 (e.g., according to the distance d4), recesses r3 can be formed in the upper surface of the insulating layer 122. The recesses r2 and r3 can have a depth d6 between 10% and 35% of the thickness d5, such as between 1.0 µm and approximately 3.0 µm. The recesses r2 and r3 can have a depth d6 between 30% and 60% of the thickness of the conductive layer 118, such as between 1.0 µm and approximately 3.0 µm. Because the recesses r2 and r3 are between 10% and 35% of the thickness d5, a planarization process can be omitted, saving time and resources.This results in an upper surface of the insulating layer 122 with waviness due to the recesses r2 and r3.

[0028] After the insulating layer 122 has formed, in Fig. 9. The insulating layer 122 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 124 in the insulating layer 122 for exposing sections of the conductive layer 118. Although the openings 124 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0029] In Fig. 10. The seed layer 126 and the conductive layer 128 can be formed in the openings 124 and extend along an upper surface of the insulating layer 122. The seed layer 126 and the conductive layer 128 can be formed using processes and materials similar to those discussed above with reference to the seed layer 116 and the conductive layer 118, which are not repeated. The seed layer 126 and the conductive layer 128 follow the shape of the openings 124, which can cause a section of the conductive layer 128 to have an upper surface in the openings 124 that extends into the openings 124 by a distance of up to about half the thickness of the insulating layer 122 above the conductive layer 128. In some embodiments, the distance d8 can be greater than the thickness d7, for example between o and (d7 + (d5) / 2).In other embodiments, the distance d8 can be smaller than the thickness d7.

[0030] In Fig. In embodiment 11, the insulating layer 132 can be deposited over the conductive layer 128 and the insulating layer 122. In some embodiments, the insulating layer 132 can be an additive polymer like the insulating layer 112 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 112, although the material composition of the insulating layer 132 may be the same as that of the insulating layer 112 or different. In other embodiments, the insulating layer 132 can be a condensation polymer like the insulating layer 122 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 122, although the material composition of the insulating layer 132 may be the same as that of the insulating layer 122 or different.

[0031] After the insulating layer 132 has formed, in Fig. 12. The insulating layer 132 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 134 in the insulating layer 132 for exposing sections of the conductive layer 128. Although the openings 134 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0032] In Fig. 13. The seed layer 136 and the conductive layer 138 can be formed in the openings 134 and extend along an upper surface of the insulating layer 132. The seed layer 136 and the conductive layer 138 can be formed using processes and materials similar to those discussed above with reference to the seed layer 116 and the conductive layer 118.

[0033] In Fig. In embodiment 14, the insulating layer 142 can be deposited over the conductive layer 138 and the insulating layer 132. In some embodiments, the insulating layer 142 can be an additive polymer like the insulating layer 112 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 112, although the material composition of the insulating layer 142 may be the same as that of the insulating layer 112 or different. In other embodiments, the insulating layer 142 can be a condensation polymer like the insulating layer 122 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 122, although the material composition of the insulating layer 142 may be the same as that of the insulating layer 122 or different.

[0034] After the insulating layer 142 has formed, in Fig. 15. The insulating layer 142 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 144 in the insulating layer 142 for exposing sections of the conductive layer 138. Although the openings 144 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0035] In Fig. 16. The seed layer 146 and the conductive layer 148 can be formed in the openings 144 and extend along an upper surface of the insulating layer 142. The seed layer 146 and the conductive layer 148 can be formed using processes and materials similar to those discussed above with reference to the seed layer 116 and the conductive layer 118.

[0036] In Fig. 17. The insulating layer 152 can be deposited over the conductive layer 148 and the insulating layer 142. In some embodiments, the insulating layer 152 can be an additive polymer like the insulating layer 112 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 112, although the material composition of the insulating layer 152 may be the same as that of the insulating layer 112 or different. In other embodiments, the insulating layer 152 can be a condensation polymer like the insulating layer 122 and can be formed by materials and processes similar to those discussed above with reference to the insulating layer 122, although the material composition of the insulating layer 152 may be the same as that of the insulating layer 122 or different.

[0037] The insulating layer 152 is illustrated as an uppermost insulating layer of the redistribution structure 100. It should be understood that more or fewer metallization structures can be used in the redistribution structure 100 by repeating or omitting the above processes of structuring the insulating layer and depositing a seed layer and a conductive layer. The redistribution structure 100 can be further processed, as described below and as described in other embodiments, to form connectors or other conductive elements. An upper surface of the insulating layer 152 can have the recesses r4, which correspond to recesses in the upper surface that are formed by the thickness of the conductive layer (e.g., the combination of the seed layer 146 and the conductive layer 148).The recesses r4 can also be recesses resulting from the transfer of recesses in the upper surface of the underlying insulating layer (e.g., insulating layer 142). The upper surface of insulating layer 152 can also have recesses r5, which correspond to a region of the underlying conductive layer (e.g., conductive layer 148) that extends through the underlying insulating layer (e.g., insulating layer 142) and is in contact with another underlying conductive layer (e.g., conductive layer 138). These recesses are similar to the recesses r2 and r3 discussed above. Therefore, the upper surface of insulating layer 152 can be wavy due to the recesses r4 and r5.

[0038] In Fig. 17 is a measure of the waviness of the uppermost insulating layer 152, the distance d9 between the average peak 152u1 of the upper surface of the insulating layer 152 and the average valley 152u2 of the upper surface of the insulating layer 152, and this can be between about 3 µm and about 5 µm. The waviness of the various layers of the redistribution structure is similar to the waviness of the uppermost insulating layer 152. Waviness in a redistribution structure is generally undesirable because it increases the possibility of layer delamination, metallization short circuits and breaks, and structuring focus defects. However, in the embodiments described herein, the waviness is controlled by the selection of the material of the insulating layers, the thicknesses of the underlying metallization structures, and the deposition techniques employed. Because of this, after the formation of each insulating layer (e.g.,(of the insulating layers 112, 122, 132, 142 and 152) there is no need for a separate planarization process, and because a planarization process is omitted, no additional material needs to be deposited for the insulating layers, which would otherwise be required to provide space for the planarization processes. Therefore, the thickness of the redistribution structure can advantageously be smaller, and the additional planarization process steps can be omitted.

[0039] After the insulating layer 152 has been formed, in Fig. 18 The insulating layer 152 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 154 in the insulating layer 152 for exposing sections of the conductive layer 148. Although the openings 154 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0040] In Fig. 19 Conductive connectors 160 are formed in the openings 154. In some embodiments, the conductive connectors 160 can be formed on under-bump metallization structures (UBMs - Under Bump Metallization Structures) (see, for example, the UBMs 394 in Fig. 51), which are first formed in the openings 154. In such embodiments, UBMs can be formed for an external connection to the front face of the redistribution structure 100. The UBMs can have bump sections on and extending along the main surface of the insulating layer 152 and have via sections extending through the insulating layer 152 to establish physical and electrical coupling to the conductive layer 148. As a result, the UBMs are electrically coupled through the various conductive layers 148 to conductive elements 101 in the substrate 102, which may be coupled to components in the substrate 102. The UBMs can be formed from the same material as the seed layer 146 and / or the conductive layer 148. In some embodiments, the UBMs have different sizes (e.g.,thickness) as the metallization structures which correspond to the conductive layers 108, 118, 128, 138, 148 and so on.

[0041] The conductive connectors 160 can be connectors with a ball grid array (BGA), solder balls, metal pillars, controlled collapse chip connection bumps (C4 bumps), micro-bumps, bumps formed using the ENEPIG (electroless nickel-electroless palladium immersion gold technique), or the like. The conductive connectors 160 can contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 160 are formed by initially forming a layer of solder by evaporation, electroplating, printing, solder feeding, ball placement, solder paste, or the like. After a layer of solder has formed on the structure, melting can be performed to shape the material into the desired bump shapes.In another embodiment, the conductive connectors comprise 160 metal columns (such as a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns can be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal columns. The metal cap layer can contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by a plating process.

[0042] The resulting redistribution structure 100 can be used and combined in various packages and components, as described below with reference to the following embodiments. Advantageously, the redistribution structure 100 employs an insulating material with extremely high shrinkage over a thick conductive metal layer, eliminating the need for planarization processes to achieve a final insulating layer that is only 25% to 50% thicker than the thick conductive metal layer. This provides excellent signal transmission capability, reliability, and heat dissipation using simplified processes. Additional insulating layers of the redistribution structure 100 also exhibit good planarity due to their high shrinkage and filler-free composition.

[0043] Fig. 20 to Fig. Figure 29 illustrates intermediate stages in the formation of a redistribution structure 200 in accordance with some embodiments. Fig. 20 to Fig. 29 use reference numbers similar to those used in Fig. 1 to Fig. 19 are used, except that the '1' in the first position of the digit '1xx' is replaced by a '2' in a corresponding digit '2xx'. Identical reference digits represent identical elements in Fig. 20 to Fig. 29, unless otherwise stated. Briefly on Fig. 29 Referring to this, the redistribution structure 200 serves to electrically couple conductive elements 201 in the substrate 202 to other conductive elements 201 in the substrate 202 and to conductive connectors 260. The redistribution structure 200 has insulating layers 212, 222, and 232 and metallization structures containing conductive layers 208, 218, and 228. The metallization structures can also be referred to as redistribution layers or redistribution lines. The redistribution structure 200 is shown as an example with three layers of metallization structures. More or fewer dielectric layers and metallization structures can be formed in the redistribution structure 200. If fewer dielectric layers and metallization structures are desired, the steps and processes discussed below can be omitted.If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below can be repeated.

[0044] Fig. Figure 20 illustrates a substrate 202, a seed layer 206, and a conductive layer 208, which are produced using processes and materials similar to those described above with the substrate 102, the seed layer 106, and the conductive layer 108, respectively, as in, for example, Fig. 3 illustrated, discussed, and can be trained. In Fig. However, in 20 the insulating material 211 is made of a different material than the insulating material 111 of the insulating layer 112, which is in Fig. 4 and Fig. Figure 5 illustrates the following. In particular, the insulating layer 212 can be formed using a condensation polymer, as described above for the insulating layer 122. The insulating material 211 can be a lacquer-like insulating material rather than a dry insulating material. The insulating material 211 can be simply a resin, i.e., the resin can be free of filler material. For example, the insulating material 211 can be a condensation polymer, such as polyimide (PI), polybenzoxazine (PBO), nylon, the like, or combinations thereof. The molecular weight of the insulating material 211 can be less than 25,000 g / mol, such as between approximately 15,000 g / mol and 25,000 g / mol. The solids content of the resin can be greater than 40%, such as between approximately 40% and approximately 60%. The shrinkage rate of the insulating material 211 can range between approximately 65% ​​and 80%, such as between approximately 68% and 75%.In other words, the insulating layer 122 can lose 20% to 35% of its thickness during curing from the freshly deposited state to the cured state. The insulating material 211 can be deposited using any technique, such as rotational coating, screen printing, spray coating, or combinations thereof. Due to the deposition technique, the upper surface of the insulating material 211 may exhibit a high degree of planarity, i.e., be flat, shortly after deposition. Thus, the thickness of the insulating material 211 varies shortly after deposition due to the underlying conductive layer 208. The insulating material 211 can be deposited to a thickness between approximately 7 µm and approximately 25 µm greater than the thickness of the underlying conductive layer 208.

[0045] In Fig. 21. The insulating material 211 cures and shrinks to form the insulating layer 212. Because the insulating material 211 shrinks by 20% to 35% when it shrinks to form the insulating layer 212 after application, the combination of the shrinkage rate, the filler-free design, the molecular weight, and the solids content tends to transfer attenuated versions of the conductive layer 208 to the top surface of the insulating layer 212, forming a wavy top surface. These attenuated protrusions protrude at a rate of about one to three, or in other words, for every 3 µm of variation, about 1 µm of it is transferred to the surface of the insulating layer 212 (plus / minus 50%).Although the insulating material 211 may be planar shortly after deposition, the insulating layer 212 may, after curing, exhibit an upper surface that is to some extent conformed to the features of the underlying material. The conductive layer 208 may be relatively thick, for example, approximately twice as thick as the insulating layer 212 above the conductive layer 208. The shrinkage between sections of the conductive layer 208 may be significant, resulting in an upper surface that dips below the plane of the upper surface of the conductive layer 208. Even if the upper surface of the insulating layer 212 did not dip below the plane of the upper surface of the conductive layer, the lack of leeway in the thickness of the insulating layer 212 would make it difficult to reliably planarize its upper surface.Therefore, instead of planarizing the upper surface of the insulating layer 212 as noted in the subsequent processes described below, the subsequent metallization structures are formed directly on the corrugated upper surface of the insulating layer 212.

[0046] The thickness d11 of the insulating material above the conductive layer 208 can be between approximately 5 µm and approximately 10 µm. In other words, the thickness d11 of the insulating layer 212 can be between approximately 25% and 50% of the combined thickness of the conductive layer 208 and seed layer 206. The relatively thin insulating layer 212 above the thick conductive metal layer 208 reduces transmission loss and increases energy efficiency. The illustrated process advantageously produces an insulating layer 212 that has a thickness of 25% to 50% of the underlying metallization (seed layer 206 and conductive layer 208) without the need for any additional planarization processes. Furthermore, if planarization is performed, traces are left behind due to the planarization process.However, in the present embodiments there are no planarization traces on the insulating layer 212 (and subsequent insulating layers).

[0047] Where the insulating layer 212 fills the spaces that laterally surround the conductive layer 208, recesses r11 can be formed in the upper surface of the insulating layer 212. The recesses r11 can have a depth d12 between 75% and 125% of the thickness d11, for example, between 5 µm and approximately 12.5 µm. The recesses r11 can have a depth d12 between 25% and 65% of the thickness of the conductive layer 208, for example, between 5 µm and approximately 13 µm.

[0048] Due to the thick metallization of the conductive layer 208 and the shrinkage rate of the insulating layer 212, the recesses r11 cause a wavy upper surface of the insulating layer 212. The insulating material 211 of the insulating layer 212 can have a shrinkage rate between 65% and 80%, as indicated above, for example, between 68% and 75%. The amount of insulating material 211 surrounding the conductive layer 208 is subject to a greater difference in shrinkage than the insulating material 211 located directly above the conductive layer 208. It is desirable to keep the distance d11 thin to reduce transmission loss and increase energy and heat dissipation efficiency.

[0049] Even if the top surface of the insulating layer 212 is wavy, it is not planarized and is instead left wavy. Because the subsequent conductive layers are deposited in thinner layers, the waviness of the insulating layer 212 can persist. The waviness of the insulating layer 212 continues in the subsequent layers of the redistribution structure; however, the distance between a high point and a low point of the subsequently formed insulating layers is reduced, and the transmission decreases with each subsequent layer.

[0050] After the insulating layer 212 has formed, in Fig. 22 The insulating layer 212 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 214 in the insulating layer 212 for exposing sections of the conductive layer 208. Although the openings 214 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0051] In Fig. 23 A metallization structure is formed which has conductive elements, such as the seed layer 216 and the conductive layer 218, which extend along the main surface of the insulating layer 212 and through the insulating layer 212 to establish physical and electrical coupling to the conductive layer 208. The seed layer 216 and the conductive layer 218 can be formed using processes and materials similar to those of the seed layer 116 and the conductive layer 118 described above with reference to Fig. 7 were discussed, will be trained.

[0052] The thickness d13 of the combined seed layer 216 and conductive layer 218 can be between approximately 15% and 35% of the thickness of the conductive layer 208. In other words, the thickness of the metallization structure for the conductive layer 208 can be between 3 and 5 times greater than the thickness d13. In some embodiments, the conductive layer 218 can be used to route signals that are not as sensitive to attenuation as the signals routed in the conductive layer 208. The reduced thickness compared to the conductive layer 208 helps to reduce the overall device thickness and to control heat dissipation. The reduced thickness of the conductive layer 218 also helps to improve the planarity of the top layer of the redistribution structure without the need for a planarization process, such as the one described below.In some embodiments, the thickness d13 of the combined seed layer 216 and conductive layer 218 can be between 3 µm and approximately 8 µm. The seed layer 216 and the conductive layer 218 follow the shape of the openings 214, causing a portion of the conductive layer 218 to have an upper surface in the openings 214, which extends into the openings 214 by a distance d14 to approximately half the thickness of the insulating layer 212 above the conductive layer 218. In some embodiments, the distance d14 can be greater than the thickness d13, for example, between 0 and (d13 + (d11) / 12). In other embodiments, the distance d14 can be less than the thickness d13.

[0053] The metallization structure also follows the contours of the wave-like upper surface of the insulating layer 212. Each of the metallization structures corresponding to the conductive layer 218 is thinner than the distance d12 and has sufficient lateral separation to prevent the conductive layers 218 from fusing together.

[0054] In Fig. 24 The insulating layer 222 is deposited over the conductive layer 218 and over sections of the insulating layer 212. In some embodiments, the insulating layer 222 can be a condensation polymer such as the insulating layer 212 and can be formed using materials and processes such as those discussed above with reference to the insulating layer 212, as in Fig. Figure 24 illustrates this, although the material composition of the insulating layer 222 may also differ from that of the insulating layer 212. In other embodiments, the insulating layer 222 may be an additive polymer similar to that of the insulating layer 112 and may be formed using materials and processes like those discussed above with reference to the insulating layer 112. Due to the deposition technique, the upper surface of the insulating material of the insulating layer 222 may exhibit a high degree of planarity, i.e., be flat, shortly after deposition. Thus, the thickness of the insulating material of the insulating layer 222 varies due to the underlying conductive layer 218 and the corrugated surface of the insulating layer 212.

[0055] The insulating layer 222 can be deposited in thicknesses between approximately 15 µm and 70 µm. As the insulating layer 222 material cures and shrinks, the underlying topography begins to show through to the surface of the insulating layer 222. However, because the shrinkage rate of the insulating layer 222 material is between 65% and 80%, such as between approximately 68% and 75%, when the insulating layer 222 material shrinks after deposition (losing between 20% and 35% of its thickness shortly after deposition), the combination of the shrinkage rate, the filler-free design, the molecular weight, and the solids content dampens the protrusions of the underlying layer. In other words, the topography of the upper surface of the insulating layer 222 is flatter after curing than the corresponding topography of the upper surface of the insulating layer 212.An example of this attenuation effect is discussed below.

[0056] After the insulating material of the insulating layer 222 has shrunk into its final shape as the insulating layer 222, the thickness d15 of the insulating layer 222 above the conductive layer 218 can be between approximately 5 µm and approximately 20 µm. The illustrated process advantageously produces the insulating layer 222, which has a thickness of 50% to 200% of the underlying metallization (seed layer 216 and conductive layer 218), without the need for any additional planarization processes.

[0057] Where the insulating layer 222 fills the spaces that laterally surround the conductive layer 218, various recesses can be formed in the upper surface of the insulating layer 222. The recesses r12 correspond to the metallization area that corresponds to the conductive layer 218, which is used as a via extending through the insulating layer 222 and in contact with the conductive layer 208. The depth d16 of the recess r12 can correspond to the topography of the underlying conductive layer 218, but can be reduced. For example, the depth d16 can be approximately 20% to 40% of the depth d14, such as between 1 µm and 4 µm.The recesses r13 correspond to the area of ​​the insulating layer 222, which has a waviness corresponding to the underlying topography of the insulating layer 212, without any part of the conductive layer 218 being located between the top surface of the insulating layer 212 and the top surface of the insulating layer 222. The depth d17 of recess r13 thus corresponds to the depth d12 of recess r11. Fig. 21. However, due to the material of the insulating layer 222, the protrusion of the recess r11 in the insulating layer 222 is attenuated. For example, the depth d17 can be approximately 20% to 40% of the depth d12, such as between 1 µm and 3 µm. The recesses r14 correspond to the area of ​​the insulating layer 222 that exhibits a waviness corresponding to a transition between the underlying topography of the insulating layer 212 and the underlying topography of the conductive layer 218. The depth d18 of the recess r14 thus corresponds to the thickness d13 of the metallization of the conductive layer 218. However, due to the material of the insulating layer 222, the protrusion of the thickness of the conductive layer 218 in the insulating layer 222 is attenuated. For example, the depth d18 can be approximately 20% to 40% of the thickness d13, such as between 0.5 µm and 1.5 µm.

[0058] Although the upper surface of the insulating layer 222 is corrugated, the corrugation is less pronounced than that of the insulating layer 212. Therefore, no separate planarization process is required before depositing additional conductive lines, saving time and resources. This results in an upper surface of the insulating layer 222 that exhibits corrugation.

[0059] After the insulating layer 222 has formed, in Fig. 25 The insulating layer 222 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 224 in the insulating layer 222 for exposing sections of the conductive layer 218. Although the openings 224 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0060] In Fig. 26 The seed layer 226 and the conductive layer 228 can be formed in the openings 224 and extend along an upper surface of the insulating layer 222. The seed layer 226 and the conductive layer 228 can be formed using processes and materials similar to those discussed above with reference to the seed layer 216 and the conductive layer 218, which are not repeated. The seed layer 226 and the conductive layer 228 follow the shape of the openings 224, which can cause a section of the conductive layer 228 to have an upper surface in the openings 224 that extends into the openings 224 by a distance of up to about half the thickness of the insulating layer 222 above the conductive layer 228, with dimensions similar to those discussed above with reference to Fig. 23 were discussed.

[0061] In Fig. 27 The insulating layer 232 is deposited over the conductive layer 228 and over sections of the insulating layer 222. In some embodiments, the insulating layer 232 can be a condensation polymer such as the insulating layer 212 and can be formed using materials and processes such as those discussed above with reference to the insulating layer 212, as in Fig. Figure 27 illustrates this, although the material composition of the insulating layer 232 may also differ from the material composition of the insulating layer 212. In other embodiments, the insulating layer 232 may be an additive polymer similar to that of the insulating layer 112 and may be formed using materials and processes such as those discussed above with reference to the insulating layer 112.

[0062] For reasons similar to those mentioned above with reference to Fig. As discussed in section 24, the protrusions of the topography from the underlying insulating layer 222 and the metallization corresponding to the conductive layer 228 are further attenuated in the upper surface of the insulating layer 232. As a result, each subsequent layer of the redistribution structure 200 generally has a flatter upper surface than the preceding one. For example, in some embodiments, the difference between the peak height and the lowest valley of the insulating layer 212 is between about 1 µm and 16 µm, whereas in some embodiments the difference between the peak height and the lowest valley of the insulating layer 222 is between about 1 µm and 8 µm, and in some embodiments the difference between the peak height and the lowest valley of the insulating layer 232 is between about 0.5 µm and 4 µm, although other values ​​are also considered.

[0063] The insulating layer 232 is illustrated as an uppermost insulating layer of the redistribution structure 200. It should be understood that more or fewer metallization structures can be used in the redistribution structure 200 by repeating or omitting the above processes of structuring the insulating layer and depositing a seed layer and a conductive layer. The redistribution structure 200 can be further processed as described below and as described in other embodiments to form connectors or other conductive elements. An upper surface of the insulating layer 232 can have the recesses r15, which correspond to the recesses resulting from the underlying features. The recesses r15 can be recesses due to the transfer of the thickness of the conductive layer (e.g., the combination of seed layer 226 and conductive layer 228; see, e.g., the recesses r14 of Fig. 24); Recesses due to the transfer of recesses in the upper surface of the underlying insulating layer (e.g., the insulating layer 222; see, e.g., the recesses r13 of Fig. 24); and recesses due to the transfer of an area of ​​the underlying conductive layer (e.g., the conductive layer 228; see, e.g., the recesses r12 of Fig. 24), which extends through the underlying insulating layer (e.g., the insulating layer 222) and is in contact with another underlying conductive layer (e.g., the conductive layer 218). The upper surface of the insulating layer 232 can therefore be wavy due to the recesses r15.

[0064] In Fig. 27 is a measure of the waviness of the uppermost insulating layer 232, the distance d19 between the average peak 232u1 of the upper surface of the insulating layer 232 and the average valley 232u2 of the upper surface of the insulating layer 232, and can be between about 3 µm and about 5 µm. The waviness of the various layers of the redistribution structure is similar to the waviness of the uppermost insulating layer 232. Waviness in a redistribution structure is generally undesirable because it increases the possibility of layer delamination, metallization short circuits and breaks, and structuring focus defects. However, in the embodiments described herein, the waviness is controlled by the selection of the insulating layer material, the thicknesses of the underlying metallization structures, and the deposition techniques employed. As a result, after the formation of each insulating layer (e.g.,(of the insulating layers 212, 222 and 232) there is no need for a separate planarization process, and because a planarization process is omitted, no additional material needs to be deposited for the insulating layers, which would be necessary to provide space for the planarization processes. Therefore, the thickness of the redistribution structure can advantageously be smaller, and the additional steps of the planarization processes can be omitted.

[0065] After the insulating layer 232 has formed, in Fig. 28 The insulating layer 232 is then photostructured using an acceptable photolithography technique, such as exposure, development, and curing, to form the openings 234 in the insulating layer 232 for exposing sections of the conductive layer 228. Although the openings 234 are illustrated as conical, they can also be rectangular, i.e., have vertical sidewalls.

[0066] In Fig. 29 Conductive connectors 260 are formed in the openings 234. In some embodiments, the conductive connectors 260 can be formed on under-bump metallization structures (UBMs), which are formed first in the openings 254. In such embodiments, UBMs can be formed for an external connection to the front of the redistribution structure 200. The UBMs can have bump sections on and extending along the main surface of the insulating layer 232 and have via sections extending through the insulating layer 232 to establish physical and electrical coupling to the conductive layer 228. As a result, the UBMs are electrically coupled through the various conductive layers 228 to conductive elements 201 in the substrate 202, which can be coupled to components in the substrate 202.The UBMs can be formed from the same material as the seed layer 216 and the conductive layer 218. In some embodiments, the UBMs have a different size (e.g., thickness) than the metallization structures corresponding to the conductive layers 208, 218, and 228, and so on.

[0067] The conductive connectors 260 can be manufactured using processes and materials similar to those mentioned above in relation to the conductive connectors of Fig. 19 were discussed, and will be trained.

[0068] The resulting redistribution structure 200 can be used and combined in various packages and components, as described below with reference to the following embodiments. Advantageously, the redistribution structure 200 employs a high-shrinkage insulating material over a thick conductive metal layer to achieve a final insulating layer that is only 25% to 50% thicker than the thick conductive metal layer. This provides excellent signal transmission capability, reliability, and heat dissipation using simplified processes. Separate planarization processes are omitted in the formation of the various layers of the redistribution structure, and the top surfaces are left corrugated.However, the waviness is reduced or dampened due to the selection of insulating materials in the insulating layers of each subsequent layer of the redistribution structure, which advantageously allows the planarization processes to be omitted.

[0069] Fig. Figure 30 illustrates the redistribution structure of 200. Fig. 29, however, is in Fig. 30 A passivation layer 265 is deposited over the insulating layer 232. The passivation layer 265 can provide a flat top surface and eliminate any remaining waviness on the top surface of the insulating layer 232. In some embodiments, the materials and deposition process of the passivation layer 265 can be selected such that the top surface is flat without the need for a planarization process. In other embodiments, a planarization process, such as grinding or a chemical-mechanical polishing (CMP) process, is used on the passivation layer 265. The passivation layer 265 can be formed before or after the openings 234, and additional openings corresponding to the openings 234 are formed through the passivation layer 265 before the conductive connectors 260 are formed.Other embodiments may omit the passivation layer 265 and use a planarization process, such as grinding or CMP, to flatten the upper surface of the last insulating layer of the redistribution structure 200, e.g., the insulating layer 232, prior to forming the openings for the conductive connectors, e.g., the openings 234.

[0070] Fig. 31 to Fig. Figure 53 illustrates cross-sectional views of various intermediate stages in the formation of a semiconductor device, such as an integrated fan-out package (InFO package), for example, for use with a MEMS device. Fig. Figure 31 illustrates a package region 300A. Package region 300A can be one of several package regions and represents a section of the entire package region 300A. Fig. Figure 31 also provides a support 302. The support 302 may have pre-formed openings, or the openings may be formed in the support 302 using any suitable process. The openings may completely traverse the support 302 (as illustrated) or may only partially traverse it. In some embodiments, the support 302 may be a ceramic support. In some embodiments, the support 302 is provided in a wafer form. Alternatively, the support 302 may also be provided in any other suitable form (e.g., a plate form, a chip form, or a strip form, etc.), depending on the process requirements. In some embodiments, the material of the support 302 is selected to have material properties of high thermal conductivity to ensure good heat dissipation.In some embodiments, the selected material of the support 302 has a permittivity (or dielectric constant (Dk)) that is higher than that of a conventional dielectric material (e.g., mold material with a Dk of about 3.3 or FR-4 with a Dk of about 4.5 to about 4.9). The selected material of the support 302 may have a dissipation factor (or dielectric loss factor (Df)) that is lower than that of the conventional dielectric material (e.g., FR-4 with a Df of about 0.013 to about 0.020). The lower the dissipation factor of the material of the support 302, the lower the signal transmission loss. In some embodiments, the material of the support 302 is selected to have good machinability so that it can withstand the semiconductor structure formed on it.The material of the support 302 can be chosen such that it has a coefficient of thermal expansion (CTE) that largely matches the CTE of the semiconductor chip (e.g. silicon material) in order to prevent the subsequently formed chip package on the support 302 from breaking or detaching under the influence of temperature fluctuations.

[0071] For example, the support material 302 can be aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al₂O₃), silicon nitride (Si₃N₄), boron nitride (BN), zirconium oxide (ZrO₂), or other suitable materials. In some embodiments where an aluminum nitride wafer is used, the support 302 has a permittivity (or dielectric constant (Dk)) value in the range of about 7.7 to about 9.9, and a dielectric loss factor (Df) can be in the range of about 0.003 at 10 GHz to about 0.00045 at 140 GHz. The support 302 can be tailored to provide a desired material property, such as increased thermal conductivity, thereby simplifying heat dissipation. In some embodiments, the thermal conductivity of the support 302 can be in a range of about 60 W / mK to about 120 W / mK.In certain embodiments, the thermal conductivity of the support 302 can be in the range of approximately 80 W / mK to approximately 180 W / mK or approximately 200 W / mK. In other embodiments, the thermal conductivity of the support 302 at room temperature is in the range of approximately 20 W / mK to approximately 150 W / mK. Alternatively, the thermal conductivity of the support 302 at room temperature is in the range of approximately 3 W / mK to approximately 150 W / mK. Other suitable support materials with good dielectric and heat dissipation properties can also be used.

[0072] In Fig. 32 The back of the carrier 302 can be attached to an adhesive tape 304 for ease of handling. It should be understood that the illustrated cross-sectional view of the carrier 302 and the adhesive tape 304 represents only a section of the carrier 302 and the adhesive tape 304.

[0073] In Fig. 33 to Fig. 35 A redistribution structure of 100 is formed ( Fig. 35). In Fig. 33 A seedbed 106 is formed. The seedbed 106 can be formed using processes and materials similar to those mentioned above with reference to the seedbed of Fig. 2 were discussed, are formed. The seed layer 106 lines the openings in the carrier 302 and, in some embodiments, can extend along the adhesive tape 304. In Fig. 34 A conductive layer 108 is formed on the seed layer 106, including in the openings of the carrier 302. The conductive layer 108 can be formed using processes and materials similar to those described above with reference to the conductive layer 108 of Fig. 3 discussed, are formed. A section of the conductive layer 108 forms a through-hole 305 through the support 302. After the conductive layer has formed, the exposed section of the seed layer 106 can be etched away using a suitable wet or dry etching process. As in Fig. As can be seen in Figure 34, an upper surface of the conductive layer 108 may in some embodiments have depressions formed therein corresponding to the openings in the carrier 302.

[0074] In Fig. 35. The remainder of the redistribution structure can be 100 using processes and materials similar to those mentioned above with reference to Fig. 4 to Fig. 17 discussed, are formed. In some embodiments, sections of the insulating layer 122 can have a bottom surface that is in contact with the conductive layer 108, which is lower than an upper surface 112s of the insulating layer 112.

[0075] In Fig. In step 36, the adhesive tape 304 is removed, and the package region 300A is attached to a substrate 308 by means of a die attachment film 306, such as a release layer. The substrate 308 can be a glass substrate, a ceramic substrate, or the like. The substrate 308 can be a wafer such that multiple packages can be formed on the substrate 308 simultaneously. The die attachment film 306 can be made of a polymer-based material that, together with the substrate 308, can be removed from the overlying structures formed in subsequent steps. In some embodiments, the die attachment film 306 is an epoxy-based thermal release material that loses its adhesive properties upon heating, such as a light-to-heat conversion release coating (LTHC release coating).In other embodiments, the die-fixing film 306 can be an ultraviolet adhesive (UV adhesive) that loses its adhesive properties when exposed to UV light. The die-fixing film 306 can be dispensed as a liquid and cured, can be a laminate film laminated onto the carrier 308, or the like. The top surface of the die-fixing film 306 can be flattened and can exhibit a high degree of planarity.

[0076] In some embodiments, such as in Fig. As illustrated in Figure 36, multiple package regions can be mounted on the carrier 308. In some embodiments, the corresponding layers of the multiple package regions can extend continuously towards each other; for example, the carrier 302 of package region 300A extends continuously to the carrier 302 of package region 300B, or in other words, the carrier 302 in package region 300A is the same carrier as the carrier 302 in package region 300B. A similar correspondence is found for each of the layers of package regions 300A and 300B. In other embodiments, package regions 300A and 300B can be separate and can each be mounted on a common carrier 308 by a die mounting film 306. In other words, in such embodiments, the carrier 302 of package region 300A is a different carrier than the carrier 302 of package region 300B.Although two package regions 300A and 300B are illustrated, any suitable number of package regions can be used, including just one package region.

[0077] In Fig. In step 37, the carrier 308 was turned over, and each of the conductive vias 312 (left side in package region 300B), the conductive traces 318 (right side in package region 300A), or a combination of both, could be formed on the now upper side of the carrier 302. If the openings in the carrier 302 (see Fig. 31) If the conductors have not traversed the entire thickness of the carrier 302, new openings can be formed in the now upper side of the carrier 302 to expose the via 305 of the conductive layer 108 and its associated seed layer 106. The small illustration in package region 300A and the small illustration in package region 300B illustrate that a via section 318v of the conductive conductors 318 and / or a bottom via section 312v of the conductive vias 312 can extend downwards through a section of the carrier 302. In such embodiments, as illustrated in the small illustrations, the resulting conductors through the carrier 302 can have an hourglass shape.

[0078] The conductive vias 312 can be formed by any suitable process, such as electroplating, electroless plating, and the like. In some embodiments, a separate seed layer (not shown) can first be deposited where the conductive vias 312 are created, while in other embodiments, the conductive vias 312 can use the seed layer 106 as a seed layer, thereby reducing the processing complexity. The conductive traces 318 can first be formed by depositing a seed layer 316, then using a mask to cover sections of the seed layer where the structure is removed, and then using any suitable deposition process, such as electroplating, electroless plating, CVD, PVD, and the like, or combinations thereof.The mask is then removed and the exposed sections of seed layer 316 are etched away. The formation of seed layer 316 and conductive lines 318 can utilize processes and materials similar to those discussed above with reference to seed layer 106 and conductive layer 108.

[0079] Fig. Figure 38 illustrates a cross-sectional view of an integrated circuit die 350 in accordance with some embodiments. The integrated circuit die 350 is packed in the following machining process to form an integrated circuit package. The integrated circuit die 350 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, etc.), a power management die (e.g., an integrated power management circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a MEMS controller (e.g.,an application-specific integrated circuit (ASIC), a signal processing die (e.g. a digital signal processing die (DSP die)), a front-end die (e.g. an analog front-end die (AFE die)), the like, or combinations thereof.

[0080] The integrated circuit die 350 can be formed on a wafer, which may contain different component regions that are subsequently separated to form multiple integrated circuit dies. The integrated circuit die 350 can be processed according to applicable fabrication processes to form integrated circuits. For example, the integrated circuit die 350 has a semiconductor substrate 352, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 352 may also include other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such asMultilayer or gradient substrates can also be used. The semiconductor substrate 352 has an active surface (e.g., the surface that is in ). Fig. 38 points upwards), which is occasionally called a front face, and an inactive surface (e.g., the surface that is in Fig. 38 points downwards), which is occasionally called a reverse side.

[0081] Components 354 (represented by a transistor) can be formed on the front surface of the semiconductor substrate 352. The components 354 can be active components (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 356 is formed over the front surface of the semiconductor substrate 352. The ILD 356 surrounds the components 354 and can cover them. The ILD 356 can have one or more dielectric layers made of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0082] For electrical and physical coupling of the components 354, conductive connectors 358 extend through the ILD 356. For example, if the components 354 are transistors, the conductive connectors 358 can couple the gates and source / drain regions of the transistors. The conductive connectors 358 can be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure 360 ​​is located above the ILD 356 and the conductive connectors 358. The interconnect structure 360 ​​connects the components 354 to form an integrated circuit. The interconnect structure 360 ​​can be formed, for example, by metallization structures in dielectric layers on the ILD 356. The metallization structures have metal conductors and vias formed in one or more low k-value dielectric layers.The metallization structures of the interconnect structure 360 ​​are electrically coupled to the components 354 by the conductive connectors 358.

[0083] The integrated circuit die 350 further comprises pads 362, such as aluminum pads, with which external connections are established. The pads 362 are located on the active side of the integrated circuit die 350, such as in and / or on the interconnect structure 360. One or more passivation films 364 are located on the integrated circuit die 350, such as on sections of the interconnect structure 360 ​​and the pads 362. Openings extend through the passivation films 364 to the pads 362. Die connectors 366, such as conductive pillars (for example, formed from a metal such as copper), extend through the openings in the passivation films 364 and are physically and electrically coupled to corresponding pads 362. The die connectors 366 can be formed, for example, by plating or the like. The die connectors 366 electrically couple the corresponding integrated circuits of the integrated circuit die 350.

[0084] Optionally, solder pads (e.g., solder balls or solder bumps) can be placed on pads 362. These solder pads can be used to perform chip verification tests (CP tests) on the 350 integrated circuit die. CP tests are performed to determine whether the 350 integrated circuit die is a known good die (KGD). Only 350 integrated circuit dies that are KGDs are then processed and packaged, while dies that fail the CP tests are not packaged. After testing, the solder pads can be removed in subsequent processing steps.

[0085] A dielectric layer 368 may (or may not) be located on the active side of the integrated circuit die 350, such as on the passivation films 364 and the die connectors 366. The dielectric layer 368 laterally encapsulates the die connectors 366 and is laterally adjacent to the integrated circuit die 350. Initially, the dielectric layer 368 may cover the die connectors 366 such that its uppermost surface is located above the uppermost surfaces of the die connectors 366. In some embodiments where solder regions are arranged on the die connectors 366, the dielectric layer 368 may also cover the solder regions. Alternatively, the solder regions may be removed before the dielectric layer 368 forms.

[0086] The dielectric layer 368 can be a polymer, such as PBO, polyimide, BCB, or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; or a combination thereof. The dielectric layer 368 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors 366 are exposed by the dielectric layer 368 during the formation of the integrated circuit die 350. In other embodiments, the die connectors 366 remain covered and are exposed during a subsequent packaging process for the integrated circuit die 350. Exposing the die connectors 366 can remove any solder regions that may be present on the die connectors 366.

[0087] In some embodiments, the integrated circuit die 350 is a stacked device comprising multiple semiconductor substrates 352. For example, the integrated circuit die 350 may be a memory device, such as a hybrid memory cube module (HMC module), a high-bandwidth memory module (HBM module), or the like, comprising multiple memory dies. In such embodiments, the integrated circuit die 350 comprises multiple semiconductor substrates 352 interconnected by substrate through-substrate vias (TSVs). Each of the semiconductor substrates 352 may (or may not) have an interconnect structure 360.

[0088] In Fig. 39 Integrated circuit dies 350, such as the integrated circuit dies 350A, are bonded together by an adhesive (see, for example, the adhesive 372 from Fig. 45) attached to carrier 308. A desired type and quantity of integrated circuit die 350A is attached to each of the package regions 300A and 300B. The integrated circuit die 350A can be any of the above with reference to Fig. The 38 discussed candidate die types include, for example, a MEMS device or a MEMS controller, such as an ASIC device. Additional 350 / 350A integrated circuit dies can be placed in either of the 300A and 300B package regions and can have the same or different functionalities as the illustrated 350A integrated circuit die. Where multiple 350A integrated circuit dies are used in each package region, they can be formed in processes of the same technology node or in processes of different technology nodes. For example, a first 350A integrated circuit die can belong to a more advanced process node than a second 350 / 350A integrated circuit die. Where multiple 350A integrated circuit dies are used in each package region, they can have different sizes (e.g.,The conductive vias 312 and / or conductive traces 318 in package region 300A and package region 300B may have different heights and / or surface areas, or they may be the same size (e.g., same heights and / or surface areas). The space available for the conductive vias 312 and / or conductive traces 318 in package region 300A and package region 300B may be limited, especially if the integrated circuit dies 350A have space-intensive components, such as SoCs. The use of the backside redistribution structure 100 allows for an improved interconnect arrangement when package region 300A and package region 300B have limited space available for the conductive vias 312 and / or conductive traces 318.

[0089] The adhesive for the 350A integrated circuit dies is located on the back side of the 350A integrated circuit dies and secures them to the 308 substrate. The adhesive can be any suitable adhesive, an epoxy, a die attach film (DAF), or the like. The adhesive can be applied to the back side of the 350A integrated circuit dies. For example, the adhesive can be applied to the back side of the 350A integrated circuit dies before singulation to separate them.

[0090] In Fig. 40. An encapsulation material 320 is formed on and around the various components. After formation, the encapsulation material 320 encapsulates the conductive vias 312 and / or the conductive lines 318 and the integrated circuit dies 350A. The encapsulation material 320 can be a molding compound, an epoxy, or the like. The encapsulation material 320 can be applied by compression molding, injection molding, or the like and can be formed over the carrier 302 such that the conductive vias 312, the conductive lines 318, and / or the integrated circuit dies 350A are buried or covered. The encapsulation material 320 is also formed in gap regions between the integrated circuit dies 350A. The encapsulation material 320 can be applied in liquid or semi-liquid form and then subsequently cured.

[0091] In Fig. 41 A planarization process is carried out on the encapsulation material 320 to expose the conductive vias 312 and / or the conductive traces 318 and the die connectors 366 (see Fig. 38) of the integrated circuit die 350A. The planarization process can also be applied to the material of the conductive vias 312 and / or the conductive traces 318, the dielectric layer 368 (see Fig. 38) and / or the die connector 366 (see Fig. 38) remove until the die connectors 366 and the conductive vias 312 and / or the conductive traces 318 are exposed. The top surfaces of the conductive vias 312 and / or the conductive traces 318, the die connectors 366, the dielectric layer 368, and the encapsulation material 320 are substantially coplanar after the planarization process, within process variations. The planarization process may be, for example, chemical-mechanical polishing (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example, if the conductive vias 312 and / or the conductive traces 318 and / or the die connectors 366 are already exposed.

[0092] In Fig. 42 A redistribution structure 322 is formed over the encapsulation material 320. The redistribution structure 322 can be a fan-out redistribution structure. In some embodiments, the redistribution structure 322 can be formed using processes and materials similar to those discussed above with reference to redistribution structures 100 and / or 200. In other embodiments, the redistribution structure 322 can be formed using other processes and materials.

[0093] For example, the dielectric layer 324 can be applied to the encapsulation material 320, the conductive vias 312 and / or the conductive traces 318 and the die connectors 366 (see Fig. 38) are deposited. In some embodiments, the dielectric layer 324 is formed from a photosensitive material, such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer 324 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 324 is then patterned. The patterning creates openings that expose sections of the conductive vias 312 and / or the conductive traces 318 and the die connectors 366. The patterning can be performed by an acceptable process, such as exposing and developing the dielectric layer 324 with light if the dielectric layer 324 is a photosensitive material, or by etching, for example, using anisotropic etching.

[0094] The metallization structure 326 can then be formed. The metallization structure 326 has conductive elements that extend along the main surface of the dielectric layer 324 and through the dielectric layer 324 to couple it physically and electrically to the conductive vias 312 and / or the conductive traces 318 and the integrated circuit dies 350A. As an example of forming the metallization structure 326, a seed layer is formed over the dielectric layer 324 and in the openings extending through the dielectric layer 324. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising several sublayers formed from different materials.In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by rotational coating or the like and can be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 326. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can contain a metal, such as copper, titanium, tungsten, aluminum, or the like.The combination of the conductive material and underlying sections of the seed layer forms the metallization structure 326. The photoresist and sections of the seed layer where the conductive material is not present are removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed sections of the seed layer are removed, for example, by using an acceptable etching process, such as wet or dry etching.

[0095] The dielectric layer 328 is then deposited onto the metallization structure 326 and the dielectric layer 324. The dielectric layer 328 can be formed in a similar manner to the dielectric layer 324 and can be made of a similar material. The metallization structure 330 is then formed. The metallization structure 330 has sections on the main surface of the dielectric layer 328 and extending along it. The metallization structure 330 further has sections that extend through the dielectric layer 328 to physically and electrically couple the metallization structure 326. The metallization structure 330 can be formed in a similar manner and made of a similar material to the metallization structure 326.In some embodiments, the metallization structure 330 has a different size than the metallization structure 326. For example, the conductive traces and / or vias of the metallization structure 330 may be wider or thicker than the conductive traces and / or vias of the metallization structure 326. Furthermore, the metallization structure 330 may be configured with a larger spacing than the metallization structure 326.

[0096] The process of forming the dielectric layers and metallization structures is repeated as often as desired to form the remaining layers of the redistribution structure. As in Fig. Figure 42 illustrates these features, including the formation of dielectric layer 332 and dielectric layer 336, as well as the metallization structure 334. In the illustrated embodiment, the metallization structure 334 is the uppermost metallization structure of the redistribution structure 322. All intermediate metallization structures of the redistribution structure 322 (e.g., metallization structures 326 and 330) are arranged between the metallization structure 334 and the integrated circuit dies 350A. In some embodiments, the metallization structure 334 has a different size than the metallization structures 326 and 330. For example, the conductive traces and / or vias of the metallization structure 334 may be wider or thicker than the conductive traces and / or vias of the metallization structures 326 and 330.Furthermore, metallization structure 334 can be formed with a greater distance than metallization structure 330. Dielectric layer 336 is the uppermost dielectric layer of redistribution structure 322. All metallization structures of redistribution structure 322 (e.g., metallization structures 326, 330, and 334) are arranged between dielectric layer 336 and the integrated circuit dies 350A. Additionally, all dielectric intermediate layers of redistribution structure 322 (e.g., dielectric layers 324, 328, and 332) are arranged between dielectric layer 336 and the integrated circuit dies 350A.

[0097] In Fig. Figure 43 illustrates an embodiment which forms the conductive connectors 340 attached to the redistribution structure 322. In some embodiments, under-bump metallurgies (UBMs) 338 are formed for external connection to the fan-out redistribution structure 322. The UBMs 338 have bump sections on and extending along the main surface of the dielectric layer 336 and have vias extending through the dielectric layer 336 to physically and electrically couple the metallization structure 334. As a result, the UBMs 338 are electrically coupled to the conductive vias 312 and / or the conductive lines 318 and the integrated circuit dies 350A. The UBMs 338 can be formed from the same material as the metallization structure 326.In some embodiments, the UBMs 338 have a different size than the metallization structures 326, 330 and 334.

[0098] Next, conductive connectors 340 are formed on the UBMs 338. The conductive connectors 340 can be connectors with a ball grid array (BGA), solder balls, metal pillars, controlled collapse chip connection bumps (C4 bumps), micro-bumps, bumps formed using the ENEPIG (electroless nickel-electroless palladium immersion gold technique), or the like. The conductive connectors 340 can have a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 340 are formed by initially forming a layer of solder by evaporation, electroplating, printing, solder feeding, ball placement, solder paste, or the like.After a layer of solder has been formed on the structure, melting can be performed to shape the material into the desired bump shapes. In another embodiment, the conductive connectors have 340 metal pillars (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer can contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by a plating process.

[0099] Fig. 44 to Fig. Figure 53 illustrates the addition of another embedded integrated circuit die above the redistribution structure 322. In some embodiments, instead of forming the conductive connectors 340, the vias 342 are formed in contact with the uppermost metallization structure, e.g., the metallization structure 334, of the redistribution structure 322. Fig. 44 The dielectric layer 336 is patterned to form openings that expose sections of the metallization structure 334. The patterning can be formed by an acceptable process, such as by exposure of the dielectric layer 336 if the dielectric layer 336 is a photosensitive material, or by etching, for example, using anisotropic etching. If the dielectric layer 336 is a photosensitive material, it can be developed after exposure. Vias 342 are formed in the openings in the dielectric layer 336 and extend away from the support 302. The vias 342 can be formed using materials and processes similar to those used for the conductive vias 312 discussed above.

[0100] In Fig. 45 Integrated circuit dies 350, such as the integrated circuit dies 350B, are adhered to the redistribution structure 322 by an adhesive 372. A desired type and quantity of the integrated circuit dies 350B is placed in each of the package regions 300A and 300B. The integrated circuit dies 350B can be any of the above with reference to the integrated circuit dies 350. Fig. The 38 discussed candidate die types include, for example, a MEMS device, an analog device, a high-frequency (RF) device, and so on. The adhesive 372 for the integrated circuit dies 350B is located on the back sides of the integrated circuit dies 350B and secures the integrated circuit dies 350B to the redistribution structure 322. The adhesive 372 can be described similarly to the one described above with reference to Fig. The adhesive was discussed in detail in section 39.

[0101] In Fig. 46. ​​An encapsulation material 374 is formed on and around the various components. After formation, the encapsulation material 374 encapsulates the vias 342 and the integrated circuit dies 350B. The encapsulation material 374 can be formed by processes and materials such as those described above with reference to the encapsulation material 320. Fig. 40 were discussed.

[0102] In Fig. 47 A planarization process is carried out on the encapsulation material 374 to expose the vias 342 and the die connectors 366 of the integrated circuit dies 350B. The planarization process can also be carried out on the material of the vias 342, the dielectric layer 368 (see Fig. 38) and / or the die connector 366 (see Fig. 38) remove until the die connectors 366 and the vias 342 are exposed. The top surfaces of the vias 342, the die connectors 366, the dielectric layer 368, and the encapsulation material 374 are essentially coplanar after the planarization process, within process variations. The planarization process can be, for example, chemical-mechanical polishing (CMP), grinding, or the like. In some embodiments, planarization can be omitted, for example, if the vias 342 and / or the die connectors 366 are already exposed.

[0103] In Fig. 48 An interconnect structure 382 is formed over the encapsulation material 374, the vias 342, and the integrated circuit dies 350B. A dielectric layer 384 of the interconnect structure 382 can be deposited on the encapsulation material 374, the vias 342, and the integrated circuit dies 350B. In some embodiments, the dielectric layer 384 is formed from a photosensitive material, such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer 384 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 384 is then patterned. The patterning creates openings that expose sections of the vias 342 and the die connectors 366. The patterning can be performed by an acceptable process, such as…by exposing and developing the dielectric layer 384, if the dielectric layer 384 is a photosensitive material, or by etching, for example using anisotropic etching.

[0104] Next, a metallization structure 386 is formed over the dielectric layer 384 and in the openings through the dielectric layer 384 and in contact with the vias 342. The metallization structure 386 can be formed using any suitable processes and materials. In some embodiments, the metallization structure 386 can be formed in a manner similar to that described above with reference to the metallization structure 326 of Fig. 42 discussed. The interconnect structure 382 can be formed from any number of dielectric layers and metallization structures. An upper dielectric layer 388 is formed over the uppermost metallization structure, i.e., the metallization structure 386, as in Fig. 48 illustrated.

[0105] In Fig. 49 An opening 390 can be formed through the dielectric layers of the interconnect structure 382 to expose an upper section of the integrated circuit dies 350B. If the integrated circuit dies 350B are, for example, MEMS devices, sensor areas of the MEMS devices can be exposed. The opening 390 can be formed by depositing a mask over the interconnect structure 382 and structuring the mask to protect the areas of the interconnect structure 382 that are to be preserved, thereby exposing areas of the interconnect structure 382 that are to be removed. Next, any suitable removal process, such as dry etching or wet etching, can be used to remove the exposed sections of the interconnect structure 382. Each layer of the dielectric layers of the interconnect structure, such asThe dielectric layer 388 and the dielectric layer 384 can be removed one after the other, thereby deepening the opening 390 until the integrated circuit dies 350B are exposed through the opening 390.

[0106] In Fig. In section 50, package regions 300A and 300B are attached to a frame 392. In some embodiments, an adhesive can be used between the frame 392 and the interconnect structure 382. In other embodiments, the frame 392 can be attached by suction or electrostatic charging. Fig. Figure 50 also illustrates a carrier substrate debonding process for separating (or “unbonding”) the carrier 308 from the redistribution structure 100. In some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the die-attachment film 306, so that the die-attachment film 306 decomposes under the heat of the light and the carrier 308 can be removed. The structure can then be flipped over in some embodiments.

[0107] In Fig. 51 In some embodiments, conductive connectors 396 are formed for coupling to the redistribution structure 100. Using an acceptable photolithography technique, for example by depositing a photostructurable mask over the redistribution structure and structuring the photostructurable mask by exposure, development and curing of the photostructurable mask, openings can be formed through the upper insulating layer (i.e. the insulating layer 152) of the redistribution structure 100, and these openings in the mask can then be used for etching the upper insulating layer of the redistribution structure 100 to expose the conductive layer 148.

[0108] For an external connection to the front of the redistribution structure 100, optional UBMs 394 can be formed in the openings. The UBMs 394 can have bump sections on and extending along the main surface of the insulating layer 152 of the redistribution structure 100, and can have vias extending through the insulating layer 152 to physically and electrically couple the conductive layer 148. As a result, the UBMs are electrically coupled through the various conductive layers 148 to the conductive vias 312 and / or the conductive lines 318, the integrated circuit dies 350A, and the integrated circuit dies 350B via the redistribution structure 322 and the interconnect structure 382. The UBMs 394 can be formed from the same material as the seed layer 146 and / or the conductive layer 148 of the redistribution structure 100.The UBMs 394 can have a different size (e.g. thickness) than the metallization structures corresponding to the conductive layers 108, 118, 128, 138, 148 and so on.

[0109] The conductive connectors 396 are formed in the openings and on the UBMs 394 (if used). The conductive connectors 396 can be manufactured using processes and materials similar to the conductive connector 160. Fig. 19 or similar to the conductive connector 340 from Fig. 43 will be trained.

[0110] In Fig. 52 A singulation process 398 can separate one package from another, so that one package is formed from the structures in package region 300A and another package is formed from the structures in package region 300B. The singulation process is carried out by sawing or laser cutting along score line regions, e.g., between package region 300A and package region 300B. Sawing separates package region 300A from package region 300B.

[0111] In Fig. 53 The resulting, isolated component stack 300 originates from either package region 300A or package region 300B. Because the component stack 300 has the redistribution structure 100, including the filler-free, high-shrinkage insulating layer 112 and the filler-free, high-shrinkage insulating layers 122, 132, 142, and 152, the component stack 300 can be fabricated with fewer planarization processes and in smaller thicknesses. It should be understood that the thickness of the redistribution structure 100, as shown in Fig. Figure 53 illustrates the figure, which is not to scale and is instead exaggerated to show the details. For example, the thickness of the resulting redistribution structure 100 may be less than 50% of the thickness of the redistribution structure 322, such as between 20% and 50%, with the same number of metallization layers.

[0112] Fig. 54 to Fig. Figure 59 illustrates cross-sectional views of various intermediate stages in the formation of a semiconductor device, such as an integrated fan-out package (InFO package), for example, for use with a MEMS device. Package regions 400A and 400B can be compared with package regions 300A and 300B discussed above. Fig. Figure 54 illustrates a redistribution structure 200 (see Fig. 29), which is formed over a carrier 402 attached to an adhesive tape 404. The carrier 402 and the adhesive tape 404 can be similar to those discussed above with reference to the carrier 301 and the adhesive tape 304. The seed layer 206 of the redistribution structure and the conductive layer 208 of the redistribution structure 200 can be similar to those discussed above with reference to the seed layer 106 and the conductive layer 108 of Fig. 34 were discussed. In particular, with regard to the seed layer 206 and the conductive layer 208, each of these has a section that extends downwards into the support 402 and, in some embodiments, extends through the support 402. An upper surface of the conductive layer 208 may have depressions which are aligned with the openings in the support 402, similar to those described above with reference to the conductive layer 108 of Fig. 34 and Fig. 35 were discussed.

[0113] In Fig. In step 55, the adhesive tape 404 is removed, and the package region 300A is attached to the carrier 408 by a die-fixing film 406. The carrier 408 and the die-fixing film 406 can be similar to those discussed above with reference to the carrier 308 and the die-fixing film 306. As discussed above, the upper surface of the redistribution structure 200 is corrugated. The upper surface of the die-fixing film 406 can have a high degree of planarity. Thus, the die-fixing film 406 has a varying thickness across the surface of the redistribution structure 200.

[0114] Fig. Figure 56 illustrates an enlarged section of the in Fig. The dashed boxes shown in Figure 55 are used to better illustrate the varying thickness of the die-attachment film 406. The distance d31 represents the fact that the die-attachment film 406 can extend into any depressions in the surface of the uppermost insulating layer (e.g., the insulating layer 232) of the redistribution structure 200. The distance d32 represents a thinnest section of the die-attachment film 406. The distance d31 can also represent a thickest section of the die-attachment film 406. In some embodiments, at the thinnest section of the die-attachment film 406, the distance d32 can be as small as 10% to 25% of the thickest section of the die-attachment film 406.The die fixing film 406 can be made thicker so that the difference between the distances d31 and d32 is minimal, however, providing the ability to have a relatively smaller distance d32 of 10% to 25% of the distance d31 allows greater flexibility in the waviness of the insulating layer 232 of the redistribution structure 200.

[0115] In Fig. In step 57, the support 408 is inverted and various structures are formed above the support 402. The same reference numbers indicate the same elements as those mentioned above with reference to... Fig. 31 to Fig. 53 were discussed. Package regions 400A and 400B are attached to a frame 392, and carrier 408 is removed using processes similar to those discussed above with reference to carrier 308.

[0116] In Fig. 58 Optional UBMs 494 and conductive connectors 496 are formed through the uppermost insulating layer of the redistribution structure 200 to make contact with the upper conductive layer 228. The UBMs 494 and the conductive connectors 496 can be formed using processes and materials similar to those discussed above with reference to the UBMs 394 and the conductive connectors 396. The package regions can then be singulated using a singulation process 398, for example, to separate package region 400A from package region 400B.

[0117] In Fig. 59 The resulting, isolated component stack 400 originates from either package region 400A or package region 400B. Because the component stack 400 has the redistribution structure 200, including the filler-free, high-shrinkage insulating layers 212, 222, and 232 (based on the design having more or fewer insulating layers), the component stack 400 can be fabricated with fewer planarization processes and in smaller thicknesses. It should be understood that the thickness of the redistribution structure 100, as in Fig. Figure 58 illustrates this, but is not to scale and is instead exaggerated to show the details. For example, the thickness of the resulting redistribution structure 200 may be less than 50% of the thickness of the redistribution structure 322, such as between 20% and 50%, with the same number of metallization layers.

[0118] Fig. 60 and Fig. Figure 61 illustrates additional embodiments that utilize redistribution structure 100 and redistribution structure 200 accordingly in a Package 500 and a Package 600. The primary difference between the embodiments in Fig. 60 and Fig. 61 is that the embodiment of Fig. 60 uses a redistribution structure which was designed according to the redistribution structure 100 discussed above, while the embodiment of Fig. 61 uses a redistribution structure which was formed according to the redistribution structure 200 discussed above. The remaining elements of Fig. 60 and Fig. 61 will be discussed together.

[0119] Each of the layers 525 of packages 500 and 600 can be individual wafer sections 505 of a wafer. In some embodiments, packages 500 and 600 can be formed by stacking wafers in a wafer-on-wafer process to create a wafer stack. Each of the wafer sections 505 can have vias 510 and bond pads 515. Devices such as transistors, resistors, capacitors, and so on can be formed in the wafers. While four wafer sections 505 are illustrated, it should be understood that more or fewer wafer sections can also be used. Next, the redistribution structures 100 and 200, respectively, are formed. Then the wafer stacks can be turned over, and an insulating layer 530 can be formed on a first side of the packages 500 and 600, and conductive connectors 535 can be formed through the insulating layer 530.The conductive connectors 535 can be formed using materials and processes similar to those used in forming the conductive connectors 160 or 396 described above.

[0120] In other embodiments, the layers 525 can also represent other structures, such as encapsulated dies, interposers, semiconductor substrates, the like, and combinations thereof.

[0121] After the conductive connectors 535 have been formed, the packages 500 and 600 can then be separated from other similar packages in the wafer stack. Each separated package 500 or 600 can then be attached to a package substrate 550 using the conductive connectors 535. The package substrate 550 has a substrate core 555 and bond pads 560 over the substrate core 555. The substrate core 555 can be made of a semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like can also be used. Furthermore, the substrate core 555 can be an SOI substrate. In general, an SOI substrate has a layer of a semiconductor material, such as...Epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 555 is based on an insulating core, such as a glass fiber-reinforced resin core. An exemplary core material is glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine resin (BT resin) or, alternatively, other PCB materials or films. Build-up films, such as ABF, or other laminates can also be used for the substrate core 555.

[0122] The 555 substrate core can incorporate active and passive components (not shown). A wide variety of components, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to create the structural and functional design requirements for the component stack. The components can be formed using any suitable methods.

[0123] The substrate core 555 can also include metallization layers and vias (not shown), wherein the bond pads 560 are physically and / or electrically coupled to the metallization layers and vias. The metallization layers can be formed over the active and passive components and are designed to connect the various components to form functional circuits. The metallization layers can be formed from alternating layers of dielectric material (e.g., dielectric material with a low k-value) and conductive material (e.g., copper), with vias connecting the conductive material layers, and can be formed by any suitable process (such as deposition, damascene, dual-damascene, or the like). In some embodiments, the substrate core 555 is essentially free of active and passive components.

[0124] In some embodiments, the conductive connectors 535 are melted to attach the packages 500 or 600 to the bond pads 560. The conductive connectors 535 couple the package substrate 550, including the metallization layers in the substrate core 555, electrically and / or physically to the packages 500 or 600. In some embodiments, a solder mask 565 can be formed on the substrate core 555. The conductive connectors 535 can be arranged in openings in the solder mask 565 so that they are electrically and mechanically coupled to the bond pads 560. The solder mask 565 can be used to protect areas of the package substrate 550 from external damage.

[0125] The conductive connectors 535 may have an epoxy flow formed on them (not shown) before they are melted, with at least a portion of the epoxy flow remaining after the packages 500 or 600 have been attached to the package substrate 550. This remaining epoxy portion can serve as an underfill to reduce stress and protect the connections resulting from the melting of the conductive connectors 535. In some embodiments, an underfill 540 may be formed between the packages 500 or 600 and the package substrate 550, surrounding the conductive connectors 535. The underfill 540 may be formed by a capillary flow process after the packages 500 or 600 have been attached, or it may be formed by a suitable deposition process before the packages 500 or 600 are attached.

[0126] In some embodiments, passive components (e.g., surface-mount devices (SMDs), not shown) can also be attached to the packages 500 or 600 (e.g., to the bond pads 515) or to the package substrate 550 (e.g., to the bond pads 560). For example, the passive components can be bonded to the same surface of the packages 500 or 600 or the package substrate 550 as the conductive connectors 535. The passive components can be attached to the packages 500 or 600 before the packages 500 or 600 are attached to the package substrate 550, or they can be attached to the package substrate 550 before or after the packages 500 or 600 are attached to the package substrate 550.

[0127] Packages 500 or 600 can also be implemented in other component stacks. For example, a PoP structure is shown and configured to accommodate an additional package component (e.g., UBMs 155 and 255). However, packages 500 or 600 can also be implemented in a package with a flip-chip sphere grid array (FCBGA package). In such embodiments, packages 500 or 600 are attached to a substrate, such as the package substrate 550, but UBMs 155 and 255 can be omitted. Instead, a cover or heat spreader can be attached to packages 500 or 600.

[0128] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of the 3D packaging or 3DIC devices. These test structures may, for example, include test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D packaging or 3DIC, the use of probes and / or test cards, and the like. The verification tests may be performed on intermediate structures as well as on the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test procedures that include intermediate verification of undoubtedly functioning dies to increase yield and reduce costs.

[0129] The embodiments offer several advantages. They utilize a redistribution structure that does not require a planarization process after the formation of an insulating layer, thus simplifying the fabrication process. Furthermore, the insulating layers between the metallization structures can be made thin because no planarization occurs. The insulating layers of the redistribution structure can also be fabricated from filler-free materials with shrinkage rates that result in flatter insulating layers even without a planarization process. The resulting corrugated insulating layers are less wavy than those produced using typical insulating materials.The redistribution structure can also feature a first metallization structure that is thicker than the other metallization structures in other layers, thereby providing better conductivity and limiting signal attenuation by the first metallization structure. Due to the thinness of the insulating layers separating each of the metallization structures, the overlying metallization structure extends along the sidewalls of openings in the insulating layers and along an exposed portion of the underlying metallization structure.

[0130] One embodiment is a redistribution structure coupled to a conductive element of a substrate. The redistribution structure may have a first conductive layer and a first insulating layer above the first conductive layer. The first insulating layer may comprise a first filler-free insulating material. A second conductive layer may be located above the first insulating layer, the second conductive layer being coupled to the first conductive layer, and a second insulating layer may be located above the second conductive layer, and the second insulating layer may comprise a second filler-free insulating material. The device also includes a conductive connector that is electrically coupled to the redistribution structure. In one embodiment, the first filler-free insulating material differs from the second filler-free insulating material.In one embodiment, the upper surface of the second insulating layer is corrugated. In another embodiment, the difference between an average peak and an average trough of the upper surface is between 3 µm and 5 µm. In another embodiment, the first conductive layer is three to five times thicker than the second conductive layer. In another embodiment, a surface of the second insulating layer is free of polishing marks. In another embodiment, the second conductive layer may have a seed layer and a metal layer over the seed layer, the seed layer conforming to a recess in the first insulating layer, the recess exposing a portion of the first conductive layer. In another embodiment, the substrate is a ceramic support, and the substrate is positioned between the redistribution structure and the encapsulated die.In one embodiment, the component may have the following: a metallization layer arranged in the same layer as the encapsulated die, wherein the thickness of the metallization layer is the same as the thickness of the encapsulated die.

[0131] Another embodiment includes a first redistribution structure, which may comprise: a first metallization structure having a first thickness, a first insulating layer adjacent to the first metallization structure, and a second metallization structure adjacent to the first insulating layer. The first insulating layer has a second thickness between the first metallization structure and the second metallization structure, the second thickness being less than the first thickness. The device also includes an encapsulated die positioned above the first redistribution structure. In one embodiment, the device may include a ceramic support positioned between the first redistribution structure and the encapsulated die.In one embodiment, the encapsulated die comprises a microelectromechanical system (MEMS) device. In another embodiment, the second metallization structure has a third thickness, wherein the third thickness is less than the first thickness, and the first metallization structure is positioned closer to the encapsulated die than the second metallization structure. In another embodiment, the second metallization structure may comprise a seed layer and a conductive layer, wherein the seed layer conformally coats the sidewalls of an opening through the first insulating layer. In another embodiment, an upper surface of the first insulating layer is corrugated.

[0132] Another embodiment is a method comprising the deposition of a first metallization structure on a substrate. The method also comprises the deposition of a first insulating layer over the first metallization structure, wherein the first insulating layer is filler-free. The method also comprises curing the first insulating layer, causing it to shrink by less than 5%. The method also comprises forming a first opening through the first insulating layer to expose a portion of the first metallization structure. The method also comprises, without flattening the first insulating layer, the deposition of a second metallization structure over the first insulating layer and within the first opening.The process also includes depositing a second insulating layer over the second metallization structure, wherein the second insulating layer is filler-free. In one embodiment, the first insulating layer shrinks by between 1% and 5%. In another embodiment, the first insulating layer has a different shrinkage rate than the second insulating layer. In one embodiment, the metallization structure is deposited over a ceramic support. In another embodiment, the ceramic support is inverted. In yet another embodiment, an integrated circuit die is attached to the ceramic support, and an encapsulation material is deposited, which laterally surrounds the integrated circuit die.

[0133] The foregoing outlines features of several embodiments so that the person skilled in the art may better understand the aspects of the present disclosure. The person skilled in the art should understand that the present disclosure can readily be used as a basis for the development or modification of other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

[1] Device comprising the following: a redistribution structure coupled to a conductive element of a substrate, wherein the redistribution structure has the following: a first conductive layer, a first insulating layer over the first conductive layer, wherein the first insulating layer comprises a first filler-free insulating material, a second conductive layer over the first insulating layer, wherein the second conductive layer is coupled to the first conductive layer, and a second insulating layer over the second conductive layer, wherein the second insulating layer comprises a second filler-free insulating material; and a conductive connector that is electrically coupled to the redistribution structure. [2] Device according to claim 1, wherein the first filler-free insulating material differs from the second filler-free insulating material. [3] Device according to claim 1 or 2, wherein an upper surface of the second insulating layer is wave-shaped. [4] Device according to claim 3, wherein the difference between an average peak of the upper surface and an average valley of the upper surface is between 3 µm and 5 µm. [5] Device according to one of the preceding claims, wherein the first conductive layer is three to five times thicker than the second conductive layer. [6] Device according to one of the preceding claims, wherein a surface of the second insulating layer is free of polishing marks. [7] Device according to one of the preceding claims, wherein the second conductive layer comprises a seed layer and a metal layer above the seed layer, wherein the seed layer conforms to the shape of a recess in the first insulating layer, wherein the recess exposes a section of the first conductive layer. [8] Device according to any of the preceding claims, further comprising: an encapsulated die, wherein the substrate is a support and the substrate is arranged between the redistribution structure and the encapsulated die. [9] Device according to claim 8, which further comprises: a metallization layer arranged in the same layer as the encapsulated die, wherein the thickness of the metallization layer is the same as the thickness of the encapsulated die. [10] Device comprising the following: a first redistribution structure, wherein the first redistribution structure has the following features: a first metallization structure, wherein the first metallization structure has a first thickness, a first insulating layer adjacent to the first metallization structure, and a second metallization structure adjacent to the first insulating layer, wherein the first insulating layer has a second thickness between the first metallization structure and the second metallization structure, the second thickness being less than the first thickness; and an encapsulated die that is positioned above the first redistribution structure. [11] Device according to claim 10, which further comprises: a carrier that is positioned between the first redistribution structure and the encapsulated die. [12] Device according to claim 10 or 11, wherein the encapsulated die comprises a microelectromechanical system device (MEMS device). [13] Device according to any one of claims 10 to 12, wherein the second metallization structure has a third thickness, wherein the third thickness is less than the first thickness, and wherein the first metallization structure is arranged closer to the encapsulated die than the second metallization structure. [14] Device according to one of claims 10 to 13, wherein the second metallization structure comprises a seed layer and a conductive layer, wherein the seed layer conforms to the shape of the side walls of an opening through the first insulating layer. [15] Device according to any one of claims 10 to 14, wherein an upper surface of the first insulating layer is wave-shaped. [16] Procedure which includes the following: Deposition of a first metallization structure on a substrate; Deposition of a first insulating layer over the first metallization structure, wherein the first insulating layer is filler-free; Curing of the first insulating layer, causing the first insulating layer to shrink by less than 5%; Forming an initial opening through the first insulating layer to expose a section of the first metallization structure; without leveling the first insulating layer, depositing a second metallization structure over the first insulating layer and in the first opening; and Deposition of a second insulating layer over the second metallization structure, wherein the second insulating layer is filler-free. [17] Method according to claim 16, wherein the first insulating layer shrinks by between 1% and 5%. [18] Method according to claim 16 or 17, wherein the first insulating layer has a different shrinkage rate than the second insulating layer. [19] Method according to any one of claims 16 to 18, wherein the first metallization structure is deposited over a support. [20] The method of claim 19, which further comprises: Turn the carrier over; Attaching an integrated circuit die to the carrier; and Deposition of an encapsulation material that laterally surrounds the integrated circuit die.