DOUBLE AMAZON STRUCTURE IN THE FORMATION OF SOURCE / DRAIN CONTACTS AND MANUFACTURING PROCESSES

Abstract

Procedure comprehensive: Forming a transistor (76) having a source / drain region (52) and a gate electrode (64); Forming a source / drain contact plug (74) over and in electrical connection with the source / drain area (52); Formation of a first interlayer dielectric (82) over the source / drain contact plug (74); Forming an etch stop layer (88) over the first interlayer dielectric (82); Etching the etch stop layer to form a first via opening (92); Formation of a second interlayer dielectric (102) over the first interlayer dielectric (82); Performing an etching process such that the second interlayer dielectric (102) is etched to form a trench (114), and the first via opening (92) in the etch stop layer (88) is extended into the first interlayer dielectric (82) to expose the source / drain contact plug (74); and Filling the trench (114) and the first via opening (92) in joint processes to form a metal conductor (124) and a via (126), wherein the etch stop layer (88) has a lower sublayer (88A) and an upper sublayer (88B) above the lower sublayer (88A), and the method further comprises: Performing a first etching process to form the first via opening (92) in the upper sublayer (88B), wherein the first etching process is stopped by the lower sublayer (88A); Performing a second etching process to form a second via opening (96) in the upper sublayer (88B), wherein the second etching process is stopped by the lower sublayer (88A); and prior to the etching process, performing a third etching process to extend the first via opening (92) and the second via opening (96) into the lower sublayer (88A), wherein the lower sublayer (88A) contains aluminium oxide, and the upper sublayer (88B) contains silicon oxycarbonitride.

Description

BACKGROUND

[0001] Metal oxide semiconductor devices (MOS devices) are fundamental components of integrated circuits. Current MOS device development involves the formation of substitute gates, which feature high-k-value gate dielectrics and metal gate electrodes overlying the high-k-value gate dielectrics. Substitute gate formation typically involves depositing a high-k-value gate dielectric layer and metal layers overlying the high-k-value gate dielectric layer, followed by chemical-mechanical polishing (CMP) to remove excess portions of the high-k-value gate dielectric layer and the metal layers. The remaining portions of the metal layers form the metal gates. The metal gates can be recessed to create depressions between adjacent gate spacers, followed by the formation of self-aligning hard dielectric masks in the depressions.

[0002] US 2012 / 0249519A1 discloses a semiconductor device and its manufacturing process, which comprises a semiconductor fin and a gate structure arranged over a channel region of the semiconductor fin. The gate structure includes a gate dielectric layer and a gate electrode separated by an air gap.

[0003] US 2014 / 0061941A1 relates to a manufacturing process for producing a semiconductor device using a middle-first dual damascene process. In this process, an etch stop film is patterned after being formed over a first intermediate insulating film. A second intermediate insulating film is formed over the etch stop film and etched to create a through-hole.

[0004] A dual Damascene process is generally described in: Dual Damascene process. In: Wikipedia, The Free Encyclopedia. Revision as of 08 September 2021, 09:03 UTC. URL: https: / / de.wikipedia.org / wiki / Dual-Damascene-Prozess [accessed on 31 October 2024] BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features / elements are not shown to scale. In fact, the dimensions of the various features / elements may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1-6, 7A, 7B and 8-20 represent perspective views and cross-sectional views of intermediate stages in the formation of fin field effect transistors (FinFETs), contact plugs and vias in accordance with some embodiments. Fig. 21 represents a process flow consistent with some embodiments. DETAILED DESCRIPTION

[0006] The invention is defined by the subject matter of the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides numerous different embodiments, or examples, for implementing various features / elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements cannot be arranged in direct contact with each other.Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms of spatial relationships, such as "underlying," "below," "lower," "above," "upper," and the like, may be used herein for a simpler description of the relationship of one element or feature to another element(s) or feature(s) shown in the figures. The terms of spatial relationships are intended to encompass various orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the terms of spatial relationships used herein may be interpreted accordingly.

[0008] Fin field-effect transistors (FinFETs), contact plugs, and vias, as well as the method for forming them, are provided. In accordance with some embodiments, FinFETs are formed which have source / drain regions and gate stacks. Low-level source / drain contact plugs and source / drain silicide regions are formed over the source / drain regions. Gate contact plugs are also formed over and connected to gate stacks. A double-damascus process is performed to form metal traces and vias, with the vias being connected to the lower source / drain contact plugs and serving as upper source / drain contact plugs. The vias in the double-damascus structure also extend into the same interlayer dielectric (ILD) as the gate contact plugs.By forming upper source / drain contact plugs and their overlying metal conductors (hereinafter referred to as M0 metal conductors) as double damascus structures, the interface between them is eliminated and contact resistance values ​​are reduced. Furthermore, copper can be used to replace the tungsten otherwise used, thereby further reducing the resistance.

[0009] Although FinFETs are used in the description of exemplary embodiments, the embodiments of the present application can also be applied to other types of transistors, such as all-around gate transistors (GAA transistors) and planar transistors. The embodiments discussed herein are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure, and adequately trained persons will readily understand modifications that can be made without departing from the intended scope of the various embodiments. The same reference numerals are used in the different views and illustrative embodiments to identify the same elements. Although embodiments of the method may be discussed in a particular order, further embodiments of the method can be carried out in any logical sequence.

[0010] The Fig. Figures 1-6, 7A, 7B, and 8-20 represent cross-sectional and perspective views of intermediate stages in the formation of fin field-effect transistors (FinFETs) in accordance with some embodiments. The processes shown in these figures are also found in process flow 200, which is described in Fig. 21 is shown schematically.

[0011] In Fig. A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a ground semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with a p- or n-type dopant) or undoped. The semiconductor substrate 20 can be part of the wafer 10, for example, a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used.In accordance with some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise silicon; germanium; a composite semiconductor comprising carbon-doped silicon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0012] Further referring to Fig. 1, a trough area 22 is formed in the substrate 20. The process in question is in process sequence 200, which is in Fig. Figure 21 is shown as process 202. In accordance with some embodiments, the trough region 22 is an n-trough region formed by implanting an n-impregnation, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. In accordance with other embodiments of the present disclosure, the trough region 22 is a p-trough region formed by implanting a p-impregnation, which may be boron, indium, or the like, into the substrate 20. The resulting trough region 22 may extend to the upper surface of the substrate 20. The concentration of the n- or p-impregnation may be equal to or less than 10 18 cm -3 , such as in the range of approximately 10 17 cm -3 and approximately 10 18 cm -3 , be.

[0013] Referring to Fig. 2, isolation zones 24 are formed such that they extend from an upper surface of the substrate 20 into the substrate 20. The isolation zones 24 are subsequently referred to as shallow trench isolation zones (STI zones). The process in question is described in process sequence 200, which is in Fig. Figure 21 is shown as process 204. The sections of substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 can be a thin film formed from silicon oxide. In some embodiments, the pad oxide layer 28 is formed in a thermal oxidation process, whereby a layer on the top surface of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesive layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. In accordance with some embodiments, the hard mask layer 30 is formed from silicon nitride, for example using low-pressure vapor deposition (LPCVD).In accordance with some other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitriding of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form the hard masks 30, as shown in [reference]. Fig. 2 shown.

[0014] Next, the structured hard mask layers 30 are used as an etching mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with one or more dielectric material(s). A planarization process, such as a chemical-mechanical polishing (CMP) process or a mechanical grinding process, is then performed to remove excess sections of the dielectric material(s), and the remaining sections of the dielectric material(s) are the STI regions 24. The STI regions 24 may contain a lining dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of an area layer of the substrate 20.The lining dielectric can also be a deposited silicon oxide layer, silicon nitride layer, or the like, for example, formed using atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI areas 24 can also have a dielectric material over the lining oxide, wherein the dielectric material can be formed using flowable chemical vapor deposition (FCVD), rotational coating, or the like. In accordance with some embodiments, the dielectric material over the lining dielectric can contain silicon oxide.

[0015] The upper layers of the hard masks 30 and the upper layers of the STI regions 24 can be arranged essentially on the same plane. Semiconductor strips 26 are arranged between adjacent STI regions 24. In some embodiments, the semiconductor strips 26 form parts of the original substrate 20, such that the material of the semiconductor strips 26 is the same as that of the substrate 20. In alternative embodiments of the present disclosure, the semiconductor strips 26 are substitute strips formed by etching the sections of the substrate 20 between the STI regions 24 to form depressions and performing epitaxy to grow further semiconductor material in the depressions. Consequently, the semiconductor strips 26 are formed from a semiconductor material that differs from that of the substrate 20.In accordance with some embodiments, semiconductor strips 26 are formed from silicon-germanium, silicon-carbon or a III-V composite semiconductor material.

[0016] Referring to Fig. 3. The STI areas 24 are deepened such that the upper sections of the semiconductor strips 26 protrude further than the upper surfaces 24T of the remaining sections of the STI areas 24, in order to form projecting fins 36. The process in question is described in process sequence 200, which is in Fig. Figure 21 is shown as process 206. The etching can be carried out using a dry etching process, using, for example, a mixture of HF3 and NH3 as the etching gas. Plasma can be generated during the etching process. Argon can also be used. In accordance with alternative embodiments of the present disclosure, the deepening of the STI areas 24 is carried out using a wet etching process. The etching chemical can, for example, contain HF.

[0017] In the embodiments shown above, the fins can be structured by any suitable method. For example, the fins can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. Typically, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing dimensions than those achievable using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed along the side of the structured sacrificial layer using a self-aligning process.Then the sacrificial layer is removed, and the remaining spacers, or mold cores, can now be used to structure the fins.

[0018] Referring to Fig. 4. Dummy gate stacks 38 are formed such that they extend along the upper surfaces and side walls of the (protruding) fins 36. The process in question is described in process flow 200, which is in Fig. 21 is shown as process 208. The dummy gate stack 38 can be dummy gate dielectrics 40 (shown in Fig. 7B) and dummy gate electrodes 42 over the dummy gate dielectrics 40. The dummy gate electrodes 42 can be formed, for example, using amorphous silicon or polysilicon, although other materials may also be used. Each of the dummy gate stacks 38 can also have one (or a plurality of) hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 can be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. Dummy gate stacks 38 can be arranged transversely over a single or a plurality of projecting fins 36 and / or STI regions 24. The dummy gate stacks 38 can also have longitudinal directions extending perpendicular to the longitudinal directions of the projecting fins 36.

[0019] Next, gate spacers 46 are formed on the side walls of the dummy gate stack 38. The process in question is in process flow 200, which is in Fig. Figure 21 is also shown as process 208. In accordance with some embodiments, gate spacer elements 46 are formed from one (or more) dielectric material(s), such as silicon nitride, silicon carbonitride or the like, and can have a single-layer structure or a multi-layer structure comprising a plurality of dielectric layers.

[0020] The sections of the foreground fins 36, which are not covered by the dummy gate stacks 38 and the gate spacers 46, are then etched, thereby creating the Fig. The structure shown in section 5 is created. The process in question is in process flow 200, which is in Fig. Figure 21 is shown as process 210. The recessing can be anisotropic, thereby protecting the sections of the fins 36 located directly beneath the dummy gate stacks 38 and the gate spacers 46 from etching. In accordance with some embodiments, the upper surfaces of the recessed semiconductor strips 26 can be positioned deeper than the upper surfaces 24T of the STI areas 24. Accordingly, recesses 50 are formed. The recesses 50 have sections located on opposite sides of the dummy gate stacks 38 and sections between remaining sections of the projecting fins 36.

[0021] Next, epitaxial regions (source / drain regions) 52 are formed by selective growth (by epitaxy) of a semiconductor material in the wells 50, thereby creating the structure in Fig. 6 arises. The process in question is in process flow 200, which is in Fig. Figure 21 is shown as process 212. Depending on whether the emerging FinFET is a p-FinFET or an n-FinFET, a p-impurity or an n-impurity can be doped in situ as epitaxy progresses. For example, if the emerging FinFET is a p-FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. In contrast, if the emerging FinFET is an n-FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. In accordance with alternative embodiments of the present disclosure, the epitaxial regions contain 52 III-V composite semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof.After the depressions 50 have been filled with the epitaxial areas 52, the further epitaxial growth of the epitaxial areas 52 causes them to expand horizontally, and facets may form. Further growth of the epitaxial areas 52 can also cause adjacent epitaxial areas 52 to merge. This can create voids (air gaps) 53.

[0022] Fig. Figure 7A shows a perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60. The process in question is described in process sequence 200, which is in Fig. Figure 21 is shown as process 214. The CESL 58 can be formed from silicon oxide, silicon nitride, silicon carbonitride, aluminum oxide, aluminum nitride, or the like, and can be formed using CVD, ALD, or the like. The ILD 60 can contain a dielectric material formed, for example, using PECVD, FCVD, spin coating, CVD, or another deposition process. In accordance with some embodiments, the deposition of the ILD 60 is carried out using plasma when, for example, PECVD is used. The ILD 60 can be formed from an oxygen-containing dielectric material, which can be a silicon-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphorus silicate glass (PSG), boron silicate glass (BSG), boron-doped phosphorus silicate glass (BPSG), or the like.A planarization process, such as a CMP process or a mechanical grinding process, can be performed to bring the upper surfaces of the ILD 60, the dummy gate stack 38 and the gate spacer elements 46 to a plane.

[0023] Fig. 7B represents a vertical plane in the reference cross-section BB of the structure in Fig. Figure 7A shows a plurality of epitaxial regions 52 and a plurality of dummy gate stacks 38, which can belong to a plurality of FinFETs. Fig. Figure 7B and subsequent figures show the plane of the upper surfaces 24T and the lower surfaces 24B of the STI areas 24. The STI areas 24 are located in the cross-section shown in the Fig. 7B and 8-20 are not shown and are therefore not depicted. The semiconductor fins 36 are the sections of the semiconductor strips 26 that are arranged higher than the plane of the upper surface 24T.

[0024] After the structure, which is in the Fig. 7A and Fig. As shown in Figure 7B, the dummy gate stacks 38 are replaced by replacement gate stacks 66, which have replacement gate dielectrics 62 and replacement gate electrodes 64, as shown in Figure 7B. Fig. 8 shown. The process in question is in process flow 200, which is in Fig. 21 is shown as process 216. When replacing the gate stacks, the hard mask layers 44, the dummy gate electrodes 42 and the dummy gate dielectrics 40, which are in the Fig. 7A and Fig. 7B are removed. Next, replacement gate stacks 66 are formed in the trenches left behind by the removed dummy gate stacks 38. The process in question is in process flow 200, which is shown in Fig. 21 is shown, represented as process 216.

[0025] In accordance with some embodiments, each of the gate dielectrics 62 has an interface layer (IL) as its lower section. The ILs are formed on the exposed surfaces of the projecting fins 36. Each IL may have an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the respective projecting fin 36, a chemical oxidation process, or a deposition process. The gate dielectrics 62 may also have high k-value dielectric layers formed over the respective ILs. The high k-value dielectric layers may be formed from or contain a dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high k-value dielectric material is greater than 3.9 and may be greater than approximately 7.0.The high k-value dielectric layers are formed as conformal layers extending along the side walls of the projecting fins 36 and the upper surfaces and side walls of the gate spacer elements 46. In some embodiments, the high k-value dielectric layers are formed using ALD or CVD.

[0026] In accordance with some embodiments, the gate electrodes 64 have stacked layers. The sublayers within the stacked layers are not shown separately, but the sublayers may differ from one another. The deposition can be carried out using conformal deposition processes, such as ALD, CVD, or the like, such that the thickness of the vertical sections and the thickness of the horizontal sections of the stacked layers (and each of the sublayers) are substantially the same. Once deposited, the stacked layers extend into the trenches left by the removed dummy gate stacks and have some sections above the ILD 60.

[0027] The stacked layers can include a diffusion barrier layer and one (or more) exit function layers above the diffusion barrier layer. The diffusion barrier layer can be made of titanium nitride (TiN), which may or may not be doped with silicon. The exit function layer determines the gate's work function and comprises at least one layer, or multiple layers, made of different materials. The exit function layer material is chosen depending on whether the FinFET is an n-type or p-type FinFET. For example, if the FinFET is an n-type FinFET, the exit function layer can include a TaN layer and a titanium-aluminum layer (TiAl layer) above the TaN layer. If the FinFET is a p-FinFET, the exit work layer can have a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer.After the deposition of the exit working layer(s), a conductive cover layer, which may be another TiN layer, is formed.

[0028] Next, a metallic filler material is applied, which may be composed of or contain, for example, tungsten or cobalt. The filler material completely fills the trenches left by the removed dummy gate stacks 38. At the time of their deposition, the gate dielectrics 62 and the gate electrodes 64 have some sections extending into the trenches left by the removed dummy gate stacks and other sections above the ILD 60. In a subsequent process, a planarization step, such as a CMP process or a mechanical grinding process, is performed such that the sections of the deposited layers above the ILD 60 are removed. As a result, metal gate electrodes 64 are formed. The replacement gate dielectrics 62 and the replacement gate electrodes 64 are subsequently referred to collectively as the replacement gate stack 66.

[0029] In accordance with some embodiments, as in Fig. As shown in Figure 8, the replacement gate stacks 66 are deepened, followed by the selective deposition of metal layers 68 on the respective gate electrodes 64. The metal layers 68 have a lower resistivity than at least some (or all) of the materials in the replacement gate stacks 66 and can contribute to reducing the resistance. In accordance with alternative embodiments, the formation of metal layers 68 is omitted.

[0030] Fig. Figure 8 further describes the formation of self-aligning hard masks 70. In accordance with some embodiments, the self-aligning hard masks 70 are formed from an oxygen-free material and may be made of or contain silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), or the like. The self-aligning hard masks 70 may be deposited using CVD, ALD, PECVD, PVD, or the like.

[0031] Fig. Figure 9 represents the formation of source / drain contact plugs 74, which are also referred to as lower source / drain contact plugs. Source / drain silicide regions 72 are formed by a silicide process in which a metal layer (such as a titanium layer or a cobalt layer) is used to react with a corresponding underlying epitaxial region 52 to form a silicide layer. Each of the source / drain contact plugs 74 may have a barrier layer, which may be a metal nitride layer, such as a titanium nitride layer or a tantalum nitride layer. The source / drain contact plugs 74 may further have a metallic material overlying the barrier layer. The metallic material may be made of or contain tungsten, cobalt, aluminum, the like, or alloys thereof.A planarization process, such as a CMP process or a mechanical grinding process, is then performed to remove the sections of the metal layer, the barrier layer, and the metallic material, with the remaining sections of these layers forming the source / drain contact plugs 74. This forms the FinFETs 76, which can be designated FinFET 76A, FinFET 76B, and FinFET 76C.

[0032] In accordance with some embodiments, as in Fig. As shown in Figure 10, an insulating layer 78 is applied. The process in question is in process sequence 200, which is in Fig. Figure 21 is shown as process 220. It is understood that the insulating layer 78 and the underlying structure are only an example, and that various structures can be formed, which are also included in the scope of this disclosure. For example, the self-aligning hard masks 70 can be omitted, and the insulating layer 78 can be formed as a conformal layer that can extend downwards to contact the metal layers 68. In accordance with these embodiments, the insulating layer 78 can be applied as a conformal or a near-conformal layer, wherein the thickness deviation is, for example, less than 30 percent of the thickness of the thickest part, which is likely to be the horizontal part on the upper surface of the ILD 60.

[0033] Fig. Figure 11 represents the formation of the etch stop layer (ESL) 80 and the dielectric layer (ILD) 82. The process in question is described in process sequence 200, which is in Fig. Figure 21 is shown as process 222. The etch stop layer 80 can be composed of or contain aluminum nitride, aluminum oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, the like, or multiple layers thereof, and can be formed using a deposition process such as CVD, ALD, or the like. The ILD 82 can contain silicon oxide, phosphorus silicate glass (PSG), boron silicate glass (BSG), boron-doped phosphorus silicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. The ILD 82 can be formed using spin coating, FCVD, or the like, or can be formed by a deposition process such as PECVD or LPCVD.

[0034] Next, the gate contact plug 84 and the butt contact 86 (which is also a gate contact plug) are formed. The process in question is in process flow 200, which is in Fig. Figure 21 is shown as process 224. The gate contact plug 84 penetrates the ILD 82, the ESL 80, the insulating layer 78, and the self-aligning hard mask 70 to contact the metal layer 68 and is thus electrically connected to the gate electrode 64 in question. In accordance with some embodiments, the gate contact plug 84 has substantially straight edges extending from the upper surface of the ILD 82 to the metal layer 68. In accordance with alternative embodiments, the gate contact plug 84 has a wider section and a narrower section, the edges of which form a step. In accordance with these embodiments, the insulating layer 78 can prevent the gate contact plug 84 from forming a connection with the adjacent lower source / drain contact plugs 74 and can thus reduce leakage currents between them.

[0035] The case contact 86 is used to connect the source / drain contact plug 74 and the gate stack 66 of the FinFET 76B. The gate contact plug 84 and the case contact 86 can share some formation processes, while other processes differ, such that the wider upper section of the case contact 86 also penetrates the insulating layer 78 to contact the source / drain contact plug 74 of the FinFET 76B, while the wider upper section of the gate contact plug 84 terminates at the insulating layer 78.

[0036] In accordance with some embodiments, both the gate contact plug 84 and the butt contact 86 have a conformal barrier layer and a metallic material above the barrier layer. The barrier layer may be made of or contain TiN, TaN, Ti, Ta, or the like. The metallic material may be made of or contain tungsten, cobalt, aluminum, alloys thereof, or the like. In accordance with alternative embodiments, the gate contact plug 84 and the butt contact 86 may not have a barrier and may be made of or contain a homogeneous material, such as tungsten, cobalt, aluminum, or alloys thereof.

[0037] Referring to Fig. 12. The ESL 88 is applied. The ESL 88 is a composite layer comprising two or more sublayers, wherein the adjacent sublayers are formed from different materials. The sublayers may be formed from or contain a nitride, a silicon-carbon-based material, a carbon-doped oxide, an oxygen-doped carbide, a metal-containing dielectric, or the like. In accordance with some embodiments, the ESL 88 has a sublayer 88A formed from or containing aluminum oxide and a sublayer 88B formed from or containing SiOC. In accordance with alternative embodiments, the ESL 88 has a sublayer 88A formed from or containing aluminum oxide, a sublayer 88B formed from or containing SiOC, and an overlying sublayer (not shown) formed from or containing aluminum oxide.The upper sublayer 88B can also be made of silicon oxide, silicon nitride or the like, while the lower sublayer 88A can also be made of other metal oxides, such as zirconium oxide.

[0038] The Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 represents a dual structuring process for defining the structures for vias that are arranged close together. Fig. 12 and Fig. Step 13 represents the formation of an initial through-hole. The relevant process is in process flow 200, which is in Fig. 21 is shown as process 226. As in Fig. As shown in Figure 12, an etch mask 90, which can be a three-layered layer, is formed. The etch mask 90 can have a bottom layer 90BL (which is sometimes also referred to as a sublayer), a middle layer 90ML above the bottom layer 90BL, and an top layer 90TL (which is sometimes also referred to as an upper layer) above the middle layer 90ML.

[0039] In accordance with some embodiments, the lower layer 90BL is formed from a carbon-containing material (by CVD), and the upper layer 90TL is formed from a photoresist (by rotational coating), which may contain organic or inorganic materials. The lower layer 90BL can be a crystalline or cross-linked photoresist. The middle layer 90ML can be formed from a mixed inorganic silicon-containing material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer 90ML can also be an inorganic film (such as silicon) applied by CVD. The upper layer 90TL is structured to form an opening 92, which is used to define a through-hole for subsequent processes.

[0040] In subsequent processes, the middle layer 90ML and the lower layer 90BL, as well as an upper sublayer, are etched in the ESL 88 such that the opening 92 extends into the upper layer. The opening 92 terminates at a lower sublayer of the ESL 88. In accordance with some embodiments in which the ESL 88 has two sublayers 88A and 88B without any further sublayers, the upper sublayer is layer 88B and the lower sublayer is layer 88A. In accordance with other embodiments in which the ESL 88 has three or more sublayers, the upper layer can be layer 88B or any other overlying sublayer, and the lower layer can be the layer immediately below and in contact with the upper layer. Then the etching mask 90 is removed, and the resulting structure is in Fig. 13 shown.

[0041] The Fig. 14 and Fig. Figure 15 represents the formation of a second through-hole in the double structuring process. The process in question is in process flow 200, which is in Fig. The process shown in Figure 21 is represented as Process 228. The processes are similar to those shown in the Fig. 12 and Fig. 13 are shown. Referring to Fig. In step 14, an etch mask 94 is formed, comprising the lower layer 94BL, the middle layer 94ML, and the upper layer 94TL. ​​The materials of the lower layer 94BL, the middle layer 94ML, and the upper layer 94TL can be similar to the materials of the lower layer 90BL, the middle layer 90ML, and the upper layer 90TL, respectively. An opening 96 is formed in the upper layer 94TL. ​​The opening 96 is then extended down into the upper layer (such as sublayer 88B) of the ESL 88 and terminates at the lower layer (such as sublayer 88A) of the ESL 88. The etch mask 94 is then removed. The resulting structure is in Fig. 15 shown.

[0042] When etching the upper sublayer 88B, and if the sublayer 88B contains SiOC, an example etching process can be performed using plasma, which is generated using high RF energy in the range of approximately 200 watts to approximately 1,000 watts and low RF energy in the range of approximately 200 watts to approximately 500 watts. The pressure of the etching chamber can be in the range of approximately 26.7 mbar to approximately 106.6 mbar. The temperature of wafer 10 during etching can be in the range of approximately 0°C to approximately 50°C. An example etching gas could be a CxFy-based gas having a flow velocity in the range of between approximately 20 sccm and approximately 50 sccm, nitrogen (N2) having a flow velocity of less than approximately 100 sccm, argon having a flow velocity in the range of between approximately 600 sccm and approximately 1.The device contains 200 sccm of hydrogen (H2) having a flow velocity of less than approximately 100 sccm, and / or a CHxFy-based gas having a flow velocity of less than approximately 100 sccm. A DC voltage may be applied to the upper electrode of the etching tool to control the C / F ratio, and the DC voltage may be less than approximately 500 volts.

[0043] Referring to Fig. 16. An etching process is carried out to etch through the remaining layers (including the lower sublayer, such as 88A) of the ESL 88. The process in question is in process flow 200, which is in Fig. Figure 21 is shown as process 230. The etching is stopped at the underlying ILD 82. In accordance with some embodiments in which the lower sublayer 88A contains aluminum oxide, the etching can be carried out using a chemical solution containing NH4F dissolved in deionized water.

[0044] Fig. Figure 17 represents the formation of the dielectric layer 102 (which is also referred to as the intermetal dielectric (IMD)). The process in question is described in process sequence 200, which is in Fig. Figure 21 is shown as process 232. A pad layer 104, a hard mask 106, and a buffer layer 108 are also applied. The process in question is in process sequence 200, which is shown in Fig. Figure 21 is shown as process 234. Trenches 110, 112, and 114 are formed in the buffer layer 108 and the hard mask 106. The formation of trenches 110, 112, and 114 can be described similarly to the process shown in the Fig. 14 and Fig. As shown in Figure 15, this can be done, for example, using a multi-layered hard mask. The formation process is not discussed in detail here.

[0045] In accordance with some embodiments, the dielectric layer 102 is formed from a low k-value dielectric material having a dielectric constant (k-value) of less than approximately 3.0 or less than approximately 3.5. The dielectric layer 102 may be formed from or contain Black Diamond (a registered trademark of Applied Materials), a low k-value carbon-containing dielectric material, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ), or the like. In accordance with some embodiments, the formation of the dielectric layer 102 involves the application of a porous dielectric material, followed by a curing process to expel the porous material, leaving the remaining dielectric layer 102 porous. The pad layer 104 and the buffer layer 108 may be formed from or contain silicon dioxide, silicon oxycarbide, or the like.The hard mask 106 may be made of or contain a metal nitride, such as titanium nitride, boron nitride or the like, a metal oxide or the like.

[0046] Trenches 110, 112, and 114 are formed in the buffer layer 108 and the hard mask 106. Formation can be carried out using a structured etching mask (not shown), which is similar to etching mask 84 ( Fig. 14) may be.

[0047] Next, the structured hard mask 106 is used to etch the underlying pad layer 102 and the dielectric layer 102. This process is described in process flow 200, which is in Fig. Figure 21 is shown as process 236. The etching is anisotropic and is stopped by the lower sublayer 88A of the etch stop layer 88. In accordance with some embodiments in which the dielectric layer 102 contains oxide, the etching can be carried out using a carbon- and fluorine-containing gas (CxFy), such as C₂F₆, CF₄, CH₂F₂, the like, or combinations thereof. Other gases, such as fluorine (F₂), chlorine (Cl₂), hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br₂), C₂F₆, CF₄, SO₂, the mixture of HBr, Cl₂, and O₂, or the mixture of HBr, Cl₂, O₂, and CH₂F₂, etc., can also be used.

[0048] Etching can be performed using plasma generated by high-frequency (HF) energy ranging from approximately 200 watts to approximately 1,000 watts and low-frequency (LF) energy ranging from approximately 200 watts to approximately 500 watts. The etching chamber pressure can range from approximately 26.7 mbar to approximately 106.6 mbar. The wafer temperature during etching can range from approximately 0°C to approximately 80°C. Example etching gases include a CxFy-based gas with a flow velocity ranging from approximately 20 sccm to approximately 50 sccm, nitrogen (N2) with a flow velocity of less than approximately 100 sccm, and argon with a flow velocity ranging from approximately 600 sccm to approximately 1.The material contains 200 sccm of hydrogen (H2) having a flow velocity of less than approximately 100 sccm, and / or a CHxFy-based gas having a flow velocity of less than approximately 100 sccm. A DC voltage can be applied to control the C / F ratio, and the DC voltage can be less than approximately 500. After the etching process, the remaining pad layer 104, the hard mask 106, and the buffer layer 108 are removed, and the resulting structure is shown in [reference missing]. Fig. 18 shown.

[0049] In etching as in Fig. As shown in Figure 18, the downward extension of trenches 110 and 112 is stopped by the sublayer 88A of the ESL 88. Below trench 114, however, the via openings 92 and 94 described in the previous paragraphs have been formed. Accordingly, the ILD 82, the etch stop layer 80, and the insulating layer 78 are etched through such a way that the underlying source / drain contact plugs 74 are exposed towards the via openings 92 and 96.

[0050] Referring to Fig. In step 19, an additional etching process is carried out to etch the sublayer 88A of the ESL 88. The etching can be anisotropic or isotropic and can be wet or dry. Consequently, the gate contact plug 84 and the butt contact 86 are also exposed towards the grooves 110 and 112, respectively.

[0051] Referring to Fig. In step 20, metal conductors 120, 122, and 124, as well as vias 126, are formed. The metal conductor 124 and the vias 126 form a double damascus structure. The metal conductors 120 and 122 are formed such that they exhibit single damascus structures. The process in question is in process sequence 200, which is in Fig. Figure 21 is shown as process 238. The formation process may include filling the trenches and vias with conductive materials and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess conductive materials. The metal conductors 120, 122, and 124 and other metal conductors in the same layer are collectively referred to as a bottom metal layer, or M0. Each of the metal conductors 120, 122, and 124 and vias 126 may have a diffusion barrier layer 128 and a metallic material 130 above the diffusion barrier layer 128. The diffusion barrier layer 128 may be formed of or contain titanium nitride, tantalum nitride, titanium, tantalum, or the like. The metallic material 130 may contain copper, ruthenium, tungsten, cobalt, or alloys thereof.

[0052] In subsequent processes, several overlying dielectric layers and corresponding double Damascus structures are deposited over the structure which is in Fig. Figure 20 shows the structure. The vias of the overlying double damascene structures can be in contact with the metal conductors 120, 122, and 124. The corresponding dielectric layers can be formed from dielectric layers with a low k-value.

[0053] In the structure which is in Fig.As shown in Figure 20, the double damascus structures 124 / 126, which may contain copper, have been formed to contact the lower contact plugs 74. The vias in the double damascus structures can serve as upper contact plugs. The vias 126 are also located on the same plane (in the same ILD 82) as the gate contact plug 84 and the butt contact 86, which are formed using a single damascus process. This is because these elements extend deep downwards and have a high aspect ratio, making it difficult to form them in the same (double) damascus process as that used for forming the metal conductors 120 and 122. The metal conductors 120 and 122 above and in contact with the gate contact plug 84 and the butt contact 86 are formed using a single damascus process.Accordingly, the elements in ILD 82 and in the dielectric layer 102 exhibit mixed double damascene and single damascene structures.

[0054] The embodiments of the present disclosure exhibit several advantageous features. By using double damascus structures, no interfaces are formed between the upper contact plugs and the overlying metal conductors. Copper can also be used to replace materials with high resistivity, such as tungsten. Consequently, the resistivity of the double damascus structure is lower than when using single damascus structures. Furthermore, when forming the double damascus structures, the vias are formed before the trenches are formed. Consequently, the metal hard mask is not damaged when the vias are formed. In contrast, if trenches are formed first, the metal hard mask is always damaged when there is a displacement of the superimposed layers and the vias overlap with the edges of the metal hard mask.The embodiments of the present disclosure thus exhibit an improved process window.

[0055] In accordance with some embodiments, a method comprises forming a transistor having a source / drain region and a gate electrode; forming a source / drain contact plug over and electrically connected to the source / drain region; forming a first interlayer dielectric over the source / drain contact plug; forming an etch stop layer over the first interlayer dielectric; etching the etch stop layer to form a first via opening; forming a second interlayer dielectric over the first interlayer dielectric; performing an etching process such that the second interlayer dielectric is etched to form a trench, and the first via opening in the etch stop layer extends into the first interlayer dielectric to expose the source / drain contact plug;and the filling of the trench and the first via opening in joint processes to form a metal conductor or a via.

[0056] In one embodiment, the etch stop layer comprises a lower sublayer and an upper sublayer above the lower sublayer, and the method further comprises performing a first etching process to form the first via in the upper sublayer, wherein the first etching process is stopped by the lower sublayer; performing a second etching process to form a second via in the upper sublayer, wherein the second etching process is stopped by the lower sublayer; and prior to the etching process, performing a third etching process to enlarge the first via and the via into the lower sublayer. In one embodiment, after the metal conductor and the via have been formed, both the lower sublayer and the upper sublayer remain.In one embodiment, the lower sublayer contains aluminum oxide, and the upper sublayer contains silicon oxycarbonitride. In another embodiment, the third etching process stops at the first interlayer dielectric.

[0057] In one embodiment, the method further comprises a gate contact plug located above and in contact with the gate electrode, wherein the etch stop layer is arranged above and in contact with both the gate contact plug and the first interlayer dielectric. In another embodiment, the gate contact plug extends into a region between gate spacers located on opposite sides of the gate electrode. In yet another embodiment, the gate contact plug is a butt contact, and the butt contact is located above and in contact with the gate electrode, wherein the etch stop layer is further arranged above and in contact with both the butt contact and the first interlayer dielectric. In yet another embodiment, the method further comprises, in the combined processes of forming the metal conductor and the via, forming an additional metal conductor above and in contact with the gate contact plug.In one embodiment, the method further comprises forming a third interlayer dielectric, wherein the source / drain contact plug is arranged in the third interlayer dielectric, and the forming of the source / drain contact plug comprises a planarization process to bring an upper surface of the source / drain contact plug to a plane with an upper surface of the third interlayer dielectric.

[0058] In accordance with some embodiments, a structure comprising a transistor has a source / drain region and a gate electrode on one side of the source / drain region; a source / drain silicide region above and in electrical connection with the source / drain region; a source / drain contact plug above and in contact with the source / drain silicide region; a gate contact plug above and in connection with the gate electrode; a first interlayer dielectric above the source / drain contact plug; a second interlayer dielectric above the first interlayer dielectric; and a double damascene structure comprising a metal conductor and a via arranged below the metal conductor, wherein the via extends into the first interlayer dielectric to be in physical contact with the source / drain contact plug, and the metal conductor extends into the second interlayer dielectric.

[0059] In one embodiment, the metal conductor and the via are continuously connected without any discernible interface between them. In one embodiment, the gate contact plug contains tungsten, and the double damascus structure contains copper. In another embodiment, the structure further comprises an etch stop layer between the first interlayer dielectric and the second interlayer dielectric, wherein the etch stop layer has a lower sublayer and an upper sublayer above the lower sublayer, and wherein the metal conductor penetrates the etch stop layer. In one embodiment, the lower sublayer contains aluminum oxide, and the upper sublayer contains silicon oxycarbide.In one embodiment, the structure further comprises an additional gate stack; an additional source / drain contact plug on one side of the additional gate stack; and a butt contact that electrically connects the additional gate stack to the additional source / drain contact plug.

[0060] In accordance with some embodiments, a structure comprises a transistor having a source / drain region and a gate electrode; a first interlayer dielectric, wherein part of the gate electrode is arranged in the first interlayer dielectric; a gate contact plug connected to the gate electrode, wherein a section of the gate contact plug extends further downward than an upper surface of the first interlayer dielectric; a second interlayer dielectric above the gate contact plug; a third interlayer dielectric above the second interlayer dielectric; and a double damascene structure comprising a metal conductor and a via, wherein the metal conductor extends into the third interlayer dielectric and the via extends into the second interlayer dielectric.

[0061] In one embodiment, the structure further comprises an etch stop layer, wherein a lower surface of the etch stop layer physically contacts an upper surface of the gate contact plug and an upper surface of the second interlayer dielectric. In another embodiment, both the metal conductor and the via have a diffusion barrier layer and a metal region above the diffusion barrier layer, wherein the diffusion barrier layers of the metal conductor and the via are continuously connected to each other. In another embodiment, the gate contact plug contains tungsten, and the metal conductor and the via contain copper.

Claims

[1] Procedure encompassing: Forming a transistor (76) having a source / drain region (52) and a gate electrode (64); Forming a source / drain contact plug (74) over and in electrical connection with the source / drain area (52); Formation of a first interlayer dielectric (82) over the source / drain contact plug (74); Forming an etch stop layer (88) over the first interlayer dielectric (82); Etching the etch stop layer to form a first via opening (92); Formation of a second interlayer dielectric (102) over the first interlayer dielectric (82); Performing an etching process such that the second interlayer dielectric (102) is etched to form a trench (114), and the first via opening (92) in the etch stop layer (88) is extended into the first interlayer dielectric (82) to expose the source / drain contact plug (74); and Filling the trench (114) and the first via opening (92) in joint processes to form a metal conductor (124) and a via (126), wherein the etch stop layer (88) has a lower sublayer (88A) and an upper sublayer (88B) above the lower sublayer (88A), and the method further comprises: Performing a first etching process to form the first via opening (92) in the upper sublayer (88B), wherein the first etching process is stopped by the lower sublayer (88A); Performing a second etching process to form a second via opening (96) in the upper sublayer (88B), wherein the second etching process is stopped by the lower sublayer (88A); and prior to the etching process, performing a third etching process to extend the first via opening (92) and the second via opening (96) into the lower sublayer (88A), wherein the lower sublayer (88A) contains aluminium oxide, and the upper sublayer (88B) contains silicon oxycarbonitride. [2] Method according to claim 1, wherein after forming the metal conductor (124) and the via (126) both the lower sublayer (88A) and the upper sublayer (88B) remain. [3] Method according to one of claims 1 or 2, wherein the third etching process stops on the first interlayer dielectric (82). [4] Method according to one of claims 1 to 3, further comprising a gate contact plug (84, 86) over and in connection with the gate electrode (64), wherein the etch stop layer (88) is arranged over and in contact with both the gate contact plug (84, 86) and the first interlayer dielectric (82). [5] Method according to claim 4, wherein the gate contact plug (84, 86) extends into a region between gate spacer elements (46) arranged on opposite sides of the gate electrode (64). [6] Method according to claim 4 or 5, wherein the gate contact plug (84, 86) is a butt contact (86), and the butt contact (86) is arranged over and in connection with the gate electrode (42), and wherein the etch stop layer (88) is arranged over and in contact with both the butt contact (86) and the first interlayer dielectric (82). [7] Method according to any one of claims 4 to 6, further comprising: Forming an additional metal conductor (120, 122) over and in contact with the gate contact plug (84, 86) in the common processes for forming the metal conductor (124) and the via (126). [8] Method according to any one of claims 1 to 7, further comprising: Forming a third interlayer dielectric (60), wherein the source / drain contact plug (74) is arranged in the third interlayer dielectric (60), wherein the formation of the source / drain contact plug (74) includes a planarization process to bring an upper surface of the source / drain contact plug (74) and an upper surface of the third interlayer dielectric (60) into a plane. [9] exhibiting structure (10): comprising a transistor (76) comprising a source / drain region (52) and a gate electrode (64) on one side of the source / drain region (52); a source / drain silicide area (72) above and electrically connected to the source / drain area (52); a source / drain contact plug (74) over and in contact with the source / drain silicide area (72); a gate contact plug (84, 86) over and in connection with the gate electrode (52); a first interlayer dielectric (82) over the source / drain contact plug (74); a second interlayer dielectric (102) over the first interlayer dielectric (102); and comprising a double damascene structure, a metal conductor (124) and a via (126) arranged beneath the metal conductor (124), the via (126) extending into the first interlayer dielectric (82) to be in physical contact with the source / drain contact plug (74), and the metal conductor (124) extending into the second interlayer dielectric (102), further comprising an etch stop layer (88) between the first interlayer dielectric (82) and the second interlayer dielectric (102), the etch stop layer (88) having a lower sublayer (88A) and an upper sublayer (88B) above the lower sublayer (88A), and the metal conductor (124) penetrating the etch stop layer (88), the lower sublayer (88A) containing aluminum oxide, and the upper sublayer (88B) Contains silicon oxycarbide. [10] Structure (10) according to claim 9, wherein the metal conductor (124) and the via (126) are continuously connected to each other without any discernible interface between them. [11] Structure (10) according to claim 9 or 10, wherein the gate contact plug (84, 86) contains tungsten and the double damascus structure contains copper. [12] Structure (10) according to any one of claims 9 to 11, further comprising: an additional gate stack (66); an additional source / drain contact plug (74) on one side of the additional gate stack (66); and a butt contact (86) which electrically connects the additional gate stack (66) to the additional source / drain contact plug (74). [13] exhibiting structure (10): comprising a transistor (76), a source / drain region (52) and a gate electrode (64); a first interlayer dielectric (60) wherein part of the gate electrode (64) is arranged in the first interlayer dielectric (60); a gate contact plug (84, 86) connected to the gate electrode (64), wherein a section of the gate contact plug (84, 86) extends further downwards than an upper surface of the first interlayer dielectric (60); a second interlayer dielectric (82) over the gate contact plug (84, 86); a third interlayer dielectric (102) above the second interlayer dielectric (82); and comprising a double damascene structure, a metal conductor (124) and a via (126), wherein the metal conductor (124) extends into the third interlayer dielectric (102), and the via (126) extends into the second interlayer dielectric (82), further comprising an etch stop layer (88) between the first interlayer dielectric (82) and the second interlayer dielectric (102), wherein the etch stop layer (88) has a lower sublayer (88A) and an upper sublayer (88B) above the lower sublayer (88A), and wherein the metal conductor (124) penetrates the etch stop layer (88), wherein the lower sublayer (88A) contains aluminum oxide, and the upper sublayer (88B) contains silicon oxycarbide. [14] Structure (10) according to claim 13, wherein both the metal conductor (124) and the via (126) each have a diffusion barrier layer (128) and a metal area (130) above the diffusion barrier layer (128), wherein the diffusion barrier layers (130) of the metal conductor (124) and the via (126) are continuously connected to each other. [15] Structure according to one of claims 13 or 14, wherein the gate contact plug contains tungsten, and the metal conductor (124) and the via (126) contain copper.

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