Display devices

Abstract

Display device (100) comprising: a stretchable substrate (111); a pattern layer (120) disposed on the substrate (111) and having a plurality of plate patterns (121) and a plurality of line patterns (122, 222, 322); a plurality of pixels (SPX) arranged on each of the plurality of plate patterns (121); a plurality of connecting lines (181, 182) coupling the plurality of pixels (SPX), wherein the plurality of connecting lines (181, 182) are arranged on each of the plurality of line patterns (122, 222); and a buffer hole (222h) arranged so as not to overlap the plurality of connecting lines (181), wherein the buffer hole (222h) is filled with a filling member (FM) having a modulus of elasticity greater than or equal to a modulus of elasticity of the plurality of conductive patterns (222).

Description

BackgroundTechnical FieldThe present disclosure relates to a display device, and more particularly, to a stretchable display device.Description of the Prior ArtDisplay devices used for a computer monitor, a television, a mobile phone, and the like include an organic light emitting display (OLED) that emits light by itself, a liquid crystal display (LCD) that requires a separate light source, and the like.Such display devices are applied to more and more various fields including not only a computer monitor and a television but also personal mobile devices, and therefore display devices of reduced volume and weight having a wide active area at the same time are being studied.Recently, a display device manufactured to be stretchable in a certain direction and changeable into various shapes by forming a display unit, wires, and the like on a flexible substrate such as plastic, which is a flexible material, has received considerable attention as a next generation display device.US 2020 / 0161276 A1 relates to a stretchable display device.US 2017 / 0294610 A1 relates to a flexible organic electroluminescent display panel having a flexible substrate.Summary of the InventionOne or more embodiments of the present disclosure provide a display device that can reduce or minimize strain of elongated lines.One or more embodiments of the present disclosure provide a display device that enables an improvement in the strain rate.Technical advantages of the present disclosure are not limited to the above-mentioned advantages, and other advantages not mentioned above may be clearly apparent to those skilled in the art from the following descriptions.A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a pattern layer disposed on the lower substrate and having a plurality of plate patterns and a plurality of line patterns; a plurality of pixels disposed on each of the plurality of plate patterns; and a plurality of connection lines connecting the plurality of pixels, the plurality of connection lines being disposed on each of the plurality of line patterns, so that the stretching reliability may be improved.Further details of the exemplary embodiments are contained in the detailed description and drawings.According to the present disclosure, an elongation rate of a display device can be improved by arranging a plurality of connection wires on a wire pattern.According to the present disclosure, a buffer hole and a filling member can distribute a tensile stress applied in a curved region.According to the present disclosure, cracks in connection wires can be reduced or minimized by arranging the connection wires on a neutral plane of a curved portion.The effects according to the present disclosure are not limited to the above-illustrated content, and other various effects are included in the present specification.Brief Description of the Several Views of the DrawingsThe foregoing and other aspects, features and other advantages of the present disclosure will become more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure; FIG. 2 is an enlarged plan view of an active area of the display device according to an exemplary embodiment of the present disclosure; FIG. 3 is a cross-sectional view taken along the line of intersection III-III' shown in FIG. 2; FIG. 4 is a cross-sectional view taken along the line of intersection IV-IV' shown in FIG. 2; FIG. 5 is a cross-sectional view taken along the line V-V' shown in FIG. 2; FIG. 6 is a circuit diagram of a sub-pixel of the display device according to an exemplary embodiment of the present disclosure; FIG. 7 is a view illustrating connection lines of the display device according to an exemplary embodiment of the present disclosure; FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7; FIG. 9 is a view illustrating connection lines of a display device according to another exemplary embodiment of the present disclosure; FIG. 10A is a cross-sectional view taken along line X-X' of FIG. 9, according to an exemplary embodiment of the present disclosure; FIG. 10B is a cross-sectional view taken along line X-X' of FIG. 9, according to another exemplary embodiment of the present disclosure; and FIG. 11 is a view illustrating connection lines of a display device according to still another exemplary embodiment of the present disclosure.Detailed DescriptionThe advantages and features of the present disclosure and methods of achieving the same will be more clearly understood from exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following exemplary embodiments, but may be implemented in various different forms. The exemplary embodiments are provided only to complete the disclosure of the present disclosure and to fully present the category of the present disclosure to those skilled in the art to which the present disclosure pertains.The shapes, dimensions, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally designate like elements throughout the specification. Further, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "comprising," "having" used herein are generally intended to allow other components to be added unless the terms are used with the term "only.". All references in the singular may include the plural, unless expressly stated otherwise.Components are designed to include a common range of errors, even if not expressly stated.When the positional relationship between two parts is described using the terms such as "on", "over", "under", and "next", one or more parts may be positioned between the two parts unless the terms are used with the term "direct" or "immediate".When an element or layer is referred to as being "on" another element or layer, it may be directly on the other element or layer or intervening elements or layers may be present.Although the terms "first / r / s", "second / r / s", and the like are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from the other components. Therefore, a first component to be mentioned below may be a second component in a technical concept of the present disclosure.Throughout the specification, the same reference numerals denote the same elements.Since the dimensions and thickness of each component shown in the drawings are illustrated for convenience of explanation, the present disclosure is not necessarily limited to the dimensions and thickness shown of each component.The features of various embodiments of the present disclosure may be partially or fully coupled or combined with each other and interlocked and operated in a technically different manner, and the embodiments may be executed independently or in dependence on each other.Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.A display device according to an exemplary embodiment of the present disclosure is a display device that can display an image even when bent or stretched, and can also be referred to as a display device, a stretchable display device, or a flexible display device. The display device may have higher flexibility and extensibility than conventional typical display devices. Accordingly, a user can bend or stretch the display device, and a shape of the display device can be freely changed depending on the manipulation of the user. For example, when the user grasps and pulls an end of the display device, the display device may be stretched in a pulling direction by the user. When the user places the display device on an uneven outer surface, the display device may be arranged to be bent according to a shape of the outer surface. When the force applied by the user is removed, the display device may return to its original shape.Stretchable Substrate and Pattern LayerFIG. 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure. FIG. 2 is an enlarged plan view of an active area of the display device according to an exemplary embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along the line of intersection III-III' shown in FIG. 2.Specifically, FIG. 2 is an enlarged plan view of the region A shown in FIG. 1.Referring to FIG. 1, a display device 100 according to an exemplary embodiment of the present disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, gate drivers GD, data drivers DD, and power supplies PS. And referring to FIG. 1, the display device 100 according to an exemplary embodiment of the present disclosure may further include a fill layer 190 and an upper substrate 112.The lower substrate 111 is a substrate for supporting and protecting various components of the display device 100. In addition, the upper substrate 112 is a substrate for covering and protecting various components of the display device 100. That is, the lower substrate 111 is a substrate that supports the pattern layer 120 on which the pixels PX, the gate drivers GD, and the power supplies PS are formed. In addition, the upper substrate 112 is a substrate covering the pixels PX, the gate drivers GD, and the power supplies PS.The lower substrate 111 and the upper substrate 112 are each a ductile substrate and may be formed of an insulating material that can be bent or stretched. For example, both the lower substrate 111 and the upper substrate 112 may be formed of silicone rubber such as polydimethylsiloxane (PDMS), or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE), and thus may have flexible properties. In addition, materials of the lower substrate 111 and the upper substrate 112 may be the same, but are not limited thereto, and may be variously modified.The lower substrate 111 and the upper substrate 112 are each a ductile substrate and may be reversibly stretchable and compressible. Accordingly, the lower substrate 111 may be referred to as a lower extensible substrate, a lower flexible substrate, a lower ductile substrate, a lower extensible substrate, a first extensible substrate, a first flexible substrate, a first ductile substrate, or a first extensible substrate, and the upper substrate 112 may be referred to as an upper extensible substrate, an upper flexible substrate, an upper ductile substrate, an upper extensible substrate, a second extensible substrate, a second flexible substrate, a second extensible substrate, or a second ductile substrate. Further, the elastic moduli of the lower substrate 111 and the upper substrate 112 may be several MPa to several hundred MPa. Further, an elongation at break rate of the lower substrate 111 and the upper substrate 112 may be 100% or higher. Here, the breaking elongation rate refers to an elongation rate at a time when an object to be elongated breaks or tears. In other words, the elongation at break rate refers to an elongation distance at a time when an object to be elongated breaks or tears. That is, the breaking elongation rate is defined as a percentage ratio of a length of an original object and a length of the stretched object when an object has been sufficiently stretched to be considered broken. For example, if a length of an object (e.g., the lower substrate 111) is 100 cm when the object is not stretched and then reaches a length of 110 cm when the object has been stretched to break or tear at that length, then it has been stretched to 110% of its original length. In this case, the breaking elongation rate of the object is 110%. The number could thus also be referred to as the elongation at break ratio, since it is the ratio of the stretched length as a numerator to the original unstretched length as a denominator at the time of breakage.A thickness of the lower substrate may be 10 μm to 1 mm, but is not limited thereto.The lower substrate 111 may include an active region AA and a non-active region NA surrounding the active region AA. However, the active region AA and the non-active region NA are not limited to the lower substrate 111, and may be so designated in the entire display device.The active area AA is an area in which an image is displayed on the display device 100. The plurality of pixels PX are arranged in the active area AA. In addition, each of the pixels PX may include a display element and various driving elements for driving the display element. The various driving elements may refer to at least one thin film transistor TFT and a capacitor, but are not limited thereto. In addition, each of the plurality of pixels PX may be connected to different lines. For example, each of the plurality of pixels PX may be connected to different lines such as gate lines, data lines, high potential voltage lines, low potential voltage lines, reference voltage lines, and initialization voltage lines.The non-active area NA is an area where an image is not displayed. The non-active region NA may be a region adjacent to the active region AA. And, the non-active region NA may be a region adjacent to and surrounding the active region AA. However, the present disclosure is not limited thereto, and the non-active region NA corresponds to a region of the lower substrate 111 except for the active region AA, and may be changed and separated into various shapes. Components for driving the plurality of pixels PX arranged in the active area AA are arranged in the non-active area NA. The gate drivers GD and power supplies PS may be disposed in the non-active region NA. In addition, a plurality of pads connected to the gate drivers GD and the data drivers DD may be disposed in the non-active area NA, and each of the pads may be connected to each of the plurality of pixels PX in the active area AA.On the lower substrate 111, the pattern layer 120 includes a plurality of first plate patterns 121 and a plurality of first conductive patterns 122 disposed in the active area AA, and a plurality of second plate patterns 123 and a plurality of second conductive patterns 124 disposed in the non-active area NA.The plurality of first plate patterns 121 may be disposed in the active area AA of the lower substrate 111. The plurality of pixels PX may be formed on the plurality of first plate patterns 121. In addition, the plurality of second plate patterns 123 may be disposed in the non-active region NA of the lower substrate 111. In addition, the gate drivers GD and the power supplies PS are formed on the plurality of second plate patterns 123.The plurality of first plate patterns 121 and the plurality of second plate patterns 123 described above may be arranged in the form of islands spaced apart from each other. Each of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be individually cut. Accordingly, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be referred to as first island patterns and second island patterns, or first individual patterns and second individual patterns.Specifically, the gate drivers GD may be mounted on the plurality of second plate patterns 123. The gate driver GD may be formed on the second plate pattern 123 in a gate-in-panel (GIP) method when various components are manufactured on the first plate pattern 121. Accordingly, various circuit components constituting the gate drivers GD, such as various transistors, capacitors, and lines, may be disposed on the plurality of second plate patterns 123. However, the present disclosure is not limited thereto, and the gate driver GD may be mounted in a chip-on-film (COF) method.In addition, the power supplies PS may be mounted on the plurality of second plate patterns 123. The power supply PS may be formed on the second plate pattern 123 with a plurality of power supply blocks patterned when various components are fabricated on the first plate pattern 121. Accordingly, the power blocks disposed on different layers may be disposed on the second plate pattern 123. That is, a lower power block and an upper power block may be sequentially disposed on the second plate pattern 123. In addition, a low potential voltage may be applied to the lower power block and a high potential voltage may be applied to the upper power block. Accordingly, the low potential voltage may be supplied to the plurality of pixels PX through the lower power block. In addition, the high potential voltage may be supplied to the plurality of pixels PX through the upper power block.Referring to FIG. 1, the sizes of the plurality of second plate patterns 123 may be larger than the sizes of the plurality of first plate patterns 121. Specifically, the size of each of the plurality of second plate patterns 123 may be larger than the size of each of the plurality of first plate patterns 121. As described above, the gate driver GD may be disposed on each of the plurality of second plate patterns 123, and a stage of the gate driver GD may be disposed on each of the plurality of second plate patterns 123. Accordingly, since an area occupied by various circuit components constituting a stage of the gate driver GD is larger relative to an area occupied by the pixels PX, the size of each of the plurality of second plate patterns 123 may be larger than the size of each of the first plate patterns 121.In FIG. 1, the plurality of second plate patterns 123 are illustrated as being arranged on both sides in a first direction X in the non-active area NA, but the present disclosure is not limited thereto, and the plurality of second plate patterns 123 may be arranged in any area of the non-active area NA. Although the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are shown in a quadrangular shape, the present disclosure is not limited thereto, and the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are changeable into various shapes.Referring to FIGS. 1 and 3, the pattern layer 120 may further include the plurality of first conductive patterns 122 disposed in the active area AA and the plurality of second conductive patterns 124 disposed in the non-active area NA.The plurality of first conductive patterns 122 are patterns disposed in the active area AA and connect the first plate patterns 121 adjacent to each other, and may be referred to as first conductive patterns. That is, the plurality of first conductive patterns 122 are disposed between the plurality of first plate patterns 121.The plurality of second conductive patterns 124 may be patterns disposed in the non-active area NA and connect the first plate patterns 121 and the second plate patterns 123 adjacent to each other or the plurality of second plate patterns 123 adjacent to each other. Accordingly, the plurality of second conductive patterns 124 may be referred to as second conductive patterns. And the plurality of second conductive patterns 124 may be disposed between the first plate patterns 121 and the second plate patterns 123 adjacent to each other and between the plurality of second plate patterns 123 adjacent to each other.Referring to FIG. 1, the plurality of first conductive patterns 122 and the plurality of second conductive patterns 124 have a waveform. For example, the plurality of first conductive patterns 122 and the plurality of second conductive patterns 124 may have a sine waveform. However, the shapes of the plurality of first conductive patterns 122 and the plurality of second conductive patterns 124 are not limited thereto. For example, the plurality of first conductive patterns 122 and the plurality of second conductive patterns 124 may extend in a zigzag shape. Alternatively, the plurality of first conductive patterns 122 and the plurality of second conductive patterns 124 may have different shapes such as shapes in which a plurality of diamond-shaped substrates are expanded by being connected at vertices thereof. In addition, the number and shapes of the plurality of first conductive patterns 122 and second conductive patterns 124 shown in FIG. 1 are examples, and the number and shapes of the plurality of first conductive patterns 122 and second conductive patterns 124 may be changed in various ways depending on the design.In addition, the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 are rigid patterns. That is, the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be rigid as compared to the lower substrate 111 and the upper substrate 112. Accordingly, the elastic moduli of the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be higher than an elastic modulus of the lower substrate 111. The modulus of elasticity is a parameter representing a strain rate against a mechanical stress applied to the substrate. When the modulus of elasticity is relatively high, the hardness may be relatively high. Accordingly, the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be referred to as a plurality of first rigid patterns, a plurality of second rigid patterns, a plurality of third rigid patterns, and a plurality of fourth rigid patterns, respectively. The elastic moduli of the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be 1000 times higher than the elastic moduli of the lower substrate 111 and the upper substrate 112, but the present disclosure is not limited thereto.The plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124, which are a plurality of rigid substrates, may be formed of a plastic material having flexibility lower than that of the lower substrate 111 and the upper substrate 112. For example, the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be formed of polyimide (PI), polyacrylate, polyacetate, or the like. In this case, the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 may be formed of the same material, but are not limited thereto, and may be formed of different materials. When the plurality of first plate patterns 121, the plurality of first conductive patterns 122, the plurality of second plate patterns 123, and the plurality of second conductive patterns 124 are formed of the same material, they may be integrally formed.In some embodiments, the lower substrate 111 may be defined to have a plurality of first lower patterns and a second lower pattern. The plurality of first lower patterns may be regions of the lower substrate 111 that overlap the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second lower pattern may be an area that does not overlap the plurality of first plate patterns 121 and the plurality of second plate patterns 123.In addition, the upper substrate 112 may be defined to have a plurality of first upper patterns and a second upper pattern. The plurality of first upper patterns may be regions of the upper substrate 112 overlapping the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second upper pattern may be an area that does not overlap the plurality of first plate patterns 121 and the plurality of second plate patterns 123.In this case, the elastic moduli of the plurality of first lower patterns and first upper patterns may be higher than the elastic moduli of the second lower patterns and the second upper patterns. For example, the plurality of first lower patterns and the first upper patterns may be formed of the same material as the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and the second lower pattern and the second upper pattern may be formed of a material having a modulus of elasticity lower than that of the plurality of first plate patterns 121 and the plurality of second plate patterns 123.That is, the first lower pattern and the first upper pattern may be formed of polyimide (PI), polyacrylate, polyacetate, or the like. And the second lower pattern and the second upper pattern may be formed of silicone rubber such as polydimethylsiloxane (PDMS), or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE).Driving Element of Non-Active RegionThe gate drivers GD are components that supply a gate voltage to the plurality of pixels PX arranged in the active area AA. The gate drivers GD include a plurality of stages formed on the plurality of second plate patterns 123, and respective stages of the gate drivers GD may be electrically connected to each other by a plurality of gate connection lines. Accordingly, a gate voltage output from any of the stages can be transmitted to another stage. Further, the respective stages may sequentially supply the gate voltage to the plurality of pixels PX connected to the respective stages.The power supplies PS may be connected to the gate drivers GD and provide a gate driving voltage and a gate clock voltage. Further, the power supplies PS may be connected to the plurality of pixels PX and supply a pixel driving voltage to each of the plurality of pixels PX. The power supplies PS may also be formed on the plurality of second plate patterns 123. That is, the power supplies PS may be formed on the plurality of second plate patterns 123 so as to be adjacent to the gate drivers GD. Further, each of the power supplies PS formed on the plurality of second plate patterns 123 may be electrically connected to the gate driver GD and the plurality of pixels PX. That is, the plurality of power supplies PS formed on the plurality of second plate patterns 123 may be connected by a gate power supply connection line and a pixel power supply connection line. Therefore, each of the plurality of power supplies PS can supply a gate drive voltage, a gate clock voltage, and a pixel drive voltage.The printed circuit board PCB is a component that transmits signals and voltages for driving the display element from a control unit to the display element. Therefore, the printed circuit board PCB may also be referred to as a driving substrate. A control unit such as an IC chip or a circuit may be mounted on the printed circuit board PCB. Further, a memory, a processor, or the like may be mounted on the printed circuit board PCB. Further, the printed circuit board PCB provided in the display device 100 may include an extensible portion and a non-extensible portion to ensure extensibility. In addition, an IC chip, a circuit, a memory, a processor, and the like may be mounted on the non-expandable region, and wires electrically connected to the IC chip, the circuit, the memory, and the processor may be disposed in the expandable region.The data driver DD is a component that supplies a data voltage to the plurality of pixels PX arranged in the active area AA. The data driver DD may be formed in the form of an IC chip and may therefore also be referred to as a data integrated circuit D-IC. Further, the data driver DD may be mounted on the non-expandable portion of the printed circuit board PCB. That is, the data driver DD may be mounted on the printed circuit board PCB in a chip-on-board (COB) form. Although it is illustrated in FIG. 1 that the data driver DD is mounted in a chip-on-board (COB) manner, the present disclosure is not limited thereto, and the data driver DD may be mounted in a chip-on-film (COF) manner, a chip-on-glass (COG) manner, a tape carrier assembly (TCP) manner, or the like.Although it is shown in FIG. 1 that a data driver DD is arranged to correspond to one row of the first disk patterns 121 arranged in the active area AA, the present disclosure is not limited thereto. That is, a data driver DD may be arranged to correspond to a plurality of columns of the first disk patterns 121.Hereinafter, for a more detailed description of the active area AA of the display device 100 according to an exemplary embodiment of the present disclosure, reference will be made collectively to FIGS. 4 and 5.Planar Structures and Cross-Sectional Structures of the Active RegionFIG. 4 is a cross-sectional view taken along the line of intersection IV-IV' shown in FIG. 2.FIG. 5 is a cross-sectional view taken along the line V-V' shown in FIG. 2.Reference is made to FIGS. 1 to 3 together for convenience of description.Referring to FIGS. 1 and 2, the plurality of first plate patterns 121 are disposed on the lower substrate 111 in the active area AA. The plurality of first plate patterns 121 are arranged to be spaced apart from each other on the lower substrate 111. For example, the plurality of first plate patterns 121 may be arranged in a matrix shape on the lower substrate 111 as shown in FIG. 1, but are not limited thereto.Referring to FIGS. 2 and 3, a pixel PX including a plurality of sub-pixels SPX is disposed on the first plate pattern 121. In addition, each of the sub-pixels SPX may include an LED 170 that is a display element, and a driving transistor 160 and a switching transistor 150 for driving the LED 170. However, the display element in the subpixel SPX is not limited to the LED, and may be an organic light emitting diode. Further, the plurality of sub-pixels SPX may include, but are not limited to, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Colors of the plurality of sub-pixels SPX may be changed in various ways as needed.The plurality of sub-pixels SPX may be connected to a plurality of connection lines 181 and 182. That is, the plurality of sub-pixels SPX may be electrically connected to the first connection lines 181 extending in the first direction X. In addition, the plurality of sub-pixels SPX may be electrically connected to the second connection lines 182 extending in a second direction Y.A cross-sectional structure of the active region AA will be described in detail below with reference to FIG. 3.Referring to FIG. 3, a plurality of inorganic insulating layers are disposed on the plurality of first plate patterns 121. For example, the plurality of inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, the present disclosure is not limited thereto. Various inorganic insulating layers may be further disposed on the plurality of first plate patterns 121. One or more of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 which are inorganic insulating layers may be omitted.Specifically, the buffer layer 141 is disposed on the plurality of first plate patterns 121. The buffer layer 141 is formed on the plurality of first plate patterns 121 to protect various components of the display device 100 from the ingress of moisture (H 2 O), oxygen (O 2) or the like from the outside of the lower substrate 111 and the plurality of first plate patterns 121. The buffer layer 141 may be formed of an insulating material. For example, the buffer layer 141 may be formed as a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or the like. However, the buffer layer 141 may be omitted depending on the structure or characteristics of the display device 100.In this case, the buffer layer 141 may be formed only in a region where the buffer layer 141 overlaps the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, the buffer layer 141 may be formed of an inorganic material. Thus, the buffer layer 141 may be easily damaged, for example, easily cracked when the display device 100 is stretched. Therefore, the buffer layer 141 may not be formed in regions between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The buffer layer 141 may be patterned into shapes of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 and may be formed only on upper portions of the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Accordingly, in the display device 100 according to an exemplary embodiment of the present disclosure, the buffer layer 141 is formed only in the region where the buffer layer 141 overlaps the plurality of first plate patterns 121 and the plurality of second plate patterns 123 which are rigid substrates, so that damage to various components of the display device 100 can be prevented even when the display device 100 is deformed, such as bent or stretched.Referring to FIG. 3, the switching transistor 150 including a gate electrode 151, an active layer 152, a source electrode 153, and a drain electrode 154, and the driving transistor 160 including a gate electrode 161, an active layer 162, a source electrode, and a drain electrode 164 are formed on the buffer layer 141.Referring to FIG. 1, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may each be formed of an oxide semiconductor. For example, the active layer 152 may be formed of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.The gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 is configured to electrically isolate the gate electrode 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150 and electrically isolate the gate electrode 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. Further, the gate insulating film 142 may be formed of an insulating material. For example, the gate insulating layer 142 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed on the gate insulating film 142. The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are arranged to be spaced apart from each other on the gate insulating film 142. Further, the gate electrode 151 of the switching transistor 150 overlaps the active layer 152 of the switching transistor 150, and the gate electrode 161 of the driving transistor 160 overlaps the active layer 162 of the driving transistor 160.The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may each be formed of any of various metal materials, for example, any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may each be formed of an alloy of two or more of these or multiple layers thereof, but are not limited thereto.The first interlayer insulating film 143 is disposed on the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160. The first interlayer insulating film 143 isolates the gate electrode 161 of the driving transistor 160 from an inter-metal film IM. The first interlayer insulating layer 143 may also be formed of an inorganic material like the buffer layer 141. For example, the first interlayer insulating film 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.The inter-metal layer IM is disposed on the first inter-layer insulating layer 143. Further, the inter-metal layer IM overlaps the gate electrode 161 of the driving transistor 160. Thus, a storage capacitor is formed in a region where the inter-metal layer IM overlaps the gate electrode 161 of the driving transistor 160. Specifically, the gate electrode 161 of the driving transistor 160, the first interlayer insulating film 143, and the metal interlayer IM constitute the storage capacitor. However, a position of the intermediate metal layer IM is not limited thereto. The inter-metal layer IM may overlap another electrode to variously form a storage capacitor.The intermediate metal layer IM may be formed of any of various metal materials, for example, any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the intermediate metal layer IM may be formed of an alloy of two or more of these or more layers thereof, but is not limited thereto.The second interlayer insulating film 144 is disposed on the intermediate metal film IM. The second interlayer insulating film 144 isolates the gate electrode 151 of the switching transistor 150 from the source electrode 153 and the drain electrode 154 of the switching transistor 150. In addition, the second interlayer insulating film 144 isolates the inter-metal film IM from the source electrode and the drain electrode 164 of the driving transistor 160. The second interlayer insulating layer 144 may also be formed of an inorganic material like the buffer layer 141. For example, the first interlayer insulating film 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.The source electrode 153 and the drain electrode 154 of the switching transistor 150 are disposed on the second interlayer insulating film 144. In addition, the source electrode and the drain electrode 164 of the driving transistor 160 are disposed on the second interlayer insulating film 144. In addition, the source electrode 153 and the drain electrode 154 of the switching transistor 150 are arranged to be spaced apart from each other on the same layer. Although FIG. 1 does not illustrate the source electrode of the driving transistor 160, the source electrode of the driving transistor 160 is also arranged to be spaced apart from the drain electrode 164 of the driving transistor 160 on the same layer. In the switching transistor 150, the source electrode 153 and the drain electrode 154 may be electrically connected to the active layer 152 to be in contact with the active layer 152. In addition, in the driving transistor 160, the source electrode and the drain electrode 164 may be electrically connected to the active layer 162 to be in contact with the active layer 162. Further, the drain electrode 154 of the switching transistor 150 may be electrically connected to the gate electrode 161 of the driving transistor 160 to be in contact with the gate electrode 161 of the driving transistor 160 through a contact hole.The source electrode 153 and the drain electrodes 154 and 164 may be formed of any of various metal materials, for example, any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the source electrode 153 and the drain electrodes 154 and 164 may be formed of an alloy of two or more of these or multiple layers thereof, but are not limited thereto.Further, in the present disclosure, the driving transistor 160 has been described as having a coplanar structure, but various types of transistors having a staggered structure or the like may also be used. In addition, in the present specification, the transistor may be formed not only in an upper gate structure but also in a lower gate structure.A gate pad GP and a data pad DP may be disposed on the second interlayer insulating film 144.Specifically, referring to FIG. 4, the gate pad GP serves to transmit a gate voltage to the plurality of sub-pixels SPX. The gate pad GP is connected to the first connection line 181 through a contact hole. In addition, the gate voltage supplied from the first connection line 181 may be transmitted from the gate pad GP to the gate electrode 151 of the switching transistor 150 through a line formed on the first plate pattern 121.Referring to FIG. 2, the data pad DP serves to transmit a data voltage to the plurality of sub-pixels SPX. The data pad DP is connected to the second connection line 182 through a contact hole. In addition, the data voltage supplied from the second connection line 182 may be transmitted from the data pad DP to the source electrode 153 of the switching transistor 150 through a line formed on the first plate pattern 121.And referring to FIG. 3, a voltage pad VP is a pad for transmitting a low potential voltage to the plurality of sub-pixels SPX. The voltage pad VP is connected to the first connection line 181 through a contact hole. In addition, the low potential voltage supplied from the first connection line 181 may be transmitted from the voltage pad VP to an n-electrode 174 of the LED 170 through a second connection pad CNT 2 formed on the first plate pattern 121.The voltage pad VP, the gate pad GP, and the data pad DP may be formed of the same material as the source electrode 153 and the drain electrodes 154 and 164, but are not limited thereto.Referring to FIG. 1, the passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. The passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect the switching transistor 150 and the driving transistor 160 from the invasion of moisture and oxygen and the like. The passivation layer 145 may be formed of an inorganic material and may be formed as a single layer or multiple layers, but is not limited thereto.In addition, the gate insulating film 142, the first interlayer insulating film 143, the second interlayer insulating film 144, and the passivation film 145 may be patterned and formed only in a region where they overlap the plurality of first plate patterns 121. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be formed of an inorganic material, like the buffer layer 141. Thus, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be easily damaged, for example, easily cracked when the display device 100 is stretched. Therefore, the gate insulating film 142, the first interlayer insulating film 143, the second interlayer insulating film 144, and the passivation film 145 may not be formed in regions between the plurality of first plate patterns 121, and may be patterned into the shapes of the plurality of first plate patterns 121 and may be formed only on upper portions of the plurality of first plate patterns 121.A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 serves to flatten upper portions of the switching transistor 150 and the driving transistor 160. The planarization layer 146 may be formed as a single layer or multiple layers and may be formed of an organic material. Thus, the planarization layer 146 may also be referred to as an organic insulating layer. For example, the planarization layer 146 may be formed of an acrylic-based organic material, but is not limited thereto.Referring to FIG. 3, the planarization layer 146 may be disposed on the plurality of first plate patterns 121 to cover upper surfaces and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. In addition, the planarization layer 146 surrounds the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 together with the plurality of first plate patterns 121. Specifically, the planarization layer 146 may be disposed to cover a top surface and a side surface of the passivation layer 145, a side surface of the first interlayer insulating layer 143, a side surface of the second interlayer insulating layer 144, a side surface of the gate insulating layer 142, a side surface of the buffer layer 141, and a part of top surfaces of the plurality of first plate patterns 121. Thus, the planarization layer 146 may compensate steps between the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, and may improve the adhesion strength between the planarization layer 146 and the connection lines 181 and 182 disposed on side surfaces of the planarization layer 146.Referring to FIG. 3, an inclination angle of the side surface of the planarization layer 146 may be smaller than those of the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 may have a lighter inclination than the side surface of the passivation layer 145, the side surface of the first interlayer insulating layer 143, the side surface of the second interlayer insulating layer 144, the side surface of the gate insulating layer 142, and the side surface of the buffer layer 141. Thus, the connection lines 181 and 182 are disposed in contact with the side surfaces of the planarization layer 146 so as to have a slight inclination. Therefore, when the display device is stretched, a stress generated in the connection lines 181 and 182 can be reduced. In addition, it is possible to suppress cracks in the connection lines 181 and 182 or peeling of the connection lines 181 and 182 from the side surface of the planarization layer 146.Referring to FIGS. 2 to 4, the connection lines 181 and 182 refer to lines that electrically connect the pads disposed on the plurality of first plate patterns 121. The plurality of connection lines 181 and 182 are disposed on the plurality of first line patterns 122. In this way, the plurality of connection lines 181 and 182 disposed on the first plate patterns 121 may also extend on the plurality of first plate patterns 121 to be electrically connected to the gate pad GP and the data pad DP on the plurality of first plate patterns 121. In addition, referring to FIG. 1, the first wiring pattern 122 is not disposed in a region between the plurality of first plate patterns 121 in which the connection wirings 181 and 182 are not disposed.The connection lines 181 and 182 include the first connection lines 181 and the second connection lines 182. The first connection lines 181 and the second connection lines 182 are disposed between the plurality of first plate patterns 121. Specifically, the first connection lines 181 refer to lines among the connection lines 181 and 182 extending in an X-axis direction X between the plurality of first plate patterns 121. The second connection lines 182 refer to lines among the connection lines 181 and 182 extending in a Y-axis direction between the plurality of first plate patterns 121.The connection lines 181 and 182 may be formed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or the connection lines 181 and 182 may have a laminated structure of metal materials such as copper / molybdenum titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), or the like, but are not limited thereto.In a display panel of a general display device, various lines such as a plurality of gate lines and a plurality of data lines extend in straight lines and are arranged between a plurality of sub-pixels, and the plurality of sub-pixels are connected to a single signal line. Therefore, in the display panel of the general display device, various lines such as a gate line, a data line, a high potential voltage line, and a reference voltage line extend continuously on a substrate from one side to the other side of the display panel of an organic light emitting display device.In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, various lines such as a gate line, a data line, a high potential voltage line, a reference voltage line, an initialization voltage line, and the like, which are formed in straight lines and are considered to be used in a display panel of a general organic light emitting display device, are disposed only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123. In the display device 100 according to an exemplary embodiment of the present disclosure, lines formed in straight lines are disposed only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123.In the display device 100 according to an exemplary embodiment of the present disclosure, the pads on two adjacent first plate patterns 121 may be connected by the connection lines 181 and 182. Accordingly, the connection lines 181 and 182 electrically connect the gate pads GP or the data pads DP on the two adjacent first plate patterns 121. Therefore, the display device 100 according to an exemplary embodiment of the present disclosure may include the plurality of connection lines 181 and 182 to electrically connect various lines such as a gate line, a data line, a high potential voltage line, and a reference voltage line between the plurality of first plate patterns 121. For example, gate lines may be disposed on the plurality of first plate patterns 121 adjacent to each other in the first direction X. In addition, the gate pads GP may be disposed at both ends of the gate lines. In this case, a plurality of gate pads GP on the plurality of first plate patterns 121 arranged adjacent to each other in the first direction X may be connected to each other by the first connection lines 181 serving as the gate lines. Therefore, the gate lines disposed on the plurality of first plate patterns 121 and the first connection lines 181 disposed on the second plate patterns 123 may serve as single gate lines. The gate lines described above may be referred to as scan signal lines. Further, lines such as an emission signal line, a low potential voltage line, and a high potential voltage line extending in the first direction X among all the various lines that may be included in the display device 100 may also be electrically connected by the first connection lines 181 as described above.Referring to FIGS. 2 and 4, the first connection lines 181 may connect the gate pads GP on two first plate patterns 121 arranged side by side among the gate pads GP on the plurality of first plate patterns 121 adjacent to each other in the first direction X. The first connection line 181 may serve as a gate line, an emission signal line, a high potential voltage line, or a low potential voltage line, but is not limited thereto. For example, the first connection line 181 may serve as a gate line and may electrically connect the gate pads GP on the two first plate patterns 121 arranged side by side in the first direction X. Accordingly, as described above, the gate pads GP on the plurality of first plate patterns 121 arranged in the first direction X may be connected by the first connection lines 181 serving as the gate lines. A single gate voltage may be transmitted to the gate pads GP.Further, referring to FIG. 2, the second connection lines 182 may connect the data pads DP on two first plate patterns 121 arranged side by side among the data pads DP on the plurality of first plate patterns 121 arranged adjacent to each other in the second direction Y. The second connection line 182 may serve as a data line, a high-potential voltage line, a low-potential voltage line, or a reference voltage line, but is not limited thereto. For example, the second connection line 182 may serve as a data line, and may electrically connect the data pads DP on the two first plate patterns 121 arranged side by side in the second direction Y. Accordingly, as described above, internal lines on the plurality of first plate patterns 121 arranged in the second direction Y may be connected by a plurality of second connection lines 182 serving as the data lines. A single data voltage may be transmitted thereto.As shown in FIG. 4, the first connection line 181 may be in contact with a top surface and the side surface of the planarization layer 146 disposed on the first plate pattern 121, and may extend to a top surface of the first line pattern 122. In addition, as shown in FIG. 1, the second connection line 182 may be disposed to be in contact with the upper surface and the side surface of the planarization layer 146 disposed on the first plate pattern 121, and may extend to the upper surface of the first line pattern 122.However, as shown in FIG. 5, there is no need to arrange a rigid pattern in a region where the first connection line 181 and the second connection line 182 are not arranged. Thus, the first conductive pattern, which is a rigid pattern, is not disposed under the first connection line 181 and the second connection line 182.Meanwhile, referring to FIG. 3, a bank 147 is formed on a first connection pad CNT 1, the connection lines 181 and 182, and the planarization layer 146. The bank 147 is a component for discriminating adjacent sub-pixels SPX. The bank 147 is disposed to cover at least a part of the pad PD, the connection lines 181 and 182, and the planarization layer 146. The bank 147 may be formed of an insulating material. Further, the bank 147 may contain a black material. Since bank 147 contains a black material, bank 147 serves to hide lines visible through active area AA. The bank 147 may be formed of, for example, a transparent carbon-based mixture. In particular, bank 147 may include, but is not limited to, carbon black. The bank 147 may also be formed of a transparent insulating material. Although a height of the bank 147 in FIG. 1 is lower than a height of the LED 170, the height of the bank 147 is not limited thereto, and the height of the bank 147 may be equal to the height of the LED 170.Referring to FIG. 3, the LED 170 is disposed on the first connection pad CNT 1 and a second connection pad CNT 2. The LED 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The LED 170 of the display device 100 according to an exemplary embodiment of the present disclosure has a flip-chip structure in which the n-electrode 174 and the p-electrode 175 are formed on a surface thereof.The n-type layer 171 may be formed by injecting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer 171 may be disposed on a separate base substrate formed of a light emitting material.The active layer 172 is disposed on the n-type layer 171. The active layer 172 is a light emitting layer that emits light into the LED 170, and may be formed of a nitride semiconductor, for example, indium gallium nitride (InGaN). The p-type layer 173 is disposed on the active layer 172. The p-type layer 173 may be formed by injecting p-type impurities into gallium nitride (GaN).As described above, the LED 170 according to an exemplary embodiment of the present disclosure is manufactured by sequentially laminating the n-type layer 171, the active layer 172, and the p-type layer 173 and then etching a predetermined portion of the layers to thereby form the n-electrode 174 and the p-electrode 175. In this case, the predetermined region is a space for separating the n-electrode 174 and the p-electrode 175 from each other, and is etched to expose a part of the n-type layer 171. In other words, a surface of the LED 170 on which the n-electrode 174 and the p-electrode 175 are to be disposed may not be flat and may have different heights.In this way, the n-electrode 174 is disposed in the etched region, and the n-electrode 174 may be formed of a conductive material. In addition, the p-electrode 175 is disposed in an unetched region, and the p-electrode 175 may be formed of a conductive material. For example, the n-electrode 174 is disposed on the n-type layer 171 exposed by an etching process, and the p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 may be formed of the same material as the n-electrode 174.An adhesive layer AD is disposed on upper surfaces of the first connection pad CNT 1 and the second connection pad CNT 2 and between the first connection pad CNT 1 and the second connection pad CNT 2. Thus, the LED 170 may be bonded on the first connection pad CNT 1 and the second connection pad CNT 2. In this case, the n-electrode 174 may be disposed on the second connection pad CNT 2, and the p-electrode 175 may be disposed on the first connection pad CNT 1.The adhesive layer AD may be a conductive adhesive layer formed by dispersing conductive balls in an insulating base member. Thus, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected to have conductive properties in a portion of the adhesive layer AD to which heat or pressure is applied. In addition, a portion of the adhesive layer AD to which no pressure is applied may have insulating properties. For example, the n-electrode 174 is electrically connected to the second pad CNT 2 through the adhesive layer AD, and the p-electrode 175 is electrically connected to the first pad CNT 1 through the adhesive layer AD. After the adhesion layer AD is applied to upper surfaces of the second bonding pad CNT 2 and the first bonding pad CNT 1 by an inkjet method or the like, the LED 170 may be transferred to the adhesion layer AD. Then, the LED 170 may be pressed and heated to thereby electrically connect the first connection pad CNT 1 to the p-electrode 175 and the second connection pad CNT 2 to the n-electrode 174. However, other portions of the adhesion layer AD except a portion of the adhesion layer AD disposed between the n-electrode 174 and the second connection pad CNT 2 and a portion of the adhesion layer AD disposed between the p-electrode 175 and the first connection pad CNT 1 have insulating properties. Meanwhile, the adhesive layer AD may be separately disposed on each of the first connection pad CNT 1 and the second connection pad CNT 2.Further, the first connection pad CNT 1 is electrically connected to the drain electrode 164 of the driving transistor 160 and receives a driving voltage for driving the LED 170 from the driving transistor 160. Although FIG. 3 shows that the first connection pad CNT 1 and the drain electrode 164 of the driving transistor 160 are indirectly connected to each other without directly contacting them, the present disclosure is not limited thereto, and the first connection pad CNT 1 and the drain electrode 164 of the driving transistor 160 may be in direct contact. In addition, a low potential driving voltage for driving the LED 170 is applied to the second connection pad CNT 2. Accordingly, when the display device 100 is turned on, different voltage levels applied to the first connection pad CNT 1 and the second connection pad CNT 2 are transmitted to the n-electrode 174 and the p-electrode 175, respectively, so that the LED 170 emits light.The upper substrate 112 serves to support various components disposed below the upper substrate 112. Specifically, the upper substrate 112 may be formed by coating a material for forming the upper substrate 112 on the lower substrate 111 and the first plate patterns 121 and curing. The upper substrate 112 may be disposed to be in contact with the lower substrate 111, the first plate patterns 121, the first wiring pattern 122, and the connection wirings 181 and 182.The upper substrate 112 may be formed of the same material as the lower substrate 111. For example, the upper substrate 112 may be formed of silicone rubber such as polydimethylsiloxane (PDMS), or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE). Thus, the upper substrate 112 may be flexible. However, the materials of the upper substrate 112 are not limited thereto.Although not shown in FIG. 3, a polarizing layer may be disposed on the upper substrate 112. The polarizing layer polarizes light incident from the outside of the display device and reduces the reflection of external light. Further, instead of the polarizing layer, other optical films or the like may be disposed on the upper substrate 112.In addition, the filling layer 190 disposed on an entire surface of the lower substrate 111 and filling a gap between components disposed on the upper substrate and the lower substrate 111112 may be disposed. The fill layer 190 may be formed of a curable adhesive. Specifically, a material for forming the filling layer 190 is applied to the entire surface of the lower substrate 111 and then cured so that the filling layer 190 can be disposed between components disposed on the upper substrate 112 and the lower substrate 111. For example, the fill layer 190 may be an optically clear adhesive (OCA), and may include an acrylic adhesive, a silicone adhesive, and a urethane adhesive.Circuit Structure and Driving Method of Active AreaFIG. 6 is a circuit diagram of a sub-pixel of the display device according to an exemplary embodiment of the present disclosure.Hereinafter, for convenience of explanation, a structure and an operation of the subpixel SPX of the display device according to an exemplary embodiment of the present disclosure will be described in a case where the subpixel SPX is a 2T1C pixel circuit (2-transistor-1-capacitor pixel circuit), but the present disclosure is not limited thereto.Referring to FIGS. 3 and 6, the sub-pixel SPX of the display device according to an exemplary embodiment of the present disclosure may be configured to include the switching transistor 150, the driving transistor 160, a storage capacitor C, and the LED 170.The switching transistor 150 applies a data signal DATA supplied via the second connection line 182 to the driving transistor 160 and the storage capacitor C according to a gate signal SCAN supplied via the first connection line 181.In addition, the gate electrode 151 of the switching transistor 150 is electrically connected to the first connection line 181, the source electrode 153 of the switching transistor 150 is connected to the second connection line 182, and the drain electrode 154 of the switching transistor 150 is connected to the gate electrode 161 of the driving transistor 160.The driving transistor 160 may operate such that a driving current may flow according to the data voltage DATA and a high potential power VDD supplied through the first connection line 181 in response to the data voltage DATA stored in the storage capacitor C.In addition, the gate electrode 161 of the driving transistor 160 is electrically connected to the drain electrode 154 of the switching transistor 150, the source electrode of the driving transistor 160 is connected to the first connection line 181, and the drain electrode 164 of the driving transistor 160 is connected to the LED 170.The LED 170 may operate to emit light according to the driving current formed by the driving transistor 160. And, as described above, the n-electrode 174 of the LED 170 may be connected to the first connection line 181 and receive a low potential power VSS, and the p-electrode 175 of the LED 170 may be connected to the drain electrode 164 of the transistor 160 and receive a drive voltage corresponding to the drive current.The subpixel SPX of the display device according to an exemplary embodiment of the present disclosure is configured to have a 2T1C structure including the switching transistor 150, the driving transistor 160, the storage capacitor C, and the LED 170, but in a case where a compensation circuit is added, may be configured to have various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.As described above, the display device according to an exemplary embodiment of the present disclosure may include a plurality of sub-pixels on a first substrate that is a rigid substrate, and each of the plurality of sub-pixels may be configured to include a switching transistor, a driving transistor, a storage capacitor, and an LED.Accordingly, the display device according to an exemplary embodiment of the present disclosure may be stretched by a lower substrate, and also includes a pixel circuit of a 2T1C structure on each first substrate so as to be capable of emitting light depending on a data voltage according to each gate timing.Shape of Connection LinesFIG. 7 is a view illustrating connection lines of the display device according to an exemplary embodiment of the present disclosure. FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7.The first connection line and the second connection line shown in FIGS. 7 and 8 are different only in arrangement directions thereof and have substantially the same shape. Therefore, the first connection line will be described in detail with reference to FIGS. 7 and 8.Referring to FIG. 7, each of the plurality of first conductive patterns 122 and the plurality of first connection lines 181- 1 and 181- 2 has a waveform. As described above, each of the plurality of first conductive patterns 122 and the plurality of first connection lines 181- 1 and 181- 2 may have different shapes such as a sine wave shape, a zigzag shape, and the like.Accordingly, each of the plurality of first conductive patterns 122 and each of the plurality of first connection lines 181- 1 and 181- 2 may include a straight portion SA and a curved portion CA. That is, a region in which each of the plurality of first conductive patterns 122 and each of the plurality of first connection conductive lines 181- 1 and 181- 2 are arranged may be divided into a straight region SA and a curved region CA. In the straight region SA, each of the plurality of first conductive patterns 122 and each of the plurality of first connection conductive lines 181- 1 and 181- 2 may extend in a straight line without being bent. In addition, in the curved region CA, each of the plurality of first lead patterns 122 and each of the plurality of first connection leads 181- 1 and 181- 2 does not extend in a straight line, but may be bent with a predetermined curvature. In FIG. 7, each of the plurality of first conductive patterns 122 and each of the plurality of first connection conductive lines 181- 1 and 181- 2 is shown as bent while maintaining a constant curvature in the curved region CA. As illustrated, the plurality of connection lines 181- 1 and 181- 2 (or the plurality of line patterns 122) have a first curvature that is constant within the curved region CA. The straight portion SA is continuous with the curved portion CA. The straight region SA has a second curvature which is also constant within the straight region SA. In the straight region SA, the second curvature is zero because a curvature of a straight line is zero. The first curvature in the curvature region CA, on the other hand, has a curvature that is greater than zero. A curvature may be determined based on the following formula R=1 / K, where R is the radius of curvature and K is the curvature.However, the present disclosure is not limited thereto, and each of the plurality of first conductive patterns 122 and each of the plurality of first connection conductive lines 181- 1 and 181- 2 may be bent while maintaining a variable curvature or may be curved at a certain angle in the curved region CA depending on the design requirement.Referring to FIGS. 7 and 8, a plurality of connection lines may be disposed on a first line pattern 122. Specifically, a 1-1 connection line 181- 1 and a 1-2 connection line 181- 2 may be disposed on a first line pattern 122 in the straight region SA and the curved region CA, respectively. In other words, on a first line pattern 122, a one-side connection line corresponding to the 1-1 connection line 181- 1 and a other-side connection line corresponding to the 1-2 connection line 181- 2 may be disposed. The 1-1 connection line 181- 1 and the 1-2 connection line 181- 2 arranged on a first line pattern 122 may be arranged at a predetermined interval and with the same shape.In addition, the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2 disposed on a first line pattern 122 may transmit different voltages. For example, when the 1-1 connection line 181- 1 serves as a gate line that transmits a gate voltage, the 1-2 connection line 181- 2 may be a high potential voltage line that transmits a high potential voltage. However, the functions of the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2 disposed on a first line pattern 122 are not limited thereto, and may be variously changed depending on the design need.In FIG. 7, the first connection line will be described in detail, and the second connection line will not be specifically illustrated. However, the second connection line may also include a 2-1 connection line and a 2-2 connection line arranged on a first line pattern in the same manner as the first connection line. In addition, the 2-1 connection line and the 2-2 connection line arranged on a first line pattern may be arranged at a predetermined interval and with the same shape.That is, in the display device according to an exemplary embodiment of the present disclosure, the plurality of connection lines 181- 1 and 181- 2 having the same shape may be disposed on a first line pattern 122.In contrast, in a conventional display device, only one connecting line was arranged on one line pattern. Accordingly, when the conventional display device was stretched, a stretching stress applied to a plurality of connecting wires in a curved region was measured to be 11.36 MPa at the maximum. As a result, in the conventional display device, the probability of occurrence of cracks in the plurality of connection lines is high, and thus there is a disconnection defect.In contrast, in the display device according to an exemplary embodiment of the present disclosure, a plurality of connection lines are arranged on a line pattern, so that the plurality of connection lines arranged on a line pattern distribute a tensile stress applied in a curved region. That is, the tensile stress applied to each of the plurality of connection wires arranged on a wire pattern can be reduced. Thus, when the display device according to an exemplary embodiment of the present disclosure is stretched, the stretching stress applied to each of the plurality of connection wires was measured to be 7.5 MPa at the maximum. That is, the stress of strain applied to each of the plurality of connection pipes was reduced to 66 % at the maximum at the same strain rate. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, a disconnection defect of the connection lines may be solved. This can improve the extension reliability of the display device.In addition, in the conventional display device, only one connection line is arranged on one line pattern, and a number of line patterns equal to the number of connection lines is required to connect adjacent board patterns. Accordingly, in the conventional display device, a ratio of a length of the connection line in an extension direction before extension to a length of the connection line in the extension direction after extension was measured to be 2.16 times.However, in the display device according to an exemplary embodiment of the present disclosure, the number of line patterns connecting adjacent plate patterns may be reduced by arranging a plurality of connection lines on one line pattern. Accordingly, a length of a straight portion of a line pattern can be increased. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, a ratio of a length of the connection line in an extension direction before extension to a length of the connection line in the extension direction after extension was measured 2.84 times. That is, it was confirmed that the strain rate was improved in the display device according to an exemplary embodiment of the present disclosure.Next, a display device according to another exemplary embodiment of the present disclosure will be described. Since differences exist between the display device according to another exemplary embodiment of the present disclosure and the display device according to an exemplary embodiment of the present disclosure only with respect to a buffer hole, this will be described in detail. In addition, in the display device according to another exemplary embodiment of the present disclosure and the display device according to an exemplary embodiment of the present disclosure, the same reference numerals are used for the same components, and detailed description thereof will be omitted.Other Exemplary Embodiment of the Present DisclosureFIG. 9 is a view showing connection lines of a display device according to another exemplary embodiment of the present disclosure.FIGS. 10A and 10B are cross-sectional views taken along the line X-X' of FIG. 9.The first connection line and the second connection line shown in FIGS. 9 and 10A and 10B differ only in arrangement directions thereof and have substantially the same shape. Therefore, the first connection line will be described in detail with reference to FIGS. 9 and 10A and 10B.Referring to FIGS. 9 and 10A and 10B, a first conductive pattern 222 in the curved region CA includes at least one buffer hole 222 h. The at least one buffer hole 222 hformed in the curved region CA is formed so as not to overlap the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2. That is, the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2 are formed only on some areas of the first line pattern 222 in which the at least one buffer hole 222 his not disposed.Specifically, as shown in FIG. 9, the at least one buffer hole 222 hmay be disposed between the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2. Alternatively, the at least one buffer hole 222 hmay be disposed outside the 1-1 connection line 181- 1 and the 1-2 connection line 181- 2. In other words, the at least one buffer hole 222 hmay be arranged on one side of the 1-1 connection line 181- 1 and / or the other side of the 1-2 connection line.In FIG. 10A, in the curved region CA, a buffer hole 222 his formed in a portion of the first conductive pattern 222. In an embodiment, the buffer hole 222 hextends through the first conductive pattern 222 and exposes an upper surface of the lower substrate 111. Here, the buffer hole 222 his located between the connection line 181- 2 and the connection line 181- 1, and does not overlap with the connection lines 181- 1, 181- 2. Further, as shown, the buffer hole 222 his not formed within the first line pattern 222 in the straight region SA, and therefore, the buffer hole 222 his not present in the straight region SA in the illustrated embodiment.On the other hand, as shown in FIGS. 9 and 10A and 10B, in the straight region SA, at least one buffer hole 222 his not formed in the first conductive pattern 222.As shown in FIG. 10A, a filler may not be disposed in the at least one buffer hole 222 h. In other words, an interior of the at least one buffer hole 222 hmay be an empty space.Alternatively, as shown in FIG. 10B, a filling member FM having a lower elastic modulus than that of the first conductive pattern 222 may be disposed inside the at least one buffer hole 222 h. That is, the filling member FM may be formed of silicone rubber such as polydimethylsiloxane (PDMS), or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE).That is, in the display device according to another exemplary embodiment of the present disclosure, the filler FM serving as a buffer may be disposed between the plurality of connection lines 181- 1 and 181- 2 in the curved region CA.Accordingly, in the display device according to another exemplary embodiment of the present disclosure, the buffer hole and the filling member distribute the tensile stress applied in the curved portion. Specifically, when the display device according to another exemplary embodiment of the present disclosure is stretched, the stretching stress applied to each of the plurality of connection wires was measured to be 4.7 MPa at the maximum. That is, the stress applied to each of the plurality of connection wires was reduced to 41 % at the maximum at the same strain rate. Accordingly, in the display device according to another exemplary embodiment of the present disclosure, a disconnection failure of the connection lines can be more effectively solved.In contrast, as shown in FIG. 10B, a filler FM having an elastic modulus equal to or higher than that of the first conductive pattern 222 may be disposed inside the at least one buffer hole 222 h. That is, the filling member FM may be formed of polyimide (PI), polyacrylate, polyacetate, or the like.That is, in the display device according to another exemplary embodiment of the present disclosure, the filler FM serving to limit the strain may be disposed between the plurality of connection lines 181- 1 and 181- 2 in the curved region CA.In one embodiment, the filling member FM fills the space defined by the buffer hole 222 h. Here, an upper surface TS_FM of the filler FM is flush with an upper surface TS_LP of the first conductive pattern 222. However, this is merely an example, and in other embodiments, the top surface TS_FM of the filler FM may not be flush with the top surface TS_LP of the first conductive pattern 222. For example, the upper surface TS_FM of the filler FM may be lower than the upper surface TS_LP of the first conductive pattern 222.Accordingly, in the display device according to another exemplary embodiment of the present disclosure, the buffer hole and the filling member may limit an amount of expansion of the curved portion. In particular, when the display device according to another exemplary embodiment of the present disclosure is stretched, a degree of stretching of the filling member FM having a high modulus of elasticity is relatively small, and accordingly, the degree of stretching of the connection lines can also be limited. Accordingly, in the display device according to another exemplary embodiment of the present disclosure, the degree of extension of the connection lines is reduced, so that the disconnection defect of the connection lines can be prevented.Next, a display device according to still another exemplary embodiment of the present disclosure will be described. Since differences exist between the display device according to still another exemplary embodiment of the present disclosure and the display device according to another exemplary embodiment of the present disclosure only with respect to buffer holes, they will be described in detail. In addition, in the display device according to still another exemplary embodiment of the present disclosure and the display device according to another exemplary embodiment of the present disclosure, the same reference numerals are used for the same components, and detailed description thereof will be omitted.Still another Embodiment of the Present DisclosureFIG. 11 is a view illustrating connection lines of a display device according to still another exemplary embodiment of the present disclosure.Referring to FIG. 11, a plurality of connection lines may be disposed on a first line pattern 322. Specifically, a 1-1 connection line 381- 1, a 1-2 connection line 381- 2, and a 1-3 connection line 381- 3 may be sequentially arranged on a first line pattern 322 in each of the straight region SA and the curved region CA. In other words, on a first line pattern 322, a one-side connection line corresponding to the 1-1 connection line 381- 1, an intermediate connection line corresponding to the 1-2 connection line 381- 2, and an other-side connection line 1- 3 corresponding to the 1-3 connection line 381- 3 may be disposed. The 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3 arranged on a first line pattern 322 may be arranged at a predetermined interval and with the same shape.In addition, the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3 disposed on a first line pattern 322 may transmit different voltages. For example, when the 1-1 connection line 381- 1 serves as a gate line that transmits a gate voltage, the 1-2 connection line 381- 2 may be a high potential voltage line that transmits a high potential voltage, and the 1-3 connection line 381- 3 may be a low potential voltage line that transmits a low potential voltage. However, functions of the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3 disposed on a first line pattern 322 are not limited thereto, and may be variously changed depending on design needs.In FIG. 11, the first connection line has been described in detail, and the second connection line is not specifically illustrated. However, the second connection line may also include a 2-1 connection line, a 2-2 connection line, and a 2-3 connection line, which are arranged on a first line pattern in the same manner as the first connection line. In addition, the 2-1 connection line, the 2-2 connection line, and the 2-3 connection line arranged on a first line pattern may be arranged at a predetermined interval and with the same shape.In addition, since the first conductive pattern 322 is curved with a constant curvature in the curved region CA, the first conductive pattern 322 can form a neutral plane NP in the curved region CA.As described above, the neutral plane NP may be a virtual plane that is not subjected to mechanical stress because the pressing force and the pulling force applied to the first conductive pattern 322 cancel each other out when the first conductive pattern 322 is stretched. Accordingly, in order to reduce or minimize the pressing force and the pulling force applied to the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3, the 1-2 connection line 381- 2 may be positioned on the neutral plane NP. Accordingly, by overlapping the 1-2 connection line 381- 2 and the neutral plane NP, cracks occurring in the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3 can be reduced or minimized.In addition, the first conductive pattern 322 includes at least one or more buffer holes 322 h- 1 and 322 h- 2 in the curved region CA in the display device according to still another exemplary embodiment of the present disclosure. The at least one or more buffer holes 322 h- 1 and 322 h- 2 formed in the curved region CA are formed so as not to overlap the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line. That is, the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3 are disposed only on some areas of the first line pattern 322 in which at least one or the plurality of buffer holes 322 h- 1 and 322 h- 2 are not disposed.Specifically, as shown in FIG. 11, the at least one or more buffer holes 322 h- 1 and 322 h- 2 include a first buffer hole 322 h- 1 and a second buffer hole 322 h- 2. The first buffer hole 322 h- 1 may be disposed between the 1-1 connection line 381- 1 and the 1-2 connection line 381- 2, and the second buffer hole 322 h- 2 may be disposed between the 1-2 connection line 381- 2 and the 1-3 connection line 381- 3. Alternatively, the at least one or more buffer holes 322 h- 1 and 322 h- 2 may be disposed outside the 1-1 connection line 381- 1, the 1-2 connection line 381- 2, and the 1-3 connection line 381- 3. In other words, the at least one or more buffer holes 322 h- 1 and 322 h- 2 may be disposed on one side of the 1-1 connection line 381- 1 and / or the other side of the 1-3 connection line 381- 3.In addition, the first buffer hole 322 h- 1 and the second buffer hole 322 h- 2 may be respectively formed to be adjacent to the 1-2 connection line 381- 2. Specifically, the first buffer hole 322 h- 1 may be disposed closer to the 1-2 connection line 381- 2 than the 1-1 connection line 381- 1, and the second buffer hole 322 h- 2 may be disposed closer to the 1-2 connection line 381- 2 than the 1-3 connection line 381- 3.More specifically, a distance D 2 between the first buffer hole 322 h- 1 and the 1-2 connection line 381- 2 is shorter than a distance D 1 between the first buffer hole 322 h- 1 and the 1-1 connection line 381- 1.By disposing the first buffer hole 322 h- 1 and the second buffer hole 322 h- 2 in the above-described shape, the strength of an inner region in the first line pattern 322 in which the 1-1 connection line 381- 1 is disposed and an outer region in the first line pattern 322 in which the 1-3 connection line 381- 3 is disposed can increase. The extension stress concentrates on the inner region and the outer region of the first conductive pattern when the display device is extended. Thus, by increasing the strength of the inner portion and the outer portion of the first conductive pattern 322 by the above-described arrangement of the first buffer hole 322 h- 1 and the second buffer hole 322 h- 2, the reliability of the display device can be improved.On the other hand, as shown in FIG. 11, in the straight region SA, at least one or more buffer holes 322 h- 1 and 322 h- 2 are not formed in the first conductive pattern 322.Meanwhile, no filling member may be disposed in the at least one buffer hole or the plurality of buffer holes 322 h- 1 and 322 h- 2. In other words, an interior of the at least one buffer hole 322 h- 1 and 322 h- 2 may be an empty space.Alternatively, the inside of the at least one buffer hole 322 h- 1 and 322 h- 2 may be filled with a filling member having a modulus of elasticity lower than that of the first conductive pattern 322. That is, it may be formed of silicone rubber such as polydimethylsiloxane (PDMS), or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE).That is, in the display device according to still another exemplary embodiment of the present disclosure, a filling member serving as a buffer may be disposed between the plurality of connection lines 381- 1 and 181- 2 in the curved region CA.Accordingly, in the display device according to still another exemplary embodiment of the present disclosure, the buffer hole and the filling member may distribute a tensile stress applied in the curved portion.In contrast, a filling member having a modulus of elasticity greater than or equal to that of the first conductive pattern 322 may be disposed within the at least one buffer hole 322 h- 1 and 322 h- 2. That is, the filling member FM may be formed of polyimide (PI), polyacrylate, polyacetate, or the like.That is, in the display device according to still another exemplary embodiment of the present disclosure, a filler member serving to limit the strain may be disposed between the plurality of connection lines 381- 1 and 181- 2 in the curved region CA.Accordingly, in the display device according to still another exemplary embodiment of the present disclosure, a degree of extension of the connection lines is reduced, so that a disconnection defect of the connection lines can be prevented.The exemplary embodiments of the present disclosure may also be described as follows:A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a pattern layer disposed on the lower substrate and having a plurality of plate patterns and a plurality of line patterns; a plurality of pixels disposed on each of the plurality of plate patterns; and a plurality of connection lines connecting the plurality of pixels, the plurality of connection lines being disposed on each of the plurality of line patterns, so that the stretching reliability may be improved.The plurality of connection lines arranged on each of the plurality of line patterns may transmit different voltages.Each of the plurality of line patterns may include a straight portion extending in a straight line and a curved portion extending in a curved line.In the curved portion of each of the plurality of lead patterns, a buffer hole that may not overlap the plurality of connection leads is formed.The buffer hole may be filled with a filling member having a modulus of elasticity lower than a modulus of elasticity of the plurality of conductive patterns.The buffer hole may be filled with a filling member having a modulus of elasticity greater than or equal to a modulus of elasticity of the plurality of conductive patterns.The plurality of connection lines arranged on each of the plurality of line patterns may include one side connection line and another side connection line.At least one buffer hole may be formed between the connection line on the one side and the connection line on the other side.The at least one buffer hole may be filled with an elastic polymer.The plurality of connection lines arranged on each of the plurality of line patterns include:a one-side connection line, an intermediate connection line, and another-side connection line, which may be arranged one after another.A first buffer hole may be formed between the one-side connection line and the intermediate connection line, and a second buffer hole is formed between the intermediate connection line and the other-side connection line.The first buffer hole may be disposed closer to the interconnection line than the one-side interconnection line, and the second buffer hole is disposed closer to the interconnection line than the other-side interconnection line.The first buffer hole and the second buffer hole are each filled with a filling member having a modulus of elasticity lower than a modulus of elasticity of the plurality of conductive patterns.The first buffer hole and the second buffer hole are each filled with a filling member having a modulus of elasticity greater than or equal to a modulus of elasticity of the plurality of conductive patterns.The interconnection line may overlap a neutral plane of a curved portion of each of the plurality of line patterns.

Claims

A display device (100) comprising: a stretchable substrate (111); a pattern layer (120) disposed on the substrate (111) and having a plurality of plate patterns (121) and a plurality of line patterns (122, 222, 322); a plurality of pixels (SPX) disposed on each of the plurality of plate patterns (121); a plurality of connection lines (181, 182) coupling the plurality of pixels (SPX), wherein the plurality of connection lines (181, 182) are disposed on each of the plurality of line patterns (122, 222); and a buffer hole (222h) disposed so as not to overlap the plurality of connection wires (181), wherein the buffer hole (222h) is filled with a filling member (FM) having an elastic modulus greater than or equal to an elastic modulus of the plurality of wire patterns (222).The display device of claim 1, wherein the plurality of connection lines arranged on each of the plurality of line patterns transmit different voltages.The display device according to claim 1 or 2, wherein each of the plurality of conduction patterns has a straight portion extending in a straight line and a curved portion extending in a curved line.The display device according to any one of the preceding claims, wherein the plurality of connection lines (181) arranged on each of the plurality of line patterns (222) include one-side connection line (181-1) and another-side connection line (181-2).The display device according to claim 4, wherein at least one buffer hole (222h) is formed between the one-side connection line (181-1) and the other-side connection line (181-2).The display device according to any one of the preceding claims, wherein the plurality of connection lines arranged on each of the plurality of line patterns (322) includes one-side connection line (381-1), an intermediate connection line (381-2), and another-side connection line (381-3) arranged one after another.The display device of claim 6, wherein a first buffer hole (322h-1) is formed between the one-side connection line (381-1) and the intermediate connection line (381-2), and wherein a second buffer hole (322h-2) is formed between the intermediate connection line (381-2) and the other-side connection line (381-3).The display device according to claim 7, wherein the first buffer hole (322h-1) is disposed closer to the intermediate connection line (381-2) than to the one-side connection line (381-1), and wherein the second buffer hole (322h-2) is disposed closer to the intermediate connection line (381-2) than to the other-side connection line (381-3).The display device according to any one of the preceding claims 6 to 8, wherein the interconnection line (381-2) overlaps a neutral plane (NP) of a curved portion of each of the plurality of line patterns (322).A display device, comprising: a substrate (111); a plurality of plate patterns (121) on the substrate (111), the plate patterns (121) being spaced apart from each other, respectively; at least one pixel (SPX) disposed on each plate pattern (121); a plurality of connection lines (181) coupled between adjacent pixels (SPX); and a plurality of line patterns (122, 222) disposed below the plurality of connection lines (122, 222); a buffer hole (222h) disposed so as not to overlap the plurality of connection lines (181); and a filling member (FM) disposed in the buffer hole (222h), wherein an upper surface of the filling member (FM) is flush with an upper surface of the plurality of line patterns (222).The display device of claim 10, wherein the at least one connection line (181) has a first curvature (CA) in a first region and a second curvature (SA) in a second region, the second region being contiguous with the first region, wherein at least one of the plurality of connection lines (181) comprises a first connection line (181-1) and a second connection line (181-2) adjacent to and spaced from the first connection line (181-1), wherein the first region has a constant first curvature that is greater than zero, and wherein the second region has a constant second curvature that is equal to zero.The display device of claim 11, wherein in the first region, at least one of the plurality of conductive patterns (222) includes the buffer hole (222h), the buffer hole (222h) extending through the at least one of the plurality of conductive patterns (222) and exposing the substrate (111).The display device of claim 12, wherein the buffer hole (222h) is located between the first connection line (181-1) and the second connection line (181-2).

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