DISPLAY DEVICE AND PROCEDURE

Abstract

A display device is disclosed comprising: pixels, each containing a drive transistor with a first electrode that receives a high-potential drive voltage, a second electrode connected to an anode of a light-emitting element, and a gate electrode that receives a data voltage; an integrated source drive circuit (source drive IC) configured to receive acquisition information output by each of the pixels corresponding to a threshold voltage of the drive transistor;and a timing control unit configured to calculate the threshold voltage of the drive transistor in each pixel based on the acquisition information, the timing control unit comprising: a fault pixel detector configured to detect a fault pixel by receiving the pixel acquisition voltages from the source drive IC, and a acquisition range control unit configured to set an initial acquisition range preset for the ADC due to the presence of the fault pixel detected by the fault pixel detector.

Description

BACKGROUNDArea of ​​Revelation

[0001] One aspect relates to a display device. Another aspect relates to a method. Description of the related field

[0002] With the development of multimedia, display devices are becoming increasingly important. Accordingly, various types of display devices are used, such as organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs).

[0003] The display device refers to a device that displays an image and includes a self-luminous display device that includes a light-emitting diode. The self-luminous display device includes an organic light-emitting display device that uses an organic material as a light-emitting material in the light-emitting diode, an inorganic light-emitting display device that uses an inorganic material as the light-emitting material, or the like. SUMMARY

[0004] One aspect of the disclosure is to provide a display device that can control a detection area and a compensation area.

[0005] According to one aspect, a display device includes: pixels each including a drive transistor having a first electrode receiving a high-potential drive voltage, a second electrode connected to an anode of a light-emitting element, and a gate electrode receiving a data voltage; a source drive integrated circuit (source drive IC) configured to receive a detection voltage output from each of the pixels and reflecting a threshold voltage of the drive transistor through an analog-to-digital converter (ADC);and a timing control unit configured to calculate the threshold voltage of the drive transistor in the pixel based on the detection voltage output from each of the pixels and reflecting the threshold voltage of the drive transistor, the timing control unit including: a defective pixel detector configured to detect a defective pixel by receiving the detection voltages of the pixels from the source drive IC, and a detection range control unit configured to set a first detection range preset for the ADC when it is identified that the defective pixel is detected by the defective pixel detector;

[0006] The pixels may include a normal pixel and the defective pixel, and a detection voltage of the normal pixel may be in the first detection range of the ADC.

[0007] The detection voltage of the defective pixel may be in a threshold range of the first detection range.

[0008] The detection range control unit may be configured to change the first detection range to a second detection range including both the detection voltage of the normal pixel and the detection voltage of the defective pixel.

[0009] The timing control unit may be configured to calculate the threshold voltage of the driving transistor in each of the normal pixel and the defective pixel based on the detection voltage of the normal pixel and the detection voltage of the defective pixel.

[0010] The timing control unit may further include a compensation range control unit configured to compensate for a deviation between the calculated threshold voltages of the driving transistors in the normal pixel and the defective pixel.

[0011] The equalization region control unit may be configured to calculate an equalization voltage applied to the gate electrode of the driving transistor and a driving reference voltage applied to a source electrode of the driving transistor in each of the normal pixel and the defective pixel.

[0012] The compensation voltage can be calculated based on the threshold voltage of the driving transistor in each pixel, a voltage constant, and a gate voltage applied to the gate electrode.

[0013] The drive reference voltage can be calculated based on the drive reference voltage which is changed based on the voltage constant.

[0014] The drive reference voltage can charge a reference capacitor during a sensing period and applies the drive reference voltage to a terminal of a sensing transistor.

[0015] A display device according to embodiments can control the detection range and the compensation range.

[0016] According to another aspect, a method comprises activating a drive transistor of each pixel of a display device during a sensing period; converting a voltage into sensing information output for each pixel using an analog-to-digital converter (ADC) configured in a first sensing range, the sensing information corresponding to a threshold voltage of the drive transistor; calculating the threshold voltage of the drive transistor in each pixel based on the sensing information; detecting a defective pixel based on the pixels' sensing information, and in response to detecting the defective pixel, adjusting a configuration of the ADC to detect the defective pixel using a second sensing range.

[0017] The second detection area may include a first portion containing a normal pixel area and a second portion corresponding to the defective pixel.

[0018] The method may further comprise calculating a first offset to apply to a drive reference voltage applied to a terminal of a sense transistor during the sense period based on the sense information; and calculating a second offset to apply to the threshold voltage; and detecting the drive transistor of the defective pixel based on the first offset, the second offset, and the second sense range. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a display device according to one aspect. Fig. 2 is a diagram showing a display device according to one aspect. Fig. 3 is a diagram illustrating a structure of a pixel according to an aspect. Fig. 4 to Fig. 7 are diagrams illustrating the equalization of characteristics of a drive transistor after turning off the display device. Fig. 8 is a diagram showing configurations of a timing control unit according to an aspect. Fig. 9 is a flowchart showing a method of driving a display device according to one aspect. Fig. 10 is a diagram showing a detection area control of a display device according to an aspect. Fig. 11 is a diagram showing a compensation range control of a display device according to an aspect. DETAILED DESCRIPTION

[0019] Aspects are described below with reference to the accompanying drawings. In this disclosure, when a particular element (or surface, layer, portion, etc.) is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, connected to, or coupled to the other element, or a third element may be disposed therebetween.

[0020] Similar reference numerals refer to similar elements. Furthermore, in the accompanying drawings, the thicknesses, ratios, and dimensions of the elements are exaggerated for effective technical description. The term "and / or" includes any one or more combinations that may be defined by associated elements.

[0021] Although the terms first, second, etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used merely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element, without departing from the scope of the disclosure. The singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] The terms "below," "under," "above," "upper," and the like are used to describe a relationship between the elements shown in the accompanying drawings. These terms are relative and are described with reference to the orientation shown in the accompanying drawings.

[0023] It should be understood that the terms "including" or "having" are intended only to indicate that the features, numbers, steps, operations, elements, components, or combinations thereof are present, and are not intended to preclude the possibility that one or more additional features, numbers, steps, operations, elements, components, or combinations thereof are present or added.

[0024] Fig. 1 is a block diagram of a display device according to one aspect.

[0025] With reference to Fig. 1, a display device 1 includes a timing control unit 10, a gate driver 20, a data driver 30, a power supply 40, and a display panel 50.

[0026] The timing control unit 10 can receive an image signal RGB and a control signal CS from an external source or device. The image signal RGB can contain multiple pieces of grayscale data. The control signal CS can contain, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0027] The timing control unit 10 can process the image signal RGB and the control signal CS to be suitable for the operating conditions of the display panel 50, and output image data DATA, a gate drive control signal CONT1, a data drive control signal CONT2, and a power supply control signal CONT3.

[0028] The gate driver 20 may be connected to the pixels PX of the display panel 50 via a plurality of gate lines GL1 to GLn. The gate driver 20 may generate gate signals based on the gate drive control signal CONT1 output from the timing control unit 10. The gate driver 20 may supply the generated gate signals to the pixels PX via the plurality of gate lines GL1 to GLn.

[0029] The data driver 30 may be connected to the pixels PX of the display panel 50 via a plurality of data lines DL1 to DLn. The data driver 30 may generate data signals based on the image data DATA and the data drive signal CONT2 output from the timing control unit 10. The data driver 30 may output the generated data signals to the pixels PX via the plurality of data lines DL1 to DLn.

[0030] The power supply 40 may be connected to the pixels PX of the display panel 50 via a plurality of power supply lines PL1 and PL2. The power supply 40 may generate a drive voltage supplied to the display panel 50 based on the power supply control signal CONT3. The drive voltage may include, for example, a high-potential drive voltage ELVDD and a low-potential drive voltage ELVSS. The power supply 40 may supply the generated drive voltages ELVDD and ELVSS to the pixels PX via the corresponding power supply lines PL1 and PL2.

[0031] A plurality of pixels PX are arranged on the display panel 50. The pixels PX can be arranged on the display panel 50, for example, in the form of a matrix.

[0032] Each pixel PX can be electrically connected to the corresponding gate line and the corresponding data line. The pixels PX can emit light with a brightness corresponding to the gate signals and the data signals supplied via the gate lines GL1 to GLn and the data lines DL1 to DLn.

[0033] Each pixel PX can display one of the first to third colors. For example, each pixel PX can display one of the colors such as red, green, and blue. Alternatively, each pixel PX can display one of the colors such as cyan, magenta, and yellow. Alternatively, the pixels PX can be configured to display one of four or more colors. For example, each pixel PX can display one of the colors such as red, green, blue, and white.

[0034] Timing controller 10, gate driver 20, data driver 30, and power supply 40 may each be configured as individual integrated circuits (ICs), or at least some of them may be integrated into a single IC. For example, at least one of data driver 30 and power supply 40 may be configured as a single IC integrated with timing controller 10.

[0035] Fig. 1 illustrates that the gate driver 20 and the data driver 30 are illustrated as separate from the display panel 50. However, at least one of the gate driver 20 and the data driver 30 may be implemented as an in-panel type and integral with the display panel 50. For example, the gate driver 20 may be integrally formed with the display panel 50 based on a gate-in-panel (GIP) type.

[0036] Fig. 2 is a diagram showing a display device according to one aspect of the disclosure.

[0037] With reference to Fig. 2, the display panel 50 has a rectangular shape and includes a plurality of pixels PX arranged in rows and columns therein. The plurality of pixels PX may include, for example, four sub-pixels, and the four sub-pixels may include a red sub-pixel R, a white sub-pixel W, a green sub-pixel G, and a blue sub-pixel B. As shown in Fig. As shown in Figure 2, the plurality of pixels PX may form a plurality of pixel rows PX_R1 to PX_Rn. The plurality of pixel rows PX_R1 to PX_Rn are spaced apart from each other in a column direction. For example, the number of pixel rows PX_R1 to PX_Rn may be 2160, but is not limited thereto.

[0038] The display device 1 further includes a gate drive IC (G-IC) 20. The display panel 50 may be implemented as a GIP type, with the gate drive IC 20 disposed therein. The gate drive IC 20 may be formed on the left side, the right side, or both the left and right sides of the display panel 50.

[0039] Further, the display device 1 includes a data drive IC (or a source drive IC (S-IC)) 30. The source drive IC 30 may be mounted on a bottom surface of the display panel 50, and a plurality of source drive ICs 30 may be mounted in a transverse direction of the display panel 50. Such a source drive IC 30 may be implemented as a chip-on-thin-film (COF) type to be mounted on a printed circuit board (PCB), a flexible PCB (FPCB), or a chip-on-glass (COG) type to be mounted on a glass board of the display panel 50. For example, in the aspect described in Fig. As shown in Figure 2, the source drive IC 30 is implemented as a COF type, and the display board 50 and the source PCB (S-PCB) are connected by a pad connection of the FPCB. The source drive IC 30 can apply voltages (a source IC drive voltage, ELVDD, ELVSS, VREF, etc.) from a control PCB (C-PCB) to the display board 50.

[0040] The source PCB (S-PCB) may be connected to the display panel 50 through the FPCB from the bottom of the display panel 50 and may be connected to the control PCB (C-PCB) through a flexible flat cable (FFC). The source PCB (S-PCB) is directly connected to the source drive IC 30 and transmits a gate signal to the gate drive IC 20. Furthermore, the source PCB (S-PCB) supplies various current sources (e.g., ELVDD, ELVSS, VGH, VHL, VREF, etc.) from the control PCB (C-PCB) to the display panel 50. Furthermore, the control PCB (C-PCB) and the gate drive IC 20 are connected via the leftmost or rightmost source drive IC 30 of the source PCB (S-PCB). For example, a gate drive IC drive voltage, a high Gate voltage VGH, a low gate voltage VGL, etc. are applied from the control PCB (C-PCB) to the gate drive IC 20 via the source PCB (S-PCB).

[0041] The control PCB (C-PCB) is arranged on the underside of the display panel 50 and is connected to the source PCB (S-PCB) via a cable (e.g., an FFC). The control PCB (C-PCB) may include a timing control unit (TCON) 10, a power supply (PMIC) 40, and a memory. The timing control unit 10 and the power supply 40 are the same as those described with reference to Fig. 1. Furthermore, a device may be configured to calculate parameters for an algorithm for different regions for each frame of output image data, store compensation data, and store various parameters for algorithm calculation or various parameters for tuning. In this case, the control PCB (C-PCB) may include a volatile memory and / or a non-volatile memory for storing parameters, compensation data, and other information for controlling the output of the display panel 50.

[0042] Fig. 3 is a diagram illustrating a structure of a pixel according to an aspect of the disclosure.

[0043] With reference to Fig. 3, a subpixel SP receives a data voltage VDATA from the source drive IC (S-IC) via a digital-to-analog converter (DAC). Furthermore, a sense voltage VSEN can be output from the subpixel SP and is supplied to the source drive IC (S-IC) via an analog-to-digital converter (ADC). Furthermore, each subpixel is connected to a high-potential drive voltage ELVDD and a low-potential drive voltage ELVSS.

[0044] The subpixel SP contains a sampling transistor S-TFT, a driving transistor D-TFT, and a detection transistor SS-TFT. Each subpixel contains a storage capacitor CST and an OLED light-emitting element.

[0045] The sampling transistor S-TFT includes a first electrode (e.g., a drain electrode) connected to a data line DATA. The source drive IC (S-IC) outputs a data voltage VDATA to the data line DATA via the DAC. The sampling transistor S-TFT includes a second electrode (e.g., a source electrode) connected to a first end of the storage capacitor CST and also connected to the gate electrode of the driving transistor D-TFT. The gate electrode of the sampling transistor S-TFT is connected to the scanning line SCAN. In this case, the sampling transistor S-TFT is turned on when the gate signal having a gate-on level is received via the scanning line SCAN and transmits a data signal applied via the data line DATA to the first end of the storage capacitor CST.

[0046] The first end of the storage capacitor CST is connected to the second electrode of the sampling transistor S-TFT. The sensing transistor SS-TFT includes a second electrode (e.g., a drain electrode) connected to a second end of the storage capacitor CST and the second electrode of the driving transistor D-TFT. The storage capacitor CST can be charged with a voltage equal to the difference between the voltage applied to its first end and a reference voltage VPRES applied to its second end via a switch SPRE and the sensing transistor SS-TFT.

[0047] The D-TFT drive transistor includes a first electrode (e.g., the drain electrode) configured to receive the high-potential drive voltage ELVDD and a second electrode (e.g., the source electrode) connected to a first electrode (e.g., an anode) of the OLED light-emitting element. The D-TFT drive transistor includes a third electrode (e.g., a gate electrode) connected to the first end of the storage capacitor CST. The D-TFT drive transistor can control the amount of a drive current flowing into the OLED light-emitting element according to the voltage applied to its gate electrode. In this case, the current can be based on the voltage difference between the D-TFT drive transistor (or the stored voltage of the storage capacitor CST) and a voltage applied to the OLED light-emitting element.

[0048] The sense transistor SS-TFT includes a first electrode (e.g., a source electrode) connected to a reference line REFERENCE, a second electrode (e.g., the drain electrode) connected to the second end of the storage capacitor CST, and a third electrode (e.g., a gate electrode) connected to a sense line SENSE. In this case, the gate drive IC (G-IC) supplies a sense signal SENSE that turns on the transistor SS-TFT and applies the reference voltage VPRES to the second end of the storage capacitor CST. When the switch SPRE and a switch SAM are all off and the sense transistor SS-TFT is on, the stored voltage of the storage capacitor CST is applied to a capacitor connected to the reference line, and the capacitor of the reference line stores the sense voltage VSEN.The reference line REFERENCE can be provided with a control switch RPRE and the control switch RPRE can optionally apply a control reference voltage VREF to the reference line REFERENCE.

[0049] When the SPRE switch is off and the SAM switch is on, the detection voltage VSEN is output to the source drive IC (S-IC) via the ADC. The output voltage is used to detect and sample the attenuation of the corresponding sub-pixel. In other words, a voltage for equalizing the corresponding sub-pixel is detected and sampled. Specifically, the mobility and threshold voltage of the drive transistor D-TFT can be measured, and compensation can be implemented based on detecting the mobility and threshold voltage of the drive transistor D-TFT.

[0050] The OLED light-emitting element emits light corresponding to a driving current. The OLED light-emitting element can emit light corresponding to one of colors such as red, white, green, and blue. The OLED light-emitting element according to one aspect may be an organic light-emitting diode (OLED) or an inorganic subminiature light-emitting diode, but is not limited thereto. In some cases, an inorganic subminiature light-emitting diode may have a size in the micro- to nanoscale range. Below, technical concepts of one aspect will be described with reference to an example in which the organic light-emitting diode is provided as the OLED light-emitting element.

[0051] In the aspect that Fig. 3, the switching transistor S-TFT, the driving transistor D-TFT, and the sensing transistor SS-TFT are, but are not limited to, N-channel metal-oxide-semiconductor (NMOS) transistors. For example, at least some or all of the transistors in each pixel PX may be P-channel metal-oxide-semiconductor (PMOS) transistors. In certain aspects, each of the switching transistor and the driving transistor may be implemented as a low-temperature polysilicon (LTPS) thin-film transistor, an oxide thin-film transistor, or a low-temperature polycrystalline oxide (LTPO) thin-film transistor.

[0052] Fig. 4 to Fig. 7 are diagrams illustrating balancing characteristics of a drive transistor after turning off the display device according to aspects of the disclosure.

[0053] In some cases, the compensation techniques of the driving transistor D-TFT in this description may be performed while the display device 1 is not displaying images and is turned off. Aspects of the disclosure include, but are not limited to, detecting a threshold voltage characteristic of the driving transistor D-TFT and compensating for a deviation therefrom. Alternatively or additionally, other characteristics of the driving transistor D-TFT, such as a mobility characteristic and techniques for compensating for a deviation of the mobility characteristic, may be detected. Below, for the sake of simplicity of description, the following description is made assuming that the compensation uses detecting the threshold voltage characteristic of the driving transistor D-TFT and compensating for the deviation therefrom as a basis.

[0054] In certain aspects, the threshold voltage characteristic may be captured during the power-off of the display device. For example, a black image may be displayed during the power-off of the display device, and the threshold voltage characteristics or mobility characteristics may be captured. The characteristics may also be captured at other times, such as during power-up.

[0055] With reference to Fig. 4, the acquisition of the characteristics can be performed based on discrete time periods including an initialization period, a programming period, an acquisition period, and a sampling period. During the initialization period, the sampling transistor S-TFT is turned on, and the first end of the storage capacitor CST is charged to correspond to the data voltage VDATA. Furthermore, the second end of the storage capacitor CST is set to a floating potential, and thus the voltage applied to the second end of the storage capacitor CST increases at the same rate as the voltage applied to the first end of the storage capacitor CST increases due to the capacitor characteristics. In the initialization section, the switch SPRE can also be turned on.

[0056] With reference to Fig. 5, during a programming period, the switch SPRE is kept in an on state and the detection transistor SS-TFT is turned on, whereby the reference voltage VPRES is applied to the second end of the storage capacitor CST. The reference voltage VPRES can be the first reference voltage. The power supply 40 can, for example, Fig. 2, supply a first reference voltage to the reference line REFERENCE.

[0057] With reference to Fig. 6, during the detection period, the scanning transistor S-TFT and the detection transistor SS-TFT are kept on, and the switch SPRE is turned off. Because the drive current flows from the first electrode of the drive transistor D-TFT to the second electrode, the voltage applied to the second end of the storage capacitor CST increases, but the voltage of the first end of the storage capacitor CST is maintained as the data voltage VDATA. Further, the drive current gradually decreases based on the increase voltage applied to the second end of the storage capacitor CST, and thus the detection voltage VSEN increases, as shown in Fig. 6 is shown.

[0058] With reference to Fig. 7, the detection transistor SS-TFT is turned off and the switch SAM is turned on during the sampling period. Therefore, the detection voltage VSEN is applied to the source select IC (S-IC) via the reference line REFERENCE using the ADC. The source select IC (S-IC) receives the detection voltage VSEN and can calculate the threshold voltage characteristics of the corresponding select transistor.

[0059] Fig. 8 is a diagram showing configurations of a timing control unit according to an aspect of the disclosure. Fig. 9 is a flowchart of a method for driving a display device according to one aspect of the disclosure. Fig. 10 is a diagram showing a detection area control of a display device according to an aspect of the disclosure. Fig. 11 is a diagram showing a compensation range control of a display device according to an aspect of the disclosure.

[0060] In one aspect, with reference to Fig. 1, Fig. 4 and Fig. 8 to Fig. 11 illustrates the detection of the threshold voltage characteristic after the display device has been turned off (e.g., during a power-off cycle). In one example, a defective pixel may be detected in block S10. Below, the description assumes that the pixels PX1 in Fig. 1 include normal pixels PX1 and defective pixels PX2. Normal pixels PX1 refer to the pixels PX whose detection voltage VSEN is within a first detection range RS1. Defective pixels PX2 refer to the pixels PX that include a detection voltage VSEN from the first detection range RS1. For example, the first detection range RS1 may have a voltage range from a first voltage (V) a1 to a second voltage (V) a2. In other words, the pixel PX whose detection voltage VSEN, which reflects the threshold voltage of its driving transistor D-TFT, is within the voltage range from the first voltage (V) a1 to the second voltage (V) a2 may be the normal pixel PX1, and the pixel whose detection voltage VSEN, which reflects the threshold voltage of its driving transistor D-TFT, is outside the voltage range from the first voltage (V) a1 to the second voltage (V) a2 may be the defective pixel PX2.

[0061] After the display device is turned off, the threshold voltage characteristic can be detected by the source drive IC (S-IC). The source drive IC (S-IC) can receive the detection voltage VSEN applied by each of the pixels PX through the ADC. For example, because the detection voltage VSEN applied by each of the pixels PX is received through the ADC, the source drive IC (S-IC) can receive a digital value converted from the detection voltage VSEN. The source drive IC (S-IC) can calculate the threshold voltages of the pixels PX based on the digital values ​​converted from the detection voltages VSEN. Similarly, the calculated threshold voltage can also be a digital value.Hereinafter, for convenience of description, a digital or analog threshold voltage or a digital or analog threshold voltage level is expressed in an analog form (in other words, although the threshold voltage is expressed in an analog format, it can simply be expressed in a digital format). Therefore, the first detection range RS1 described above is illustrated as having an analog voltage range from the first voltage (V) a1 to the second voltage (V) a2, but it may also be a voltage range converted from the analog format to the digital format.

[0062] The source drive IC (S-IC) can provide information corresponding to the calculated threshold voltage of the pixels PX to the timing control unit 10.

[0063] The timing control unit 10 may include a defective pixel detector 11, a detection area control unit 12, a compensation area control unit 13, a compensation device 14, a defective pixel memory 15, and a defective pixel identifier 16.

[0064] The source drive IC (S-IC) may provide the information corresponding to the calculated threshold voltages of the pixels PX to the defective pixel detector 11. The defective pixel detector 11 may detect the defective pixel in block S10 by distinguishing between the normal pixel PX1 and the defective pixel PX2 based on the detection voltage VSEN. The defective pixel detector 11 may detect the defective pixel based on the detection voltage VSEN supplied to the source drive IC (S-IC) via the ADC. In certain aspects, the detection voltage VSEN may reflect correction values ​​to compensate for a deviation between the source drive ICs (S-ICs). For example, the detection voltage VSEN may have a voltage level for which the detection voltage supplied via the ADC is corrected (e.g., a gain or an offset).The corrected detection voltage VSEN will be described below. The range of the detection voltage VSEN to be detected by the ADC may be predetermined. The detectable range of the detection voltage VSEN may be the first detection range RS1. However, when the detection voltage VSEN, which may be from the first detection range RS1 for the defective pixel PX2, is supplied to the ADC, (1) the detection voltage VSEN for the defective pixel PX2 is not supplied to the source drive IC (S-IC) because the detection voltage VSEN from the first detection range RS1 is not detected by the ADC, or (2) the first voltage a1 or the second voltage a2, or (3) a voltage approximating the voltage a1 or a2 is detected and supplied to the source drive IC (S-IC) as the detection data. In other words, the defective pixel detector 11 can detect the pixels PX corresponding to cases 1) to 3) as the defective pixel PX2.

[0065] Cases (2) and (3) are described below. To increase the reliability of detecting defective pixels in block S10, the detection voltage VSEN may be calculated by detecting the pixel PX whose detection voltage VSEN is detected at least once, as case (2), the first voltage a1 or the second voltage a2, or as case (3), the voltage near the voltage a1 or a2. The first detection range RS1 may include a threshold range TH. For example, the threshold range TH may have a range from a minimum value a1 of the first detection range RS1 to the minimum value a1 * 1.1, from the minimum value a1 * 0.9 to the minimum value a1, a maximum value a2 * 0.9 to the maximum value a2, or the maximum value a2 to the maximum value a2 * 1.1, but is not limited to these.In other words, to increase reliability, if the detection voltages VSEN calculated after detection are performed multiple times and are all within the threshold range TH, the defective pixel detector 11 can detect the corresponding pixels PX as the defective pixels PX2. However, in some cases regarding speed, even in the cases of (2) and (3), when the detection voltage VSEN is within the threshold range TH, the defective pixel detector 11 can detect the corresponding pixel PX as the defective pixel PX2.

[0066] Next, if the defective pixel PX2 is present, the detection range is adjusted in block S20. The detection range control unit 12 adjusts the first detection range RS1 (e.g., a sensitivity) preset in the ADC when identifying that the defective pixel PX2 is present. The adjustment of the first detection range RS1 by the detection range control unit 12 may be performed based on the detection voltage VSEN of the calculated defective pixel PX2. In other words, the detection range control unit 12 may adjust the first detection range RS1 of the ADC such that the range of the detection voltage VSEN can be detected by the ADC and includes the detection voltage VSEN of all pixels PX (the normal pixels PX1 + the defective pixels PX2). Meanwhile, the detection range adjustment S20 may be repeated multiple times.

[0067] In certain aspects, the first detection range RS1 may be set based on a detection range reference voltage EVREF2 (such as in Fig. 3). The detection range reference voltage EVREF2 may be supplied to the ADC. The first detection range RS1 may be adjusted by subtracting the detection range reference voltage EVREF2 from the detection voltage VSEN supplied to the ADC. In other words, the detection range control unit 12 may adjust the first detection range RS1 by adjusting the level of the detection range reference voltage EVREF2 supplied to the ADC.

[0068] With reference to Fig. 9, the detection area adjustment is performed once in block S20, and then the defective pixel can be detected again in block S30. The detection of defective pixels can be performed in the same way as the detection of defective pixels S10, thus avoiding their repeated descriptions. If the defective pixel PX2 is detected via the re-detection of defective pixels in block S30 (Yes in Fig. 9), the defective pixel redetection S30 is performed again. The number of detection times for the defective pixel redetection S30 can be set to less than or equal to N in block S60. The detection area for which the detection area setting S20 was performed twice or more as described above is set to a final detection area (or a second detection area RS2).

[0069] Fig. 10 illustrates an exemplary adjustment from the first detection range RS1 to the second detection range RS2 (the first voltage (a1 to a1') and the second voltage (a2 to a2')) according to certain aspects of the disclosure.

[0070] With further reference to Fig. 9, when the number of detections (settings) for redetecting defective pixels in block S30 is greater than N, the display device is turned off and then the acquisition of the threshold voltage characteristic is terminated.

[0071] If the faulty pixel PX2 is not detected after the redetection of faulty pixels in block S30 (see 'N' in Fig. 9), a compensation range is controlled in block S40.

[0072] About the detection of faulty pixels in blocks S10 and S30 and the detection area setting in block S20 in Fig. 9, the threshold voltages of the driving transistors D-TFT in all pixels PX (PX1 and PX2) of the display panel 50 can be accurately calculated. The threshold voltage of the driving transistor D-TFT can be accurately calculated by a threshold voltage calculator of the timing control unit 10. The compensation range controller in block S40 can control (or adjust) the compensation range to compensate for the deviation between the calculated threshold voltages of the normal pixel PX1 and the defective pixel PX2. Referring to Fig. 11, the compensation range control in block S40 may be performed by the compensation range control unit 13. The compensation range (RC) for compensating the deviation between the threshold voltages may be a compensation range from b1V to b2V for compensating the threshold voltages of the drive transistors D-TFT, between which the deviation is generated, in the pixels PX.

[0073] With reference to Fig. 4, the drive current Ids flowing into the OLED light-emitting element may be proportional to (VDATA - Vth - Vs)2. The data voltage VDATA is a voltage (hereinafter referred to as Vg) applied to the gate electrode of the drive transistor D-TFT, Vth is a threshold voltage of the drive transistor D-TFT, and Vs is a voltage applied to the source electrode of the drive transistor D-TFT.

[0074] The voltage Vg applied to the gate electrode of the drive transistor D-TFT can have the same level as the data voltage VDATA.

[0075] When the threshold voltages of the driving transistors D-TFT in all pixels PX (PX1 and PX2) of the display panel 50 are accurately calculated by the detection of defective pixels in blocks S10 and S30 and the detection area adjustment in block S20, deviations between a normal threshold voltage (hereinafter referred to as Vth1) and the threshold voltages Vth of the driving transistors D-TFT in the pixels PX can be calculated based on the normal threshold voltage Vth1, and the calculated deviations can be compensated by adjusting the level of the data voltage VDATA.

[0076] Meanwhile, because the data voltage VDATA has a level greater than zero, it may be difficult to equalize the threshold voltages Vth of the driving transistors D-TFT in some pixels PX.

[0077] Therefore, the equalization range control unit 13 controls an equalization voltage (hereinafter referred to as Vcom) and a drive reference voltage VREF, thereby equalizing the threshold voltages Vth of the drive transistors D-TFT in all pixels PX.

[0078] The compensating voltage Vcom can be calculated using the following equations 1 and 2. Vcom=Vth+α

[0079] In Equation 1, Vth is the threshold voltage of the driving transistor D-TFT of each pixel PX, and α is a voltage constant which is a rational number greater than 0. Vg=VDATA+Vcom

[0080] Because Vg is the voltage applied to the gate electrode of the driving transistor D-TFT and cannot be negative, a common voltage constant α is introduced to make Vg positive. For example, the voltage constant α can be calculated as the minimum value Vth' among the threshold voltages Vth of the driving transistors D-TFT in all pixels PX.

[0081] The drive reference voltage VREF can be calculated using the following equation 3. VREF=VREF'+α

[0082] In equation 3, VREF' is a drive reference voltage and α is a voltage constant.

[0083] For example, the drive reference voltage VREF' may be 0 V, but is not limited to that.

[0084] The compensation voltage Vcom and the drive reference voltage VREF are calculated using the previous equations 1 to 3.

[0085] After the compensation area control S40, data about the pixels PX identified as the defective pixels PX2 by the defective pixel detection in block S10 (or the coordinates of the defective pixels PX2) are stored in the defective pixel memory 15, the display device is turned off, and then the detection of the threshold voltage characteristic is terminated.

[0086] The equalizer 14 controls the voltage applied to the gate electrode and the voltage applied to the source electrode of the drive transistor D-TFT in the pixel PX based on the equalization voltage Vcom calculated by the equalization range control unit 13 and the drive reference voltage VREF, thereby controlling the drive current Ids flowing into the light-emitting element OLED.

[0087] In other words, as in Fig. As shown in Figure 4, the amount of drive current Ids flowing into the OLED light-emitting element may be proportional to (Vg - Vth - Vs)2. In this case, Vs is the voltage applied to the source electrode of the drive transistor D-TFT, which may have the same level as the drive reference voltage VREF, and Vg is the voltage applied to the gate electrode of the drive transistor D-TFT, which may have the same level as the sum of the data voltage VDATA and the equalization voltage Vcom. In other words, the amount of drive current Ids flowing into the OLED light-emitting element may be proportional to (VDATA + Vcom - Vth - Vs)2.

[0088] With further reference to Fig. 9, if the defective pixel PX2 is not detected after the detection of defective pixels in block S10, the defective pixel identifier 16 identifies the stored coordinates of the defective pixel in block S70.

[0089] When it is identified by the defective pixel identifier 16 that no coordinates of the defective pixel PX2 have been stored in the defective pixel memory 15, the display device is turned off and then the detection of the threshold voltage characteristic is terminated.

[0090] When the defective pixel identifier 16 identifies that the coordinates of the defective pixel PX2 have been stored in the defective pixel memory 15, the compensation range is controlled in block S80. The compensation range control in block S80 can be performed by the same processes as the compensation range control S40, thus avoiding repeated descriptions thereof. After performing the compensation range control S80, the coordinates of the defective pixel stored in the defective pixel memory 15 are cleared in block S90. After clearing the coordinates of the defective pixel stored in the defective pixel memory 15 in block S90, the display device is turned off, and then the detection of the threshold voltage characteristic is terminated.

[0091] For example, a display device may include: pixels each including a drive transistor having a first electrode receiving a high-potential drive voltage, a second electrode connected to an anode of a light-emitting element, and a gate electrode receiving a data voltage; a source drive IC configured to receive a detection voltage output from each of the pixels and reflecting a threshold voltage of the drive transistor via an ADC;and a timing control unit configured to calculate the threshold voltage of the drive transistor in the pixel based on the detection voltage output from each of the pixels and reflecting the threshold voltage of the drive transistor, the timing control unit including: a defective pixel detector configured to detect a defective pixel by receiving the detection voltages of the pixels from the source drive IC, and a detection range control unit configured to set a first detection range preset for the ADC when it is identified that the defective pixel is detected by the defective pixel detector;

[0092] For example, the pixels may include a normal pixel and the faulty pixel, and the detection voltage of the normal pixel may be in the first detection range of the ADC.

[0093] For example, the detection voltage of the defective pixel may be in a threshold range of the first detection range.

[0094] For example, the detection range control unit may change the first detection range to a second detection range that includes both the detection voltage of the normal pixel and the detection voltage of the defective pixel.

[0095] For example, the timing control unit may calculate the threshold voltage of the driving transistor in each of the normal pixel and the defective pixel based on the detection voltage of the normal pixel and the detection voltage of the defective pixel.

[0096] For example, the timing control unit may further include a compensation range control unit to compensate for a deviation between the calculated threshold voltages of the driving transistors in the normal pixel and the defective pixel.

[0097] For example, the equalization region control unit may calculate an equalization voltage applied to the gate electrode of the driving transistor and a driving reference voltage applied to a source electrode of the driving transistor in each of the normal pixel and the defective pixel.

[0098] For example, the compensation voltage can be calculated by equations 1 to 2 above.

[0099] Although embodiments of the disclosure have been described above with reference to the accompanying drawings, those skilled in the art to which the disclosure belongs will understand that the disclosure may be embodied in other specific forms without departing from the technical spirit or essential characteristics of the disclosure. It should therefore be understood that the embodiments described above are illustrative and not limited in all aspects. In addition, the scope of the disclosure is defined by the appended claims rather than by the foregoing detailed description. Furthermore, all modifications or variations that come within the meaning and scope of the appended claims and their equivalents should be construed as falling within the scope of the disclosure.

Claims

[1] A display device comprising: Pixels (PX) each comprising a drive transistor (D-TFT), the drive transistor (D-TFT) comprising a first electrode receiving a high-potential drive voltage (ELVDD), a second electrode connected to an anode of a light-emitting element (OLED), and a gate electrode receiving a data voltage (VDATA); a source drive integrated circuit (S-IC) configured to receive detection information output by each of the pixels (PX) and corresponding to a threshold voltage of the drive transistor (D-TFT); and a timing control unit (10) configured to calculate the threshold voltage of the drive transistor (D-TFT) in each pixel (PX) based on the output detection information, wherein the timing control unit (10) comprises: a defective pixel detector (11) configured to detect a defective pixel (PX2) by receiving the pixel (PX) detection information from the source drive IC (S-IC), and a detection range control unit (12) configured to set a first detection range (RS1) preset for an analog-to-digital converter, ADC, based on the defective pixel (PX2) detected by the defective pixel detector (11). [2] The display device according to claim 1, wherein the pixels (PX) include a normal pixel (PX1) and the defective pixel (PX2), and a detection voltage (VSEN) of the normal pixel (PX1) is in the first detection range (RS1) of the ADC. [3] The display device according to claim 2, wherein the detection voltage (VSEN) of the defective pixel (PX2) is in a threshold range (TH) of the first detection range (RS1). [4] The display device according to claim 2 or 3, wherein the detection range control unit (12) is configured to change the first detection range (RS1) to a second detection range (RS2) including both the detection voltage (VSEN) of the normal pixel (PX1) and the detection voltage (VSEN) of the defective pixel (PX2). [5] The display device according to claim 4, wherein the timing control unit (10) is configured to calculate the threshold voltage of the driving transistor (D-TFT) in each of the normal pixel (PX1) and the defective pixel (PX2) based on the detection voltage (VSEN) of the normal pixel (PX1) and the detection voltage (VSEN) of the defective pixel (PX2). [6] The display device according to claim 5, wherein the timing control unit (10) further comprises a compensation range control unit (13) configured to compensate for a deviation between the calculated threshold voltages of the driving transistors (D-TFT) in the normal pixel (PX1) and the defective pixel (PX2). [7] The display device according to claim 6, wherein the equalization area control unit (13) is configured to calculate an equalization voltage (VCom) applied to the gate electrode of the drive transistor (D-TFT) and a drive reference voltage (VREF) applied to a source electrode of the drive transistor (D-TFT) in each of the normal pixel (PX1) and the defective pixel (PX2). [8] The display device according to claim 7, wherein the compensation voltage (VCom) is calculated based on the threshold voltage of the drive transistor (D-TFT) in each pixel (PX), a voltage constant (α) and a gate voltage (Vg) applied to the gate electrode. [9] A display device according to claim 8, wherein the drive reference voltage (VREF) is calculated based on the drive reference voltage (VREF) changed based on the voltage constant (α). [10] The display device according to claim 9, wherein the drive reference voltage (VREF) charges a reference capacitor (CST) during a detection period and applies the drive reference voltage (VREF) to a terminal of a detection transistor (SS-TFT). [11] A method comprising: activating a drive transistor (D-TFT) of each pixel (PX) of a display device during a detection period; Converting a voltage into detection information output for each pixel (PX) using an analog-to-digital converter, ADC, configured in a first detection area (RS1), wherein the detection information corresponds to a threshold voltage of the drive transistor (D-TFT); Calculating the threshold voltage of the driving transistor (D-TFT) in each pixel (PX) based on the detection information; Detecting a defective pixel based on the pixel detection information (PX) and Setting, in response to detecting the faulty pixel (PX2), configuring the ADC to detect the faulty pixel (PX2) using a second detection range (RS2). [12] The method according to claim 11, wherein the second detection area (RS2) comprises a first portion containing a normal pixel area and a second portion corresponding to the defective pixel (PX2). [13] The method of claim 12, further comprising: Calculating a first offset to be applied to a drive reference voltage (VREF) applied to a terminal of a sense transistor (SS-TFT) during the sense period based on the sense information; and Calculating a second offset to apply to the threshold voltage and Detecting the driving transistor (D-TFT) of the defective pixel (PX2) based on the first offset, the second offset and the second detection range (RS2).