Device for processing incoming and / or outgoing data elements

Abstract

The invention relates to a device (200) for the cyclic processing of incoming and / or outgoing data elements (11), wherein the data elements (11) represent numeric and / or logical values ​​that are linked to a higher-level application.

Description

[0001] The present invention relates to a device for processing incoming and / or outgoing data elements. Furthermore, the invention relates to a system, a method, a computer program, a data processing device, and a computer-readable storage medium. State of the art

[0002] IO-Link is a communication protocol standardized in IEC 61131-9. It is typically used in industrial fieldbus environments to connect sensors or actuators to various fieldbus systems. Special linking devices, called IO-Link masters, are used to connect IO-Link devices to different fieldbus systems. IO-Link communication is based on a simple point-to-point protocol. This means that IO-Link devices only need to support a single, simple interface and can still interact with a variety of host systems via a suitable IO-Link master. IO-Link masters are available not only for fieldbuses, but also for other client systems such as web browsers, MQTT servers, cloud systems with artificial intelligence, and other IT-based technologies such as OPC UA or JSON.

[0003] The information transmitted via IO-Link is based on telegrams called m-sequences. An M-sequence is always initiated by an IO-Link master with a first part at predefined intervals or cycles and responded to by the IO-Link device with a second part. M-sequences comprise data elements that are transmitted in each cycle. These data elements are referred to as cyclic data or process data. They also include elements that are typically distributed across multiple cycles. These data elements are only transmitted upon request—hence they are called on-request data or acyclic data. On-request data is used, for example, for parameters or event messages.

[0004] Different m-sequence types are used to specify different fixed-size data elements. Which m-sequence types are used in IO-Link communication is defined by the IO-Link devices. An IO-Link master with, for example, 8 IO-Link ports enables the connection of up to 8 IO-Link devices. The properties of the connected IO-Link devices are described in electronic data sheets, the IO-Link Device Descriptor "IODD" files. Each IO-Link device type is uniquely identified by an address consisting of a 16-bit vendor ID and a 24-bit device ID. This identification is listed in the IODD and can also be read from the IO-Link device via the IO-Link protocol.

[0005] The current IO-Link system is very successful and widely used, especially in combination with fieldbus systems and programmable logic controllers (PLCs).

[0006] There are various disadvantages associated with the use of communication systems, especially IO-Link. These include, for example, a lack of master ports. This occurs when additional sensors or actuators need to be added for expanded or improved functionality, and all ports of the current master are already occupied, making adding a new master insufficient. Another disadvantage arises when a particular device needs to be replaced by a similar device with similar or comparable features but a different cyclic data structure.

[0007] Another challenge is providing low-latency feedback from a sensor to an actuator without using PLCs as clients. It can also be challenging to implement a simple flow control system as an extension of the low-latency feedback, including execution loops and decisions. Another challenge is meeting the requirements of clients that require data in a specific, preprocessed data format not provided by the connected IO-Link device.

[0008] Existing solutions include devices such as the "Balluf BNI IOL-302-002-K006," which allow an IO-Link device to be extended with an extender port. However, these solutions are not generic, as only specific devices can be connected to the extender port. Disclosure of the invention

[0009] The invention relates to a device having the features of claim 1, a system having the features of claim 8, a method having the features of claim 9, a computer program having the features of claim 15, a data processing device having the features of claim 16, and a computer-readable storage medium having the features of claim 17. Further features and details of the invention are disclosed in the respective dependent claims, the description, and the drawings. Features and details described in connection with the device according to the invention also correspond to the system, the method, the computer program, the data processing device, and the computer-readable storage medium, and vice versa.

[0010] The subject matter of the invention is, in particular, a device for the, in particular cyclic, processing of incoming and / or outgoing data elements. The data elements can represent numerical and / or logical values ​​that are linked to, and in particular are specific to, a higher-level application, for example an industrial automation application and / or a control and / or evaluation of sensors and / or actuators. In other words, the numerical and / or logical values ​​can be used in the higher-level application, for example for controlling an automation system, and in particular evaluated and / or generated. The device can be designed as an electronic device and / or as a computer system and / or comprise a computer program.

[0011] The device may comprise a distributor block, also called a distributor, for converting at least one or more data elements after a linear operation (on the data elements) into at least one or more input scalar signals, also called input scalars, of a generic data type, in particular an IEEE 754 float, and / or after additional quantization into at least one or more Boolean signals, also called Bools or Bool signals. The distribution block may be embodied as at least part of a computer program and / or an electronic circuit.

[0012] The device may comprise a combiner block, also called a combiner, for performing at least one or more combining operations. Each combining operation may comprise the combination of at least one or more input scalar signals into a (single) output scalar signal. In other words, the combiner may combine multiple input scalar signals to generate a single output scalar signal, also referred to as an output scalar. Thus, if multiple combining operations are performed, each of them may generate a single output scalar signal resulting from the combination of at least one or more input scalar signals. The combiner block may be embodied at least as part of a computer program and / or an electronic circuit.

[0013] The device may comprise a merger block for reconverting (or converting) at least one or more of the output scalar signals and / or Boolean signals and / or other outputs based on these signals into one or more data elements, particularly for these signals / outputs, after a linear operation and / or a quantization step. In other words, the merger block may convert the outgoing signals or Boolean signals into one or more data elements after a linear operation and an optional quantization step. The merger block may be embodied at least as part of a computer program and / or an electronic circuit.

[0014] The device may comprise a logic block for performing logical operations on at least one or more Boolean signals, and in particular for providing both inputs (which may therefore also be referred to here and below as inputs) and outputs (which may therefore also be referred to here and below as outputs) for the Boolean signals. In other words, the logic block may perform logical operations on Boolean signals and provide both inputs and outputs for Boolean signals. The logic block may also be embodied as at least part of a computer program and / or an electronic circuit.

[0015] The device may further comprise processing blocks that can be inserted between the distributor and combiner blocks, in particular into one or more input scalars, or between the combiner block and the merging block, in particular into one or more output scalars. In other words, the processing blocks can process the input / output scalar signals into which they have been inserted. The processing blocks can be inserted individually or jointly into the input scalar signals. Each of the processing blocks can be embodied at least as part of a computer program and / or an electronic circuit.

[0016] The device can use the described block structure to provide a configurable logic adapter, thereby enabling flexible, reliable, and easily configurable processing of data elements. The device can be configured, in particular, as an aggregator device and / or as an IO-Link device and / or as a fieldbus device and / or as a network device and / or as a communication device.

[0017] The device according to the invention can be designed as a communication device, in particular as an IO-Link device, and / or for a communication system designed for connection to a master device, in particular an IO-Link master, and to at least one secondary device, in particular a different type of IO-Link device. The master device can provide a communication system such as IO-Link for data exchange with the secondary devices. A communication system can refer to a digital communication network that enables real-time data exchange between the secondary devices in the form of industrial devices such as sensors, actuators, and controllers. It can be used, for example, to connect devices in a manufacturing or process control environment and enables efficient and reliable communication between the devices. The communication system can be designed as a point-to-point communication system and is thus distinguished from fieldbus systems.For this purpose, IO-Link in particular uses an IO-Link master, which establishes a point-to-point connection to one or more IO-Link devices, i.e., sensors or actuators. The IO-Link master can form the interface to a higher-level unit such as the higher-level controller (PLC) and controls communication with the connected IO-Link devices. An IO-Link master can have one or more IO-Link ports, to which only one device can be connected at a time. This can also be a "hub," which acts as a concentrator for connecting conventional switching sensors and actuators. Furthermore, the communication system can also be implemented as a wired communication system. In contrast to a wireless solution, the communication system can therefore use cables to establish the physical connection between the ports of the master and the devices.

[0018] Typically, a (primary) master device is used as an interface between various fieldbus or similar systems and multiple (secondary) devices. The master can be responsible for controlling communication with the secondary devices, especially for IO-Link, including data transfer, configuration, and parameterization. Optionally, the master can also supply power to the secondary devices, enabling simplified and cost-effective cabling. The master can also be an active remote station, connected via ports to one to n (secondary) devices and providing a gateway interface to the higher-level communication systems or higher-level units such as PLCs (programmable logic controllers).

[0019] IO-Link specifically refers to a standardized communication protocol defined in IEC 61131-9 and used to connect sensors and actuators to industrial automation systems. It can enable bidirectional communication between devices and the control system and allows real-time data exchange and parameterization. IO-Link is supported by a wide range of industrial equipment manufacturers, making it a cost-effective and flexible solution for industrial automation applications.

[0020] An MCU (short for microcontroller unit) can be used to execute software, i.e. at least one computer program, in particular a computer program according to the invention, and / or also referred to as an application. The MCU can comprise a processor, a memory and input / output peripherals. The application can implement a standard master interface (SMI) for higher-level communication and an IO-Link master interface for communication with the devices. Information transmitted via IO-Link can be based on telegrams referred to as m-sequences. An M-sequence can always be initiated at predefined intervals or cycles by an IO-Link master with a first part and responded to by the IO-Link device with a second part. M-sequences can comprise data elements that are transmitted in each cycle. These data elements are referred to as cyclic data or process data.They also include elements that are typically distributed across multiple cycles. These data elements can only be transmitted upon request—therefore, they are referred to as on-request data or acyclic data. On-request data is used, for example, for parameters or event messages. The processing unit of the device according to the invention can also be implemented as a (further) MCU.

[0021] Different m-sequence types can be used to specify different fixed-size data elements. Which m-sequence types are used in IO-Link communication is preferably determined by the IO-Link devices. If an IO-Link master sends process data "PD" to a (secondary) device, this data can be called PDOut in the IO-Link interface and system specification. If an IO-Link master receives PD, this data can be called PDIn. The total size of the process data for an IO-Link device is limited to 32 bytes PDOut and 32 bytes PDIn. If the direction of the data flow is not important for a given analysis, the suffixes In / Out can be skipped in the following description.

[0022] A PHY can be provided, which is in particular a specific electrical circuit connected to the MCU. This converts the electrical characteristics of the MCU signal into signals that are compliant with the IO-Link physical layer. The PHY therefore refers specifically to the physical layer of the communication protocol. This can be the first layer of the ISO-OSI reference model, which provides the mechanical, electrical, functional, and procedural means for activating, maintaining, and deactivating physical connections for bit transmission between data transmission units. It can be responsible for transmitting the electrical signals over the physical medium, such as wires or cables, between the IO-Link master and the IO-Link device. The PHY layer can define the electrical characteristics of the communication, such as:the voltage levels, signal timing and signal coding, and ensures reliable and accurate data transmission.

[0023] The physical layer can use a three-wire interconnect system, with three lines used as follows: one for power, one for ground, and one (C / Q) for the switching signal or SDCI (Single-Drop Digital Communication Interface) communication. The physical layer is responsible for configuring the C / Q line and the associated line driver and receiver for a specific port.

[0024] In the device and / or method according to the invention, it is further possible for the processing blocks to be configured to process the one or more input scalars and / or the one or more output scalars for which they were inserted, in particular processing blocks that perform digital filter operations or spectral transforms such as fast Fourier transforms. Therefore, the processing blocks can be structured to maintain the number of scalar signals, enabling stable and resource-efficient processing.

[0025] It is also possible for the blocks to be configured to be processed in a defined order, preferably such that all input scalars of a current block are evaluated before the current block is evaluated. This can have the advantage of making the blocks more reliable and / or resource-efficient, and in particular, allowing the results of previous blocks to be used as input for subsequent blocks in the same cycle. This can increase the overall accuracy of the system and reduce the probability of errors.

[0026] It is also possible for the device to be configured to process the incoming and / or outgoing data elements cyclically, such that the Boolean signals evaluated in one cycle are provided as input for a subsequent block in the following cycle. This can have the advantage of making the processing of the data elements more efficient and faster, since the Boolean signals can be passed continuously and without unnecessary delays.

[0027] It is also possible for at least one of the blocks, in particular the logic block, to be configured based on a configuration specification. The configuration specification can be customizable by a user, thereby enabling the processing and in particular the logical operations and / or the insertion of the processing blocks to be configured. The configuration specification can, in particular, be stored on a storage medium. It is also possible for the configuration to be performed by loading a memory dump into the device. The configuration in the memory dump can then be linked to the operation of the device in a resource-efficient manner.

[0028] It is also possible for the device to provide a configurable logic adapter that uses configurable logic to process, preferably transform, and / or select, the data elements of the data received from at least one or more secondary devices, and that processes and / or combines the data elements to generate data to be sent to a master device. In this way, the device can enable communication between the devices, for example, for data aggregation.

[0029] It is also possible for the device to comprise and / or provide an interface, in particular an electronic and / or graphical and / or human-machine interface. The interface can be provided to allow a user to configure the processing and, in particular, a configurable logic, and thus to adapt the processing of the data elements to the higher-level application, in particular an evaluation and / or control of at least one or more secondary devices, in particular sensors and / or actuators.

[0030] The invention further relates, in particular, to a system for providing communication in an automation system. The system may comprise at least one of the following elements: - a higher-level unit, e.g. a programmable logic controller, for providing a higher-level application, in particular an automated control of industrial processes of the automation system, - a master device for connection to the higher-level system, in particular to a programmable logic controller, to provide a communication system, - at least one or more secondary devices which are controlled and / or evaluated by the higher-level unit, in particular the programmable logic controller, via the master device, whereby the higher-level application is at least partially executed, - the device according to the invention for connecting the at least one or more secondary devices to the master device, whereby a data exchange for controlling and / or evaluating the secondary devices is enabled via the communication system.

[0031] The invention further relates, in particular, to a method for cyclically processing incoming and / or outgoing data elements. As described above, the data elements may represent numerical and / or logical values ​​linked to a higher-level application. The method may comprise the following steps, or at least one of them, which are performed, in particular, cyclically: - converting at least one or more of the data elements after a linear operation into at least one or more input scalar signals of a generic data type, in particular an IEEE 754 float and / or after an additional quantization into at least one or more Boolean signals, wherein the conversion can be carried out in particular by a distribution block, - performing at least one or more combining operations, wherein each combining operation may consist of combining at least one or more of the input scalar signals into a (single) output scalar signal, wherein the combining operations may in particular be performed by a combiner block, - reconverting at least one or more of the scalar output signals and / or the Boolean signals and / or an output based on these signals into one or more data elements after a linear operation and / or a quantization step, wherein the reconversion can be carried out in particular by a merging block, - performing logical operations on at least one or more of the Boolean signals and in particular providing both input (hence also input) and output (hence also output) for the Boolean signals, wherein the logical operations can in particular be performed by a logic block, - Inserting processing blocks, in particular in one or more input scalar signals, between the distribution block and the combiner block or, in particular in one or more output scalar signals, between the combiner block and the merging block.

[0032] The method according to the invention thus provides the same advantages as those described in detail with reference to a device according to the invention. The method steps can be carried out at least partially by a computer program and / or an electronic circuit. For this purpose, each of the blocks described above can be embodied as part of the computer program and / or the electronic circuit.

[0033] It is possible for the processing blocks to process the one or more input scalar signals and / or the one or more output scalar signals for which they were inserted. Alternatively or additionally, it is possible for the number of scalar signals to remain unchanged as they pass through the processing blocks. This has the advantage of efficient processing using a device with limited resources.

[0034] It is possible for the blocks to be processed in a defined order, preferably such that all input scalars of a current block are evaluated before the current block is evaluated. Alternatively or additionally, it is possible for the Boolean signals evaluated in one cycle to be provided as input to a subsequent block in the following cycle. This also enables efficient processing with a device with limited resources.

[0035] It is possible that the processing of the data elements includes: - Inputting the data elements into a group of processing blocks, thereby generating an output of the group of processing blocks, - Generating modified data elements based on the output of the group of processing blocks, wherein connections and / or a structure of the group of processing blocks can be defined by an adaptable configuration of logic.

[0036] The device can also be configured to connect at least one or more secondary devices to a master device. The device can be configured as an IO-Link-capable device to be inserted between the at least one or more secondary devices, each configured as an IO-Link device, and the master device configured as an IO-Link master. The device can comprise a device port configured for connection to the master device. Furthermore, the device can comprise at least one or more master ports configured for connection to the at least one or more secondary devices.It is also conceivable for the device to comprise a processing unit configured to establish data communication with the master device via the device port and to establish data communication with the secondary devices via the at least one or more master ports, thereby providing data exchange between the secondary devices and the master device via the device, each data communication being configured as point-to-point communication. Furthermore, the processing unit may be configured to process, preferably aggregate, the data received from the at least one or more secondary devices for point-to-point communication with the master device via the device port using configurable logic. The processing unit may also be configured to carry out the steps of a method according to the invention.

[0037] A further aspect of the invention may be a method for connecting at least one or more secondary devices to a master device via a device, the method comprising the following steps, which are carried out in particular by the device and / or the system according to the invention: - receiving data from the at least one or more secondary devices via at least one or more master ports of the device, wherein the at least one or more master ports are designed such that they can be connected to the secondary devices, in particular via cables, - processing the received data for point-to-point communication of the device with the master device, the processing being carried out using configurable logic, - Providing modified data based on the processing, wherein the modified data is specific to the data received from each of the at least one or more secondary devices and to a current configuration of the logic, - Sending the modified data to the master device via a device port of the device, wherein the device port is designed such that it can be connected to the master device, in particular via cable.

[0038] In a further aspect of the invention, a computer program, in particular a computer program product, can be provided that comprises instructions that, when executed by a computer, cause the computer to perform the method according to the invention. In this way, the computer program according to the invention can have the same advantages as those described in detail with reference to a method according to the invention.

[0039] The computer may be a data processing device that executes the computer program. The computer may include at least one processor that can be used to execute the computer program. A non-volatile data memory may also be provided in which the computer program can be stored and from which the computer program can be read for execution by the processor.

[0040] According to a further aspect of the invention, a computer-readable storage medium can be provided that comprises the computer program according to the invention. The storage medium can be embodied as a data storage device, such as a hard disk and / or a non-volatile memory and / or a memory card and / or a solid-state drive. The storage medium can, for example, be integrated into the computer.

[0041] Furthermore, the method according to the invention can be carried out as a computer-implemented method.

[0042] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. The drawings show: Fig. 1 Parts of a device according to embodiments of the invention. Fig. 2 Further parts of a device according to embodiments of the invention. Fig. 3 Visualization of a method according to embodiments of the invention. Fig. 4 An example of an IO-Link process data structure. Fig. 5-13 Further visualizations of a method according to embodiments of the invention and of a device according to the invention. Fig. 14 Method, a computer program, a device and a storage medium according to embodiments of the invention.

[0043] Fig. 1-14 and in particular Fig. 6 show a device 200 according to embodiments of the invention for cyclically processing incoming and / or outgoing data elements 11. The data elements 11 can represent numerical and / or logical values ​​that are linked to a higher-level application. The device 200 can comprise a distribution block 13, in particular a distribution group, which converts at least one or more of the data elements 11 after a linear operation into at least one or more input scalar signals 105a of a generic data type, in particular an IEEE 754 float, and / or after additional quantization into at least one or more Boolean signals 106. Furthermore, the device can comprise a combiner block 14 that performs at least one or more combining operations, wherein each combining operation comprises combining at least one or more of the input scalar signals 105a into an output scalar signal 105b.Furthermore, the device may comprise a merging block 16 that reconverts at least one or more of the output scalar signals 105b and / or the Boolean signals 106 and / or an output based on these signals 105b, 106 into one or more data elements 11 after a linear operation and / or a quantization step. The device may also comprise a logic block 17 that performs logical operations on at least one or more of the Boolean signals 106 and, in particular, provides both input and output for the Boolean signals 106. Furthermore, the device may comprise processing blocks 15 that are configured to be inserted, in particular, into one or more input scalar signals 105a between the distributor block 13 and the combiner block 14, or, in particular, into one or more output scalar signals 105b between the combiner block 14 and the merging block 16.

[0044] There are several scenarios that cause conventional IO-Link setups to fail. The first and simplest scenario is the lack of IO-Link master ports in a given industrial setup. This scenario occurs when additional sensors or actuators need to be added for extended or improved functionality, and all ports of the current IO-Link master are in use, making adding an additional master inappropriate. A second failure scenario occurs when a specific device needs to be replaced with a similar device with similar or comparable properties but a different cyclic data structure. A third failure scenario arises from the need for low-latency feedback from a sensor to an actuator, especially in configurations where a PLC is not used as a client.Simple sequencing is an extension of low-latency feedback that provides means for execution loops and decision-making. A fourth error scenario arises with clients of the IO-Link system that require data in a specific, possibly preprocessed format that does not match the data format provided by the connected IO-Link device. These scenarios are resolved by embodiments of the invention, in particular by the aggregator device 'AGG' and the configurable logic adapter 'CLA' included therein.

[0045] Fig. 1 shows a schematic example view of the AGG device 3 with a device port 2 that can be connected to an IO-Link master 7 and a number of master ports 1a to 1d that can be connected to IO-Link devices 8.

[0046] Fig. Figure 2 shows the core components of an AGG device according to embodiments of the invention. The device PHY4 is an electronic circuit that converts IO-Link signals exchanged with an external IO-Link master 7 via the device connector 2 into signals compatible with the microcontroller unit 5 (MCU). The microcontroller unit executes software for data exchange with an external master 7, and it executes software for data exchange via master PHYs 6 and master ports 1 to IO-Link devices 8.

[0047] In Fig. Figure 3 shows an example basic structure of the software executed by the MCU 5. The IO-Link data exchange 100 with an external IO-Link master is handled by the IO-Link device stack 8. Another software module is the IO-Link master stack 10b, which is responsible for the IO-Link data exchange 101, 102, 103, 104 with the connected IO-Link devices 8. An AGG device application 9 with a configurable logic adapter 200 is responsible for processing the data exchanged with the IO-Link device stack 8 on the one hand and for processing the data exchanged with the IO-Link master 10b on the other hand. The data exchange with the IO-Link master 10b takes place via a standardized master interface 10a, called "SMI". Limitations of the AGG device

[0048] According to embodiments of the invention, when an IO-Link master sends process data "PD" to a device, this data is referred to as PDOut in the IO-Link interface and system description. When an IO-Link master receives PD, this data is referred to as PDIn. The total size of the process data for an IO-Link device is limited to 32 bytes PDOut and 32 bytes PDIn. If the direction of data flow is not important for a given analysis, the suffixes In / Out are omitted in the following description.

[0049] A limitation of an AGG device according to embodiments of the invention is that the cumulative PDIn / PDOut of any four IO-Link devices 8 connected to an AGG device 3 can amount to up to 128 bytes in each direction. In such cases, a selection is required that determines which process data is transmitted to the external master 7 via the IO-Link interface 100. It is a further task of the AGG device application 9 to make a corresponding selection.

[0050] According to embodiments of the invention, a further limitation of the AGG device results from the time required to transmit a certain amount of data serially over the IO-Link cable. An expression for estimating this time is provided in Chapter A.3.6, M-Sequence Time, of the IO-Link System and Interface Specification. tM−sequence=11(m+n)TBIT+tA+t1(m−1)+t2(n−1)

[0051] Where m is the number of bytes sent from the IO-Link master to the device, n is the number of bytes sent from the device to the IO-Link master, T BIT the time required to transmit one bit with TBIT=1Baudrate,1TBIT≤tA≤10TBIT,0TBIT≤t1≤10TBIT and 0TBIT≤t1≤3TBIT.

[0052] The formula shows how the time for data transmission increases with its amount. For the minimum cycle time of an IO-Link device, the following inequality t cycle > t M-sequence always apply.

[0053] For example, the minimum cycle time of AGG device 3 can be greater than the minimum cycle time of the connected IO-Link device 8 if the process data size of the AGG device is larger. Direct process data mapping

[0054] As mentioned above, PDIn or PDOut have a fixed byte length for a specific m-sequence type. The process data structure, as defined in the IODD, divides the process data into smaller elements with specific data types, here called data elements.

[0055] An example of a typical process data structure is shown in Fig. 4. Here, the process data, with a total size of four bytes, is divided into five typed data elements 11: a 16-bit integer representing a distance, two Boolean values ​​representing threshold values, a 14-bit integer representing a level, and an 8-bit integer representing a temperature. The data structure and physical units of the data elements are specified in the IODD electronic data sheet of the IO-Link device.

[0056] According to embodiments of the invention, the direct assignment of process data between the AGG device port 2 and the AGG master ports can be carried out in a two-stage process, as in Fig. 11 for two connected devices. In a first step, the data elements 11a and 11b of the devices 8 connected to the incoming AGG master ports 1a, 1b can be selected. The selection is based on the given PD structure of the connected devices, as specified in the IODD. In a second step, these data elements can be combined to form the process data structure of the AGG device port 2 as a combination 11 of selected data elements 11a and 11b. The combination of the data elements is determined using a configuration tool that allows for a flexible combination of the PD elements.

[0057] However, direct mapping of process data can only be a solution for the first scenario - port expansion. Configurable logic adapter

[0058] Other scenarios, according to embodiments of the invention, require a more complex device application that enables the routing and processing of process data. A practical solution for this task presents significant challenges, as it must meet certain requirements to be generally applicable in automation systems. These requirements are: The device application should be usable for any IO-Link devices 8 connected to the master ports 1.

[0059] The device application 9 must enable the routing of process data elements 11 between an IO-Link device and other IO-Link devices 12a and between IO-Link devices and the external master 12b, as described in Fig. 5 shown. Configurable logic adapter CLA

[0060] Embodiments of the invention offer a new solution to these requirements with a structure referred to in this context as a configurable logic adapter “CLA” 200, which may be part of the device application 9, as shown in Fig. 6. The CLA is based on a fixed structure. Only one configuration is required to solve the desired scenarios. In particular, no software changes are required. This allows the CLA to be tested once for its basic functionality and stability, since reconfiguring the CLA does not affect fundamental properties of the CLA, such as stability or integrity. CLA data types

[0061] According to embodiments of the invention, the CLA uses only two data types, called scalars 105 and boolean values ​​106, which are handled differently. Scalars can be used to transmit numerical process data in a generic manner. Their value range should therefore be sufficiently large to process all numerical process data without significant loss of accuracy. In the preferred implementation of the CLA, the FLOAT32 "float" data type according to IEEE754 is used. However, other data types such as DOUBLE would also meet these requirements.

[0062] According to one embodiment of the invention, process data elements 11 are converted to float types by converting them to scalars. Conversion to scalars or boolean values ​​can only be applied to the following process data element types: Boolean, Ulnteger, Integer, and Float32 (see A.1.4 of the IO-Link Interface and System Specification). The remaining types (Time, TimeSpan, String, and OctetString) can, in particular, only be used for the aforementioned direct mapping and are not handled by the CLA.

[0063] The logical (Boolean) values ​​106 can be represented by two states: "True" and "False." In a preferred implementation of the CLA, these states are mapped to a byte, with the byte value 0 being mapped to "False" and any other byte value being mapped to "True." Both data types can be used to transmit numeric information within the CLA. CLA blocks

[0064] According to embodiments of the invention, CLA blocks may have scalars or Boolean values ​​as input data and generate new scalars or Boolean values ​​as output data. The process of generating the output data may be defined by an algorithm that executes a finite number of steps. The execution of the steps may be triggered by an event, referred to in this context as a "block cycle."

[0065] With a main cycle “Cycle” all block cycles for all CLA blocks can be executed in a defined configured order at a specific time.

[0066] In a preferred embodiment of the present invention, the order of execution is chosen such that each scalar input to a current block must be evaluated before the current block is executed. The initial input scalars of the data elements are all sampled in this main cycle, which represents the beginning of the cycle.

[0067] In a preferred embodiment of the present invention, six types of blocks are defined. (1) Distribution blocks 13 are characterized by the fact that they accept data elements of the process as input and produce scalars or bools as output. (2) The processing blocks 15 are characterized by accepting scalars or bools as inputs and generating scalars or bools. In a preferred embodiment of this invention, the processing blocks must have an identical number of incoming and outgoing scalars. (3) Binarization blocks 15a are special processing blocks characterized by having at least one input scalar, no output scalars, and at least one boolean output. (4) Logic blocks 17, which only have Boolean inputs or outputs. (5) Combiners 14, which are characterized by having several input scalars but only one output scalar. (6) Merge blocks 16 are characterized by having an input scalar that can be forwarded to various outgoing data elements of the process. (7) Signal generators 18, which cyclically generate simple signals in conjunction with an IO-Link signal. CLA operation

[0068] According to embodiments of the invention, the process data sources are considered as data input devices 2i, 1ai, 1bi, 1ci, 1di and 18 and are located on the left side of Fig. 6. Incoming data elements are selected by the distribution block 13 and converted to scalars or boolean values. The details of the selection and conversion are configurable.

[0069] In a preferred embodiment of the CLA, the conversion of data elements to scalars is adjusted by a scaling factor and an offset. For example, an IntegerT type is converted to a scalar by an operation that realizes the following equation: Scalari=scale∗float(IntegerT)+offset

[0070] According to embodiments of the invention, converting a data element to bool requires a quantization step if the data element is not of type bool. The quantization step can be performed by an operation that realizes the following inequality: bool=(data element≥threshold)

[0071] Scalars and bools can be treated differently in the configurable logic adapter. Signal generators

[0072] To support simple sequence logic, according to embodiments of the invention, an artificial device port 18 can be added to the AGG device, which generates some simple value sequences such as a counter. The counter output can be used to generate control signals required for the sequence logic. Dealing with scalars

[0073] According to embodiments of the invention, the input scalars 105a can be routed from the distributor 13 to the combiner 14. It is possible to insert processing blocks 15 into the route. In a preferred embodiment of the present invention, the number of scalars input to a processing block is identical to the number of scalars output from a processing block. Processing blocks between the distributor and the combiner are also referred to as preprocessing blocks.

[0074] The output scalars 105b can be routed from the combiner 14 to the merge block 16. It is possible to insert processing blocks 15 into the route. Processing blocks between the combiner and the merge block are referred to as post-processing blocks.

[0075] The operation of a processing block can be specified by a procedure that performs operations on the input scalars to produce output scalars. A processing block may include a state memory. A typical example of a processing block with an input scalar and an output scalar is a moving average block, which produces the average of the last N input signals as the output signal.

[0076] A processing block with two input scalars can be a coordinate conversion block that converts from Cartesian coordinates (x, y) to polar coordinates (amplitude and phase). However, processing blocks that require configurable coefficients can also be supported, such as a finite impulse response (FIR) filter block that performs an operation according to the following equation: y(n)=∑i=0N−1h(i)x(n−1) where x(n) is the input scalar, y(n) is the output scalar and h(i) are the filter coefficients.

[0077] An important feature of embodiments of the present invention is that scalars cannot be used to create a direct feedback loop within the CLA. Combiner 14

[0078] Fig. Figure 7 shows an example structure of the combiner block 14. The combiner block is organized into rows. Each row can combine any input scalars and generates an output scalar. The number of rows 14a ... 14n of the combiner block is configurable.

[0079] Preferred embodiments of the combiner are described by the following equations: SO(j)=∑i=0I−1c(i)∗si(i)m(i)+o(i) SO(j)=o(j)+c(j)∏i=0I−1si(i)m(i)

[0080] A first preferred embodiment allows for a linear combination of all input scalars. For example, if the input scalar si(0) represents a first distance measured by device 8a and the scalar si(1) represents a second distance measured by another device 8b, a simple linear combination with I = 2, c(i) = 1, m(i) = 1, and o(i) = 0 results in an operation that evaluates the sum of the two distances so(j) = si(0) + si(1).

[0081] The second preferred embodiment is tied to the product of the input scalars. For example, if the input scalar si(0) represents a current I measured by device 8a and the scalar si(1) represents a voltage U measured by device 8b, the product term with o(j) = 0, c(j) = 1, m(i) = 1 leads to an operation that evaluates an electrical power as the product of both scalars: s0(j) = si(0) ∗ si(1) = U ∗ I. Merge block 16

[0082] Finally, according to embodiments of the invention, the merging block 16 can be used to convert scalars and Boolean values ​​back into data elements 11a...11f. The merging process may require a quantization step. To convert a scalar into a data element, in a preferred embodiment of the invention, a linear operation may be applied to the output scalar s0(j). DataElement=Limit(Integer(so(j)∗scale+offset))

[0083] The scaling factor and offset are configurable to adapt the range of output scalar values ​​to the limited data range of the data element. For an 8-bit integer, all float values ​​less than -128 would be mapped to -128, and all float values ​​> 127 would be mapped to 127. The non-integer part of the float value is discarded.

[0084] The outgoing merged data elements 11a ... 11f can be sent to the output ports 2o, 1ao, 1bo, 1co, 1do. The output port 2o and the input port 2i can be physically realized as the AGG device port 2. The output port 1ao and the corresponding input port 1ai can be physically realized by the same master port 1a, etc. Handling Bools

[0085] According to embodiments of the invention, Boolean data can be passed arbitrarily from input data elements to output data elements. The order of processing Boolean values ​​cannot be specified. Each block that uses a Boolean value uses the value stored before the block's execution. The result of a Boolean operation is stored and made available to other blocks for the next cycle.

[0086] Thus, each boolean can include a delay. This allows the implementation of feedback loops with booleans without creating unstable recursions. Conversion of scalars to booleans can be performed using binarization blocks 15a. Configuring the CLA

[0087] According to embodiments of the invention, the requirement for simple configuration of the CLA without programming effort and taking into account the limited resources of the AGG hardware can be realized as follows. The setup of the device application should be simple and involve no programming and take into account the available memory resources of the AGG device hardware. The device application must be flexible and offer expandability to meet future requirements. The requirements for the CLA can be easily met if the operations to be performed by the CLA are implemented by a software program. However, such a solution requires software engineers to write a corresponding program, which must be adapted or modified and retested with each change.Such a program is usually written in an interpreted programming language, which requires interpreter software running within the CLA - and slows down the execution of the code. Configuration tool

[0088] Fig. 20 shows an example of how a configuration tool “CLA-Composer” 20 can be provided, which can be run on a PC. The configuration tool (see Fig. 8) has functionality for importing IODD files 23 from connected IO-Link devices. The IODD contains information about the process data elements of the connected IO-Link devices. The TCLA also provides the user with a list of processing blocks for insertion. The list of processing blocks refers to the processing blocks present in the current AGG device. The details of the processing blocks are described in defined XML files, the so-called Processing Block Descriptor (PBD) files 21.

[0089] According to embodiments of the invention, the existing processing blocks must be extended when new requirements arise, e.g., the need for data transformation from the time domain. In this case, the existing firmware of the AGG device can be extended with the new processing block via a firmware update.

[0090] Fig. Figure 9 shows an example of a CLA layout. The process data elements "Alarm," "VMA," and "Level" shown in the example under Inputs are taken from the imported IODD of the connected device. The data element "Level" is mapped to two scalars, "S1" and "S2," in the example. The signals are routed through two processing blocks, "prcallpass_1_chain_1" and "prcblc_delay_1." The blocks can be inserted into scalar lines using GUI components of the TCLA Composer. Configuration transfer between TCLA Composer and AGG device

[0091] According to embodiments of the invention, after the routing of booleans and scalars is completed and all blocks are formed, the configuration must be transferred to the AGG device.

[0092] Since the AGG device has limited resources, especially limited memory, it is desirable to perform a resource check during the configuration phase. This is achieved, in particular, by creating an image of the entire volatile memory within the composer 24.

[0093] The CLA can check whether the generated memory image fits into the memory area reserved in the AGG before executing the transfer. The memory image can be downloaded to the AGG device using an IO-Link function called BLOB transfer.

[0094] The AGG device application may include a parser 201 for the memory map 24 to link coefficients, memory elements, etc., to the CLA 200. Parsing depends on a formal description of the memory map. An example for the "BLOCK" element is given below.

[0095] The memory map 24 of the processing blocks can be uniquely linked to the structural description of the PBD files 21. Thus, the extensibility requirement is met if the new processing block is described by the PBD.

[0096] In a preferred embodiment of the invention, certain portions of the memory may be reorganized during parsing (e.g., to support different ENDIANESS). In particular, elements of the memory map that only contain data supporting correct parsing may be reused by the application after parsing by the algorithm. Alternative scenario of the CLA

[0097] Fig. Figure 13 shows another preferred embodiment of the CLA. The CLA 200 is now directly connected to the higher-level side of an external IO-Link master 7, which controls at least one IO-Link connection 100. Data exchange between a higher-level system 500, which can be a PLC, a web server, or another client of the IO-Link master, runs via the CLA. In this case, the CLA can be used for signal conditioning or feedback loops, as described for the AGG device.

[0098] In Fig. 14 shows a method 300 for cyclically processing incoming and / or outgoing data elements 11, wherein the data elements 11 represent numerical and / or logical values ​​that are linked to a higher-level application. According to a first method step 301, at least one or more of the data elements 11 can be converted after a linear operation into at least one or more input scalar signals 105a of a generic data type, in particular an IEEE 754 float, and / or after additional quantization into at least one or more Boolean signals 106, wherein the conversion is carried out in particular by a distribution block 13.According to a further method step 302, at least one or more combining operations can be performed, wherein each combining operation comprises combining at least one or more of the input scalar signals 105a into an output scalar signal 105b, wherein the combining operations are carried out in particular by a combiner block 14. According to a further method step 303, at least one or more of the output scalar signals 105b and / or the Boolean signals 106 and / or an output based on these signals 105b, 106 can be converted back into one or more data elements 11 after a linear operation and / or a quantization step, wherein the reconversion is carried out in particular by a merging block 16.According to a further method step 304, logical operations can be performed on at least one or more of the Boolean signals 106, wherein, in particular, both an input and an output are provided for the Boolean signals 106, wherein this step is performed, in particular, by a logic block 17. Processing blocks 15 can also be inserted, in particular, into one or more input scalar signals 105a, between the distributor block 13 and the combiner block 14, or, in particular, into one or more output scalar signals 105b, between the combiner block 14 and the merging block 16.

[0099] In Fig. 14 also shows a computer program 420, a data processing apparatus 410, a system, and a computer-readable storage medium 430 according to embodiments of the invention.

[0100] The preceding explanation of the exemplary embodiments describes the present invention within the framework of examples. Of course, individual features of the exemplary embodiments can be freely combined with one another, provided this is technically feasible, without departing from the scope of the present invention. List of reference symbols 1 master port 1a first (secondary) master port 1b or second (secondary) master port 1c third (secondary) master port 1d fourth (secondary) master port 1ao output port 1bo output port 1co output port 1do output port 2 Device port, device port connection, port to external master 2i input port 2o Output port 1ai input port 1bi input port 1ci input port 1di input port 3 Device, aggregator device, AGG 4 Device PHY 5 Microcontroller unit, controller unit 6,6a-6d Master PHYs 7 external IO-Link master, master device, external master 7a Port of 7 7b Remaining ports 8 IO-Link device stack 8a,8b,8c,8d secondary devices 9 AGG device application, IO-Link device, secondary device 10a IO-Link master interface “SMI”, Agg device application 10b IO-Link Master Stack 11 Data elements of the AGG device port 11a,11b Data elements of embedded master ports 11c Data element 11d Data Element 11e Data Element 11f Data element 12a Feedback path 12b Transmission path 13 distributors 14 combiners 14a Combiner row a 14n combiner row n 15 Processing block 15a Binarization block 16 Merge block 17 Logic block 18 Signal generator 19 CLA configuration file 20 CLA 21 IODD files 22 PBD files 23 selected data elements 24 Composers PLC Programmable Logic Controller 100 external IO-Link 101 IO-Link to device 8a 102 IO-Link to device 8b 103 IO-Link to device 8c 104 IO-Link to device 8d 105 Scalar signal 105a Input scalars 105b Output scalars 106 Boolean signal 200 CLA 201 parsers 300 procedures 301-304 Procedural steps 400 Higher-level system, e.g., PLC 410 Data processing device 420 computer program 430 storage medium 500 communication system QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] Balluf BNI IOL-302-002-K006

[0008]

Claims

[1] Device (200) for cyclically processing incoming and / or outgoing data elements (11), wherein the data elements (11) represent numerical and / or logical values ​​associated with a higher-level application, the device (200) comprising: - a distribution block (13) for converting at least one or more of the data elements (11) after a linear operation into at least one or more input scalar signals (105a) of a generic data type, in particular an IEEE 754 float and / or, after an additional quantization, into at least one or more Boolean signals (106), - a combiner block (14) for performing at least one or more combining operations, each combining operation comprising combining at least one or more of the input scalar signals (105a) into an output scalar signal (105b), - a merging block (16) for reconverting at least one or more of the scalar output signals (105b) and / or the Boolean signals (106) and / or an output based on these signals (105b, 106) into one or more data elements (11) after a linear operation and / or a quantization step, - a logic block (17) for performing logical operations with at least one or more of the Boolean signals (106) and in particular for providing both an input and an output for the Boolean signals (106), - processing blocks (15) which are designed to be inserted, in particular in one or more input scalar signals (105a), between the distributor block (13) and the combiner block (14) or, in particular in one or more output scalar signals (105b), between the combiner block (14) and the merging block (16). [2] Device (200) according to claim 1,characterized by that the processing blocks (15) are configured to process the one or more input scalars (105a) and / or the one or more output scalars (105b) for which they were inserted, in particular processing blocks that perform digital filter operations or spectral transforms such as fast Fourier transforms. [3] Device (200) according to one of the preceding claims, characterized by that the blocks (14, 15, 16) are configured to be processed in a defined order, preferably such that input scalars of a current block are evaluated before the current block is evaluated. [4] Device (200) according to one of the preceding claims, characterized bythat the device (200) is configured to process the incoming and / or outgoing data elements cyclically such that the Boolean signals (106) evaluated in one cycle are given as input for a subsequent block in the following cycle. [5] Device (200) according to one of the preceding claims, characterized by that the blocks (14, 15, 16) and in particular the logic block (17) are configured on the basis of a configuration specification, wherein the configuration specification is adaptable by a user, whereby the processing and in particular the logical links and / or the insertion of the processing blocks (15) are made configurable, and wherein the configuration specification is stored in particular in a storage medium. [6] Device (200) according to one of the preceding claims, characterized bythat the device (200) provides a configurable logic adapter which uses configurable logic to process, preferably convert and / or select the data elements (11) of the data received from at least one or more secondary devices (8), and processes and / or combines the data elements (11) to generate data to be sent to a master device (7a). [7] Device (200) according to one of the preceding claims, characterized by that the device (3) comprises an interface, wherein the interface is provided for configuring the processing and in particular a configurable logic by a user, whereby the processing of the data elements (11) is adapted to the higher-level application, in particular an evaluation and / or control of at least one or more secondary devices (8), in particular sensors and / or actuators. [8] System for providing communication in an automation system, comprising: - a programmable logic controller (PLC) for providing a higher-level application, in particular an automated control of industrial processes of the automation system, - a master device (7a) connected to the programmable logic controller (PLC) to provide a communication system, - at least one or more secondary devices (8) which are controlled and / or evaluated by the programmable logic controller (PLC) via the master device (7a), whereby the higher-level application is at least partially executed, - the device (3) according to one of claims 1 to 7 for connecting the at least one or more secondary devices (8) to the master device (7a), whereby a data exchange for controlling and / or evaluating the secondary devices (8) takes place via the communication system. [9] Method (3001) for cyclically processing incoming and / or outgoing data elements (11), wherein the data elements (11) represent numerical and / or logical values ​​associated with a higher-level application, the method comprising: - converting (301) at least one or more of the data elements (11) after a linear operation into at least one or more input scalar signals (105a) of a generic data type, in particular an IEEE 754 float and / or after an additional quantization into at least one or more Boolean signals (106), wherein the conversion is carried out in particular by a distribution block (13), - performing (302) at least one or more combining operations, each combining operation comprising combining at least one or more of the input scalar signals (105a) into an output scalar signal (105b), the combining operations being performed in particular by a combiner block (14), - reconverting (303) at least one or more of the output scalar signals (105b) and / or the Boolean signals (106) and / or an output based on these signals (105b, 106) into one or more data elements (11) after a linear operation and / or a quantization step, wherein the reconversion is carried out in particular by a merging block (16), - performing (304) logical operations on at least one or more of the Boolean signals (106) and in particular providing both input and output for the Boolean signals (106), wherein the logical operations are performed in particular by a logic block (17), - Inserting processing blocks (15), in particular into one or more input scalar signals (105a), between the distributor block (13) and the combiner block (14) or, in particular into one or more output scalar signals (105b), between the combiner block (14) and the merging block (16). [10] Method according to claim 9, characterized by that the processing blocks (15) process the one or more input scalar signals (105a) and / or the one or more output scalar signals (105b) for which they were inserted. [11] Method according to claim 9 or 10, characterized bythat the number of scalar signals (105a, 105b) is not changed when passing through processing blocks (150). [12] Method according to one of claims 9 to 11, characterized by that the blocks (14, 15, 16) are processed in a defined order, preferably such that all input scalars of a current block are evaluated before the current block is evaluated. [13] Method according to one of claims 9 to 12, characterized by that the Boolean signals (106) evaluated in one cycle are given as input for a subsequent block in the following cycle. [14] Method according to one of claims 9 to 13, characterized by that the processing (102) of the data elements (11) comprises: - inputting the data elements (11) into a group of processing blocks (150), thereby generating an output of the group of processing blocks (50), - generating modified data elements (11) based on the output of the group of processing blocks (150), wherein connections and / or a structure of the group of processing blocks (150) is defined by an adaptable configuration of logic. [15] A computer program comprising instructions which, when the computer program is executed by a computer, cause the computer to carry out the method according to any one of claims 9 to 14. [16] A data processing device comprising means for carrying out the method according to any one of claims 9 to 14. [17] A computer-readable storage medium comprising instructions which, when the computer program is executed by a computer, cause the computer to carry out the method according to any one of claims 9 to 14.

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