Procedures for terminal stage diagnosis

Abstract

The invention relates to a device and a method for final stage diagnostics in automotive engineering with a transistor (T1) connected to a first load (12) and with a microcontroller (14) having a digital input / output (Dig1) and a digital output (Dig2), wherein Dig1 and Dig2 are connected to the first load (12) via a transistor (T1), wherein in a first step (100) the transistor (T1) is switched off.

Description

[0001] The invention relates to a method for final stage diagnosis. State of the art

[0002] To control loads in automotive applications, intelligent power amplifiers are typically used. These amplifiers incorporate a power amplifier transistor as well as self-protection and diagnostic functions. The power amplifier is controlled via a microcontroller. Traditionally, voltage dividers are connected in parallel to several inputs of an ECU to distinguish between different faults (short circuit to battery, short circuit to ground, or open circuit / load drop). This ties up ECU resources. Alternatively, so-called intelligent ECUs can be used, although these are more expensive. Disclosure of the invention

[0003] Against this background, the present invention proposes determining the potential of the input after a certain waiting time when the circuit is open (e.g. transistor deactivated). Normally a high level should be present because the plug-in capacitor is charged via the attached load. If, on the other hand, a low level is present, an error (short circuit to ground or OL) can be assumed. In order to be able to distinguish between these two possible errors, the invention proposes an attempt to charge the plug-in capacitor via the control unit connection. If this is successful, an OL error is assumed because the capacitor could apparently not be charged via the load. However, if a low level is still present after the charging attempt, the charging current must have flowed away elsewhere, so a short circuit to ground can be assumed. In this way, a full diagnosis can be carried out with low resource consumption.

[0004] Advantages include: - Cost-effective implementation of power amplifiers for automotive control units through the use of simple standard transistors - Full power stage diagnostics (SCB, SCG, OL) for pulsed signals - Minimal resource consumption (of components and µC resources) - Higher control frequencies possible compared to Smart MOS FETs

[0005] Further advantages are taken from the figure description. Drawings

[0006] They show: Fig. 1: a first realization of a power amplifier, Fig. 2: a second realization of a power amplifier, Fig. 3: a method for power stage diagnosis. Description

[0007] The same reference numbers are used for the same components occurring in the different embodiments.

[0008] Fig. Figure 1 shows a first implementation of an output stage 10 that drives a first load 12. In this exemplary embodiment, the first load is embodied as an engine control unit (ECU). A microcontroller (µC) 14 has two digital outputs Dig1, Dig2, which are connected to the ECU via a transistor T1. A plug-in capacitor Cst is connected in parallel with T1. A second load LSS is connected to the output Dig2. The potential of LSS is at the battery voltage potential.

[0009] Fig. 2 shows a second realization of an output stage 10, which controls a first load 12, in particular an engine control unit, with a shunt 16.

[0010] The following describes a power stage diagnostic procedure that is performed by both circuit variants. The two fault cases SCG (short circuit to ground) and OL (load drop or open circuit) are diagnosed.

[0011] Normal operation: In a first step 100, transistor T1 is turned off. In a further step 110, the plug-in capacitor Cst is charged via a resistor R1. The time constant is Cst*RL. After a time t1, which is queried in 115, the level at digital input 1 (Dig 1) is read back in 120. This level is "high" in normal operation.

[0012] Error case: If the level in 125 is "low," an error has occurred. This error can be SCG or OL.

[0013] Differentiating between the two errors: In step 130, Dig 1 is switched to high level. If an OL error is present, Cst is charged via resistor R1.

[0014] If there is an SCG error, Cst cannot recharge and the level remains low.

[0015] In 140, after a waiting time tw, Dig 1 is switched back to input and the level is read back. Tw is determined by the time constant R1*Cst.

[0016] If an SCG is present, the level at Dig1 is low (145.

[0017] If an OL is present, the level at Dig1 is high (150).

[0018] The normal control sequence is then continued to confirm the error.

[0019] The diagnostic sequence is usually executed in the Global Timer Module (GTM) of the microcontroller (µC) to keep the runtime load low.

Claims

[1] Output stage (10) which controls a first load (12), in particular an engine control unit, with a microcontroller (14), wherein the microcontroller (14) has a digital input or output (Dig1) and a digital output (Dig2), wherein Dig1 and Dig2 are connected to the first load (12) via a transistor (T1) and wherein a plug capacitor (Cst) is connected in parallel to transistor (T1). [2] Method for final stage diagnosis in automotive technology with a transistor (T1) which is connected to a first load (12) and with a microcontroller (14) which has a digital input or output (Dig1) and a digital output (Dig2), wherein Dig1 and Dig2 are connected to the first load (12) via a transistor (T1), wherein in a first step (100) the transistor (T1) is switched off. [3] Method according to claim 2, wherein in a further step (110) a plug capacitor (Cst) connected in parallel with the transistor (T1) is charged via a second load (LSS) arranged at the output (Dig1). [4] Method according to claim 3, wherein after a time (t1) the level at the digital input or output (Dig 1) is read back, said level being high in normal operation. [5] The method of claim 4, wherein in a step (130) Dig 1 is switched to high level, wherein Cst is charged via resistor R1 if an open load fault is present, wherein Cst cannot charge if a CSL fault is present. [6] Method according to claim 4, wherein in a step (140) Dig 1 is switched back to input and the level is read back.

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