CONCEPT FOR MEASURING A BASEBAND GROUP DELAY AND LOCAL OSCILLATOR PHASE TRANSFER FUNCTION FOR RADAR APPLICATIONS

Abstract

The present disclosure describes an integrated radar transceiver circuit (100). The integrated radar transceiver circuit (100) comprises a local oscillator (LO) circuit configured to provide an LO signal (123) having an LO frequency, a test signal generator (112) circuit configured to generate at least one test signal (113; 113') having at least one test signal frequency component, a booster circuit (126) configured to mix the test signal (113; 113') and the LO signal (123) to obtain a booster test signal (127), and at least one receive channel (130) comprising a step-down circuit (134) configured to mix the booster test signal (127) and the LO signal (123) to obtain a step-down test signal (135;139), a phase detector circuit (140) configured to determine a phase of the down-converted test signal (135; 139), and a processor (140) configured to determine delay information with respect to the integrated radar transceiver circuit based on the determined phase.

Description

Area

[0001] The present disclosure relates to integrated radar transceiver circuits and methods for measuring delay information, such as group delay or phase transfer functions, relating to the integrated radar transceiver circuits. background

[0002] Group delay is a concept used in signal processing and communication systems to characterize the time delay experienced by different frequency components of a signal as it passes through a system or device. In simpler terms, it measures how much a system delays the propagation of different frequencies within a signal. When a multi-frequency signal passes through a system, each frequency component can experience a different delay, resulting in a phase shift for each component. Group delay represents the rate of change of the phase shift with respect to frequency. Mathematically, the group delay τ at a specific angular frequency ω = 2πf is calculated as the negative derivative of the system's phase response φ with respect to the angular frequency. τ(ω)=−dφ(ω) / dω where τ(ω) is the group delay at angular frequency ω, φ(ω) is the phase response at angular frequency ω, and dφ(ω) is the derivative of the phase response with respect to angular frequency ω.

[0003] Group delay can be expressed in time units, such as seconds or milliseconds, and is a function of frequency. It can provide information about the time dispersion introduced by a system, making it possible to analyze and optimize system behavior, especially in applications where precise timing is important.

[0004] Accurate and absolute phase and group delay measurement / monitoring of a receiver (Rx) subsystem becomes a key requirement for cascaded frequency-modulated continuous-wave (FMCW) monolithic microwave integrated circuits (MMICs). The Rx subsystem refers to a receiver section of the MMIC responsible for detecting and processing radar echoes or return signals. Particularly with an increasing number of radar MMICs used for cascading, meaning that different MMICs operate at different process, voltage, and temperature (PVT) parameters, it is anticipated that each MMIC in the cascaded system would need to be calibrated to achieve the required inter-chip phase synchronization.

[0005] Furthermore, future radar systems will operate with increasingly higher intermediate frequency (IF) bandwidths, making inter-chip phase synchronization an even greater challenge. In an FMCW radar system, the IF bandwidth refers to the range of frequencies over which received radar signals are processed and analyzed. The IF bandwidth determines the system's ability to detect and accurately measure the frequency difference (beat frequency) between the transmitted and received signals, which is essential for calculating the range and velocity of targets.

[0006] Current solutions to the problems include, for example, phase calibration by measuring the corner frequency, for which errors begin to increase with the IF bandwidth.

[0007] Therefore, there is a need for an improved concept for phase and group delay measurement / monitoring. Summary

[0008] This need is addressed by devices and methods according to the attached claims.

[0009] According to a first aspect, the present disclosure proposes an integrated radar transceiver circuit (e.g., MMIC). The integrated radar transceiver circuit comprises a local oscillator (LO) circuit configured to provide an LO signal having an LO frequency. The integrated radar transceiver circuit further comprises a test signal generator circuit configured to generate at least one test signal having at least one test signal frequency component. While the LO frequency may be in the millimeter-wave frequency range (e.g., 76 to 81 GHz), the at least one test signal may have test signal frequency components in a much lower IF frequency range, for example, from 300 kHz to 30 MHz. The at least one test signal may be a digital test signal that can be converted from a digital to an analog domain within the integrated radar transceiver circuit.The integrated radar transceiver circuit further includes an up-conversion circuit designed to mix the test signal and the LO signal to obtain an up-converted test signal (in the millimeter wave frequency range).

[0010] The integrated radar transceiver circuit further comprises at least one Rx channel (of an Rx subsystem). The Rx channel includes a step-down conversion circuit configured to mix the step-up test signal (in the millimeter-wave frequency range) and the LO signal to obtain a step-down test signal (in the IF frequency range). The Rx channel further comprises a phase detector circuit configured to determine at least one phase of the step-down test signal. The integrated radar transceiver circuit further comprises a processor configured to determine delay information with respect to the integrated radar transceiver circuit based on the at least one determined phase.

[0011] When a test signal with a plurality of test signal frequency components (e.g., a non-sinusoidal test signal) or a plurality of test signals with individual test signal frequency components (e.g., sinusoidal test signals) is used, a plurality of phases and thus a baseband (BB) or IF group delay relative to the frequency of one or more Rx channels can be measured.

[0012] In some embodiments, the test signal generator circuit is configured to generate at least one further second test signal after the phase of the step-down test signal has been determined. The second test signal has a second test signal frequency component that differs from the (first) test signal frequency component (i.e., is higher or lower). The step-up circuit is configured to mix the second test signal and the LO signal to obtain a second step-up test signal. The step-down circuit is configured to mix the second step-up test signal and the LO signal to obtain a second step-down test signal. The phase detector circuit is configured to determine a second phase of the second step-down test signal.The processor is trained to determine a BB or IF group delay based on the specified (first) phase and the second phase. The group delay τ can be expressed as... τ=−Ø(f2)−Ø(f1)2π(f2−f1) where Ø(f) is the phase in radians at the test frequency component f.

[0013] In this way, phase errors caused by IF or BB processing of the integrated radar transceiver circuit can be measured and compensated for by further processing.

[0014] The person skilled in the art, benefiting from the present disclosure, will recognize that more than two test signals (with different test signal frequencies) can be used to increase the granularity of the group delay information.

[0015] In some embodiments, the test signal generator circuit is configured to generate the (first) test signal with the (first) test signal frequency component at a lower frequency end of an operating baseband (BB or IF) frequency range, and to generate the second test signal with the second test signal frequency component at an upper frequency end of the operating baseband (BB or IF) frequency range, or vice versa. The operating baseband (BB or IF) frequency range of the integrated radar transceiver circuit can, for example, extend from 300 kHz to 30 MHz.

[0016] In some embodiments, the test signal generator circuit is configured to generate the (first) test signal as a (first) sinusoidal signal exhibiting the (first) test signal frequency component, and subsequently to generate a second test signal as a second sinusoidal signal exhibiting a second test signal frequency component. Here, each sinusoidal test signal has a distinct test signal frequency.

[0017] In some embodiments, the test signal generator circuit is configured to generate the test signal as a non-sinusoidal signal containing a plurality of test signal frequency components. For example, the non-sinusoidal signal may comprise a square wave pulse containing multiple test signal frequency components within the operating baseband (BB or IF) frequency range. The phase detector circuit is configured to determine the respective phases of the plurality of test signal frequency components of the down-converted test signal, and the processor is configured to determine a group delay with respect to the integrated radar transceiver circuit based on the respective phases of the plurality of test signal frequency components. For this purpose, the processor may be configured to perform a fast Fourier transform (FFT) of the down-converted test signal.

[0018] In some embodiments, the test signal generator circuit is configured to generate the at least one test signal as a digital test signal. The integrated radar transceiver circuit further comprises a digital-to-analog conversion (DAC) circuit arrangement configured to convert the at least one digital test signal from a digital to an analog signal range. Thus, the resulting analog test signal can then be mixed with the analog local area (LO) signal to obtain the analog up-converted test signal (in the millimeter-wave frequency range).

[0019] In some embodiments, the Rx channel includes an analog-to-digital conversion (ADC) circuit designed to convert at least one down-converted test signal from an analog to a digital signal domain. Thus, the resulting down-converted test signal (in the IF frequency range) can then be processed by digital signal processing algorithms, such as an FFT.

[0020] In some embodiments, the test signal generator circuit is configured to generate at least one test signal based on a digital clock signal exhibiting a clock spread of less than 200 ps over a range of ±10% of a nominal supply voltage and a temperature range of -40 °C to 135 °C. This clock spread can also be referred to as PVT clock spread due to PVT variations caused by manufacturing processes, supply voltage levels, and operating temperatures, which can lead to variability in the behavior of electronic components.

[0021] As previously mentioned, the integrated radar transceiver circuit can include a DAC circuit designed to convert the at least one digital test signal from a digital to an analog signal domain. The RX channel can include an ADC circuit designed to convert the at least one down-converted test signal from an analog to a digital signal domain. The integrated radar transceiver circuit is designed to synchronize the test signal generator circuit, the DAC circuit, and the ADC circuit based on the digital clock signal. The low clock spread of the digital clock signal can result in highly synchronized subsystems of the integrated radar transceiver circuit.

[0022] In some embodiments, the integrated radar transceiver circuit further includes a compensation circuit configured to perform phase compensation in the Rx channel based on the specified delay information. For example, when a range Doppler map is determined, the delay information (group delay) can be used to correct the phases of range Doppler bins according to the respective delay information.

[0023] According to another aspect, the present disclosure proposes a method for measuring a (group) delay in an integrated radar transceiver circuit. The method comprises generating at least one test signal that has at least one test signal frequency component. The method comprises mixing the test signal and a local oscillator (LO) signal having an LO frequency to obtain an up-converted test signal. This can be performed in a transmitter (Tx) section of the integrated radar transceiver circuit. The method further comprises mixing the up-converted test signal and the LO signal to obtain a down-converted test signal. This can be performed in a receiver (Rx) section of the integrated radar transceiver circuit. The method further comprises determining at least one phase of the down-converted test signal. This can be done, for example, by FFT processing.The procedure further includes determining delay information relating to the integrated radar transceiver circuit, based on at least one specific phase. The delay information can result in group delay information if at least two sinusoidal test signals with different test signal frequencies are used, or if a non-sinusoidal test signal with multiple frequency components is used.

[0024] In some embodiments, the method further includes generating a second test signal that has a second test signal frequency component distinct from the test signal frequency component. The second test signal and the LO signal are mixed (in the Tx section) to obtain a second up-converted test signal. The second up-converted test signal and the LO signal are mixed (in the Rx section) to obtain a second down-converted test signal. A second phase of the second down-converted test signal is determined (for example, by FFT processing in the Rx section). The (group) delay information can then be determined based on the first and second phases, for example, according to τ=−Ø(f2)−Ø(f1)2π(f2−f1).

[0025] In some embodiments, the (first) test signal is generated as a sinusoidal signal containing the (first) test signal frequency component, and the second test signal is generated as a sinusoidal signal containing the second test signal frequency component. Alternatively, the test signals can each be generated as digital test signals.

[0026] In some embodiments, the test signal is generated as a non-sinusoidal signal (e.g., square wave pulses) containing a plurality of test signal frequency components. The respective phases of these multiple test signal frequency components of the down-converted test signal can be determined, for example, by FFT processing. A group delay relevant to the integrated radar can then be determined based on these respective phases of the multiple test signal frequency components.

[0027] According to yet another aspect, the present disclosure proposes an integrated radar transceiver circuit. The integrated radar transceiver circuit comprises a test signal generator circuit configured to generate a test signal having a test signal frequency. The integrated radar transceiver circuit further comprises: a local access (LO) circuit configured to provide a first LO signal having a first LO frequency, and a boost converter circuit configured to mix the test signal and the first LO signal to obtain a first boosted test signal. The integrated radar transceiver circuit comprises at least one receiver channel (Rx) comprising a step-down converter circuit configured to mix the first boosted test signal and the first LO signal to obtain a first step-down test signal.The Rx channel further includes a phase detector circuit configured to determine the first phase of the first step-down test signal. After the first LO signal has been processed, the LO circuit is configured to provide a second LO signal with a second LO frequency that differs from the first LO frequency. The step-up circuit is configured to mix the test signal and the second LO signal to obtain a second step-up test signal. The step-down circuit is configured to mix the second step-up test signal and the second LO signal to obtain a second step-down test signal. The phase detector circuit is configured to determine the second phase of the second step-down test signal.A processor is designed to determine a (group) delay information relating to the integrated radar transceiver circuit, based on the first and second phases. The group delay τ can then be expressed as... τ=−Ø(f2)−Ø(f1)2π(f2−f1) where Ø(f) is the specific phase in radians for the LO frequency f i is.

[0028] In this way, phase errors caused by LO processing of the integrated radar transceiver circuit can be measured and compensated.

[0029] In some embodiments, the test signal generator circuit is designed to generate the test signal as a sinusoidal signal (which has only a single frequency component).

[0030] In some embodiments, the test signal generator circuit is configured to generate the test signal as a digital test signal. The integrated radar transceiver circuit further includes a DAC circuit arrangement configured to convert the test signal from a digital to an analog signal domain.

[0031] In some embodiments, the step-up conversion circuit and the step-down conversion circuit are designed to perform the respective mixing in the analog signal range.

[0032] In some embodiments, the Rx channel includes an ADC circuit arrangement configured to convert the first and second down-converted test signals from an analog to a digital signal domain.

[0033] In some embodiments, the test signal generator circuit is designed to generate the test signal based on a digital clock signal that has a clock spread of less than 200 ps over a supply voltage range of + / - 10% of a nominal supply voltage and a temperature range of -40°C to 135°C.

[0034] In some embodiments, the integrated radar transceiver circuit is configured to synchronize the test signal generator circuit, the digital-to-analog conversion circuit arrangement, and the analog-to-digital conversion circuit arrangement based on the digital clock signal.

[0035] In some embodiments, the LO circuit is configured to generate the first LO signal with the first LO frequency at a lower frequency end of an FMCW frequency ramp and the second LO signal with the second LO frequency at an upper frequency end of the FMCW frequency ramp, or vice versa. The FMCW frequency ramp can, for example, be located in a frequency band between 76 GHz and 81 GHz.

[0036] In some embodiments, the integrated radar transceiver circuit further includes a compensation circuit designed to perform phase compensation in the Rx channel based on the specified delay information.

[0037] According to yet another aspect, the present disclosure proposes a corresponding method for measuring a group delay in an integrated radar transceiver circuit. The method comprises generating a test signal having a test signal frequency, generating a first LO signal having a first LO frequency, mixing the test signal and the first LO signal to obtain a first up-converted test signal, mixing the first up-converted test signal and the first LO signal to obtain a first down-converted test signal, determining a first phase of the first down-converted test signal, generating a second LO signal having a second LO frequency that differs from the first LO frequency, and mixing the test signal and the second LO signal to obtain a second up-converted test signal.a mixing of the second up-converted test signal and the second LO signal to obtain a second down-converted test signal, a determination of a second phase of the second down-converted test signal, and a determination of (group) delay information relating to the integrated radar transceiver circuit, based on the first and second phases.

[0038] According to another aspect, the present disclosure proposes a radar transceiver circuit integrated into a semiconductor chip, comprising: a test signal generator circuit configured to generate at least one baseband test signal having at least one test signal frequency component. The radar transceiver circuit further comprises at least one receive channel having a node for receiving the baseband test signal, wherein the at least one receive channel is configured to process the baseband test signal to generate a processed test signal. A phase detector circuit is provided and configured to determine a phase of the processed test signal, and a processor (140) is configured to determine delay information relating to the integrated radar transceiver circuit based on the determined phase.

[0039] The person skilled in the art who benefits from the present disclosure will recognize that the concepts of measuring and compensating the phase errors caused by baseband processing and measuring and compensating the phase errors caused by LO processing can be combined. Brief description of the characters

[0040] Some examples of devices and / or methods are described below only by way of example and with reference to the accompanying figures, in which Fig. Figure 1 shows a block diagram of an integrated radar transceiver circuit (MMIC); Fig. 2A shows an effective clock spread of 230 ps with 4 buffers after a fork point between an ADC and a test signal generator (TSG); Fig. 2B shows an effective clock spread of 150 ps with 2 buffers before a fork point between an ADC and a TSG and 2 buffers after; Fig. Figure 3A illustrates the effect of clock spreading on phase estimation in the Rx subsystem for different IF frequencies; Fig. Figure 3B illustrates how phase estimation errors translate into errors in arrival angle (AoA) measurements for different AoA; Fig. 4 a flowchart of a method for measuring a group delay in a radar MMIC according to a first embodiment; Fig. 5 a flowchart of a method for measuring a group delay in a radar MMIC according to a second embodiment; and Fig. 6 a flowchart of a method for measuring a group delay in a radar MMIC according to a third embodiment. Detailed description

[0041] Some examples are now described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these detailed embodiments. Other examples may exhibit modifications of the features, as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be considered restrictive for other possible examples.

[0042] Identical or similar reference symbols throughout the description of the figures refer to identical or similar elements and / or features, which may be implemented identically or in a modified form, while providing the same or a similar function. Furthermore, the thickness of lines, layers, and / or areas in the figures may be exaggerated for clarity.

[0043] When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly defined otherwise in a specific case. As an alternative formulation for the same combinations, "at least one of A and B" or "A and / or B" can be used. This applies accordingly to combinations of more than two elements.

[0044] When a singular form, e.g., "ein, eine" and "der, die, das", is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, subsequent examples may also use multiple elements to implement the same function. If a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "include", "comprehensive", "exhibit" and / or "exhibit" when used describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0045] Fig. Figure 1 shows a block diagram of an integrated radar transceiver circuit (MMIC) 100, for which various types of delay information are to be measured with respect to the radar MMIC 100. The delay information can be used to compensate for errors in phase estimation. If left uncompensated, such errors can lead to errors in angle measurements of a radar system.

[0046] The Radar-MMIC 100 can be an FMCW radar-MMIC and includes a digital subsystem 110, a transmitter (Tx) subsystem 120 and a receiver (Rx) subsystem 130, which has one or more Rx channels of the Radar-MMIC 100.

[0047] The digital subsystem 110 of the radar MMIC 100 includes a digital test signal generator circuit 112 configured to generate at least one digital test signal 113. The digital test signal 113 has at least one test signal frequency component f1. This test signal frequency component f1 can be within the IF bandwidth of the radar MMIC 100, sometimes referred to as the baseband of the radar MMIC 100. The IF bandwidth refers to the range of frequencies over which received radar signals are processed and analyzed. The IF bandwidth determines the ability of the MMIC 100 to detect and accurately measure the frequency difference (beat frequency) between Tx and Rx signals, which is essential for calculating the range and velocity of targets. For example, the IF bandwidth of the radar MMIC 100 can range from 300 kHz to 30 MHz.Thus, at least one test signal frequency component f1 of the digital test signal 113 can be in this frequency range.

[0048] As explained in more detail in the continuation of this disclosure, in some embodiments, the digital test signal generator circuit 112 can generate a plurality of sinusoidal test signals 113 at different test signal frequencies, for example, during different time intervals. In other embodiments, the digital test signal generator circuit 112 can generate a single digital test signal 113 that has one or more frequency components. In the latter case, the digital test signal generator circuit 112 can be configured, for example, to generate a digital test signal 113 with a square wave pulse shape. In another implementation, the digital test signal generator circuit 112 can be configured, for example, to generate a digital test signal 113 that comprises a plurality of frequency components based on an inverse FFT (IFFT).In the illustrated example, the digital test signal 113 is a digital IQ signal that has an in-phase (I) data component and a quadrature (Q) data component.

[0049] The digital test signal generator circuit 112 is configured to generate the digital test signal(s) based on a clock signal 114 provided by a clock generation circuit (not shown) of the MMIC 100. The clock signal 114 can determine a sampling rate of the digital test signal 113 as well as a sampling frequency of various DAC and ADC circuits of the Tx subsystem 120 and the Rx subsystem 130. In the illustrated example, the clock signal 114 has a clock rate of 200 MHz. The clock signal 114 can be a highly stable clock signal and, for example, exhibit a clock spread or clock variation of less than 200 ps over a supply voltage range of ±10% of the nominal supply voltage and a temperature range of -40 °C to 135 °C.This means that the edges of the clock signal 114 do not shift by more than 200 ps within the supply voltage range of + / - 10% of the nominal supply voltage and within the temperature range of -40 °C to 135 °C. As described, low clock spreads can be achieved, for example, by reducing the number of buffers.

[0050] As in Fig. As illustrated in Figure 1, the clock signal 114 is used jointly as a clock signal by the digital subsystem 110, the Tx subsystem 120, and the Rx subsystem 130 for test signal generation, DAC processing (in the Tx subsystem 120), and ADC processing (in the Rx subsystem 130), thus providing synchronization between the various subsystems of the radar MMIC 100. Using the same clock source for test signal generation and ADC processing minimizes errors caused by spreading of the clock signal 114. The length of clock signal lines after a junction point (not shown) between ADC processing and test signal generation is implemented as short as possible. Any buffers used before the junction point do not contribute to phase errors.Buffers used after the junction between Rx-ADC processing and digital test signal generation can contribute to phase errors depending on their position. Fig. Figure 2A illustrates an effective clock spread (of clock signal 114) of 230 ps with four buffers after the fork point between an Rx-ADC processing and a digital test signal generation. Fig. Figure 2B illustrates an effective clock spread (of clock signal 114) of only 150 ps with two buffers before and two buffers after the fork between an Rx-ADC processing stage and a digital test signal generation stage. Accordingly, in some examples, the number of buffers after the fork between an Rx-ADC processing stage and a digital test signal generation stage is reduced, for example, to 2 or fewer.

[0051] Fig. Figure 3A illustrates the effect of clock spreading on phase estimation in Rx subsystem 130 for different IF frequencies. It is evident that a large clock spreading can lead to significant errors in phase estimation. Fig. Figure 3B illustrates how phase estimation errors translate into errors in angle-of-arrival (AoA) measurements for different AoA values. The person skilled in the art, benefiting from the present disclosure, will therefore recognize that a low clock spread of the clock signal 114 and / or knowledge of signal delays due to BB or IF processing, as well as due to LO processing, can be advantageous for reducing and compensating for phase estimation errors.

[0052] The digital test signal 113, generated by the digital test signal generator circuit 112, and the clock signal 114 are routed from the digital subsystem 110 to the Tx subsystem 120. There, the clock signal 114 is used to clock an IQ-DAC 122, which is configured to convert the I and Q components of the digital test signal 113 from a digital to an analog signal domain. The output of the IQ-DAC 122 then provides the I and Q components of an analog test signal 113' corresponding to the digital test signal 113.

[0053] In some examples, the digital test signal 113 or the analog test signal 113' can be supplied directly to a node of a baseband of one or more Rx channels of the Rx subsystem 130. In other examples, as described below, the analog test signal 113' is mixed with an LO signal and supplied to an RF node of the Rx subsystem 130. For this purpose, the Tx subsystem 120 has an LO amplifier 124 configured to amplify an analog LO signal 123. The LO amplifier 124 is followed by an IQ boost converter 126, which includes a quadrature mixer. The LO signal 123 can be generated inside or outside the radar MMIC 100 using a phase-locked loop (PLL) circuit. The LO signal 123 has an LO frequency in the millimeter wave frequency range (e.g.76 to 81 GHz) and thus a higher frequency than at least one test signal frequency component of the test signal 113, 113'.

[0054] The IQ boost converter 126, connected downstream of the LO amplifier 124, has a 90-degree phase shifter 125 to generate the I and Q components of the analog LO signal 123, as well as two mixers 126-I and 126-Q, one for each of the I and Q components of the analog test signal 113', to generate quadrature components 127-I and 127-Q of a boosted test signal 127 at the output of the IQ boost converter 126 by mixing the quadrature components of the analog test signal 113' with the respective quadrature components of the LO signal 123. The quadrature components 127-I and 127-Q can be combined by the combiner 128 to form the boosted test signal 127.

[0055] The upconverted test signal 127 can then be coupled into one or more Rx channels via the respective couplers 132 of the Rx subsystem 130. The upconverted test signal 127 can then be treated as a received signal of the respective Rx channel. In the example of Fig. 1 The radar MMIC 100 has four Rx channels. The person skilled in the art, who benefits from the present disclosure, will recognize that the number of Rx channels of the radar MMIC 100 may be lower or higher.

[0056] Each Rx channel of the radar MMIC 100 has a step-down converter circuit or mixer 134 configured to mix the received step-up test signal 127 and the LO signal 123 to obtain an analog step-down test signal 135 in the IF band of the radar MMIC 100. The analog step-down test signal 135 can optionally be amplified by an amplifier 136 (e.g., a low-noise amplifier, LNA) and then converted from an analog to a digital signal range using an ADC circuit arrangement 138. It should be noted that for a direct insertion of the analog test signal 113' into the baseband of the RX subsystem 130, as mentioned above, the processing of the inserted analog test signal 113' corresponds to the processing of the down-converted test signal 135, as described below.The ADC circuit arrangement 138 of each Rx channel is clocked by the clock signal 114, thereby providing synchronization between the digital subsystem 110, the Tx subsystem 120, and the Rx subsystem 130. In the ideal case, where there are no frequency or phase errors, the resulting digital down-converted test signal 139 in the Rx channel will correspond to the digital reference test signal 113. However, due to signal processing delays in the Rx channel, it is likely that the digital down-converted test signal 139 will be phase-shifted with respect to the digital reference test signal 113, resulting in non-zero phases (with respect to the digital test signal 113) of the digital down-converted test signal 139 for one or more test signal frequency components.

[0057] Fig. Figure 1 also shows a processor 140 downstream of the ADC 138. The processor 140 can be located inside (integrated) or outside the radar MMIC 100. The processor 140 can include a digital signal processing circuitry configured to determine at least one phase of the digital down-converted test signal 139. Thus, the processor 140 can include a phase detector. For example, the at least one phase of the digital down-converted test signal 139 can be determined by performing an FFT on the digital down-converted test signal 139. The phase of a bin in the FFT represents the complex angle of the sinusoidal component contributing to that specific frequency bin. In other words, the phase of the bin indicates the starting angle of the sine wave at that particular frequency.Phase information is crucial for reconstructing the original time-domain signal from the frequency-domain representation provided by the FFT. To determine the phase of a bin, the arctangent (or inverse tangent) of the imaginary part divided by the real part of the complex number corresponding to that bin can be calculated. This can be expressed as follows: Phase(bin) = tan. -1 (Imaginary (binary), Real (binary)). Furthermore, the processor 140 is configured to determine a (group) delay information relating to the integrated radar transceiver circuit 100, based on the specified phase(s).

[0058] The present disclosure proposes either at least two (sinusoidal) digital test signals 113 with respective different test signal frequencies or one (non-sinusoidal) test signal with at least two test signal frequency components.

[0059] In the first alternative, the (internal or external) LO circuit is designed to output the LO signal 123 with a fixed LO frequency f. LO to generate. The test signal generator circuit 112 is configured to generate a first digital sinusoidal test signal 113, which has a first test signal frequency f1 in the IF band. The boost converter circuit 126 is configured to mix the first test signal 113, 113' and the LO signal 123 to obtain a first boosted test signal 127. The step-down converter circuit 134 of the Rx channel is configured to mix the first boosted test signal 127 and the LO signal 123 to obtain a first step-down test signal 135, 139. The phase detector circuit or processor 140 is configured to determine a first phase φ(f1) of the first step-down test signal according to the first test signal frequency f1. While the LO frequency f LOSince the LO signal 123 remains unchanged, the test signal generator circuit 112 is configured to subsequently generate a second sinusoidal test signal 113, which has a second test signal frequency f2 that differs from the first test signal frequency f1. The different test signal frequencies f1 and f2 can be generated, for example, according to a time-division multiplexing scheme. While the first test signal frequency f1 can be at a lower end of the IF frequency range, the second test signal frequency f2 can be at an upper end of the IF frequency range, or vice versa. In this way, most of the IF frequency range of the radar MMIC 100 can be covered. The boost converter circuit 126 is configured to mix the second test signal 113 (which has the second test signal frequency f2) and the LO signal 123 to obtain a second boosted test signal 127.The downconversion circuit 134 of the Rx channel is configured to mix the second upconverted test signal 127 and the LO signal 123 to obtain a second downconverted test signal 135, 139. The phase detector circuit or processor 140 is configured to determine a second phase φ(f2) of the second downconverted test signal 135, 139 corresponding to the second test signal frequency f2. With this delay information, the processor 140 can be configured to determine a group delay τ, which relates to the radar MMIC 100, based on the determined first phase φ(f1) and the second phase φ(f2) accordingly. τ=−Ø(f2)−Ø(f1)2π(f2−f1).

[0060] This first alternative for determining the BB group delay is summarized by Procedure 400 for measuring the group delay in the Radar MMIC 100. A flowchart of Procedure 400 is shown in Fig. Figure 4 illustrates this. In other examples, the first and second test signals 113, 113' described above, which have a first test signal frequency f1 and a second test signal frequency f2, can be inserted directly into the baseband, as mentioned above, with processing corresponding to the processing of the down-converted signals 135, 139.

[0061] The procedure 400 includes a step 410 of providing the LO signal 123 with a fixed LO frequency f LOMethod 400 comprises step 420 of generating a first test signal 113, 113' having a first test signal frequency f1. Method 400 comprises step 430 of mixing the first test signal 113' and the LO signal 123 to obtain a first up-converted test signal 127, and of mixing the first up-converted test signal 127 and the LO signal 123 to obtain a first down-converted test signal 135, 139. Method 400 comprises step 440 of measuring a first phase φ(f1) of the first down-converted test signal 139. Steps 410 to 440 can then be repeated for at least one further second test signal 113, 113' having a second test signal frequency f2. Then the procedure 400 includes a step 460 of determining the group delay τ, which relates to the radar MMIC 100, based on the determined first phase φ(f1) and the second phase φ(f2) according to the formula above.

[0062] In the second alternative, the test signal generator circuit 112 is configured to generate a non-sinusoidal test signal 113, 113' that has both a first test signal frequency component f1 and at least one second test signal frequency component f2 in the IF band. The person skilled in the art, taking advantage of the present disclosure, will recognize that more than two test signal frequency components are possible. While the first test signal frequency component f1 can be at a lower end of the IF frequency range, the second test signal frequency component f2 can be at an upper end of the IF frequency range, or vice versa. The (internal or external) LO circuit is configured to generate the LO signal 123 with a fixed LO frequency f. LOThe boost-conversion circuit 126 is configured to mix the non-sinusoidal test signal 113' and the LO signal 123 to obtain a boosted test signal 127. The step-down circuit 134 of the Rx channel is configured to mix the boosted test signal 127 and the LO signal 123 to obtain a step-down test signal 135, 139, which has the first and second test signal frequency components f1, f2. The processor 140 is configured to determine a first phase φ(f1) of the step-down test signal corresponding to the first test signal frequency component f1 and to determine a second phase φ(f2) of the step-down test signal corresponding to the second test signal frequency component f2. This can be done, for example, using an FFT.With this phase information, the processor 140 can be trained to determine the group delay τ, which relates to the radar MMIC 100, based on the determined first phase φ(f1) and the second phase φ(f2) according to the formula above.

[0063] This second alternative for determining the BB group delay is summarized by Procedure 500 for measuring the group delay in the Radar MMIC 100. A flowchart of Procedure 500 is shown in Fig. 5 illustrates.

[0064] The procedure 500 includes a step 510 of providing the LO signal 123 with a fixed LO frequency f LOMethod 500 comprises step 520 of generating the test signal 113, 113', which has a first test signal frequency component f1 and at least a second test signal frequency component f2. Method 500 comprises step 530 of mixing the test signal 113' and the LO signal 123 to obtain an up-converted test signal 127, and of mixing the up-converted test signal 127 and the LO signal 123 to obtain a down-converted test signal 135, 139. Method 400 comprises step 540 of measuring a first phase φ(f1) corresponding to the first test signal frequency component f1 and a second phase φ(f2) corresponding to the second test signal frequency component f2 of the down-converted test signal 139.Then the procedure 500 includes a step 550 of determining the group delay τ, which relates to the radar MMIC 100, based on the determined first phase φ(f1) and the second phase φ(f2) according to the formula above.

[0065] Again, the methods described above can be used in a similar way for baseband test signals that are inserted directly into the baseband processing of the Rx channel.

[0066] The present disclosure further provides a measurement of an LO transfer function.

[0067] Here, the test signal generator circuit 112 is configured to generate a sinusoidal test signal, which has a test signal frequency f, as shown in 113, 113'. test The LO circuit is designed to generate a first LO signal 123, which has a first LO frequency f. LO1The step-up circuit 126 is configured to mix the test signal 113' and the first LO signal 123 to obtain a first step-up test signal 127. The step-down circuit is configured to mix the first step-up test signal 127 and the first LO signal 123 to obtain a first step-down test signal 135, 139. The phase detector circuit or processor 140 is configured to detect a first phase φ(f LO1 ) of the first step-down test signal resulting from the first LO signal. While the test signal frequency of the test signal exhibiting 113, 113' remains unchanged, the LO circuit is configured to subsequently generate a second LO signal 123, which has a second LO frequency f LO2 exhibits, which differ from the first LO frequency f LO1 differs. The different LO frequencies f LO1 and f LO2can be generated, for example, according to a time-division multiplexing scheme. While the first LO frequency f LO1 The second LO frequency can be f at the lower end of an FMCW frequency ramp. LO2 at one end of the FMCW frequency ramp, or vice versa. In this way, most of the RF frequency range of the radar MMIC 100 can be covered. The boost converter circuit 126 is designed to convert the sinusoidal test signal 113 (which has the fixed test signal frequency f) test exhibits) and to mix the second LO signal 123 to obtain a second step-up converted test signal 127. The step-down conversion circuit 134 of the Rx channel is configured to mix the second step-up converted test signal 127 and the second LO signal 123 to obtain a second step-down converted test signal 135, 139. The phase detector circuit or processor 140 is configured to generate a second phase φ(f LO2) of the second down-converted test signal 135, 139 resulting from the second LO signal. With this delay information, the processor 140 can be configured to generate an LO transfer function τ, which relates to the radar MMIC 100, based on the determined first phase φ(f LO1 ) and the second phase φ(f LO2 ) to determine accordingly τ=−Ø(fLO2)−Ø(fLO1)2π(fLO2−fLO1).

[0068] This alternative method for determining the LO transfer function is summarized by Method 600 for measuring the LO transfer function in the Radar MMIC 100. A flowchart of Method 600 is shown in Fig. 6 illustrates.

[0069] The procedure 600 comprises a step 610 of providing the test signal 113, 113' with a fixed test signal frequency f testThe procedure 600 comprises a step 620 of generating a first LO signal 123, which has a first LO frequency f LO1 The procedure 600 comprises a step 630 of mixing the test signal 113' and the first LO signal 123 to obtain a first up-converted test signal 127, and of mixing the first up-converted test signal 127 and the first LO signal 123 to obtain a first down-converted test signal 135, 139. The procedure 600 comprises a step 440 of measuring a first phase φ(f LO1 ) of the first down-converted test signal 139. Steps 610 to 640 can then be used for at least one further second LO signal 123, which has a second LO frequency f LO2 exhibits, are repeated. Then the procedure 600 comprises a step 660 of determining the LO transfer function / group delay τ, which relates to the radar MMIC 100, based on the determined first phase φ(f LO1) and the second phase φ(f LO2 ) according to the formula above.

[0070] The baseband phase can be calculated from the group delay by assuming a 0° phase at a reference frequency. The phase difference compared to a reference channel is the phase error caused by the baseband. The LO phase can be determined by Ø=2π∗τ∗c0λ The phase difference compared to a reference channel is the phase error caused by the local oscillator (LO). This phase error, caused by the baseband and LO, can be adjusted in the phase response of each channel before an angle FFT is performed.

[0071] The aspects and features described in connection with one of the previous examples can also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the feature into the further example.

[0072] Examples may also include a (computer) program with program code for executing one or more of the above procedures, if the program is executed on a computer, processor, or other programmable hardware component. Steps, operations, or processes of various procedures described above may therefore also be executed by programmed computers, processors, or other programmable hardware components. Examples may also include program storage devices, such as digital data storage media, that are machine-, processor-, or computer-readable and / or encode and / or contain machine-executable, processor-executable, or computer-executable programs and instructions. The program storage devices may, for example,Digital storage devices, magnetic storage media such as magnetic disks and tapes, hard disk drives, or optically readable digital data storage media. Further examples may include computers, processors, control units, field-programmable logic arrays (PLAs), field-programmable gate arrays (PGAs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), integrated circuits (ICs), or system-on-a-chip (SoC) systems programmed to perform the steps of the procedures described above.

[0073] It is further understood that the disclosure of several steps, processes, operations, or functions disclosed in the description or claims should not be interpreted as necessarily occurring in the described sequence, unless explicitly stated in a specific case or required for technical reasons. Therefore, the preceding description does not restrict the execution of several steps or functions to a specific sequence. Furthermore, in other examples, a single step, function, process, or operation may comprise and / or be broken down into several sub-steps, functions, processes, or operations.

[0074] When certain aspects related to a device or system are described, these aspects should also be understood as a description of the corresponding procedure. For example, a block, device, or functional aspect of the device or system may correspond to a feature, such as a process step, of the corresponding procedure. Similarly, aspects described in connection with a procedure should also be understood as a description of a corresponding block, element, property, or functional feature of that device or system.

[0075] The following claims are hereby included in the detailed description, each claim being a separate example. It should also be noted that, although a dependent claim may refer to a specific combination with one or more other claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed unless it is stated in a specific case that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also intended to be included, even if that claim is not directly defined as dependent on that other independent claim.

Claims

[1] An integrated radar transceiver circuit (100) comprising: a local oscillator, LO, circuit configured to provide an LO signal (123) having an LO frequency; a test signal generator circuit (112) configured to generate at least one test signal (113; 113') having at least one test signal frequency component; an up-conversion circuit (126) configured to mix the test signal (113; 113') and the LO signal (123) to obtain an up-converted test signal (127); at least one receiving channel (130), comprising: a down-conversion circuit (134) configured to mix the up-converted test signal (127) and the LO signal (123) to obtain a down-converted test signal (135; 139); a phase detector circuit (140) configured to determine a phase of the down-converted test signal (135; 139); and a processor (140) configured to determine delay information related to the radar transceiver integrated circuit based on the determined phase. [2] The radar transceiver integrated circuit (100) according to claim 1, wherein the test signal generator circuit (112) is configured to generate a second test signal (113; 113') having a second test signal frequency component that differs from the test signal frequency component; the up-conversion circuit (126) is configured to mix the second test signal (113; 113') and the LO signal (123) to obtain a second up-converted test signal (127); the down-conversion circuit (134) is configured to mix the second up-converted test signal (127) and the LO signal (123) to obtain a second down-converted test signal (135; 139); the phase detector circuit (140) is configured to determine a second phase of the second down-converted test signal; and the processor (140) is configured to determine a group delay with respect to the radar transceiver integrated circuit based on the determined phase and the second phase. [3] The radar transceiver integrated circuit (100) according to claim 2, wherein the test signal generator circuit (112) is configured to generate the test signal (113; 113') having the test signal frequency component at a lower frequency end of an operating baseband frequency range and to generate the second test signal having the second test signal frequency component at an upper frequency end of the operating baseband frequency range, or vice versa. [4] The integrated radar transceiver circuit (100) according to any one of the preceding claims, wherein the test signal generator circuit (112) is configured to generate the test signal (113; 113') as a sinusoidal signal having the test signal frequency component and to subsequently generate a second test signal as a sinusoidal signal having a second test signal frequency component. [5] The radar transceiver integrated circuit (100) according to claim 1, wherein the test signal generator (112) circuit is configured to generate the test signal (113; 113') as a non-sinusoidal signal having a plurality of test signal frequency components; the phase detector circuit (140) is configured to determine respective phases of the plurality of test signal frequency components of the down-converted test signal; and the processor (140) is configured to determine a group delay with respect to the integrated radar based on the respective phases of the plurality of test signal frequency components. [6] The radar transceiver integrated circuit (100) according to claim 1, wherein the LO circuit is configured to provide a second LO (123) signal having a second LO frequency different from the LO frequency; the up-conversion circuit (126) is configured to mix the test signal (113; 113') and the second LO signal (123) to obtain a second up-converted test signal (127); the down-conversion circuit (134) is configured to mix the second up-converted test signal (127) and the second LO signal (123) to obtain a second down-converted test signal (135; 139); the phase detector circuit (140) is configured to determine a second phase of the second down-converted test signal; and a processor (140) configured to determine the delay information based on the determined phase and the second phase. [7] The radar transceiver integrated circuit (100) of claim 6, wherein the LO circuit is configured to provide the LO signal having the LO frequency at a lower frequency end of an FMCW frequency ramp and the second LO signal having the second LO frequency at an upper frequency end of the FMCW frequency ramp. [8] The integrated radar transceiver circuit (100) according to any one of the preceding claims, wherein the test signal generator circuit (112) is configured to generate the at least one test signal as a digital test signal (113), and wherein the integrated radar transceiver circuit (100) further comprises digital-to-analog conversion circuitry (122) configured to convert the at least one digital test signal (113) from a digital to an analog signal domain. [9] The integrated radar transceiver circuit (100) according to claim 8, wherein the test signal generator (112) circuit is configured to generate the at least one digital test signal (113) based on a clock signal (114) having a clock spread of less than 200 ps over a supply voltage range of + / - 10% of a nominal supply voltage and a temperature range of -40 to 135 degrees C. [10] The integrated radar transceiver circuit (100) according to claim 9, further comprising digital-to-analog conversion circuitry (122) configured to convert the at least one digital test signal (113) from a digital to an analog signal domain, wherein the Rx channel (130) comprises an analog-to-digital conversion circuit arrangement (138) configured to convert the at least one down-converted test signal (135) from an analog to a digital signal domain, and wherein the radar transceiver integrated circuit (100) is configured to synchronize the test signal generator circuit (112), the digital-to-analog conversion circuitry (122), and the analog-to-digital conversion circuitry (138) based on the clock signal (114). [11] The radar transceiver integrated circuit (100) according to any one of the preceding claims, further comprising a compensation circuit (140) configured to perform phase compensation in the Rx channel (130) based on the determined delay information. [12] A method (400; 500; 600) for measuring a group delay in a radar transceiver integrated circuit (100), the method comprising: Generating at least one test signal (113; 113') having at least one test signal frequency component; Mixing the test signal (113; 113') and an LO signal (123) having an LO frequency to obtain an up-converted test signal (127); Mixing the up-converted test signal (127) and the LO signal (123) to obtain a down-converted test signal (135; 139); Determining a phase of the first down-converted test signal (135; 139); and Determining delay information related to the radar transceiver integrated circuit (100) based on the determined phase. [13] The method (400) of claim 12, further comprising: generating a second test signal (113; 113') having a second test signal frequency component that is different from the test signal frequency component; Mixing the second test signal (113; 113') and the LO signal (123) to obtain a second up-converted test signal (127); Mixing the second up-converted test signal (127) and the LO signal (123) to obtain a second down-converted test signal (135; 139); Determining a second phase of the second down-converted test signal (135; 139); and Determining the delay information based on the first and second phases. [14] The method (400) of claim 13, wherein the test signal (113; 113') is generated as a sinusoidal signal having the test signal frequency component, and the second test signal (113; 113') is generated as a sinusoidal signal having the second test signal frequency component. [15] The method (500) according to claim 12, comprising: generating the test signal (113; 113') as a non-sinusoidal signal having a plurality of test signal frequency components; Determining respective phases of the plurality of test signal frequency components of the down-converted test signal (135; 139); and Determining a group delay with respect to the radar transceiver integrated circuit (100) based on the respective phases of the plurality of test signal frequency components. [16] The method (500) of claim 15, wherein the respective phases of the plurality of test signal frequency components are determined based on a fast Fourier transform, FFT, of the down-converted test signal. [17] The method (600) according to claim 12, comprising: Providing a second LO (123) signal having a second LO frequency different from the LO frequency; Mixing the test signal (113; 113') and the second LO signal (123) to obtain a second up-converted test signal (127); Mixing the second up-converted test signal (127) and the second LO signal (123) to obtain a second down-converted test signal (135; 139); Determining a second phase of the second down-converted test signal; and Determining the delay information based on the determined phase and the second phase. [18] The method (600) of claim 17, wherein the LO signal is provided at the LO frequency at a lower frequency end of an FMCW frequency ramp and the second LO signal is provided at the second LO frequency at an upper frequency end of the FMCW frequency ramp, or vice versa. [19] A radar transceiver circuit (100) integrated into a semiconductor chip, comprising: a test signal generator (112) circuit configured to generate at least one baseband test signal having at least one test signal frequency component; at least one receive channel (130) comprising a node for receiving the baseband test signal, wherein the at least one receive channel is configured to process the baseband test signal to generate a processed test signal; a phase detector circuit (140) configured to determine a phase of the processed test signal (135; 139); and a processor (140) configured to determine delay information related to the radar transceiver integrated circuit based on the determined phase. [20] The radar transceiver circuit (100) of claim 19, wherein the test signal generator circuit is configured to generate a first baseband test signal having a first frequency and a second baseband test signal having a second frequency.

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