READ FOR STORAGE CELL WITH THRESHOLD SWITCHING ELECTOR

Abstract

A technology for reading memory cells with threshold switching selectors is disclosed. A sensing amplifier can include a set of capacitors that can be used to exchange charge with a sensing node connected to the selected word line. A capacitor can be used to drain excess charge from the sensing node or to supply charge to the sensing node. A control circuit introduces a current into the selected word line to charge it and turn on the threshold switching selector of the selected memory cell. A capacitor can be connected to the selected word line when, or shortly after, the threshold switching selector turns on. The capacitor can drain excess charge to prevent a snapback current from flowing through the memory cell, thereby preventing erroneous readouts.The capacitor can reduce read latency by accelerating the rate of voltage change across a word line.

Description

BACKGROUNDMemory is used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. The memory may include a nonvolatile memory or a volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Nonvolatile memory may be caused to appear nonvolatile for at least a limited time by adding a battery pack to the power supply outside the memory chip.The memory cells may be in a cross-point memory array. In a cross-point architecture memory array, one set of traces runs over the surface of a substrate and another set of traces is formed over the other set of traces and runs in a direction orthogonal to the initial layer. The memory cells are located at the cross-point contacts of the two sets of conductive tracks.A programmable resistive memory cell is formed of a programmable resistor material. In a binary approach, the programmable resistor memory cell may be programmed into one of two resistor states: high impedance state (HRS) and low impedance state (LRS). In some approaches, more than two resistor states may also be used. One type of programmable resistor memory cell is a magnetoresistive random access memory (MRAM) cell. An MRAM cell uses magnetization to represent stored data, as opposed to some other memory technologies that use electronic charges (DRAM) or voltages (SRAM) to store data. A bit of data is written into an MRAM cell by changing the magnetization direction of a magnetic element ("the free layer") within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell, such resistance changing with the magnetization direction.In a cross point memory array, each memory cell may include a threshold switching selector in series with the material having the programmable resistor. The threshold switch selector has a high resistance (in a turned-off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or a current above its threshold current (It) and until its bias voltage falls below Vhold ("Voffset") or its current falls below a holding current Ihold. After exceeding Vt and while exceeding Vhold across the threshold switch selector, the threshold switch selector has a relatively lower resistance (in an on or conducting state). The threshold switch selector remains on until its current is lowered below a hold current Ihold or the voltage is lowered below a hold voltage Vhold. When this occurs, the threshold switching selector returns to the off state (higher resistance). To read a memory cell, the threshold switch selector is activated by turning on before the resistance state of the memory cell is determined. An example of a threshold switch selector is an Ovonic threshold switch (OTS). Further examples of threshold switching selectors include, but are not limited to, volatile conductive bridge (VCB), metal-insulator-metal (MIM), or other materials that provide a highly non-linear dependence of current on the selected voltage.In a forced current technique for reading programmable resistance memory cells in a cross-point array, current is directed into the memory cell in a direction whose address is selected for reading ("selected memory cell"). A wire with selected address in the Y direction is actively routed to the opposite direction power supply; e.g., voltage forces. The current charges the voltage on the selected memory cell until the threshold switch selector turns on. As the read current is conducted through the programmable resistance memory element of the selected memory cell, the voltage across the selected cell is sensed.One technique for reading programmable resistor memory cells may be referred to as globally referenced reading. A globally referenced read operation is sometimes referred to as a midpoint read operation or a midpoint referenced read operation. A globally referenced read operation may use a reference voltage that is between the lower impedance state (LRS) and the higher impedance state (HRS). Here, LRSand HRS refer to the voltage occurring in response to the read current at the cell. The midpoint reference may be, for example, a reference voltage that is midway between two voltages corresponding to sensing a cell with either LRS or HRS. In a forced current approach, the state of the memory cell is determined based on whether the sensed voltage Vsense is higher or lower than the midpoint reference voltage VREF.Another technique for reading programmable resistor memory cells is commonly referred to as destructive self-referenced reading (SRR). In an SRR, the reference is generated not using a center point independent of the state of the cell, but based on the detection of the cell itself. In destructive SRR, it is possible that the state of the memory cell is changed (e.g., destroyed) by a write operation of the SRR. An SRR technique includes a first read operation (Read 1), destructive write to a known state (e.g., high resistance state HRS), and a second read operation (Read 2). The results of the two reads are compared to determine the original state of the cell. One technique for the first read operation is to apply a read current to the memory cell, resulting in a voltage across the cell having a magnitude representative of the resistance of the memory cell. The voltage is stored and may be adjusted for comparison with a voltage sample from the second read operation (e.g., 150 mV up or down). The voltage adjustment may be about half the signal difference across the MRAM for each state. For example, if the low impedance MRAM state (LRS) is 25 Kohm, the high impedance state is 50 Kohm, and the read current is 15 μa, the difference in a state transition is 375 mV, so that an adjustment of about 180 mV could be made from the voltage of SRR stored in Read 1. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage of Read1 was adjusted upward from SRR and was the write to the HRS, then the second sampled voltage of Read2 should be about the same as Read1 and therefore lower than the first adjusted upward voltage. However, if the cell was originally in the LRS, the second sampled voltage of Read2 should be higher than the upwardly adjusted voltage of Read1 due to the higher Read2 voltage resulting from the writing of the bit from a low impedance LRS to the HRS.For both center read operations during SRR, signals, voltages, and currents are applied to conductive traces such as word lines and / or bit lines. The time until completion of the read operation depends on how long it takes for the voltages on the word lines and / or bit lines to reach a stable voltage.For memory elements such as, but not limited to, MRAM and OTS elements, their state could change without warning due to currents flowing through the memory elements during the read operation. Turning on a threshold switch selector may result in a snapback current flow through the memory element, which could potentially change the state of the MRAM memory element prior to sensing the memory element.BRIEF DESCRIPTION OF THE DRAWINGSLike numbered elements refer to common components in the various figures. FIG. 1 is a block diagram of an embodiment of a nonvolatile memory system connected to a host. FIG. 2 is a block diagram of an embodiment of a memory die. FIG. 3 is a block diagram of an embodiment of an integrated memory device including a control die and a memory structure die. FIG. 4A illustrates an embodiment of a portion of a memory array forming a cross-point architecture in an oblique view. FIGS. 4B and 4C show side and top views, respectively, of the cross-point structure in FIG. 4A. FIG. 4D illustrates an embodiment of a portion of a two-stage memory array forming a cross-point architecture in an oblique view. FIG. 5 illustrates an embodiment for the structure of an MRAM memory cell, here, for example, the selected cell is passed through a current source for reading or writing. FIGS. 6A and 6B illustrate embodiments for integrating threshold switch selectors into an MRAM memory array having a cross-point architecture. FIG. 7 illustrates an embodiment of a memory array having a cross-point architecture accessed using a forced current approach. FIG. 8 is a schematic of an embodiment of a system for reading a memory cell with a threshold switching selector. FIG. 9 is a flow diagram of an embodiment of a process for reading programmable resistance memory cells in a cross-point array. FIG. 10 shows voltages on the bit line and the word line during reading of a memory cell with a threshold switching selector. FIG. 11 is a schematic diagram of an embodiment of a read path connected to a sense amplifier. FIG. 12 is a schematic diagram of an embodiment of the sense amplifier. FIG. 13 is a table indicating the timing of signals in the sense amplifier for a globally referenced read embodiment in which capacitor C1 is used as a snapback discharge capacitor. FIGS. 14A and 14B illustrate further details of timing signals during a globally referenced read embodiment. FIG. 15 is a table indicating the timing of signals in the sense amplifier for an embodiment of an SRR in which capacitor C1 is used as a snapback discharge capacitor. FIG. 16 is a table indicating the timing of signals in the sense amplifier for an embodiment of an SRR in which capacitor C4 is used as a write-reset charging capacitor. FIGS. 17A and 17B illustrate further details of timing signals during an embodiment of an SRR. FIG. 18 is a flow diagram of an embodiment of a process for controlling a capacitor during an SRR to accelerate charging of the wordline during a destructive write phase. FIG. 19 is a flow diagram of an embodiment of a process for controlling a capacitor during an SRR to speed the discharge of the wordline after a destructive write phase. FIG. 20 is a table indicating the timing of signals in the sense amplifier for an embodiment of a write back phase of an SRR. FIG. 21 is a flow diagram of an embodiment of a process for controlling a capacitor during a write back phase of an SRR to accelerate the charging of the word line.DETAILED DESCRIPTIONA technology for a memory system and a method for reading memory cells with threshold switching selectors is disclosed. In one embodiment, a capacitor is used to exchange charge with a sensing node connected to a selected conductive trace, which in turn is connected to a selected memory cell. For example, the capacitor may be used to subtract overcharge from the sense node to speed up the rate at which voltage on the selected word line falls, thus reducing read latency. In one embodiment, the capacitor may be used to provide charge to speed up the rate at which voltage across the selected word line increases, thus reducing read latency. In one embodiment, the capacitor sinks charge that would otherwise have flowed through the selected memory cell after snapback of the threshold switch selector, thereby preventing the state of the memory cell from inverting. This prevents misreading.In some embodiments, a sense amplifier includes a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A control circuit directs a current into the selected word line to charge the selected word line to turn on the threshold switch selector of the selected memory cell. In one embodiment, a capacitor is connected to the selected word line when or shortly after the threshold switch selector turns on. Turning on the threshold switch selector could possibly result in a snapback current that undesirably flows through the memory cell. If a significant snapback current were to flow through the memory cell, the state of the memory cell could change, resulting in a misread. The capacitor may draw overcharge to thereby prevent such snapback current from flowing through the memory cell, thereby preventing misreading. Moreover, the capacitor can shorten the time taken for the word line voltage to settle to a stable voltage (Vfinal) to detect the state of the memory cell. This reduces read latency. In one embodiment, in a globally referenced read, a capacitor is used to exchange charge with a sense node connected to the selected word line. In one embodiment, a capacitor is used in an SRR to exchange charge with a sense node connected to the selected word line.The set of capacitors may be used at different times in an SRR. A capacitor may be used to speed up the rate at which the voltage on the selected word line is increased for destructive writing of the SRR. A capacitor may be used to speed up the rate at which the voltage on the selected word line is decreased after destructively writing the SRR. A capacitor may be used to speed up the rate at which the voltage on the selected word line is increased and / or decreased during a write back phase of the SRR in which the original state of the memory cell is restored.In one embodiment, the memory system is used to read programmable resistor memory cells located in a cross-point memory array. In a memory array having a cross point architecture, one set of traces runs over the surface of a substrate, and another set of traces is formed over the other set of traces and runs over the substrate in a direction perpendicular to the other set of traces. The memory cells are located at the cross-point contacts of the two sets of conductive tracks. Cross-point memory arrays are sometimes referred to as crossbar memory arrays. In one embodiment, the memory cells each include a magneto-resistive memory element in series with an OTS, which may be referred to as an MRAM memory cell. However, the cross point memory array may include other types of memory cells. The cross point memory array may include, for example, memory cells of other technologies such as ReRam, PCM (Phase Change Memory), FeRam. Also, the threshold switching selector may not necessarily be an OTS.In some embodiments, the programmable resistor memory cell includes a magneto-resistive random access memory (MRAM) element. As used herein, the direction of magnetization is the direction in which the magnetic moment is aligned with respect to a reference direction set by another element of the MRAM ("the reference layer"). In some embodiments, the low impedance state is referred to as a parallel or P state or LRS, and the high impedance state is referred to as an anti-parallel or AP state or HRS. MRAM can use the spin transfer torque effect to change the direction of magnetization from the P state to the AP state and vice versa, which usually requires a bipolar operation (bidirectional writing) for writing. However, the SRR of programmable resistor memory cells described herein is not limited to memory cells having MRAM elements or OTS elements.FIG. 1 is a block diagram of an embodiment of a non-volatile memory system (or "memory system" for short) 100 coupled to a host system 120. The memory system 100 may implement the technology herein for a system for reading a memory cell with a threshold switch selector. In one embodiment, the memory cells include a programmable resistance memory element (e.g., MRAM element) in series with a threshold switching selector, such as an OTS. Many types of storage systems may be used with the technology proposed herein. Examples of storage systems include dual inline memory modules (DIMMs), solid state drives ("SSDs"), memory cards, and embedded storage devices; however, other types of storage systems may be used.The memory system 100 of FIG. 1 includes the memory controller 102, the memory 104 for storing data, and the local memory 140 (e.g., MRAM / ReRAM / DRAM). The local memory 140 may be nonvolatile and may hold data even after power-off. The local memory 140 may be non-volatile and may not be expected to hold data after power-off. In one embodiment, local memory 140 is an MRAM. In one embodiment, the local MRAM memory is not required to retain data after power-off. However, the local MRAM memory may retain data after power-off. In one embodiment, memory controller 102 and / or local memory controller 164 provide access to programmable resistance memory cells in local memory 140. For example, the memory controller 102 may provide access in a cross-point array of MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126 is omitted or both are omitted and the memory packets are directly connected to the host 120 via a bus such as DDRn. Or they are connected to a memory management unit (MMU) of the host. In another case, the memory controller 102 or portions are moved to the memory 104 to directly connect the memory 104 to the host, such as by providing parity bits, ECC, and amount of wear in the memory 104, along with a DDRn interface to / from the host or the MMU. The term storage system as used herein is not limited to storage system 100. For example, local memory 140 or the combination of local memory 140 and local memory controller 164 could be considered a memory system. Similarly, host memory 124, or the combination of host processor 122 and host memory 124, is considered a storage system.The components of the memory system 100 shown in FIG. 1 are electrical circuits. The memory controller 102 includes a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, the local memory controller 164, update logic 172, and a wear level 174. Host interface 152 is connected to and in communication with host 120. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOCs may span synchronous and asynchronous clock domains or use untimed asynchronous logic. NOC technology applies network theory and methods to on-chip communications and makes significant improvements over conventional bus and crossbar interconnects. A NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the connections of the NOC are shared by many signals. High parallelism is achieved because all connections in the NOC can operate simultaneously on different data packets. Thus, as integrated subsystem complexity grows, a NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced with a bus. Connected to and in communication with the NOC 154 are the processor 156, the ECC engine 158, the memory interface 160, the local memory controller 164, the update logic 172, and the amount of wear 174. Local memory controller 164 is used to operate and communicate with high speed local memory 140 (e.g., MRAM). In other embodiments, the high speed local memory 140 may be DRAM, SRAM, or another type of volatile memory.The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding of parity bits provided inside or outside the memory as part of the codeword used for error correction of the data retrieved from the memory 140 or 104. In one embodiment, the ECC engine 158 is an electrical circuit programmed by software. For example, the ECC engine 158 may be a processor that can be programmed. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In one embodiment, the function of the ECC engine 158 is implemented by the processor 156. In one embodiment, local memory 140 includes an ECC engine with or without a wear-level engine. In one embodiment, the memory 104 includes an ECC engine with or without a wear-level engine.The processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes, including the amount of wear. A separate amount of wear 174 is shown, but the amount of wear 174 may be implemented by the processor 156. Update logic 172 is also shown, but the update may also be implemented by processor 156. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. The processor 156 also implements a translation module, as a software / firmware process, or as dedicated hardware circuitry. In many systems, nonvolatile memory within the storage system is addressed using physical addresses associated with one or more memory dies. However, the host system uses logical addresses to address the various memory locations. This allows the host to assign data to successive logical addresses while the storage system can freely store the data at any location of the one or more memory dies. To implement this system, the memory controller 102 (e.g., translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die. An example implementation is to maintain tables (i.e., the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and a corresponding physical address. Although tables with a logical address to physical address (or L2P tables) map include the word "tables", they do not actually need to be tables. Rather, the logical address to physical address (or L2P) tables may be any type of data structure. In some examples, the storage space of a storage system is so large that local memory 140 cannot carry all L2P tables. In such a case, the entire set of L2P tables is stored in the memory 104, and a subset of the L2P tables is cached in the high-speed local memory 140 (L2P cache).The memory interface 160 communicates with the nonvolatile memory 104. In one embodiment, the non-volatile memory 104 includes programmable resistance memory cells in a cross-point array. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 102) implements a scheduler and buffer to transmit data to and receive data from one or more memory dies.In one embodiment, local memory 140 includes an ECC engine. Local memory 140 may be used to help perform other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Pat. No. 10,545,692 entitled "Memory Maintenance Operations During Refresh Window" and U.S. Pat. No. 10,885,991 entitled "Data Rewrite During Refresh Window", both of which are hereby incorporated by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.In one embodiment, the memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Thus, the memory controller 102 is connected to one or more memory dies. In one embodiment, the memory package may include memory types, such as memory class memories (SCM) based on programmable resistive random access memories (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, memory controller 102 provides access to memory cells in a cross-point array in a memory package 104.The memory controller 102 communicates with the host system 120 via an interface 152 implementing a protocol such as a compute express link (CXL). Or such a controller may be omitted and the memory packets placed directly on the host bus, for example DDRn or CXL. For operation with the storage system 100, the host system 120 includes a host processor 122, a host memory 124, and an interface 126 connected via the bus 128. The host memory 124 is the physical memory of the host and may be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or other type of memory. In one embodiment, the host memory 124 includes a cross-point array of programmable resistor memory cells, each memory cell having a programmable resistor memory element and a threshold switch selector in series with the programmable resistor memory element.The host system 120 is external to and separate from the storage system 100. In one embodiment, the storage system 100 is embedded in the host system 120. The host memory 124 may be referred to herein as a storage system. The combination of the host processor 122 and the host memory 124 may be referred to herein as a storage system. In one embodiment, such host memory may be a cross point memory using MRAM.FIG. 2 is a block diagram illustrating an example of a memory die 292 that may implement the technology described herein. In one embodiment, the memory die 292 is included in the local memory 140, and in one embodiment, the memory die 292 is included in the memory 104. In one embodiment, memory chip 292 is enclosed within host memory 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include the various layers of word lines organized as rows and the various layers of bit lines organized as columns. However, other orientations may be implemented, including diagonal patterns, for example, to save space. The memory die 292 includes row control circuitry 220 having outputs 208 connected to respective word lines of the memory structure 202. Row control circuitry 220 receives a set of M row address signals and one or more different control signals from system control logic circuitry 260, and may typically include circuitry such as row decoders 222, row drivers 224, and block selection circuitry 226 for both read and write operations. Row control circuitry 220 may also include read / write circuitry. In one embodiment, row decode and control circuitry 220 includes sense amplifiers 228, each including circuitry for sensing a state (e.g., voltage) of a wordline of memory structure 202. In one embodiment, by sensing a wordline voltage, a state or a bit state of a memory cell in a cross-point array is determined, either directly by a sense amplifier that compares the voltage of the accessed memory cell voltage to a reference voltage. Or less directly, by first accessing the memory cell and storing a read voltage generated by forcing a read current through the cell and adjusting it up or down by 150 mV (or by half the voltage difference resulting from the change of the bit state), then writing the cell to the AP state and accessing the memory cell again with a read current, and comparing the resulting voltage with the stored voltage adjusted by, for example, 150 mV (or by half the voltage difference resulting from 2 different bit states). The memory die 292 also includes column decode and control circuitry 210 having input / output 206 connected to respective bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, a memory die may include multiple arrays or "tiles" that may be accessed individually. Column control circuitry 210 receives a group of N column address signals and one or more different control signals from system control logic 260, and may typically include circuits such as column decoders 212, column decoders and drivers 214, block selection circuitry 216, as well as read / write circuitry and I / O multiplexers.System control logic 260 receives data and commands from a host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, the controller circuit communicating with the host system. Such a controller system may implement an interface such as DDR, DIMM, CXL, PCIe, and others. In another embodiment, these data and commands are sent from and received from the memory packages directly to and from the host without requiring a separate controller, and any controller that is needed resides in each die or die added to a multichip memory package. In some embodiments, system control logic 260 may include a state machine 262 that enables control of memory operations at the die level. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is fully implemented in hardware (e.g., electrical circuits). In another embodiment, state machine 262 is replaced with a microcontroller or microprocessor. The system control logic 260 may also include a power control module 264 that controls the power, currents from the current source, and voltages provided to the rows and columns of the memory structure 202 during memory operations, and may include charge pumps and a control circuit for generating control voltages, as well as an on / off controller for wordline / bitline selection of the memory cells, respectively. In some embodiments, the power controller 264 includes one or more current sources. The current source(s) may / may be used to provide read and / or write currents. The system control logic 260 includes storage 266, which may be used to store parameters for operating the memory structure 202. System control logic 260 also includes update logic 272 and wear compensation logic 274. Such system control logic may be commanded by the host 120 or the memory controller 102 to the update logic 272, which may load a row and column address (pointer) stored on a chip that may be incremented after the update. This address bit(s) may / may only be selected (to reload the OTS). Or, such an address may be read, corrected by control of the ECC engine 269, and then stored in a "replacement" memory location that is also incremented (such that all codewords are periodically read, corrected, and shifted throughout the chip under the control of the wear compensation logic 274) to compensate for wear, such that the use of each bit on the chip is more uniform. Such operation may be controlled more directly by the host of an external controller, for example, by a PCIe or CXL or DDRn controller located separately from the memory chip or on the memory die.Commands and data are transmitted between the memory controller 102 and the memory die 292 via a memory controller interface 268 (also referred to as a "communication interface"). Such an interface may be, for example, PCIe, CXL, DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a switching mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a toggle mode interface that is connected to the toggle mode interfaces of memory interfaces 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface supports the JEDEC standard DDRn or LPDDRn, e.g., DDR5 or LPDDR5, or a subset thereof with a smaller page and / or more generous timing.System control logic 260, located in a controller on the memory die in the memory packages, may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it is on the same semiconductor die as the memory cells. That is, the on-die ECC engine 269 may be used to encode data and parity bits to be stored in the memory structure 202, and to decode the decoded data and correct errors. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 may be used to perform a decoding algorithm and perform error correction. Therefore, the ECC engine 269 may decode the ECC codeword. In one embodiment, the ECC engine 269 is capable of decoding the data more quickly by direct decoding without iteration. The faster decoding is possible because the ECC engine 269 is on the same die as the memory cells. The ECC engine 269 may use a wide variety of decoding algorithms including, but not limited to, Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low density parity check (LDPC).In some embodiments, all elements of memory die 292, including system control logic 260, may be formed as part of a single die. In other embodiments, a portion or all of the system control logic 260 may be formed on another die; e.g., an external controller chip.In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile or volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. The memory structure may include any type of non-volatile or volatile memory monolithically formed in one or more physical levels of memory cells having an active area disposed over a silicon or a silicon-on-insulator (or other type of) substrate. In another embodiment, the memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells.The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies may be used to form the memory structure 202. No special non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM (resistive random access memory) memories, magneto-resistive memories (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memories (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.An example of a ReRAM or MRAM cross-point memory includes programmable resistance switching elements in series with an OTS selector arranged in cross-point arrays accessed via X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the cross point is a PCM in series with an OTS selector. In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge storage element may be used as a state changing element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge storage element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin sheet of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds as a function of temperature.Magneto-resistive random access memory (MRAM) stores data using magnetic storage elements. The elements are formed of two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. In a field controlled MRAM, one of the two layers is a permanent magnet set to a certain polarity; the magnetization of the other layer can be changed by applying an external field to store the memory. Other types of MRAM cells are possible. A memory device may be constructed from a grid of MRAM cells or as a magnetoresistive SOT memory. MRAM-based memory embodiments are discussed in more detail below.Phase Change Memory (PCM) takes advantage of the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase changes by simply changing the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). The memory cells are programmed by current pulses which can alter the coordination of the PCM material or switch it between amorphous and crystalline states. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes a / n (continuous / n or non-continuous / n) oscillation or impact of sound, current, voltage, light or other wave. For example, the write forced current may be quickly peaked and then linearly decreased at, for example, an edge rate of 500 ns. This peak current may be limited by a zoned voltage conformance that varies by the location of the memory cell along the wordline or the bitline. In one embodiment, a phase change memory cell includes a phase change memory element in series with a threshold switching selector such as an OTS.Those of ordinary skill in the art will appreciate that the technology described herein is not limited to a single specific memory structure, memory construction, or material composition, but covers many relevant memory structures in accordance with the spirit and scope of the technology as described herein and as known to one of ordinary skill in the art.The elements of FIG. 2 may be grouped into two parts, the memory structure 202 and peripheral circuitry including all other elements. An important characteristic of a memory circuit is its capacity that can be increased by increasing the area of memory die 292 allocated to memory structure 202; however, this reduces the area of the memory die available to the peripheral circuits or increases the die area related cost. This can place quite considerable restrictions on these peripheral elements. For example, the need to fit sense amplifier circuits into the available area may present a significant limitation to sense amplifier design architectures. With respect to system control logic 260, reduced availability of area may limit the available functionalities that may be implemented on the chip. Thus, a basic compromise in the design of a memory die 292 is how much area of the memory structure 202 and how much area of the peripheral circuitry is to be dedicated. These tradeoffs can result in more IR drops when larger x-y arrays of memories are used between driver circuits on the word line and the bit line, which in turn produces greater advantages through the use of voltage limitations and a zonalization of voltage conformance by a memory cell position along the word line and the bit line.Another area where the memory structure 202 and peripheral circuitry are often conflicting is processing involved in forming these areas, as these areas often involve different processing technologies and the trade-off of having different technologies on a single die. For example, elements such as sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260, often use PMOS devices. In some cases, the memory structure is based on CMOS devices. Processing operations for fabricating a CMOS die will in many respects be different from the processing operations optimized for pure NMOS technologies.To alleviate these limitations, embodiments described below may split the elements of FIG. 2 into separately formed dies, which are then interconnected. FIG. 3 illustrates an integrated memory array 270 including a memory structure die 280 and a control die 290. The memory structure 202 is formed on the memory structure die 280 and some or all of the peripheral circuitry elements, including one or more control circuits, are formed on the control die 290. For example, a memory structure die 280 may be formed of only the memory elements, such as the array of memory cells of the MRAM memory, PCM memory, ReRAM memory, or another type of memory. Some or all of the peripheral circuitry, even including elements such as decoders, current sources, and sense amplifiers, may then be moved to the control die. Thereby, each of the semiconductor dies can be individually optimized according to its technology. This allows more space for the peripheral elements, which can now accommodate additional capabilities that could not be readily accommodated if limited to the edges of the same die that includes the memory cell array. The two chips may then be bonded together into a bonded multi-chip integrated memory array, the array on one chip being connected to the peripheral elements on the other chip. Although focus is now on an integrated memory array of a memory die and a control die, other embodiments may use additional dies, such as two memory dies and one control die.As with the memory die 292 of FIG. 2, the memory structure die 280 of FIG. 3 includes a memory structure 202, which may include multiple arrays or "tiles" that may be accessed independently of one another. The system control logic 260, the row control circuitry 220, and the column control circuitry 210 are located in the control die 290. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory structure die 280. In some embodiments, a portion of the circuitry in system control logic 260 resides on memory structure die 280.FIG. 3 shows column control circuitry 210 on control die 290 coupled via electrical paths 293 to memory structure 202 on memory structure die 280. For example, the electrical paths 293 may provide an electrical connection between the column decoder 212, the column driver circuitry 214, and the block select 216, and bit lines of the memory structure 202. The electrical paths may extend from the column control circuitry 210 in the control die 290 via pads on the control die 290 bonded to corresponding pads of the memory structure die 280 connected to bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in the electrical paths 293 including a pair of bonded pads connected to the column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, row drivers 224, block select 226, and sense amplifier 228, is coupled to memory structure 202 via electrical paths 294. Each of the electrical paths 294 may correspond to a wordline, for example. Additional electrical paths may also be provided between the control die 290 and the memory structure die 280.For the purposes of this document, the term "control circuitry" may include one or more of the memory controller 102, the local memory controller 164, the processor 156, the system control logic 260, the column control circuitry 210, the row control circuitry 220, the host processor 122, a microcontroller, a state machine, and / or other control circuitry or other analog circuitry used to control non-volatile memory. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, an integrated circuit, or other type of circuit. This control circuitry may include drivers, such as direct driving via the connection of a node through fully-turned-on transistors (gate to power supply) that are routed to a fixed voltage, such as a power supply. This control circuit may include a current source driver.For purposes of this document, the term "device" may include, but is not limited to, one or more of the memory system 100, the local memory 140, the combination of the local memory controller 164 and / or the memory controller 102 and the local memory 140, the memory package 104, the memory die 292, the integrated memory array 270, and / or the control die 290.In the following discussion, the memory structure 202 of FIGS. 2 and 3 will be discussed in the context of a cross point architecture. In a cross-point architecture, a first set of conductive traces or wires, such as word lines, extend in a first direction relative to the underlying substrate and a second set of conductive traces or wires, such as bit lines, extend in a second direction relative to the underlying substrate. The memory cells are located at the intersection of the word lines and bit lines. The memory cells at these cross-points may be formed according to any of a number of technologies, including those described above. The following discussion focuses primarily on embodiments based on a cross-point architecture using MRAM memory cells each connected in series with a threshold switching selector, such as an Ovonic threshold switching selector (OTS), to have a selectable memory bit. However, embodiments are not limited to providing currents to a cross-point architecture that includes MRAM cells each with a magnetic storage element with an OTS selector connected in series.FIG. 4A illustrates an embodiment of a portion of a memory array 402 forming a cross-point architecture in an oblique view. The memory array 402 of FIG. 4A is an example of an implementation for the memory array 202 of FIG. 2 or 3, wherein a memory die 292 or memory structure die 280 may include multiple such memory arrays 402. The memory array 402 may be included in the local memory 140 or the host memory 124. The bit lines BL 1- BL 5 are arranged (shown as going into the page) in a first direction relative to an underlying substrate (not shown), and the word lines WL 1- WL 5 are arranged in a second direction perpendicular to the first direction or diagonally to provide intersections at which memory cells between WLs and BLs are connected to each other. FIG. 4A is an example of a horizontal cross-point structure in which both word lines WL 1- WL 5 and BL 1- BL 5 extend in a horizontal direction relative to the substrate, while the memory cells, two of which are designated 401, are aligned so that current flows through a memory cell in a vertical direction (as shown at I cell ). In a memory array having additional layers of memory cells, as discussed below with respect to FIG. 4D, there would be corresponding additional layers of bit lines and word lines. A pattern of the lower layer would be, for example: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.As shown in FIG. 4A, memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as may be implemented using ReRAM, MRAM, PCM, or other programmable resistor material. The memory cells 401 may be referred to herein as programmable resistor memory cells. One type of programmable resistor memory cell is referred to as an MRAM cell, which is a memory cell that includes an MRAM memory element. The memory cells 401 may also include threshold switch selectors as an additional row element within the memory cells 401, as may be implemented using an Ovonic threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or another material that provides a highly non-linear dependence of current or resistance to vary the selection voltage. The following discussion focuses on memory cells comprised of MRAM memory elements connected in series with an ovonic threshold switching element, although much of the discussion may also be applied more generally. The current in the memory cells of the first memory level is shown to flow upward as indicated by arrow I cell but current may flow in both directions to either read or write the memory cell bit state, as will be explained in more detail below.FIGS. 4B and 4C show side and top views, respectively, of the cross-point structure in FIG. 4A. The side view of FIG. 4B shows a lower wire or wordline WL 1 and the upper wires or bitlines BL 1- BL n. At the cross point between each top wire and each bottom wire is an MRAM memory cell 401, although PCM, ReRAM, FeRAM, or other technologies may also be used as the memory element. FIG. 4C is a plan view illustrating the cross point structure for M lower wires WL 1 to WL M and N upper wires BL 1 to BL N. In a binary embodiment, the MRAM cell can be programmed into one of two resistance states at each cross point: high and low. Further embodiments for MRAM memory cells and techniques for reading the MRAM memory cells are described below. In some embodiments, sets of these wires are continuously arranged as a "tile", and these tiles may be paired side by side in the wordline (WL) direction and orthogonally in the bitline direction to create a module. Such a module may be composed of 2 x 2 tiles to form a four tile combination, with the WL drivers "centered" between tiles, with the WL continuously passing over the transistor driver at the approximate center of the line. Similarly, BL drivers may be arranged between the pair of tiles paired in the BL direction to be centrally conducted, sharing the transistor driver and its area between a pair of tiles. Vias made of copper or other types of low resistance may decode the transistor drivers / selectors and connect to the WL or BL. In addition to the memory element in the memory cell between WL and BL, a row selection element such as an OTS may also be included.The cross-point array of FIG. 4A illustrates an embodiment having a layer of word lines and bit lines, where the MRAM or other memory technology for the memory cells is disposed at the intersection of the two sets of conductive traces. In order to increase the storage density of a memory chip, a plurality of layers of such memory cells and conductor tracks can be formed. A two-layer example is illustrated in FIG. 4D.FIG. 4D illustrates an embodiment of a portion of a two-stage memory array forming a cross-point architecture in an oblique view. As in FIG. 4A, FIG. 4D shows a first layer 418 of memory cells 401 of a memory array 403 connected at the crossing points of the first layer of the protruding word lines WL 1,1- WL 1,4 and bit lines BL 1- BL 5 respectively. The memory array 403 may be included in the memory structure 202 of FIG. 2 or 3. Above the bit lines BL 1- BL 5 and between these bit lines and a second set of word lines WL 2,1- WL 2,4 a second layer 420 of memory cells is formed. The BLs are shared. Alternatively, a second layer may include a further layer of BL above the BL shown and below the second layer of WL. Although FIG. 4D shows two layers 418 and 420 of memory cells, the structure may be extended upward by additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array of FIG. 4D may be biased for read or program operations such that current flows in each layer from the word line layer to the bit line layer, or vice versa. The two layers may be structured such that the current for a particular operation flows in the same direction in each layer or that the current flows in opposite directions by the driver selection in the positive or negative direction. The memory cell may be placed in the same orientation within the first and second layers, allowing for the use of current in opposite directions per layer for reading or writing. Or, the memory cell is placed in the reverse or reverse direction when placed between the BL and the WL in the second layer (allowing for the use of current in the same direction as used for reading or writing to memory cells within the first layer).The use of a cross point architecture enables arrays with a small footprint, and multiple such arrays can be formed on a single chip. The memory cells formed at each crossing point may be a resistive type of memory cell in which data values are encoded as different resistance levels, either two levels, such as MRAM, or in two or more levels for other memory element technologies, such as PCM. Depending on the embodiment, the memory cells may be binary, either with a low impedance state or a high impedance state, or multilevel cells (MLCs) that may have an additional resistance between the low impedance state and the high impedance state. The cross-point arrays described herein may be used in the memory die 292 of FIG. 2, the local memory 140 of FIG. 1, and / or the host memory 124 of FIG. 1, or any other configuration in which additional memory is useful. Resistive type memory cells may be formed according to many of the above technologies, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented primarily in the context of memory arrays using a cross-point architecture with binary valued MRAM memory cells, although much of the discussion is more generally applicable to other memory elements in memory cells within a cross-point array or other configurations that will be apparent to those skilled in the art.FIG. 5 illustrates the structure of an embodiment for an MRAM cell. The MRAM cell may be used as the programmable resistor memory cell 401 in FIGS. 4A-4D, for example. The MRAM cell includes a bottom electrode 501, a spacer 512, a threshold switch selector 502, a spacer 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated by a separation or tunnel layer, in this example, magnesium oxide (MgO) 505, and a top electrode 511 separated from the free layer 507 by a spacer 509. The spacer 509 may be made of a MgO capping layer that contacts the free layer 507. Spacer 509 may also include additional metal layers. In another embodiment, the locations of the reference layer 503 and the free layer 507 are interchanged such that the reference layer 503 is on the MgO 505 and the free layer 507 is under the MgO 505. In another embodiment, the location of the threshold switch selector 502 is between the free layer 507 and the top electrode 511.In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 503 and the free layer 507: when the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low impedance state (LRS); and when they are in the opposite orientation, the memory cell is in an anti-parallel (AP) high resistance state (HRS). An MLC embodiment would include additional intermediate states. The orientation of the reference layer 503 is fixed and in the example of FIG. 5 it is oriented upwards. The reference layer 503 is also known as a fixed layer or pinned layer. The reference layer 503 may consist of multiple ferromagnetic layers that are antiferromagnetically coupled in a structure commonly referred to as a synthetic antiferromagnetic or SAF for short.Data is written to an MRAM memory cell by programming the free layer 507 to have either the same or opposite orientation as the reference layer 503. An array of MRAM memory cells may be placed in an initial or erased state by placing all of the MRAM memory cells in the low resistance state in which all of the free layers have a magnetic field orientation that matches that of their reference layers. Each of the memory cells is then selectively programmed (also referred to as "written") by placing its free layer 507 in the high impedance state opposite that of the reference layer 503 by reversing the magnetic field. The reference layer 503 is formed to maintain its orientation when programming the free layer 507. The reference layer 503 may have a more complicated configuration including synthetic antiferromagnetic layers and additional reference layers. For simplicity, these additional layers are omitted from the figures and discussion, focusing only on the fixed magnetic layer, which is primarily responsible for the tunneling magneto-resistance in the cell.The threshold switch selector 502 has a high resistance (in a turned-off or non-conductive state) until it is biased to a voltage that is higher than its threshold voltage, or until the current is above its threshold current, and until its bias voltage falls below Vhold ("Voffset") or its current falls below Ihold. After exceeding Vt and while exceeding Vhold across the switching selector, the switching selector has a low resistance (on or on). The threshold switch selector remains on until its current is lowered below a hold current Ihold or the voltage is lowered below a hold voltage Vhold. When this occurs, the threshold switching selector returns to the off state (higher resistance). Accordingly, to program a memory cell at a cross point, a voltage sufficient to turn on the associated threshold switch selector and set or reset the memory cell is applied; and to read a memory cell, the threshold switch selector is similarly activated by turning it on before the resistance state of the memory cell is determined. One set of examples of a threshold switch selector is an ovonic threshold switch material of an ovonic threshold switch (OTS). Exemplary threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe 6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, wherein atomic percentages for each element range from a few percent to more than 90 percent. In one embodiment, the threshold switch selector is a two pole device. The threshold switch selector 502 may also include additional conductive layers at the interface to the reference layer 503. For example, the spacer 514 is shown between the switching selector 502 and the reference layer 503. The spacer layer 514 at the interface to the reference layer 503 may be a single conductive layer or may consist of multiple conductive layers. The threshold switch selector 502 may also include additional conductive layers at the interface to the bottom electrode 501. For example, the spacer 512 is shown between the switching selector 502 and the reference layer 503. The spacer layer 512 at the interface to the bottom electrode 501 may be a single conductive layer or may be comprised of multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. Threshold voltage switches have a threshold voltage (Vt) above which the resistance of the device substantially changes from insulating or quasi-insulating to conducting.In one embodiment, a current-force approach is used to access the MRAM cell. The current-force approach may be used to read or write the MRAM cell. In the forced current approach, an access current (e.g., I read or I write) is conducted through the lower electrode 501 by a current driver. The current is provided by a transistor- or resistor-based current source. In one embodiment, the current driver may be a portion of the row driver circuitry with selected address (e.g., array drivers 224) for electrode 501. Alternatively, however, the current driver may be a portion of the column driver circuitry with selected address (e.g., driver circuitry 214) for the electrode 501. A voltage (e.g., V select) is provided to the top electrode 511. Herein, the terms "read current" (I read) and "write current" (I write) are used in conjunction with access currents driven by MRAM cells (or other programmable resistive cells). The write current may change the state of the MRAM cell. As an example, a write current of about 30 μA for 50 ns may be used with an MRAM cell having a critical dimension (CD) of about 20 nanometers at RA 10 Ωμm 2 to switch the MRAM state from the P state to the AP state. The read currents may be about half as high as the write currents when applied for a limited time, such as < 20 ns. A write current flowing in one direction through the MRAM cell changes an MRAM cell in the AP state from the AP state to the P state. A write current flowing through the MRAM cell in the other direction, such as in the read direction, changes an MRAM cell in the P state from the P state to the AP state. Generally, until the cell state is determined or a voltage level correlated with the memory cell state is recorded and stored, a read current is preferably set low and the read time is set so short that the state of an MRAM cell does not change from the P state to the AP state or from the AP state to the P state during reading. Typically, the write current required to transition the MRAM state from the P state to the AP state is greater in absolute magnitude than the write current required to transition the MRAM state from the AP state to the P state. Current intensities can be adjusted according to the writing direction, or the current used for P to AP if a single intensity is used.In some embodiments, a read current may be applied in a P2AP direction, or alternatively, in an AP2P direction. In some embodiments, the MRAM cell is read by performing a self-referenced read (SRR). In one embodiment, the SRR includes a first read operation (Read 1 in the P2AP direction), a first write operation (Write 1 in the AP state), and a second read operation (Read 2 in the P2AP direction). Then, the cell's original state can be restored by a second write (Write_Back back to the P state for bits that were originally in the P state). In another embodiment, the SRR read current and write current / s are reversed; for example, when the second layer is addressed with a memory cell that is aligned the same as in the first layer.In one embodiment, the voltage level of the memory cell is sensed and stored due to Read1 in the P2AP direction, for example on a capacitor; or by conversion to digital bits by an analog-to-digital converter and the bits stored in memory, for example in SRAM, until after use in Read2. The state stored in a capacitor may be corrected by, for example, 150 mV, positive or negative, by forcing a voltage at one terminal of a capacitor connected to the storage capacitor. Or, the digitally stored level may be adjusted to the stored bits by digitally adding or subtracting 150 mV. The 150 mV may be adjusted to depend on the typical bit resistance. For example, if the low resistance bit state is 25 kiloohms and the high resistance amounts to 50 k, the difference is 25 k. If the read current is 15 ua, the differential voltage between the states at 25 k × 15 ua = 375 mV makes a selection of 150 mV acceptable, but in some circumstances it may be more optimal to propose, for example, 187 mV.Although the above describes reads in the P2AP direction and destructive writes to the AP state (with writes back to SRR in the P state), in an alternative embodiment, the first SRR includes a first read (Read1 in the AP2P direction), a destructive write (Write1) to the P state, and a second read (Read2) in the AP2P direction.In one embodiment, the MRAM cell is read by, for example, applying about 0 V to the top electrode 511 by turning on a transistor connected between 511 and a current source while passing a current of, for example, 15 microamperes (μA) through the bottom electrode 501. This read current may flow from the lower electrode 501 to the upper electrode 511. Note that the read Read 1 or Read 2 may be performed in the P2AP direction. P2AP means that the current flows in the direction that the bit would write from P to AP or AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In an embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the upper electrode 511 while passing a write current of, for example, -30 μA through the lower electrode 501. This write current flows from the upper electrode 511 to the lower electrode 501. In an embodiment, the MRAM cell is written from the P state to the AP state by, for example, applying 0 V to the top electrode 511 while driving a current of, for example, 30 μA through the bottom electrode 501. This write current flows from the electrode 501 to the electrode 511.Alternatively to the approach in FIG. 5, the selection voltage may be applied to the lower electrode 501, with the access current applied through the upper electrode 511. In such an embodiment, the MRAM cell is read by applying, for example, 3 V to the lower electrode 501 while driving a read current of, for example, -15 μA through the upper electrode 511. This read current may flow from the lower electrode 501 to the upper electrode 511.In an embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, -3 V to the lower electrode 501 while passing a write current of, for example, 30 μA through the upper electrode 511. The electron current flows from the lower electrode 501 to the upper electrode 511. In an embodiment, the MRAM cell is written from the P state to the AP state by, for example, applying 0 V to the bottom electrode 501 while passing a current of, for example, -30 μA through the top electrode 511. This electron current flows from the upper electrode 511 to the lower electrode 501. In this discussion, it is also believed that the direction of current polarity for switching the magnetization of the bit to the P or AP state may vary depending on the design of the reference layer and the location of the reference layer with respect to the free layer.Some biasing techniques may result in a voltage across unselected memory cells of the array that may induce currents in unselected memory cells. Although this power dissipation consumption can be mitigated to some extent by configuring the memory cells to have relatively high resistance levels for both high and low resistance states when no address is selected for WL or BL, this overhead leakage current still results in increased current and power consumption as well as additional design constraints for the design of the memory cells and array. One approach to remedy this undesirable leakage current is to place a selection element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a select transistor may be connected in series with each resistive memory cell element in FIGS. 4A-4D, such that memory cells 401 are now a combination of a select transistor and a programmable resistor. Such an architecture may be referred to as 1T1R. However, the use of a selection transistor requires the introduction of additional control lines and additional cell area to enable the corresponding transistor of a selected memory cell to be turned on. Moreover, transistors often do not scale in the same way as the write current of the resistive memory element, so for ever smaller memory arrays, the use of transistor-based selectors may be a limiting factor, for example for reducing costs. An alternative approach to selecting transistors is to use a threshold switch selector (e.g., threshold switch selector 502) in series with the programmable resistor element. A bipolar threshold switching selector does not require any of the above-mentioned additional control lines and additional cell area to enable the corresponding selection transistor of a selected memory cell to be turned on. In some embodiments, the memory system performs a read operation, as disclosed herein, to read memory cells that include a threshold switch selector having two terminals in series with a programmable resistor memory element.FIGS. 6A and 6B illustrate embodiments for integrating threshold switch selectors into an MRAM memory array having a cross-point architecture. The examples of FIGS. 6A and 6B show two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer cross-point array as shown in FIG. 4D but in a side view. If the orientation of the MRAM layers in the layer 1 cell and the layer 2 cell remains the same, as illustrated in FIG. 6A, the manufacturing process may be the same for each layer. On the other hand, at 6B, the memory cell is inverted so that the drive circuitry may operate the same; e.g., BL goes low to read P2AP for each layer. FIGS. 6A and 6B show a lower first word line conductive line 1 600, an upper first word line conductive line 2 620, and an intermediate second bit line conductive line 610. In these figures, all of these lines are shown extending across the page from left to right for ease of illustration, but in a cross-point array, they would be more fully illustrated as in the oblique view of Figure 4D, with the word lines or first traces or wires extending in a direction parallel to the surface of the underlying substrate and the bit lines or second traces or wires extending in a second direction parallel to the surface of the substrate that is substantially orthogonal to the first direction. The MRAM memory cells are also shown in a simplified form, showing only the reference layer, the free layer, and the inter-tunnel barrier, but in an actual implementation would typically include the additional structure described above with respect to FIG. 5.An MRAM element 602 including the free layer 601, the tunnel barrier 603, and the reference layer 605 is formed above the threshold switching selector 609, and this series combination of the MRAM element 602 and the threshold switching selector 609 together forms the layer 1 cell between the bit line 610 and the word line 1 600. The series combination of the MRAM element 602 and the threshold switching selector 609 operates substantially as described above when the threshold switching selector 609 is turned on. Initially, however, the threshold switch selector 609 must be turned on by applying a voltage above the threshold voltage V th of the threshold switch selector 609, and then the bias current or voltage must be held sufficiently high above the hold current or voltage of the threshold switch selector 609 to remain on / during the subsequent read or write operation.On the second layer, an MRAM element 612 includes the free layer 611, the tunnel barrier 613, and the reference layer 615 is formed over the threshold switching selector 619, wherein the series connection of the MRAM element 612 and the threshold switching selector 619 together form the layer 2 cell between the bit line 610 and the word line 2 620. The layer 2 cell operates like the layer 1 cell, although the bottom conductor now corresponds to a bit line 610 and the top conductor now is a word line, word line 2 620. Additional paired layers may similarly have a different bit line between them, with a pattern of WL1, BL1, WL2; WL3, BL2, WL4; or separate bit lines in a pattern like WL1, BL1, WL2, BL2. Or separate bit lines in a pattern such as WL1, BL1, BL2, WL2.In the embodiment of FIG. 6A, threshold switch selector 609 / 619 is formed below MRAM element 602 / 612, but in alternative embodiments, the threshold switch selector may be formed above the MRAM element for one or both layers. The MRAM memory cell is directional. In FIG. 6A, the MRAM elements 602 and 612 have the same orientation, with the free layer 601 / 611 over (relative to the substrate not shown) the reference layer 605 / 615. Forming the layers between the conductive traces having the same structure may have a number of advantages, particularly with respect to processing, as each of the two layers as well as subsequent layers may be formed according to the same processing order in embodiments with multiple layers.FIG. 6B illustrates an alternative embodiment arranged similar to that of FIG. 6A, except that in the layer 2 cell, the positions of the reference layer and the free layer are reversed. More specifically, as in FIG. 6A, between word line 1 650 and bit line 660, layer cell 1 includes an MRAM element l having a free layer 651 formed over tunnel barrier 653, which is in turn formed over reference layer 655, and MRAM element 652 is formed over threshold switch selector 659. The second layer of the embodiment of FIG. 6B again includes an MRAM element 662 formed over a threshold switch selector 669 between the bit line 660 and the word line 2 670, however with reference to FIG. 6A, the MRAM element 662 is inverted, with the reference layer 661 now formed over the tunnel barrier 663 and the free layer 665 now formed under the tunnel barrier 663. Alternatively, the configuration of the MRAM element 662 may be used for the layer 1 cell, and the configuration of the MRAM cell 652 may be used for the layer 2 cell.Although the embodiment of FIG. 6B requires a different processing sequence for forming layers, in some embodiments it may have advantages. In particular, directionality of the MRAM structure may make the embodiment of FIG. 6B attractive because when writing or reading in the same direction (with respect to the reference and free layers), the bit line is biased the same for both the bottom layer and the top layer and both word lines are biased the same. For example, when both layer 1 and layer 2 memory cells are sensed in the P2AP direction (with respect to the reference and free layers), the bitline layer 660 is biased as in the P2AP direction, the bitline 660 is low biased (e.g., 0 V) for both the upper and lower cells, with both wordline 1 650 and wordline 2 670 biased to a higher voltage level. Similarly, for writing to the high impedance AP state, bit line 660 is biased low (e.g., 0 V) for both the upper and lower cells, with word line 1 650 and word line 2 670 both biased to a higher voltage level.Reading data from an MRAM memory cell or writing data to an MRAM memory cell includes flowing a current through the memory cell. In embodiments where a threshold switch selector is placed in series with the MRAM element, the threshold switch selector may be turned on before current can flow through the MRAM element by applying a sufficient voltage to and current through the series combination of the threshold switch selector and the MRAM element.FIG. 7 illustrates an embodiment of a memory array 700 having a cross point architecture. The memory array 700 may be included in the memory structure 202 of FIG. 2 or 3. Array 700 includes a set of first conductive traces 706 a- 706 hand a set of second conductive traces 708 a- 708 d. In one embodiment, the set of first conductive traces 706 a- 706 are h wordlines and the set of second conductive traces 708 a- 708 bare bitlines. For simplicity, the set of first conductive traces 706 a- 706 hmay be referred to as word lines and the set of second conductive traces 708 a- 708 bmay be referred to as bit lines. However, the set of first conductive traces 706 ato 706 hmay be bitlines and the set of second conductive traces 708 ato 708 bmay be wordlines.Memory array 700 includes a number of programmable resistor memory cells 401. Each memory cell 401 is connected between one of the first conductive traces 706 and one of the second conductive traces 708. In one embodiment, each memory cell 401 includes a magneto-resistive random access memory (MRAM) element in series with a threshold switching selector. The threshold switch selector 502 is configured to become conductive with a lower resistance and remain conductive with a lower resistance in response to application of a voltage level that exceeds a threshold voltage of the threshold switch selector 502 until the current through the threshold switch selector 502 is reduced below the selector holding current, Ihold. The threshold switch selector 502 may be a two-pole device. In one embodiment, the threshold switch selector 502 includes an OTS.For purposes of discussion, memory cell 401a is selected for access. This could be a read or a write access. The selected memory cell 401a is located at the cross point of the selected word line 706g and the selected bit line 708b. A selected memory cell is a memory cell selected for a memory operation such as reading or writing. A selected memory cell is connected between a selected word line and a selected bit line. To select a memory cell 401, a select voltage (V select_BL), such as near ground, is provided to the selected bit line (e.g., bit line 708 b), and an access current (I access) is conducted (or forced) through a selected word line (e.g., word line 706 g). A selected word line means that the word line is connected to at least one selected memory cell. The selected word line is typically connected to one or more unselected memory cells. A selected bit line means that the bit line is connected to at least one selected memory cell. The selected bit line is typically connected to one or more unselected memory cells.In one embodiment, V select_BL is of an appropriate size such that threshold switch selector 502 is turned on in a selected memory cell, assuming that I access is applied to the selected word line with an appropriate maximum voltage with respect to the BL voltage. For example, V select_BL may be about 0 V. In contrast, Vunsel_BLeinen has such an amount that the threshold switching selector 502 is not turned on in a non-selected memory cell, for example, V select_BL may be about 1.65 V when the positive supply voltage is 3.3 V. Access current (I access) is conducted through at least a portion of the selected word line 706g. This access current may also flow through the selected memory cell 401 aand into a portion of the selected bit line 708 bafter the OTS is turned on. Such a selected WL may be driven up by 15 μA for reading or 30 μA for writing, for example, using a current source having a maximum voltage of 3.3 V, for example. For writing the opposite polarity, the selected word line is forced to be, for example, -30 μA and the selected bit line is forced to be near 3.3 V.The other memory cells are not selected for access (i.e., unselected memory cells). A "non-selected memory cell" means that the memory cell is not currently selected for access (e.g., read or write operation). An unselected word line is connected only to unselected memory cells. An unselected bit line is connected only to unselected memory cells. Word lines and bit lines that are not selected are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, a word line or bit line may be deselected by being forced to a non-selection voltage, such as Vmid, for example 1.65V, at about half the drive maximum voltage, for example 3.3V. A non-select voltage (Vunsev_BL) is applied to the non-selected bit lines (e.g., bit lines 708 a, 708 c, 708 d). An unselected voltage (Vunsel_WL), such as Vmid, is provided to unselected word lines (e.g., word lines 710 a, 710 b, 710 c, 710 d, 710 e, 710 f, and 710 h). I access could flow in both directions through the selected word line (as well as the selected bit line). In one embodiment, no current except leakage current is forced through unselected word lines (e.g., 706 a, 706 b, 706 c, 706 d, 706 e, 706 f, and 706 h).In the example of FIG. 7, there are more word lines than bit lines in the cross-point array. In one embodiment, there are more bit lines than word lines in the cross point array. In one embodiment, the number of bit lines corresponds to the number of word lines in the cross-point array. In the example of Figure 7, there are twice as many word lines as bit lines in the cross-point array; however, a different ratio could be used. This allows different tile sizes to be realized. For example, a tile may have 1024 BL by 848 WLs, which may be assembled into a module of 848×4096 cells by driving the WLs and BLs centrally between the four tiles. In one embodiment, a read is performed on a group of memory cells by, for example, selecting a memory cell in each of a number of tiles. In some embodiments, more than one memory cell may be selected from a tile for reading.In some embodiments, a forced current approach is used to access memory cells in a cross-point memory array. Threshold switch selectors may be used in series with the memory cells. The threshold switch selector may be connected in series with the memory element between the word line and the bit line. Thus, any voltage through the switching selector reduces the voltage through the memory element. As a rule, some variation of the offset or hold voltage occurs in the switching selectors. A forced current approach may help mitigate the offset voltage variations occurring from one threshold switch selector to the other to help minimize the current variations occurring from one cell to the other of the selected cell.FIG. 8 is a schematic of an embodiment of a system for reading a memory cell with a threshold switching selector. The system includes a current source 802, a control circuit 804, and a sense amplifier 806. Each memory cell 401 includes a programmable resistor storage element 702 in series with a threshold switching selector 502. In one embodiment, memory cell 401 is an MRAM cell in which programmable resistor storage element 702 is a magneto-resistor storage element and threshold switch selector 502 is an OTS. However, the memory cell could be a PCM cell, a ReRam cell, etc. The threshold switch selector 502 is not required to be an OTS. The threshold switch selector 502 could instead be a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other material that provides a highly non-linear dependence of the current on the selection voltage. The voltage Vselecton the bit line (BL) is a voltage having an appropriate magnitude to select the memory cell, for example 0 V. In one embodiment, Vselecton the bit line is near 3.3 V, and in another embodiment, near 0 V.The output of current source 802 is connected to a node referred to as VXSP. Node VXSP is connectable to the word line via the address decode transistors with a source-drain connected between VXSP and a word line and gates connected to binary address signals. Such transistors may be p- or n-channel. The system may include WL decoders used to select which wordline is connected to current source 802. Such WL decoders are not shown in FIG. 8. Node VXSP is connectable to an input of sense amplifier 806 and may therefore be referred to as a sense node. Current source 802 provides a current (Isource) to the selected word line. It should be appreciated that current source 802 may use current generators of different sizes for a read current and a write current. In one embodiment, current source 802 provides a first write current for "setting (set)" the memory cell and a second write current for "resetting (reset)" the memory cell, these two write currents having opposite polarities. In a read operation, the current may charge the selected word line until the threshold switch selector 502 turns on. After the threshold switch selector 502 is turned on, Isource is routed through the memory cell 401 in the direction and with the strength provided for reading and / or writing.Sense amplifier 806 ("ERF-Verst." for short) may be connected to node VXSP and may sense memory cell 401 while Isource is passed through memory cell 401. Sense amplifier 806 includes a set of capacitors 810. In one embodiment, the sense amplifier includes a differential amplifier that can compare the voltage across VXSP with a reference voltage (e.g., Vref). In one embodiment, one of these capacitors in sense amplifier 806 may be connected to node VXSP to sense and store a voltage on VXSP to sense the memory cell. In one embodiment, capacitors 810 include one or more additional capacitors, which may be connected to node VXSP (and thus the selected word line) during the read operation. As will be discussed in greater detail below, these one or more additional capacitors may be used to add or remove charge from node VXSP (and thus the selected word line). In one embodiment, a capacitor may be connected to node VXSP (and thus the selected word line) immediately after the threshold switch selector 502 is turned on. The OTS is turned off at Vth on the WL when the BL is close to 0. Until power-on, only leakage current flows to unselected bits on the selecting WL and BL, and the read current charges the WL to power-on the OTS and then through the selected memory cell. Then, the voltage between the WL and the BL collapses from Vth to Voffset plus Iread×path resistance from VXSP to ground (as described later, such as select transistors T 1+T 3 to WL and T 1+T 3 to BL, and memory cell resistance and voltage (mram+ots) and drive transistor from ground to bit line T 1+T 3. A differential voltage is discharged across the memory cell and other loads. This capacitor is a load that can be precharged to a lower voltage and thereby removes charge from node VXSP (and hence the selected word line) when the transistor is connected to VXSP. Removal of the charge from node VXSP (and thus the selected wordline) may prevent undesired current flow beyond Iread from flowing into memory element 702, thereby contributing to avoiding memory element 702 from changing state before the voltage across memory element 702 is sensed after it has stabilized after address selection and turning on OTS. Another advantage of charge removal from node VXSP (and thus the selected word line) immediately after threshold switch selector 502 is turned on is that the rate at which the selected word line drops to a stable voltage is accelerated, thereby reducing read latency in the sense read operation or reducing the time to build up the write voltage during writing.The capacitors 810 may be used in a globally referenced read operation (also referred to as a midpoint read operation) or in an SRR. In an embodiment of an SRR, one of the capacitors is used to provide a charge to node VXSP (and thus the selected word line) to speed up the rate of charging of the word line to a write voltage. This write operation may be for destructive writing that is between Read 1 and Read 2, or a write back operation used to restore the original state of the memory element 702 when needed. In an embodiment of an SRR, one of the capacitors is used to discharge node VXSP (and thus the selected wordline) after the current from current source 802 is decreased from a write current to a read current. Therefore, such a capacitor may be used to speed up the rate at which the selected word line is discharged, so that Read2 may be performed earlier, thereby reducing read latency.FIG. 9 is a flow diagram of an embodiment of a process 900 for reading programmable resistor memory cells in a cross-point array. The process may be used for reading memory cells with a threshold switch selector 502, such as an OTS, without being limited thereto. Process 900 may reduce read latency. Process 900 may improve read accuracy (bit error rate) by preventing the memory cell from inadvertently reversing state before the cell is detected. In one embodiment, process 900 is used in a center point read operation. In one embodiment, process 900 is used in an SSR.Step 902 includes applying a selection voltage to a first conductive trace. For example, the control circuit 804 provides a select voltage to the bit line. As an example, the bit line may be grounded to select the bit line; however, other voltages could be used. Step 902 may include applying voltages to a global and / or local bit line decoder based on the address of the selected memory cell.Step 904 includes providing a signal (e.g., current) to a second conductive path to turn on threshold switch selector 502. For example, control circuit 804 controls current source 802 to apply Isource to the word line. The control circuit 804 may control the magnitude of the current by selecting which current to apply from the current source 802. Step 902 may include applying voltages to a global and / or local wordline decoder based on the address of the selected memory cell.Step 906 includes connecting a first capacitor of a sense amplifier 806 to the second conductive path after the threshold switch selector 502 is turned on. Step 906 may include connecting the first capacitor to the sensing node VXSP connected to the word line, thereby connecting the first capacitor to the word line. The threshold switch selector 502 may have a high resistance before being turned on; however, the resistance may drop rapidly when the threshold switch selector 502 is turned on. The fast resistance drop may result in a so-called "overcharge" at the node VXSP and / or the word line. The overcharge could potentially flow into the storage element 702, which could potentially change the state of the storage element 702, which could lead to a read error. In one embodiment, the overcharge is transferred from node VXSPand / or from the wordline to the first capacitor, which may reduce unwanted current flow into memory element 702 (above the desired Iread current), thereby preventing a change in the state of memory element 702. By removing charge from node VXSP and / or the word line, the first capacitor may also help to shorten the time taken for the voltage on the second word line to stabilize, so that the memory cell may be sensed.Step 908 includes separating the first capacitor from the second conductive trace. The first capacitor may be disconnected after the voltage on the second conductive trace stabilizes, but the memory system is not required to wait until the voltage stabilizes to disconnect the first capacitor from the second conductive trace. In one embodiment, the memory system connects more than one capacitor to the second conductive trace to quickly reduce the voltage on the second conductive trace. After the voltage has dropped significantly, the memory system disconnects one of the capacitors while the other capacitor remains connected to the second conductive path. These two capacitors may include a larger and a smaller capacitor. A purpose of the larger capacitor is to be sufficiently large to discharge VXSP quickly. However, a large capacitance may result in a longer settling time on Vfinal required to differentiate the two states of the memory cell. By connecting two capacitors, VXSP can therefore be discharged quickly. If the larger capacitor is disconnected and a smaller capacitor remains, the settling time can be accelerated so that VXSP arrives at Vfinal more quickly. This technique of using two capacitors can reduce the time required to stabilize the voltage on the second conductive path.Step 910 includes sensing the memory cell while current is being conducted through the memory cell and both capacitors or the first or second capacitor or neither of which is / are separated from the second conductive trace. In one embodiment, the detection is performed for a Read1 of an SRR. In one embodiment, a second capacitor is connected to the VXSP to sense the memory cell. The second capacitor may be used in a Read1 of an SRR to sense and store a voltage on VXSP. In one embodiment, the detection is for a center point reading operation. In one embodiment of a center read operation, sense amplifier 806 may compare the voltage at VXSP to a reference voltage (Vref) after VXSP has settled sufficiently close to Vfinal (such that the difference is less than the available margin in sensing the bit state).FIG. 10 shows voltages on the bit line and the word line during reading of a memory cell with a threshold switching selector. Initially, the voltage on the bit line and the word line is set to Vmid (e.g., about 1.65 V), respectively. At t 1, the bit line is connected to ground, reducing the voltage on the bit line from Vmidto ground until t 2. In this example, near ground is the select voltage for the bit line. Also at t 1, the voltage on the word line (WL) begins to increase because current source 802 provides current to the word line. This current may be equal to the read current used when the voltage is sensed and used. At t 3, the threshold switch selector 502 turns on. The resistance of the threshold switch selector 502 may quickly reduce upon turn-on, which may be referred to herein as "snapback", which is the difference between the voltage on the wordline at which the OTS is turned on and the voltage on the wordline after it has settled with the read current flowing through the selected memory element. The voltage on the word line begins to drop at t 3 (see plot 1010). At t 4, a first capacitor is connected to the wordline, which quickly discharges the wordline (see plot 1012). The word line may reach a stable voltage more quickly (see plot 1016). The memory cell may be sensed while the word line is at a stable voltage, as at t 5, rather than having to wait until t 6 when a first capacitor is not connected to the word line. In an embodiment, the first capacitor is separated from the word line prior to sensing the memory cell. In one embodiment, a second (sense) capacitor may be connected to the word line to sense and store the voltage from the memory cell to be later matched to the midpoint of the possible signal difference from the memory cell. This second (sensing) capacitor may also be connected to the word line, while the first capacitor is connected to the word line. The first capacitor may also be used instead of the second capacitor for sensing and storing. The size of the first capacitor can be adjusted such that the VXSP voltage falls optimally, since this is primarily responsible for the discharge of the word line. If the first capacitor were not connected to the word line, it would take much longer for the voltage at the word line to reduce and settle (see diagram 1014). Therefore, the sensing of the memory cell would have to wait until after t6. Therefore, connecting the first capacitor to the word line after turning on the threshold switch selector 502 may reduce read latency. Furthermore, the snapback could result in an undesirable current in the storage element 702, which could potentially reverse the state of the storage element 702, which could result in a read error. However, connecting the first capacitor to the wordline after turning on the threshold switch selector 502 may result in the undesired current being diverted and no longer flowing into the storage element 702, but instead flowing into the first capacitor, thereby preventing the above-mentioned inversion of the state of the storage element.FIG. 11 is a schematic diagram of an embodiment of a read path and sense amplifier. The read path includes a current source, word line decode transistors, the selected word line, the memory cell, the selected bit line, and bit line decode transistors. The read path has a Vp positive power supply, such as 4V. Read current source 1102 is connected to power supply (Vp) and provides Iread to the memory cell. The read current may be activated by setting Read* low to turn on transistor T1. The output of T1 corresponding to node VXSP also drives the noninverting input (+) of differential sense amplifier 806. P-channel transistor T3P serves as a global WL decoder which can be selected when the gate of T3P is low, such as when driven by a binary decoder address signal from the host. P-channel transistor T1P serves as a local WL decoder which can be selected when the gate of T1P is low, such as when driven by a binary decoder address signal from the host. P-channel transistor T3P may serve as a driver for the selected WL. The memory cell 401 is connected between the selected WL and the selected BL. The memory cell (or bit) includes a threshold switch selector 502 and a memory element 702. The selected WL may be 1 of N WLs in an array. The selected BL may be 1 of M BLs in an array. The memory cell 401 may be located at an intersection of the selected WL and the selected BL on a chip having one or more arrays. N-channel transistor T1N may serve as a local decode driver into the selected BL. The BL may be selected when the T1N gate is high, such as when driven by a binary decoder address signal from the host. N-channel transistor T3N may serve as a global decoder selected when the T3N gate is high, such as when driven by a binary decoder address signal from the host. The output of T3N is VYS. A driver (YEN) is located between VYS and a negative power supply (GND). For reverse writing, a separate driver connected to VYS and a positive power supply Vp to which VYS is directed may be present and a parallel p-ch transistor decode path (n-ch-T1 and -T3) may be provided in parallel with the n-ch driver path described herein. The n-ch path is then turned off and the p-ch path is activated along with a driver transistor on Vp with gate to ground. Likewise, an n-ch path may be provided along with a current source to ground that is provided in parallel with the above-described p-ch path to the word line with its current source at Vp or another more suitable voltage. The p-ch path is then turned off and the n-ch path is activated by turning on an n-ch driver transistor in series with a current source to ground. Sense amplifier 806 has a non-inverting input (+) and an inverting input (-). The inverting input (-) is provided with a reference voltage (Vref). The non-inverting input (+) is connected to VXSP.The operation of the read path may be as follows, in one embodiment. Node VXSP, selected WL, selected BL, and VYS may be transistor-precharged to Vmid during a standby phase. The desired WL line (1 of N) can be selected by turning off the precharge and applying a low voltage to the gates of the transistors T3P and T1P (the gate voltages are referred to as decode address signals). The BL line can be selected by turning off the precharge and applying a high voltage to the gates of the transistors T1N and T3N (the gate voltages are referred to as decoding address signals). The gate of transistor YEN may be switched high to connect node VYS to GND. Ireadmay then be turned on and connected to VXSP by switching the gate from T1 low (e.g., read* goes low). The BL can therefore be pulled rapidly to GND by its active driver on power-up when YEN goes high. The selected WL and VXSP are increased to Vp by Iread at a rate of time =Total × V / Iread. Threshold switch selector 502 turns on when the voltage on WL approximately reaches voltage Vth(OTS), as IxR drops due to leakage current are relatively low. Here, Vth(OTS) refers to the threshold switching voltage of the threshold switching selector 502, which may or may not be an OTS. Then, the voltage on VXSPin the sense amplifier 806 again oscillates at Vfinal=Vread(final)=Voff(OTS)+Rpath×Iread. Here, Rpath includes WL and BL wire resistances, the address transistors (T3P, T1P, T1N, T3N), and the driver (YEN) at GND, as well as the resistance of the memory element 702 itself. Here, Voff(OTS) refers to a voltage across the threshold switching selector 502. The sense amplifier 806 compares Vfinal input to the sense amplifier (+) with Vref at the sense amplifier (-).FIG. 12 is a schematic diagram of an embodiment of the sense amplifier 806. For each of the n- or p-ch transistors, the complementary transistor (p- or n-ch) may be connected in parallel and driven by the complementary signal, except for the cross-coupled and clocked transistors T 16, T 17, T 21. The sense amplifier 806 includes a number of capacitors C1, C2, C3, and C4. In one embodiment, C1 is a snapback discharge capacitor used to discharge VXSPwhen or shortly after threshold switch selector 502 is turned on. In one embodiment, C2 is a read1 storage capacitor used to sense VXSP (e.g., to sense the memory cell). Note that C2 may also store the voltage sensed at VXSP to later compare to a voltage sensed at VXSP during Read2 (with appropriate adjustment of the voltage stored at C2 by turning off T28 and then sufficiently pulsing positive Vbridge to raise the voltage, for example 150 mV). Transistors T19 and T20 provide the ability to switch between Vump and ground using the Bump and Bump_Bar signals. Bump Bar is the logical addition to bump here. In one embodiment, C3 is a write-reset discharge capacitor used to discharge VXSP (e.g., discharge the selected WL) after destructively writing an SRR. Capacitor C3 can be used to speed up the discharge of the selected WL that occurs as the current decreases from Iwrite to Iread. In one embodiment, C4 is a write-reset charging capacitor used to charge VXSP (e.g., charge the selected WL) at the beginning of destructive writing of the SRR. Capacitor C 4 may be used to accelerate the charge of the selected WL as the current increases from a read current to a write current. In one embodiment, sense amplifier 806 includes a fifth capacitor C 5 (not shown in FIG. 12 ) that may be used as a write set charging capacitor. Optional fifth capacitor C 5 may be used to charge VXSP (e.g., to charge the selected WL) in the second write of the SRR used to restore the original state of memory cell 401, if necessary. Further details of the sense amplifier 806 are discussed below.In some embodiments, a capacitor in the sense amplifier is used during a globally referenced read operation to discharge the selected word line when (or shortly after) the threshold switch selector is turned on. In one embodiment, C1 is a snapback discharge capacitor used to discharge VXSPwhen or shortly after threshold switch selector 502 is turned on. In one embodiment, the process 900 of FIG. 9 is used for a globally referenced read, in which C1 is used as a snapback discharge capacitor, which is used to discharge VXSP when or shortly after the threshold switch selector 502 turns on.FIG. 13 is a table 1300 indicating the timing of signals in sense amplifier 806 for an embodiment of a globally referenced read in which C1 is used as a snapback discharge capacitor. Table 13 lists signals applied to gates of various transistors in sense amplifier 806 of Figure 12. The read signal refers to the signal that activates the read current (see read* at gate of T 1 in FIG. 11 ). Table 1300 provides a description of each signal. Each time field represents a time interval in which a signal is activated (black) or deactivated (white). The time fields are ordered from earlier times to later times, but each time field does not necessarily have the same duration. The table is provided to illustrate the simultaneous relationships between the signals. The optimum transitions between activated and deactivated signal states do not have to take place at the beginning of the time interval and can be shifted in time relative to other signals in the same time field. In Box0, one or more capacitors in sense amplifier 806 are precharged. In one embodiment, C1 is precharged to a voltage, such as near ground, which is set to provide a fast discharge of VXSP near its ReadInal value during Read1. In one embodiment, C1 is precharged to near GND and in another embodiment to near Vmid. The size of C1may be selected based on other capacitances in the circuit. The size of C1may be selected based on capacitances along the read path, for example. This read path capacitance may be segmented into two separate capacitances C_CMOS and C_array. C_CMOS is, for example, the combined capacitance of the transistors, wires, and circuitry between the read path between the current mirror and the cross point array. Namely, C_CMOS stands for the entire capacitance outside the cross point array whose stored charge would discharge through the selected memory cell after the selector turns on. C_array is the combined capacitance of the selected WL or BL, vias, and other wirings located between the select transistor and the selected memory element. As an example, C1may be between 10% and 50% of the combined CMOS and array capacitance. The CMOS and array capacitance may range from 50 to 200 fF or higher. An exemplary range for C1 is between 10 and 100 femtofarads (fF) (i.e., between 10×10^-15 farads and 100×10^-15 farads), with the actual range and size being adjusted by the choice of process for the CMOS transistors and their size, array wire length, width and pitch (pitch), as well as memory cell diameter (CD), and height and side skew angle along the memory and selector elements. In field 0, trap, precharge, S1 and S3 are high. In field 1, trap, precharge, S1 and S3 are low.In field 1 in FIG. 13 (time t 1 in FIG. 10 ), the read signal is used to activate the read current (e.g., T 1 in FIG. 11 is turned on). As mentioned above, the read current charges the selected WL. The duration of field 1 is sufficiently long to provide an appropriate voltage for turning on the threshold switch selector 502 (time t 3 in FIG. 10 ). Trap is low in field 1 and high in fields 2 and 3. When Trap is low, the sense amplifier is isolated from the data input. Trap high activates the signal in the sense amplifier. In fields 2 to 4, S1 is high. In field 2, S3 is high. Referring to Figure 12, "Trap" is applied to T12 and T13 in fields 2 and 3. In field 2, connections VXSP and VREF are activated. Referring to Fig. 12, S1 is applied to T11 to connect sense amplifier 806 to VXSP. In field 2 (time t 4 in FIG. 10 ), the signal S 3 is used to activate the snapback discharge capacitor C 1, which is separated in field 3. Referring to FIG. 12, S3 is applied to the gate of T26 to connect C1 to VXSP. Therefore, the snapback discharge capacitor C 1 can discharge VXSP (and thus discharges the voltage on the WL). After field 3, the snapback discharge capacitor C1 is disconnected from VXSP. Note that T11 and T12, and T13 and T14 are all on, while T16 and T17 are connected to VXSP and Vref. Also, S2 in fields 3 and 4 is high to enable the Vref connection. Referring to FIG. 12, S2 is applied to T14 to activate Vref. Note that when T13 and T14 are on, cross-coupled T16 and T17 are connected to Vref and VXSP. Therefore, the voltage VXSPat the noninverting input (+) can be compared to Vrefat the inverting input (-) by bringing Clock into an active state. In field 4, the sense amplifier output is clocked in. Referring to FIG. 12, clock is applied to T 21.FIGS. 14A and 14B illustrate further details of timing signals during a globally referenced read embodiment. FIG. 14A illustrates the read current 1410 provided to the selected WL between t 1 and t 4. FIG. 14B illustrates the voltage at the selected WL. The voltage across the memory cell increases from t1 to ts. The threshold switch selector is off between t1 and ts. Between t1 and ts, the current causes the wordline voltage to increase. The flow also assists any leaks in the path. Once the voltage across the threshold switch selector reaches the threshold voltage V th of the threshold switch selector 502, it turns on and switches to a low impedance state (at ts). Once the threshold switch selector 502 is in the on state (at ts), the current may flow through the selected memory cell 401. The WL voltage drops to a level that depends on the series resistance of the memory element 702, the on-state resistance of the threshold switch selector 502, along with the address select transistors and the metal resistance in the read path. At t2, snapback discharge capacitor C1 is connected to VXSP, which can speed up the rate at which the word line falls to its stable voltage. When the memory cell is in the HRS state, the voltage falls on line 1430. When the memory cell is in the LRS state, the voltage falls on line 1440. Sense amplifier 806 may then sense VXSP and compare it to Vref to determine whether the memory cell is in HRS or LRS. Note that after the snapback discharge capacitor C1 is connected to VXSP at t2, the wordline voltage falls very quickly and stabilizes to reduce read latency. In addition, the snapback discharge capacitor C 1 may prevent the state of the memory cell from reversing before sensing the cell by diverting current to the capacitor that could otherwise flow through the memory element 702.In some embodiments, a capacitor in sense amplifier 806 is used during an SRR read operation to discharge the selected word line when (or shortly after) the threshold switch selector is turned on. In one embodiment, C1 is used as the snapback discharge capacitor used to discharge VXSPwhen or shortly after the threshold switch selector 502 in an SRR is turned on. In one embodiment, process 900 of FIG. 9 is used during an SSR read operation in which C1is used as a snapback discharge capacitor that is used to discharge VXSPwhen or shortly after threshold switch selector 502 turns on. In another embodiment, the snapback discharge capacitor remains connected in SRR throughout the first read operation. In some embodiments, a capacitor in the sense amplifier is used during an SRR read operation to discharge the selected word line after a write stage of the SRR to prepare the second read operation after destructively writing the bit to AP. In one embodiment, C3 is used as a discharge capacitor for write reset during SRR by bringing S5 to an active state.FIG. 15 is a table 1500 indicating the timing of signals in sense amplifier 806 for an embodiment of an SRR in which C1 is used as a snapback discharge capacitor. C2 is used as the read reference capacitor. In addition, C3 is used as a discharge capacitor for write reset. Table 1500 lists signals applied to the gates of various transistors in sense amplifier 806 of Figure 12. The read signal refers to the signal that activates the read current (see read* at gate of T 1 in FIG. 11 ). In array 0, one or more capacitors are precharged in sense amplifier 806. The precharge voltages of C1, C2 and C3 may be different. In one embodiment, C1 is precharged to a voltage set to provide a fast discharge of VXSP after the threshold switch selector 502 is turned on. In another embodiment, C1 is precharged to GND. In another embodiment, C1 is precharged to Vmid (VPC), for example, when Vth is closer to Read Vfinal. The size of capacitors C 1 and C 3 may be selected based on other capacitances in the circuit. For example, the size of capacitors C 1 and C 3 may be selected based on capacitance along the read path. An exemplary range for C1is between 10 and 100 femto farads (fF). In one embodiment, C2 is precharged to a voltage suitable for sensing. In one embodiment, C2 is precharged to GND and in another to Vmid (VPC). An exemplary range for C2is between 1 and 10 femto farads (fF). In one embodiment, C3 is precharged to a voltage set to provide a fast discharge of VXSP after destructively writing the SRR. In one embodiment, C3 is precharged from GND to Vmid (VPC). As an example, C3may be between about 10% and 50% of C_CMOS+C_array. An exemplary range for C3is between 10 and 100 femto farads (fF). Referring to FIG. 12, the signal "Precharge (Precharge)" applied to gates of T 23 may be used for precharging C 1 and C 3 to VPC. The Precharge signal applied to the gates of T25 may be used to precharge C2 to VPC or to GND. S1 and S2 are off / L during precharge. During precharge, Trap, S1, S3, S4 and S5 are set high in field 0. Vump is set to 0 V during precharge.In field 1 in FIG. 15, the read signal is used to activate the read current (e.g., T 1 in FIG. 11 is turned on). As mentioned previously, the read current loads the selected WL and turns on the threshold switch selector 502. In field 2 to field 4, trap is high. In array 2 through array 4, signal S1 at transistor T11 connects sense amplifier 806 to VXSP through array 4 after sample is brought out of the active state. In field 2 to field 3, S 3 is used to activate the snapback discharge capacitor C 1. Referring to FIG. 12, S3 is applied to the gate of T26 to connect C1 to VXSP. Therefore, the snapback discharge capacitor C 1 can discharge VXSP (and thus discharge the voltage across the WL). In one embodiment, S 3 may remain high during field 3 to allow for a longer settling time before the VXSP voltage at C 2 is disabled for later use.At the beginning of field 3, read reference capacitor C2 is enabled by putting it in an active state of sample and S4 until the end of field 3. At the beginning of field 3, the snapback discharge capacitor C1 is disconnected from VXSP. During field 3, sample is brought high to connect C2 to VXSP. Referring to FIG. 12, S4 is applied to T28 to activate read reference capacitor C2, and "sample" at the gate of T24 is high to connect C2 to VXSP. Therefore, the read reference capacitor C2 may be used to sense and store the voltage on VXSP resulting from the read during the first read1 of the memory cell 401. Read reference capacitor C2 stores the result of Read1 and allows its level to be adjusted using Vbridge. Also in field 4 after sample L, the VXSP connection is disabled by setting S1 low. In one embodiment, read reference capacitor C 2 is activated along with snapback discharge capacitor C 1 during field 2, where C 1 is deactivated at the end of field 2 and C 1 is deactivated at the end of field 3.In field 4, the read current, sample, and trap are disabled before the write current is enabled, preferably as a transition from increasing read current to write current without the current falling below the read current. The read current may be disabled by turning off T 1 (see FIG. 11 ). Between field 4 and field 6, Trap is low, which can avoid disturbing the precharge during writing. In one embodiment, there is a separate write current source, similar to read current source 1102. However, the write current may be larger than the read current. In box 4, the write current source may be connected to VXSP to provide Iwrite, similar to read current source 1102 may be connected to VXSP to provide Iread, or the read current may be increased to become Iwrite, or a parallel current source may be turned on in VXSP to be added to the Iread current source. In box 5, the read voltage sampled is stepped up using Vump conducted in C2. The step-up of the voltage may be about half of the expected voltage difference between the LRS and the HRS (e.g., about 150 mV). FIG. 12 shows how T19 can be used to step up the voltage by Vump.In field 7, the write current is disabled and a read current is enabled. The read current may be activated by turning T 1 on again (see FIG. 11 ). In field 7, the VXSP connection is reactivated. Referring to FIG. 12, S 1 is applied to T 11 to connect sense amplifier 806 to VXSP (note that Trap is high at t 7 and t 8). In field 7, after the write current is reduced to the read current, the write-reset discharge capacitor C 3 is activated. Referring to FIG. 12, S5 is raised at the gate of T27 to connect C3 to VXSP. Therefore, C3 may speed up the rate of discharge to VXSP to speed up the rate at which the WL voltage drops after the current is reduced from Iwrite to Iread.Trap is high in fields 7 and 8 and then low in field 9 before clock is brought to an active state in field 9. Referring to Figure 12, "Trap" is applied to T12 and T13 to re-open the sense amplifier for the signal. Thus, T16 and T17 are connected to VXSP to sample the cell voltage. Also, T16 and T17 are connected through T13 to the boosted voltage of Read1. In one embodiment, Vref is removed because it is not used for SRR. Therefore, the voltage at the inverting input (+) can be compared to the boosted voltage provided by T19. In box 9, the sense amplifier is clocked out. Referring to FIG. 12, clock is applied to T 21.In some embodiments, a capacitor in the sense amplifier is used during an SRR read operation to charge the selected word line at the beginning of the destructive write operation. In one embodiment, C4 is used as a write-reset charging capacitor. FIG. 16 is a table 1600 indicating the timing of signals in sense amplifier 806 for an embodiment of an SRR in which C4 is used as a write-reset charging capacitor. In addition, C1 is used as a snapback discharge capacitor, and C3 is used as a write-reset discharge capacitor, similarly to the example in Table 1500. Thus, many of the signals in table 1600 are similar to those in table 1500 and will not be discussed again. In field 4, the read current is disabled and the write current is enabled, similar to the discussion of table 1500. Between field 4 and field 6, Trap is low, which can avoid disturbing the precharge during writing. Table 1600 shows that the capacitors may be precharged at t 0. Referring to FIG. 12, the signal "Precharge" applied to the gate of T 22 may be used to precharge C 4 to Vpcw. The pre-charging of C1, C2 and C3 has already been described in connection with Table 1500. The size of the capacitor C 4 may be selected based on other capacitances in the circuit. The size of the capacitor C 4 may be selected based on the capacitance along the read path, for example. As an example, C4may be between about 10% and 50% of C_CMOS+C_array. An exemplary range for C4is between 100 and 200 femto farads (fF). Table 1600 shows that in field 4 the write-reset charging capacitor C 4 is activated. Referring to FIG. 12, signal S6 goes high at the gate of T15 to connect write-reset charging capacitor C4 to VXSP. Note that S1is applied again to T11in field 7 through field 10 to connect the sense amplifier to VXSP. Note also that trap is high in fields 7 and 8.FIGS. 17A and 17B illustrate further details of timing signals during an embodiment of an SRR. FIG. 17A illustrates the read current 1702 applied to the selected WL between t 1 and t 4, the write current 1704 applied to the selected WL between t 4 and t 7, and the read current 1706 applied to the selected WL between t 7 and t 10. FIG. 17B illustrates the voltage at the selected WL. The voltage across the memory cell increases from t1 to ts. The threshold switch selector is off between t1 and ts. Between t1 and ts, the current causes the wordline voltage to increase. The flow also assists any leaks in the path. Once the voltage across the threshold switch selector reaches the threshold voltage V th of the threshold switch selector 502, it turns on and switches to a low impedance state (at ts). Once the threshold switch selector 502 is in the on state (at ts), the discharge current induced by the turning on of the OTS and also the read current (minus the leakage current to unselected cells) may flow through the selected memory cell 401. The WL voltage drops to a level that depends on the series resistance of the memory element 702, the on-state resistance, and the Voffset voltage of the threshold switch selector 502 along with the address selection transistors and the metal resistance in the read path. At t2, snapback discharge capacitor C1 is connected to VXSP, which can speed up the rate at which the word line falls to its stable value. When the memory cell is in the HRS state, the voltage falls on line 1710. When the memory cell is in the LRS state, the voltage falls on line 1712. Note that after the snapback discharge capacitor C1 is connected to VXSP at t2, the wordline voltage falls very quickly and stabilizes to reduce read latency. Moreover, the snapback discharge capacitor C 1 may prevent the state of the memory cell from reversing before sensing the cell by diverting a portion of the discharge current that would otherwise flow through the memory element 702.At t4, the current increases from Iread to Iwrite. To help speed up the rate at which the WL voltage rises in response to the increased current through memory cell 401, write-reset charging capacitor C4 is connected to the WL at t4 (and S2 is left on during use of C4 at t4 to allow its effect on VXSP1, and). The WL voltage may increase to level 1720 when the memory cell is already in HRS. The WL voltage may increase to level 1722 when the memory cell is initially in the LRS. The write current resets the memory cell to HRS, so that the memory cell completes the write phase at level 1720 after LRS is written to HRS during this write operation. And remains in the HRS if it was initially in the HRS state.At t7, the current decreases from Iwrite to Iread. To help speed up the rate at which the WL voltage decreases in response to the decreased current through memory cell 401, write-reset discharge capacitor C 3 is connected to the WL at t 7. The WL voltage rapidly decreases to level 1730.FIG. 18 is a flow diagram of an embodiment of a process 1800 for controlling a capacitor during an SRR to accelerate charging of the wordline during a destructive write phase. Step 1802 includes pre-charging the write-reset charging capacitor C 4. In one embodiment, the write-reset charging capacitor C 4 is precharged to a charge assist voltage. As used herein, the term "auxiliary charging voltage" refers to a voltage across a capacitor that allows the capacitor to transfer charge to a node (e.g., VXSP) to increase the voltage across the node. In one embodiment, the write-reset charging capacitor C 4 is precharged to Vp (see Vp in FIG. 11 ). As an example, Vpmay be about 4V. Step 1804 includes increasing the current from Iread to Iwrite. Step 1806 includes connecting the write-reset charging capacitor C 4 to the selected WL to speed up the rate of charge of the selected WL. Step 1808 includes disconnecting the write-reset charging capacitor C 4 from the selected WL to speed the WL dropping to a read voltage level after the end of the write operation.FIG. 19 is a flow diagram of an embodiment of a process 1900 for controlling a capacitor during an SRR to speed the discharge of the wordline after a destructive write phase. Step 1902 includes pre-charging the write-reset discharge capacitor C 3. In one embodiment, the write-reset discharge capacitor C 3 is precharged to Vmid (or VPC). In another embodiment, the write-reset discharge capacitor C 3 is precharged to a voltage at or near GND. The capacitor and precharge voltage are adjusted to ensure that the coupled voltage is not below Read Vfinal, as this could turn off the OTS and require recharging the WL to Vth before the Read2 voltage is sensed and compared to the adjusted Read1 voltage. Step 1904 includes reducing the current from Iwrite to Iread. Step 1906 includes connecting the write-reset discharge capacitor C3 to the selected WL to speed up the rate of discharge of the selected WL. Step 1908 includes disconnecting the write-reset discharge capacitor C 3 from the selected WL. Step 1910 includes sensing the memory cell while the read current is conducted through the memory cell.A final phase of an SRR may include writing the memory cell to restore its original state in the event that destructive writing has changed state. This last phase may be referred to as a write set or a write back. The write back phase may include increasing the current to a write current. In one embodiment, a capacitor may be used in sense amplifier 806 to speed up the rate of charging the wordline toward GND in the write back phase. In one embodiment, a capacitor may be used in sense amplifier 806 to speed up the rate of discharge of the wordline at the completion of the write back phase. FIG. 20 is a table 2000 indicating the timing of signals in sense amplifier 806 for an embodiment of a write back phase of an SRR. Table 2000 relates to a write set charging capacitor (C5), which may be sense amplifier 806 in one embodiment. The size of the capacitor C 5 may be selected based on other capacitances in the circuit. The size of the capacitor C 5 may be selected based on the capacitance along the read path, for example. As an example, C5may be between about 10% and 50% of C_CMOS+C_array. An exemplary range for C5is between 5 to 50 femto farads (fF). At t0, C5 is precharged. In one embodiment, C5 is precharged to GND (since the write operation for mram is in the reverse WL and BL directions from destructive write reset). Trap is high in field 11. Between field 12 and field 14, Trap is low, which can avoid disturbing the precharge during writing. At t 12, a write set current is activated. The write set current may have the opposite polarity as the write current in destructive writing. At t12, the VXSP link is activated by applying S1 to T11 as previously discussed. At t 12, the write set charge capacitor C 5 is activated. In one embodiment, the write set charging capacitor C 5 is added to the sense amplifier 806 of FIG. 12, along with a transistor that can be used to select the write set charging capacitor C 5. A signal S7 may be applied to the gate of this transistor to connect the write set capacitor to VXSN (using the n-ch path for write set). Therefore, the write set discharge capacitor C5 can be used to speed up the rate at which the WL is charged at the beginning of the write back phase. Another possibility is to add a write set discharge capacitor to speed up the rate of discharge of the word line at the end of the write back phase.FIG. 21 is a flow diagram of an embodiment of a process 2100 for controlling a capacitor during a write back phase of an SRR to accelerate charging of the wordline. Step 2102 includes precharging a write set charging capacitor C5. In one embodiment, write set charge capacitor C 5 is precharged to Gnd. Step 2104 includes increasing the current to Iwrite. Step 2106 includes connecting the write set discharge capacitor C5 to the selected WL to speed up the rate of charging the selected WL. Step 2108 includes disconnecting the write set discharge capacitor C5 from the selected WL. Step 2110 includes reducing the current after write back, such as to 0 A. In other embodiments, these steps 2108 and 2110 are reversed or occur at about the same time. Another possibility is to connect a write set discharge capacitor to speed up the rate of discharge of the word line at the end of the write back phase. In another embodiment, a transistor is turned on that connects the WL and BL to Vmid (pre-charge) (along with all other WL and BL when the cycle is complete).A cross point memory array may have multiple levels (or tiers). The voltages of WL and BL may be different for the upper layer and the lower layer. Thus, the various circuits illustrated herein (e.g., sense amplifier 806) may be modified accordingly.In view of the foregoing, it can be seen that, according to one embodiment, an apparatus includes a sense amplifier having a plurality of capacitors. The apparatus includes a control circuit in communication with the array and the plurality of capacitors. The control circuit is configured to be connected to an array including a plurality of first conductive traces, a plurality of second conductive traces, and memory cells. Each memory cell is located at an intersection of a first conductive trace and a second conductive trace. Each memory cell includes a threshold switching selector in series with a memory element. The control circuit is configured to provide a signal for turning on the threshold switching selector of a selected memory cell during a read operation. The selected memory cell is located between a selected first conductive trace and a selected second conductive trace. The control circuit is configured to connect a first capacitor of the plurality of capacitors to the selected first conductive path after the threshold switch selector is turned on to transfer charge between the selected first conductive path and the first capacitor when a voltage on the selected first conductive path changes. The control circuit is configured to control the sense amplifier to sense the selected memory cell during the read operation while the first capacitor is separated from the selected first conductive trace.In another embodiment, the control circuit is configured to connect the first capacitor to the selected first conductive path to speed the discharge of the selected first conductive path to a stable voltage after the threshold switch selector is turned on. The control circuit is configured to control the sense amplifier to sense the selected memory cell while the selected first conductive trace is at the stable voltage.In another embodiment, the control circuit is configured to pre-charge the first capacitor to a pre-charge voltage having a magnitude that is adjusted to speed the discharge of the selected first conductive trace to the stable voltage after the threshold switch selector is turned on.In a further embodiment, the control circuit is configured to disconnect the first capacitor from the selected first conductive track. The control circuit is configured to connect a second capacitor of the plurality of capacitors to the selected first conductive path. The first capacitor has a different capacitance than the second capacitor. The control circuit is configured to sense the selected memory cell with the second capacitor while the selected first conductive trace is at a stable voltage and the first capacitor is separated from the selected first conductive trace.In a further embodiment, the control circuit is configured to connect the second capacitor to the selected first conductive track while the first capacitor is connected to the first conductive track. The control circuit is configured to disconnect the first capacitor from the selected first conductive trace while the second capacitor remains connected to the first conductive trace.In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a charge assist voltage prior to connecting the first capacitor to the selected first conductive trace. The control circuit is configured to direct a write current to the selected first conductive trace to write the selected memory cell after turning on the threshold switch selector and after a first read of a self-referenced read of the selected memory cell during the read operation. The control circuit is configured to connect the first capacitor to the selected first conductive path to accelerate charging of the selected first conductive path in response to the write current.In another embodiment, the control circuit is configured to direct a current having a write magnitude to the selected first conductive trace to charge the selected first conductive trace to write the selected memory cell after a first read of a self-referenced read of the selected memory cell during the read operation. The control circuit is configured to reduce the current conducted to the selected first conductive trace after writing the selected memory cell to a read size. The control circuit is configured to connect the first capacitor to speed the discharge of the selected first conductive path after the current is reduced to the read amount.In another embodiment, the control circuit is configured to pre-charge the first capacitor to a voltage set to speed up the discharge of the selected first conductive path after the current is reduced to the read amount.In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a charge assist voltage prior to connecting the first capacitor to the selected first conductive trace. The control circuit is configured to direct a write current to the selected first conductive trace to write the selected memory cell during a write back phase of a self-referenced read of the read operation. The control circuit is configured to connect the first capacitor to the selected first conductive path to accelerate charging of the selected first conductive path during the write-back phase.In a further embodiment, the device comprises the array. The threshold switch selector includes an ovonic threshold switch (OTS). The memory element includes a magneto-resistive random access memory (MRAM) element.An embodiment includes a method for reading a selected memory cell in a cross-point array. The method includes applying a select voltage to a selected bit line in the cross-point array. The method includes directing a current to a selected word line in the cross-point array to charge a voltage on the selected word line. The selected memory cell is located between the selected bit line and the selected word line. The selected memory cell includes a threshold switching selector in series with a memory element. The method includes connecting a first capacitor in a sense amplifier to the selected word line after the threshold switch selector is turned on to speed the discharge of the selected word line to a stable voltage while passing the current through a path including the selected word line, the selected memory cell, and the selected bit line. The method includes isolating the first capacitor from the selected word line. The method includes sensing the selected memory cell with the sense amplifier while the selected word line is at the stable voltage while the current continues to be conducted through the path with the first capacitor that is separated from the selected word line.One embodiment includes a memory system having a cross-point array including word lines, bit lines, and programmable resistor memory cells. Each memory cell is located at an intersection of a word line and a bit line. Each memory cell includes a threshold switching selector in series with a programmable resistance memory element. The threshold switching selector has a high resistance in an off state and a low resistance in an on state. The memory system includes one or more sense amplifiers coupled to the cross point array. Each sense amplifier includes one or more capacitors. The memory system includes a control circuit in communication with the array and sense amplifiers. The control circuit is configured to apply a selection voltage to a selected bit line in the cross point array. A selected memory cell is located between the selected bit line and a selected word line on a read path that includes a sense node, the selected word line, the selected memory cell, and the selected bit line. The control circuit is configured to direct a current into the selected word line to charge a voltage at the sensing node to turn on the threshold switching selector of the selected memory cell. The control circuit is configured to connect a first capacitor in a first sense amplifier of the one or more sense amplifiers to the sense node after the threshold switch selector is turned on to speed up the discharge of the sense node to a stable voltage. The control circuit is configured to disconnect the first capacitor from the sensing node. The control circuit is configured to control the first sense amplifier to sense a voltage at the sense node while the sense node is at the stable voltage and while a read current is conducted through the read path, wherein the first capacitor is separated from the sense node. Such a control circuit may be configured to connect the first capacitor to the sensing node and then disconnect the capacitor after its voltage is nearly equal to the sensing node. The separated voltage may be adjusted by an up-bound voltage and used as a reference to be compared by the sense amplifier with another read voltage at the sense node after a destructive write operation.For the purposes of this document, reference in the specification to "one embodiment," "some embodiments," or "another embodiment" may be used to describe various embodiments or the same embodiment.For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other portions). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" when they are directly or indirectly connected to each other so that they can transmit electronic signals to each other.For the purposes of this document, the term "based on" may be read as "at least partially based on.".For the purposes of this document, without additional context, the use of numerical expressions such as a "first" object, a "second" object, and a "third" object may not imply sorting of objects, but may instead be used for identification purposes to identify different objects.The terms "top" and "bottom", "upper" and "lower", "vertical" and "horizontal" and forms thereof, as may be used herein, are merely exemplary and illustrative and are not intended to limit the description of the technology in that the subject matter may be interchanged in position and orientation. Also, as used herein, the terms "substantially" and / or "about" mean that the specified dimension or parameter can be varied within an acceptable tolerance for a given application.The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thus enabling others skilled in the art to best utilize them in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedU.S. Pat. No. 10,545,692

[0022]

Claims

An apparatus comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to connect to an array comprising a plurality of first conductive traces, a plurality of second conductive traces, and memory cells, each memory cell located at an intersection of a first conductive trace and a second conductive trace, each memory cell comprising a threshold switch selector in series with a memory element, the control circuit communicating with the array and with the plurality of capacitors, the control circuit configured to: provide a signal to turn on the threshold switch selector of a selected memory cell during a read operation, the selected memory cell located between a selected first conductive trace and a selected second conductive trace; connecting a first capacitor of the plurality of capacitors to the selected first conductive path after the threshold switching selector is turned on to transfer charge between the selected first conductive path and the first capacitor when a voltage on the selected first conductive path changes; and controlling the sense amplifier to sense the selected memory cell during the read operation while the first capacitor is separated from the selected first conductive path.The apparatus of claim 1, wherein the control circuit is configured to: connect the first capacitor to the selected first conductive path to speed the discharge of the selected first conductive path to a stable voltage after the threshold switching selector is turned on; and control the sense amplifier to sense the selected memory cell while the selected first conductive path is at the stable voltage.The apparatus of claim 2, wherein the control circuit is configured to: precharge the first capacitor to a precharge voltage having a magnitude set to speed the discharge of the selected first conductive path to the stable voltage after the threshold switching selector is turned on.The apparatus of claim 1, wherein the control circuit is configured to: disconnect the first capacitor from the selected first conductive trace; connect a second capacitor of the plurality of capacitors to the selected first conductive trace, the first capacitor having a different capacitance than the second capacitor; and sense the selected memory cell with the second capacitor while the selected first conductive trace is at a stable voltage and the first capacitor is disconnected from the selected first conductive trace.The apparatus of claim 4, wherein the control circuit is configured to: connect the second capacitor to the selected first conductive trace while the first capacitor is connected to the first conductive trace; and disconnect the first capacitor from the selected first conductive trace while the second capacitor remains connected to the first conductive trace.The apparatus of claim 1, wherein the control circuit is configured to: precharge the first capacitor to a charge assist voltage prior to connecting the first capacitor to the selected first conductive trace; conduct a write current to the selected first conductive trace to write the selected memory cell after turning on the threshold switch selector and after first reading a self-referenced reading of the selected memory cell during the read operation; and connect the first capacitor to the selected first conductive trace to accelerate charging of the selected first conductive trace in response to the write current.The apparatus of claim 1, wherein the control circuit is configured to: conduct a current having a write size to the selected first conductive trace to charge the selected first conductive trace to write the selected memory cell after a first read of a self-referenced read of the selected memory cell during the read operation; reduce the current conducted through the selected first conductive trace after a write of the selected memory cell to a read size; and connect the first capacitor to accelerate the discharge of the selected first conductive trace after the current has been reduced to the read size.The apparatus of claim 7, wherein the control circuit is configured to: precharge the first capacitor to a voltage set to speed the discharge of the selected first conductive path after the current is reduced to the read amount.The apparatus of claim 1, wherein the control circuit is configured to: precharge the first capacitor to a charge assist voltage prior to connecting the first capacitor to the selected first conductive trace; conduct a write current to the selected first conductive trace to write the selected memory cell during a write back phase of a self-referenced read of the read operation; and connect the first capacitor to the selected first conductive trace to accelerate charging of the selected first conductive trace during the write back phase.The device of claim 1, wherein: the device comprises the array; the threshold switch selector comprises an ovonic threshold switch (OTS); and the memory element comprises a magneto-resistive random access memory (MRAM) element.A method of reading a selected memory cell in a cross-point array, the method comprising: applying a selection voltage to a selected bit line in the cross-point array; directing a current to a selected word line in the cross-point array to charge a voltage across the selected word line, the selected memory cell being between the selected bit line and the selected word line, the selected memory cell comprising a threshold switching selector in series with a memory element; connecting a first capacitor in a sense amplifier to the selected word line after the threshold switching selector is turned on to speed the discharge of the selected word line to a stable voltage while directing the current through a path comprising the selected word line, the selected memory cell, and the selected bit line; disconnecting the first capacitor from the selected word line and sensing the selected memory cell with the sense amplifier while the selected word line is at the stable voltage while the current continues to be conducted through the path with the first capacitor that is disconnected from the selected word line.The method of claim 11, further comprising: pre-charging the first capacitor to a pre-charge voltage having a magnitude that is adjusted to speed the discharge of the selected word line to the stable voltage after the threshold switch selector is turned on.The method of claim 11, further comprising: performing destructive writing of the selected memory cell after sensing the selected memory cell, including passing a write current through the path; sinking the current through the path from the write current to a read current after performing the destructive writing; and connecting a second capacitor to the selected word line while the current through the path is on the read current to accelerate the discharge of voltage on the selected word line in response to sinking the current through the path.The method of claim 13, further comprising: isolating the second capacitor from the selected word line and sensing the selected memory cell with a third capacitor while the read current continues to be conducted through the path and the second capacitor is isolated from the selected word line.A memory system comprising: a cross point array comprising word lines, bit lines, and programmable resistor memory cells, each memory cell located at a cross point of a word line and a bit line, each memory cell comprising a threshold switch selector in series with a programmable resistor memory element, the threshold switch selector having a high resistance in an off state and a low resistance in an on state; one or more sense amplifiers coupled to the cross point array, each sense amplifier comprising one or more capacitors; A control circuit in communication with the array and the one or more sense amplifiers, the control circuit configured to: apply a selection voltage to a selected bit line in the cross-point array, wherein a selected memory cell is located between the selected bit line and a selected word line on a read path including a sense node, the selected word line, the selected memory cell, and the selected bit line; conduct a current to the selected word line to charge a voltage at the sense node to turn on the threshold switch selector of the selected memory cell; connect a first capacitor in a first sense amplifier of the one or more sense amplifiers to the sense node after the threshold switch selector is turned on to accelerate discharge of the sense node to a stable voltage; separating the first capacitor from the sensing node and controlling the first sensing amplifier to sense a voltage at the sensing node while the sensing node is at the stable voltage and while a sense current is conducted through the sense path, wherein the first capacitor is separated from the sensing node.The memory system of claim 15, wherein the control circuit is further configured to: precharge the first capacitor to a precharge voltage having a magnitude set to accelerate discharge of the sensing node after the threshold switching selector is turned on.The memory system of claim 15, wherein the control circuit is further configured to: sense the selected memory cell with a second capacitor in the first sense amplifier while the sense node is at the stable voltage; perform destructive writing of the selected memory cell after sensing the selected memory cell with the second capacitor, including passing a write current through the read path; sink the current to the read path to a read current after performing the destructive writing; and connect a third capacitor of the first sense amplifier to the sense node while the current is at the read current to accelerate discharge of the voltage at the sense node in response to the sink of the current.The memory system of claim 17, wherein the control circuit is further configured to: precharge the third capacitor to a precharge voltage having a magnitude that is set to speed the discharge of the sensing node in response to the decrease in current.The memory system of claim 17, wherein the control circuit is further configured to: precharge a fourth capacitor of the first sense amplifier to a charge assist voltage; increase the current to the read path from a read current to a write current after the selected memory cell is sensed with the second capacitor; and connect the fourth capacitor to the sense node while the current reaches the write current to speed up charging of the voltage at the sense node.The memory system of claim 15, wherein the control circuit is further configured to: disconnect the first capacitor from the sensing node after the voltage at the first capacitor is approximately equal to the voltage at the sensing node; adjust the voltage at the first capacitor by a surge voltage; and use the boosted voltage at the first capacitor as a reference voltage for comparison with another read voltage of the selected memory cell at the sensing node after destructively writing the selected memory cell.

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