DISPLAY DEVICE

Abstract

A display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to an embodiment of the present disclosure comprises a substrate (110) having a display region (DA), an optical region (OA) having a through-hole (TH) arranged in the display region (DA), and a non-display region (NDA) configured to surround the display region (DA); a plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114) arranged on the substrate (110); at least one dam (301, 302) arranged on the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114);and at least one connection protection part (200) disposed on the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114) and arranged to be closer to the through-hole (TH) than the at least one dam (301, 302), in which one or more first trenches (T1) are disposed in some of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114) that overlap the at least one connection protection part (200) in the optical region (OA). Therefore, it is possible to prevent the propagation of cracks that occur due to external disturbances in an optical region (OA).

Description

Field

[0001] The present disclosure relates to a display device and, more particularly, to a display device capable of blocking a crack propagation path in an area where a camera or a sensor is disposed. Description of the related technology

[0002] Display devices that visually represent electrical information signals have undergone rapid development since the entry into the information age. Various studies are continuously being conducted to develop a variety of display devices that are thin and lightweight, consume low power, and offer improved performance.

[0003] Representative display devices include liquid crystal displays (LCDs), field emission displays (FEDs), electrowetting displays (EWDs), organic light-emitting displays (OLEDs), and similar devices.

[0004] An electroluminescent display device, such as the representative organic light-emitting display device, refers to a display device that emits light independently. Unlike a liquid crystal display, the electroluminescent display device does not require a separate light source and can therefore be manufactured as a lightweight, thin display device. Furthermore, the electroluminescent display device is advantageous in terms of power consumption because the electroluminescent display device operates at a low voltage. Furthermore, the electroluminescent display device is expected to be used in various fields because the electroluminescent display device also excels in implementing colors, response speeds, viewing angles, and contrast ratios (CRs). SUMMARY

[0005] An object to be achieved by an embodiment of the present disclosure is to provide a display device capable of suppressing the propagation of cracks caused by external interference in an area where a camera or a sensor is arranged.

[0006] An object to be achieved by another embodiment of the present disclosure is to provide a display device capable of ensuring product yield and reliability.

[0007] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following descriptions. According to one aspect of the present disclosure, a display device according to claim 1 is provided. Further embodiments are described in the dependent claims.

[0008] A display device according to at least one embodiment of the present disclosure, comprising a substrate having a display region, an optical region disposed in the display region and having a through-hole, and a non-display region configured to surround the display region, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection protection part disposed on the plurality of insulating layers and disposed to be closer to the through-hole than the at least one dam, in which one or more first trenches are disposed in some of the plurality of insulating layers and overlap the at least one connection protection part in the optical region.

[0009] Further details of the exemplary embodiments are included in the detailed description and the drawings.

[0010] According to the display device according to one or more embodiments of the present disclosure, the plurality of connection protection members are provided on the peripheral portion of the through-hole, thereby preventing the intrusion of moisture and oxygen introduced from the through-hole. A suppression member can block the movement paths of moisture and oxygen by interrupting the common organic layer, that is, the light-emitting layer of the light-emitting element disposed on the end face of the display panel.

[0011] According to the display device according to one or more embodiments of the present disclosure, a plurality of dams may be disposed near the plurality of connection protection parts to prevent the organic insulating layer of the encapsulating layer from overflowing into the camera hole. The plurality of dams can suppress contamination of the camera hole area that may occur when the organic insulating layer overflows into the camera hole and suppress interference with the camera to be disposed in the through-hole.

[0012] According to the display device according to one or more embodiments of the present disclosure, the trenches are arranged by partially etching the plurality of inorganic insulating layers so that the trenches overlap the plurality of connection protection parts, so that even if the through hole cracks, the path on which the crack propagates can be blocked and the crack propagation can be suppressed.

[0013] The effects according to the present disclosure are not limited to the contents exemplified above, and the present disclosure has other various effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a display device according to an embodiment of the present disclosure; Fig. 2 is a cross-sectional view along the line II-II' in Fig. 1; Fig. 3 is an enlarged plan view of area A in Fig. 1; Fig. 4 is an enlarged plan view of area B in Fig. 3; Fig. 5 is a cross-sectional view taken along the line VV' in Fig. 4; Fig. Figure 6A is an enlarged cross-sectional view of area C in Fig. 5 according to the embodiment of the present disclosure. Fig. 6B is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 6C is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 6D is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 6E is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 7A is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 7B is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig. 7C is a cross-sectional view of a display device according to another embodiment of the present disclosure; and Fig. 7D is a cross-sectional view of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENT

[0015] Advantages and characteristics of the present disclosure and a method for achieving the advantages and characteristics will become apparent by reference to exemplary embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various forms. The exemplary embodiments are presented only by way of example so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure.

[0016] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally designate like elements throughout the disclosure. Furthermore, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted so as not to unnecessarily obscure the subject matter of the present disclosure. The terms "comprise," "having," and "consisting of" as used herein are generally intended to allow for the addition of other components unless the terms are used with the term "only." All references to the singular include the plural unless expressly stated otherwise.

[0017] Components are interpreted to have a normal margin of error, even if this is not explicitly stated.

[0018] When the positional relationship between two parts is described using terms such as "on", "over", "under" and "next to", one or more parts may be located between the two parts unless the terms are used together with the term "immediate" or "direct".

[0019] When an element or layer is placed "on top of" another element or layer, another layer or element may be placed directly on top of the other element or inserted between them.

[0020] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0021] Like reference numerals generally refer to like elements throughout the disclosure.

[0022] The size and thickness of each component illustrated in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated component.

[0023] The features of various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may interact and operate in technically different ways, and the embodiments may be practiced independently of each other or in conjunction with each other.

[0024] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Fig. 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0026] With reference to Fig. 1, a display device 100 of an embodiment of the present disclosure may include an image processing part 151, a timing controller 152, a data driving part 153, a gate driving part 154, and a display panel DP.

[0027] In this case, the image processing part 151 may output a data signal DATA, a data enable signal DE, and the like supplied from the external source. In addition to the data enable signal DE, the image processing part 151 may output one or more vertical synchronization signals, a horizontal synchronization signal, and a clock signal.

[0028] The timing controller 152 receives the data signal DATA in addition to the data enable signal DE or the drive signals including the vertical synchronization signal, the horizontal synchronization signal, and the clock signal from the image processing part 151. Based on the drive signal, the timing controller 152 can output a gate timing control signal GDC for controlling an operation timing of the gate driving part 154 and a data timing control signal DDC for controlling an operation timing of the data driving part 153.

[0029] Furthermore, in response to the data timing control signal DDC supplied from the timing controller 152, the data driver section 153 can sample and store the data signal DATA supplied from the timing controller 152, convert the data signal DATA into a gamma reference voltage, and output the gamma reference voltage. The data driver section 153 can output the data signal DATA via the data lines DL1 to DLn.

[0030] Furthermore, the gate driving part 154 may output the gate signal while shifting a level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 152. The gate driving part 154 may output the gate signal via the gate lines GL1 to GLm.

[0031] The display panel DP can display an image when a pixel P emits light in response to the data signal DATA and the gate signal supplied from the data driving part 153 and the gate driving part 154. A detailed structure of the pixel P will be described with reference to Fig. 2 described in detail.

[0032] The display panel DP may include a display area DA, an optical area OA disposed in the display area DA and having through-holes TH, and a non-display area NDA configured to surround the display area DA.

[0033] The display area DA is an area of ​​the display panel DP in which images are displayed.

[0034] A plurality of pixels P and a circuit for driving the plurality of pixels P may be arranged in the display area DA. The plurality of pixels P is a minimum unit constituting the display area DA. The display element may be arranged in each of the plurality of pixels P. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode may be arranged in each of the plurality of pixels P. However, the present disclosure is not limited thereto. Furthermore, the circuit for driving the plurality of pixels P may include drive elements, lines, and the like. For example, the circuit may include a thin-film transistor, a storage capacitor, a gate line, a data line, and the like.

[0035] The optical area OA is an area located in the display area DA, and the through-holes TH may be located in the optical area OA. The through-hole TH may be located in the display area DA of the display panel DP, thereby reducing a bezel area that is a non-display area NDA and maximizing the display area DA. A design product with the maximized display area DA maximizes the degree of user immersion in the screen, thereby improving the aesthetic appearance.

[0036] The through-hole TH may be shaped to correspond to an optical electronic device such as a camera or an optical sensor.

[0037] Fig. 1 illustrates two through-holes TH. However, the present disclosure is not limited thereto. The number of through-holes TH can be provided in various ways. For example, one or two holes are arranged in the display area DA. A camera can be arranged in a first hole, and a distance detection sensor, a face detection sensor, or a wide-angle camera can be arranged in a second hole.

[0038] The non-display area (NDA) is an area where no image is displayed.

[0039] The non-display area (NDA) may be curved so that the non-display area (NDA) is not visible from an end face. The non-display area (NDA) may be covered by a housing (not illustrated). The non-display area (NDA) is referred to as the bezel area.

[0040] Fig. 1 illustrates that the non-display area NDA surrounds the display area DA, which has a quadrangular shape. However, the shapes and arrangements of the display area DA and the non-display area NDA are not limited to the Fig. 1. That is, the display area DA and the non-display area NDA may be suitable for the design of an electronic device equipped with the display device 100. For example, an exemplary shape of the display area DA may also be a pentagonal shape, a hexagonal shape, a circular shape, an elliptical shape, or the like.

[0041] Various lines and circuits for operating the organic light-emitting element in the display area DA may be arranged in the non-display area NDA. For example, the non-display area NDA may include connection lines for transmitting signals to the plurality of subpixels and to the circuitry in the display area DA. The non-display area NDA may include gate-in-panel (GIP) lines or driver ICs such as the gate driver part 154 and the data driver part 153. However, the present disclosure is not limited thereto.

[0042] The display device 100 may also include various additional elements configured to generate various signals or operate the pixel in the display area DA. The additional elements for operating the pixel may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, and the like. The display device 100 may also include additional elements related to functions other than the function of operating the pixel. For example, the display device 100 may include additional elements that provide a touch detection function, a user certification function (e.g., fingerprint detection), a multi-level pressure detection function, a tactile feedback function, and the like.The above-mentioned additional elements may be arranged in the non-display area NDA and / or in an external circuit connected to a connection interface.

[0043] Hereinafter, a cross-sectional structure of the display area DA of the display device 100 will be described with reference to Fig. 2 described in more detail.

[0044] Fig. 2 is a cross-sectional view illustrating a cross-sectional structure of a pixel arranged in the display area according to the embodiment of the present disclosure.

[0045] The display device 100 according to the embodiment of the present disclosure may include a substrate 110, a first buffer layer 111, a first thin-film transistor TR1, a second thin-film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a terminal electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 115, a bank 116a, a spacer 116b, an anode 121, a light-emitting layer 122, a cathode 123, an encapsulation layer 117, and a touch detection part.

[0046] The substrate 110 serves to support and protect the components of the flexible display device that are arranged above the substrate 110.

[0047] The substrate 110 is a component for accommodating various components of the display device 100 and may be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 consists of the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c, which can prevent moisture penetration. For example, the first substrate 110a and the second substrate 110b may each be a polyimide (PI) substrate, and the interlayer insulating film 110c may be implemented as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multilayer including the above-mentioned layers.

[0048] A light-blocking layer 125 may be disposed on the substrate 110.

[0049] The first buffer layer 111 may be disposed on the substrate 110 while covering the light-blocking layer 125. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110 while covering the light-blocking layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0050] The multi-buffer layer 111a may retard the diffusion of moisture or oxygen that has penetrated into the substrate 110 and may include at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0051] The active buffer layer 111b may protect a first active layer A1 and suppress various types of defects introduced from the substrate 110. The active buffer layer 111b may, for example, comprise at least one of the following materials: a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0052] The first thin-film transistor TR1 may be disposed on the first buffer layer 111. The first thin-film transistor TR1 may include the first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. In this case, depending on the design of a pixel circuit, the first source electrode S1 may be a first drain electrode, and the first drain electrode D1 may be a first source electrode.

[0053] The first active layer A1 may be disposed on the first buffer layer 111 so as to overlap the light-blocking layer 125. The first active layer A1 may be made of amorphous silicon or polysilicon (polycrystalline silicon). For example, the first active layer A1 may comprise low-temperature polysilicon (LTPS). Since a polysilicon material has a high mobility (100 cm 2 / Vs or more), low power consumption, and excellent reliability, the polysilicon material can be used, for example, for gate drivers and / or multiplexers (MUX) for driving elements for driving thin-film transistors for display elements. In the display device 100 according to the embodiment of the present disclosure, the polysilicon material can be deposited on a first active layer A1 of the thin-film transistor. However, the present disclosure is not limited thereto. For example, the polysilicon material can also be deposited on a second active layer A2 of the switching thin-film transistor in accordance with the characteristics of the display device 100.The first active layer A1 may be formed by depositing amorphous silicon (a-Si) on the first buffer layer 111, forming polysilicon through a dehydration process and a crystallization process, and then patterning the polysilicon. In this case, the first active layer A1 may include a first channel region in which a channel is formed when the first thin-film transistor TR1 operates, and a first source region and a first drain region arranged on two opposite sides of the first channel region. The first source region means a portion of the first active layer A1 connected to the first source electrode S1, and the first drain region means a portion of the first active layer A1 connected to the first drain electrode D1.The first source region and the first drain region may be configured, for example, by doping the first active layer A1 with ions (impurities). The first source region and the first drain region may be formed by doping the polysilicon material with ions. The first channel region may be a portion where the polysilicon material remains without being subjected to ion doping.

[0054] The first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multilayer comprising the above-mentioned layers. The first gate insulating layer 112a may include contact holes through which the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 are respectively connected to the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1.

[0055] The first gate electrode G1 of the first thin-film transistor TR1 and a first capacitor electrode C1 of a storage capacitor Cst may be arranged on the first gate insulating layer 112a.

[0056] In this case, the first gate electrode G1 and the first capacitor electrode C1 may each be formed as a single layer or multi-layer of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode G1 may be formed on the first gate insulating layer 112a so as to overlap the first channel region of the first active layer A1 of the first thin-film transistor TR1.

[0057] The first capacitor electrode C1 may be omitted based on the operating characteristics of the display device 100 and the structure, type, and the like of the thin-film transistor. The first gate electrode G1 and the first capacitor electrode C1 may be manufactured using the same method. Furthermore, the first gate electrode G1 and the first capacitor electrode C1 may be made of the same material and formed on the same layer.

[0058] The first interlayer insulating layer 113a may be disposed over the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multilayer comprising the above-mentioned layers. Furthermore, the first interlayer insulating layer 113a may include a contact hole through which the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1 are exposed.

[0059] A second capacitor electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 may be formed as a single layer or multi-layer of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 may be formed on the first interlayer insulating layer 113a so as to overlap the first capacitor electrode C1. Furthermore, the second capacitor electrode C2 may be made of the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted based on the operating characteristics of the display device 100 and the structure, type, and the like of the thin-film transistor.

[0060] The second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multilayer including the above-mentioned layers. The second buffer layer 114 may include a contact hole through which the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1 are exposed. Furthermore, the second buffer layer 114 may include a contact hole through which the second capacitor electrode C2 of the storage capacitor Cst is exposed.

[0061] The second buffer layer 114 may be implemented as a multilayer. However, the present disclosure is not limited thereto.

[0062] A second active layer A2 of the second thin-film transistor TR2 may be disposed on the second buffer layer 114. In this case, the second thin-film transistor TR2 may include the second active layer A2, the second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. In this case, depending on the design of the pixel circuit, the second source electrode S2 may be a drain electrode and the second drain electrode D2 may be a source electrode.

[0063] Furthermore, the second active layer A2 may include a second channel region in which a channel is formed when the second thin-film transistor TR2 operates, and a second source region and a second drain region located on two opposite sides of the second channel region. The second source region may be a part of the second active layer A2 connected to the second source electrode S2, and the second drain region may be a part of the second active layer A2 connected to the second drain electrode D2.

[0064] The second active layer A2 may be made of an oxide semiconductor. The oxide semiconductor material is a material with a larger band gap than a silicon material and has a low off-current because electrons cannot move through the band gap in the off state. Therefore, the thin-film transistor having the oxide semiconductor active layer may be suitable for a switching thin-film transistor that maintains a short on-time and a long off-time. However, the present disclosure is not limited thereto. The oxide semiconductor may also apply to the thin-film driver transistor in accordance with the characteristics of the display device 100. Since the oxide semiconductor material has a low off-current and can reduce the size of an auxiliary capacitance, the oxide semiconductor material is suitable for a high-resolution display element. The second active layer A2 may be made of, for example, a metal oxide, e.g.from various metal oxides such as indium gallium zinc oxide (IGZO). In this case, the description assumed that the second active layer A2 of the second thin-film transistor TR2 is made of IGZO among various metal oxides. However, the present disclosure is not limited thereto. The second active layer A2 of the second thin-film transistor TR2 may also be made of another metal oxide instead of IGZO, e.g., indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO).

[0065] The second active layer A2 can be formed by applying a metal oxide to the second buffer layer 114, a heat treatment for stabilization and then structuring the metal oxide.

[0066] The second gate insulating layer 112b may be arranged on the entire substrate 110, including the second active layer A2. The second gate insulating layer 112b may, for example, be implemented as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer comprising the above-mentioned layers.

[0067] The second gate electrode G2 may be arranged on the second gate insulating layer 112b.

[0068] The second gate electrode G2 can be designed as a single or multiple layer of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or an alloy thereof.

[0069] The second gate electrode G2 is formed, for example, by forming a metallic material on the second gate insulating layer 112b, forming a photoresist pattern on the metallic material, and then wet-etching the metallic material using the photoresist pattern as a mask. As the wet etching liquid for etching the metallic material, a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof, constituting the metallic material, and does not etch the insulating material, can be used.

[0070] The second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate electrode G2. The second interlayer insulating layer 113b may include a contact hole through which the first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 are exposed. For example, the second interlayer insulating layer 113b may include a contact hole through which the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1 are exposed. The second interlayer insulating layer 113b may include a contact hole through which the second source region and the second drain region of the second active layer A2 of the second thin-film transistor TR2 are exposed.

[0071] The second interlayer insulating layer 113b may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer comprising the above-mentioned layers.

[0072] The terminal electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be arranged on the second interlayer insulating layer 113b.

[0073] The terminal electrode CE may be electrically connected to the second drain electrode D2 of the second thin-film transistor TR2. Furthermore, the terminal electrode CE may be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 113b. That is, the terminal electrode CE may serve to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin-film transistor TR2.

[0074] In this case, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 can be connected to the first active layer A1 of the first thin film transistor TR1 via contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114 and the second interlayer insulating layer 113b.

[0075] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be connected to the second active layer A2 through a contact hole formed in the second interlayer insulating layer 113b.

[0076] The terminal electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be manufactured by the same method and from the same material.

[0077] For example, the terminal electrode CE, the first source electrode S1, and the first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 may each be implemented as a single layer or multi-layer of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the terminal electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 may each have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). However, the present disclosure is not limited thereto.

[0078] The terminal electrode CE may be integrally connected to the second drain electrode D2 of the second thin-film transistor TR2. However, the present disclosure is not limited thereto.

[0079] The first planarization layer 115a may be disposed over the terminal electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0080] The first planarization layer 115a may be an organic layer for planarizing and protecting an upper portion of the first thin-film transistor TR1 and an upper portion of the second thin-film transistor TR2. For example, the first planarization layer 115a may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0081] The auxiliary electrode 145 may be arranged on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin-film transistor TR2 through a contact hole of the first planarization layer 115a. The auxiliary electrode 145 may serve to electrically connect the second thin-film transistor TR2 and an anode 121. Furthermore, the auxiliary electrode 145 may be implemented as a single layer or multi-layer of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. The auxiliary electrode 145 may be made of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2.

[0082] The second planarization layer 115b may be disposed over the auxiliary electrode 145 and the first planarization layer 115a. The second planarization layer 115b may be made of, for example, an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0083] A light-emitting element 120 may be arranged on the second planarization layer 115b.

[0084] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 via a contact hole provided in the second planarization layer 115b. The anode 121 may be made of a metallic material.

[0085] If the display device 100 is a top-emission type display device in which the light emitted by the light-emitting element 120 propagates toward a top surface of the substrate 110 on which the light-emitting element 120 is disposed, the anode 121 may further include a transparent conductive layer and a reflective layer disposed on the transparent conductive layer. The transparent conductive layer may be made of, for example, a transparent conductive oxide such as ITO or IZO. The reflective layer may be made of, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0086] A bank 116 may be arranged to cover the anode 121. A part of the bank 116a corresponding to the light-emitting region of the subpixel may be opened. A part of the anode 121 may be exposed through the opened portion (hereinafter referred to as the open region) of the bank 116a. In this case, the bank 116a may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene-based resin, acrylic resin, or imide-based resin. However, the present disclosure is not limited thereto. The spacer 116b may be further arranged on the bank 116a.

[0087] The light-emitting layer 122 may be disposed in the open area of ​​the bank 116a and in a region at the periphery of the open area. Therefore, the light-emitting layer 122 may be disposed on the anode 121 exposed through the open area of ​​the bank 116.

[0088] The cathode 123 may be arranged on the light-emitting layer 122.

[0089] The light-emitting element 120 may be formed by the anode 121, the light-emitting layer 122, and the cathode 123. The light-emitting layer 122 may include a plurality of organic films.

[0090] An encapsulation layer 117 may be disposed on the light-emitting element 120.

[0091] The encapsulation layer 117 may have a single-layer or multi-layer structure. For example, the encapsulation layer 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0092] In this case, the first encapsulation layer 117a and the third encapsulation layer 117c may each be made of an inorganic film, and the second encapsulation layer 117b may be made of an organic film. Of the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c, the second encapsulation layer 117b may be the thickest and serve as a planarization layer.

[0093] The first encapsulation layer 117a may be disposed on the cathode 123 and closest to the light-emitting element 120. The first encapsulation layer 117a may be made of an inorganic insulating material that can be deposited at a low temperature. For example, the first encapsulation layer 117a may be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer 117a is deposited in a low-temperature environment, it is possible to prevent damage to the light-emitting layer 122, which is made of an organic material susceptible to a high-temperature environment, during a deposition process.

[0094] The second encapsulation layer 117b may have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be shaped to expose two opposite ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer to mitigate stresses between the layers that arise when the flexible display device is bent. The second encapsulation layer 117b may serve to improve planarization performance.

[0095] The second encapsulation layer 117b may, for example, be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). The second encapsulation layer 117b may also be formed, for example, using an inkjet process. However, the present disclosure is not limited thereto.

[0096] The third encapsulation layer 117c may be formed on the upper part of the substrate 110, which has the second encapsulation layer 117b, to cover a top surface and a side surface of both the second encapsulation layer 117b and the first encapsulation layer 117a. In this case, the third encapsulation layer 117c may minimize or block the penetration of moisture or oxygen from the outside into the first encapsulation layer 117a and the second encapsulation layer 117b. The third encapsulation layer 117c may be made of, for example, an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0097] A touch detection layer may be arranged on the encapsulation layer 117.

[0098] For example, a touch buffer layer 118a may be disposed on the third encapsulation layer 117c and a touch electrode TE may be disposed on the touch buffer layer 118a.

[0099] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM disposed on different layers. A touch interlayer insulating layer 118b may be disposed between the touch sensor metal TS and the bridge metal BM.

[0100] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be arranged so as to eliminate a level difference at a point where the touch electrode TE is arranged and realize appropriate electrical insulation.

[0101] Meanwhile, a polarizing layer may be disposed on the touch detection layer, but is not illustrated.

[0102] The polarizing layer suppresses the reflection of external light in the display area DA of the substrate 110. If the display device 100 is used outdoors, external natural light may be introduced and reflected by the reflective layer in the anode 121 of the light-emitting element 120 or by a metal electrode arranged at a lower part of the light-emitting element 120. The light rays reflected as described above may prevent an image on the display device 100 from being visually recognized. The polarizing layer can polarize the externally introduced light in a specific direction, thereby preventing the reflected light from being re-emitted to the outside of the display device 100.

[0103] Although not illustrated, a cover glass may be bonded to the polarizing layer via a bonding layer. The bonding layer may serve to bond the individual elements of the display device 100 together. The bonding layer may be formed, for example, by using a bonding agent for an optically transparent display, such as a pressure-sensitive bonding agent, an optically transparent bonding agent (OCR), or an optically transparent resin (OCR). However, the present disclosure is not limited thereto.

[0104] The cover glass can protect the components of the display device 100 from external influences and prevent damage such as scratches.

[0105] Fig. Figure 3 is an enlarged plan view illustrating the area A corresponding to the optical area in Fig. 1 corresponds.

[0106] With reference to Fig. 3, the through-hole TH for arranging an optical electronic device may be provided in the center of the optical region OA, and the camera module or the sensor may be arranged in the through-hole TH. The optical region OA may include all regions in which a dam structure 300 adjacent to the circular or elliptical through-hole TH, a connection protection part 200, and the like are arranged. The through-hole TH may be removed with a laser in a panel finishing step. The non-display region NDA may be positioned between the through-hole TH and the display region DA, and a high-potential power line PL, a gate line SL, and the like may be arranged in the non-display region NDA. The connection protection part 200 and the dam structure 300 may be arranged around the through-hole TH. Referring to Fig. 3, the connection protection part 200 may include a first suppression part 210 and a second suppression part 220, and the dam structure 300 may include a first dam 301 and a second dam 302. The first suppression part 210, the first dam 301, the second suppression part 220, and the second dam 302 may be arranged sequentially from the through-hole TH. In general, the dam structure may serve to maintain a bonding force between the upper and lower substrates constituting the display panel DP by preventing the second encapsulation layer 117b, which is a part of the encapsulation part 117 on the outer peripheral portion of the display panel DP, from flowing downward to one end of an outer peripheral portion of the display panel 100.The dam structure 300 in the optical region OA may also include a plurality of structures, such as the first dam 301 and the second dam 302, to prevent the second encapsulation layer 117b of the encapsulation layer 117, which serves to protect the light-emitting element 150, from invading or leaking into the optical region OA. The connection protection part 200 may be configured to suppress the intrusion of moisture or oxygen by interrupting the light-emitting layer 122. The present disclosure provides two dams. However, the present disclosure is not limited thereto. An additional dam may be arranged in accordance with the layout of a space. Referring to FIG. Fig. 3, the first suppression member 210 may be disposed near the through-hole TH, and then the first dam 301, the second suppression member 220, and the second dam 302 may be disposed sequentially. The first suppression member 210 and the second suppression member 220 may be disposed to serve to protect the light-emitting element 120 in the display area from moisture or oxygen that may be introduced from the through-hole TH. The light-emitting layer 122 of the light-emitting element 120 may be deposited on an end surface of the display panel 100 and may also be uniformly deposited in the optical area OA.Due to the nature of the organic material, the light-emitting layer 122 has high reactivity and dispersity with respect to moisture and oxygen, so that moisture and oxygen may be transferred to the light-emitting element 120 in the display area DA. The first and second suppression parts 210 and 220 may partially interrupt the light-emitting layer 122 to suppress this problem. In the present disclosure, the two suppression parts are illustrated. However, the present disclosure is not limited thereto.

[0107] The light-emitting element 120 and the pixel circuit in the corresponding region are removed to establish the optical region OA. However, the light-emitting elements 120 and the pixel circuits arranged on the upper, lower, left, and right sides from the optical region OA must be electrically connected. For this purpose, the high-potential power line PL, the gate line SL, and the like may be arranged in the non-display region NDA adjacent to the optical region OA to be connected on the upper, lower, left, and right sides while bypassing the optical region OA.

[0108] Fig. 4 is an enlarged plan view of area B in Fig. 3.

[0109] With reference to Fig. 4, the first suppression member 210 may be arranged to be near the through-hole TH, the first dam 301 may be arranged between the first suppression member 210 and the second suppression member 220, and the second dam 302 may be arranged on the right side of the second suppression member 220. The first suppression member 210 may include a first structure 211, a second structure 212, a third structure 213, and a fourth structure 214, and the second suppression member 220 may include a fifth structure 221, a sixth structure 222, a seventh structure 223, and an eighth structure 224. Referring to FIG. Fig. 3 and Fig. 4, the first suppression member 210, the first dam 301, the second suppression member 220, and the second dam 302 may be arranged in a closed loop shape around the through-hole TH. If any of the first suppression member 210, the first dam 301, the second suppression member 220, and the second dam 302 is penetrated, moisture and oxygen may penetrate into the display area DA from the outside, or the second encapsulation layer 117b may flow over the optical area OA and flow into the through-hole TH from the inside. Therefore, the first suppression member 210, the first dam 301, the second suppression member 220, and the second dam 302 are arranged in a closed loop shape. Referring to Fig. 4, the first suppression member 210 and the second suppression member 220 may each have four structures. However, the present disclosure is not limited thereto. For example, the first suppression member 210 and the second suppression member 220 may each have three or fewer or five or more structures. However, the present disclosure is not limited thereto.

[0110] Fig. 5 is a cross-sectional view of the optical section along the line VV' in Fig. 4.

[0111] The first suppression part 210 and the second suppression part 220 form a closed loop shape around the through hole TH, the first dam 301 may be arranged between the first suppression part 210 and the second suppression part 220, and the second dam 302 may be arranged in a closed loop shape on another side surface of the second suppression part 220. Referring to Fig. 5, the through hole TH may be arranged to be near the first suppression part 210.

[0112] With reference to Fig. 4, the first suppression member 210 may include the first pattern 211 to the fourth pattern 214. The first to fourth patterns 211, 212, 213, and 214 may each be formed as a two-stage structure including the upper and lower portions to interrupt the light-emitting layer 122, which may become a moisture permeation path for moisture from a region where the through-hole TH is disposed, and to define an undercut pattern on a side surface of the upper portion.Specifically, the upper portion of each of the first to fourth structures 211, 212, 213, and 214 is arranged to have a trapezoidal cross section having a conical shape, and the lower portion of each of the first to fourth structures 211, 212, 213, and 214 is arranged to have a rectangular cross section having an inverted conical or approximately vertical side surface and having a predetermined height, so that a width difference can occur between a bottom surface of the upper portion and a top surface of the lower portion, which are points where the upper and lower portions meet. Since the top surface of the lower portion can be formed narrower than the bottom surface of the upper portion, the undercut structure through which a part of the bottom surface of the upper portion is exposed can be formed.Therefore, the light-emitting layer 122 deposited on the end face of the display panel DP can be interrupted by the undercut structures of the side surfaces of the upper portions of the first to fourth structures 211, 212, 213, and 214.

[0113] The first to fourth structures 211, 212, 213, and 214 constituting the first suppression member 210 may be made of an organic material and an inorganic material. For example, the upper portion of each of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the first planarization layer 115a or the second planarization layer 115b. However, the present disclosure is not limited to this. Furthermore, the lower portion of each of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the second interlayer insulating layer 113b. However, the present disclosure is not limited to this.

[0114] The second suppression part 220 may include the fifth to eighth structures 221, 222, 223, and 224. The fifth to eighth structures 221, 222, 223, and 224 constituting the second suppression part 220 may each have a two-stage structure with an upper and a lower portion, like the first to fourth structures 211, 212, 213, and 214. The second encapsulation layer 117b disposed on the second suppression part 220 may make it difficult for moisture or oxygen to penetrate into the upper portion. Like the first suppression part 210, the second suppression part 220 may have an undercut structure formed in the side surface of the upper portion to block a path through which moisture or oxygen mainly penetrates into the through-hole TH or the side surface on which the first suppression part 210 is disposed.The arrangement of the first suppression part 210 and the second suppression part 220 can prevent the penetration of moisture or oxygen into the light-emitting element 120 in the display area DA from the optical area OA through the light-emitting layer 122.

[0115] The fifth to eighth structures 221, 222, 223, and 224 constituting the second suppression part 220 may also be made of an organic and an inorganic material. For example, the upper portion of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the first planarization layer 115a or the second planarization layer 115b. However, the present disclosure is not limited thereto. The lower portion of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the second interlayer insulating layer 113b. However, the present disclosure is not limited thereto.

[0116] As in Fig. 5, the first dam 301 and the second dam 302 may be formed by stacking the second planarization layer 115b, the bank 116a, and the spacer 116b. However, the present disclosure is not limited thereto. The first dam 301 and the second dam 302 may further include the first planarization layer 115a and other layers.

[0117] With reference to Fig. 3, the optical area OA may vary depending on the size of a camera to be mounted on a product. The corresponding area is illustrated as an empty space, but some insulating films or wiring patterns may be arranged in this area. However, a separate description of a dummy area is omitted because the dummy area does not remain in the finished product when the through-hole TH is removed by a laser. The laser beams may be emitted circularly or elliptically depending on the shape of the optical area OA. All areas on the substrate, including the substrate 110, may be removed by the emitted laser beams. There may be a difference between the actual optical area OA and a laser irradiation area. For example, the laser irradiation area of ​​the optical area OA may be an area formed inward by about 100 μm.The distinction between the laser irradiation area and the optical area OA must be defined so that the insulating layer of the optical area OA is not damaged during laser irradiation. A picosecond laser or a femtosecond laser can be used as the laser, but the present disclosure is not limited to these. The laser refers to a device that amplifies light generated by supplying energy to a specific material and utilizes induced and emitted light. The laser beams have the same characteristics as radio waves and have a directionality of monochromatic light. Therefore, the laser is used for communication, medical, or industrial purposes. With the help of the laser, a pattern can be formed on a desired portion, or a specific location can be easily removed. The laser utilizes energy to form or remove patterns.When laser energy is emitted onto the object, the thermal energy melts the object to form patterns. The longer the laser beams are applied, the more thermal effects can occur, which are transmitted to the adjacent areas where the patterns are formed. This thermal effect is the accumulation of heat around a laser irradiation area of ​​an object, and the heat can burn or deform the surrounding area that is larger than the specified pattern. Due to these characteristics of lasers, if the laser irradiated area overlaps or is adjacent to an insulating film, the thermal energy of the laser can deform the insulating film. The deformation of the insulating film can cause cracks that can propagate through the insulating film, leading to detachment of the insulating film and subsequent penetration of moisture and oxygen.For example, in order to suppress the deformation or peeling of the insulating films such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, all the insulating films may be removed at a distance of about 100 µm from a laser beam position.

[0118] One problem is that a crack generated when cutting the substrate 110 with a laser propagates through the inorganic insulating layer. Moisture or oxygen are characterized by reacting with and being transferred to the light-emitting layer 122 of the light-emitting element 120, while cracks can be transferred through hard, inorganic insulating layers that are not flexible. When the camera or sensor is mounted on the through-hole TH formed by a laser, cracks may be generated due to interference. The cracks that occur as described above may also propagate through the inorganic insulating layer. If the cracks that occur in the through-hole TH propagate through the inorganic insulating layer, a line defect or a growing dark spot (GDS) defect may occur.

[0119] Therefore, in the display device 100 according to the embodiment of the present disclosure, first trenches T1 may be arranged in some of the plurality of insulating layers arranged in the optical region OA, so that stepped structures that can block crack propagation paths are formed on the plurality of insulating layers. Throughout the description, reference is made to "a first trench T1" and "the first trench T1" as well as to "first trenches T1" and "the first trenches T1". It is understood that the description applies both to a display device having a first trench T1 and to a display device having more than one, i.e., a plurality of, first trenches T1. That is, at least one first trench T1 (i.e., one or more first trenches T1) may be arranged in a display device according to the embodiments of the present disclosure.

[0120] Fig. Figure 6A is an enlarged cross-sectional view of area C in Fig. 5 according to the embodiment of the present disclosure.

[0121] With reference to Fig. 5 and Fig. 6A, according to the embodiment of the present disclosure, the first trenches T1 may be disposed in some of the plurality of insulating layers that overlap at least one connection protection part 200 in the optical region OA. For example, the plurality of insulating layers may include or be at least one of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b disposed on the substrate 110, and the first trenches T1 may be disposed in some insulating layers disposed on top of the plurality of insulating layers.

[0122] In particular, with reference to Fig. 3 and Fig. 6A together, the first trench T1 may be provided by at least partially etching the plurality of insulating layers, ie, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b and the second interlayer insulating layer 113b, which overlap at least one connection protection part 200 arranged in the optical area OA.

[0123] The stepped structures can be formed on the plurality of insulating layers through the first trenches T1. Therefore, even if the through-hole TH cracks, crack propagation can be suppressed because the inorganic insulating layer through which the crack can propagate is removed from the region where the first trenches T1 are formed.

[0124] Furthermore, according to the embodiment of the present disclosure, at least one of the first planarization layer 115a and the second planarization layer 115b may be arranged in the first trench T1 to fill the first trench T1.

[0125] According to the embodiment of the present disclosure, the first trenches T1 may be formed by at least partially removing the plurality of inorganic insulating layers through which cracks may propagate, and the interior of the first trench T1 is filled with an organic material. Therefore, the crack in the first trench T1 cannot propagate further even if the through-hole TH cracks.

[0126] Fig. 5 and Fig. 6A illustrate a first trench arranged in the optical region OA. However, the first trench in the optical region OA according to the embodiment of the present disclosure is not limited thereto.

[0127] Fig. 6B is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 6C is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 6D is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 6E is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0128] As in Fig. 6B, a display device 1000 according to another embodiment of the present disclosure may further include the first trench T1 (or first trenches T1) configured to overlap at least one connection protection part 200 arranged in the optical region OA, and a second trench T2 arranged in some of the plurality of insulating layers that overlap the dam structure 300 arranged in the optical region OA.

[0129] In particular, as in Fig. 6B, the optical region OA may include the first trench T1 formed by at least partially etching the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b that overlap at least one connection protection part 200, and the second trench T2 formed by at least partially etching the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b that overlap the dam structure 300.

[0130] Therefore, in the display device 1000 according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 are arranged in the optical region OA. Therefore, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress a defect caused by crack propagation even if cracks occur at the time of forming the through-hole TH in the optical region OA or mounting an optical electronic device to the through-hole TH.

[0131] For example, after the plurality of insulating layers are formed, the depths of the first trench (or trenches) T1 and the second trench T2 formed in some of the plurality of insulating layers may be adjusted using a masking process. In this case, the first trench T1 and the second trench T2 may be formed by the same masking process.

[0132] The depth of the first and second trenches T1 and T2 can be adjusted if necessary by changing the conditions of the mask process.

[0133] Fig. 6C is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0134] As in Fig. 6C, in a display device 1100 according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 may overlap at least one connection protection part 200 and the dam structure 300 and may be at least partially disposed on the gate metal GM disposed on the same layer as the gate electrode G1 of the first thin film transistor, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0135] Fig. 6D is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 6E is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0136] As in Fig. 6D, in a display device 1200 according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 may overlap at least one connection protection part 200 and the dam structure 300 and may be at least partially disposed on the light-blocking layer 125, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0137] Fig. 6E is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0138] As in Fig. 6E, in a display device 1300 according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 may overlap at least one connection protection part 200 and the dam structure 300 and may be at least partially disposed on the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0139] Therefore, according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 are arranged in the optical region OA. Therefore, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress a defect caused by crack propagation even if cracks occur at the time of forming the through-hole TH in the optical region OA or mounting an optical electronic device at the through-hole TH.

[0140] Furthermore, according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 are arranged in the optical region OA to overlap at least one connection protection part 200 and the dam structure 300, so that a separate space for suppressing crack propagation is not required and the non-display area NDA adjacent to the optical region OA can be minimized.

[0141] In the following, a more detailed description of the optical area OA of the display device according to another embodiment of the present disclosure will be given with reference to Fig. 7 described.

[0142] Fig. 7A is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 7B is a cross-sectional view of a display device according to another further embodiment of the present disclosure. Fig. 7C is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 7D is a cross-sectional view of a display device according to another embodiment of the present disclosure. The cross-sectional views in Fig. 7A to 7D are essentially identical to the cross-sectional views in Fig. 6A to 6E, except for the first and second metal layers. Therefore, for the sake of simplicity, a repeated description excluding the first and second metal layers will be omitted.

[0143] In a display device 1400 according to another embodiment of the present disclosure, first metal layers 410 may further be arranged in the first and second trenches T1 and T2 and along the surfaces of some of the plurality of insulating layers.

[0144] For example, the first metal layers 410 may be arranged in the first and second trenches T1 and T2 and may be adjacent to the surfaces of the plurality of insulating layers.

[0145] As in Fig. As illustrated in Figure 7A, the first metal layers 410 may be disposed in the first and second trenches T1 and T2 and may be adjacent to the surfaces of the plurality of insulating layers. For example, the first metal layer 410 may be made of the same material as the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1.

[0146] In the display device 1400 according to another embodiment of the present disclosure, the crack propagation path can be blocked by the stepped structures of the plurality of insulating layers formed by the first and second trenches T1 and T2, and the crack propagation can be further blocked by the first metal layers 410 arranged in the first and second trenches T1 and T2 so as to be adjacent to the surfaces of the plurality of insulating layers. Therefore, the crack propagation path can be completely blocked by the first trench T1, the second trench T2, and the first metal layer 410, which can suppress a defect caused by crack propagation even if cracks occur at the through-hole TH at the time of forming the through-hole TH in the optical region OA or assembling the optical electronic device.

[0147] Fig. 7A illustrates the structures of the first metal layers 410 disposed in the first and second trenches T1 and T2 in the optical region OA and along the surfaces of some of the plurality of insulating layers. However, the structure of the optical region OA according to the embodiment of the present disclosure is not limited thereto.

[0148] Fig. 7B is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0149] A display device 1500 according to another embodiment of the present disclosure may further include second metal layers 520 arranged under the first and second trenches T1 and T2 in the optical region OA.

[0150] For example, as in Fig. 7B illustrates, first metal layers 510 may be disposed in the first and second trenches T1 and T2 and may be adjacent to the side surfaces of some of the plurality of insulating layers. The first metal layer 510 and the second metal layer 520 may be adjacent to each other. For example, the first metal layer 510 may be disposed on the same layer and made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 520 may be disposed on the same layer and made of the same material as the first gate electrode G1.

[0151] In the display device 1500 according to another embodiment of the present disclosure, the crack propagation path can be blocked by the stepped structures of the plurality of insulating layers formed by the first and second trenches T1 and T2, and the crack propagation path can be additionally blocked by the first metal layers 510 disposed in the first and second trenches T1 and T2 and the second metal layers 520 disposed below the first and second trenches T1 and T2. Therefore, the crack propagation path can be completely blocked by the first trench T1, the second trench T2, the first metal layer 510, and the second metal layer 520, which can suppress a defect caused by crack propagation even if cracks occur at the time of forming the through-hole TH in the optical region OA or mounting the optical electronic device at the through-hole TH.

[0152] According to another embodiment of the present disclosure, the depths of the first and second trenches T1 and T2 arranged in some of the plurality of insulating layers may be adjusted. In this case, the materials for forming the first and second metal layers 510 and 520 may vary depending on the depths of the first and second trenches T1 and T2.

[0153] Fig. 7C is a cross-sectional view of a display device according to another embodiment of the present disclosure. As in Fig. 7C, in a display device 1600 according to another embodiment of the present disclosure, a first metal layer 610 may be made of the same material as the first source electrode S1 and the first drain electrode D1, and a second metal layer 620 may be made of the same material as the light-blocking layer 125.

[0154] Fig. 7D is a cross-sectional view of a display device according to another embodiment of the present disclosure. As in Fig. 7D, in a display device 1700 according to another embodiment of the present disclosure, second metal layers 720 may be disposed in the first and second trenches T1 and T2 and adjacent to the surfaces of the plurality of insulating layers, and first metal layers 710 may be disposed in the first and second trenches T1 and T2 and adjacent to the surfaces of the second metal layers 720. For example, the first metal layer 710 may be disposed on the same layer and made of the same material as the second source electrode S2 and the second drain electrode D2, and the second metal layer 720 may be disposed on the same layer and made of the same material as the first source electrode S1 and the first drain electrode D1.

[0155] Therefore, according to another embodiment of the present disclosure, the first trench T1 and the second trench T2 are arranged in the optical region OA. Therefore, even if cracks occur at the time of forming the through-hole TH in the optical region OA or mounting an optical electronic device to the through-hole TH, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress a defect caused by the crack propagation. Moreover, the first trench T1 and the second trench T2 are arranged in the optical region OA to overlap at least one connection protection part 200 and the dam structure 300, so that a separate space for suppressing crack propagation is not required, and the non-display area NDA located adjacent to the optical region OA can be minimized.

[0156] Furthermore, according to another embodiment of the present disclosure, the first metal layers 410, 510, 610, and 710 may be disposed in the first and second trenches T1 and T2, and the second metal layers 420, 520, 620, and 720 may be disposed adjacent to the first metal layers 410, 510, 610, and 710, so that crack propagation can be further blocked. Therefore, the crack propagation path can be completely blocked by the first trench T1, the second trench T2, the first metal layers 410, 510, 610, and 710, and the second metal layers 420, 520, 620, and 720, which can suppress a defect caused by crack propagation even if cracks occur at the time of forming the through-hole TH in the optical region OA or mounting the optical electronic device at the through-hole TH.

[0157] The exemplary embodiments of the present disclosure may also be described as follows:

[0158] According to one aspect of the present disclosure, a display device includes a substrate having a display region, an optical region disposed in the display region and having a through-hole, and a non-display region configured to surround the display region, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection protection part disposed on the plurality of insulating layers and arranged to be closer to the through-hole than the at least one dam, in which one or more first trenches are disposed in some of the plurality of insulating layers and overlap the at least one connection protection part in the optical region.

[0159] The plurality of insulating layers may include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate, and the one or more first trenches may be disposed in some insulating layers disposed on a top surface of the plurality of insulating layers.

[0160] The display device may further comprise a second trench disposed in some of the plurality of insulating layers and overlapping the at least one dam in the optical region.

[0161] The display device may further comprise a first metal layer disposed in each of the first and second trenches and along the surfaces of some of the plurality of insulating layers.

[0162] The first metal layer may be disposed in each of the first and second trenches and may be adjacent to the surfaces of the plurality of insulating layers.

[0163] The display device may further comprise a first thin-film transistor arranged on the substrate in the display region and having a first active layer, a first gate electrode, a first source electrode and a first drain electrode, at least one insulating layer arranged on the first gate electrode and a second thin-film transistor arranged on the at least one insulating layer and having a second active layer, a second gate electrode, a second source electrode and a second drain electrode.

[0164] The first metal layer may be made of the same material as the first source electrode and the first drain electrode.

[0165] The display device may further comprise a second metal layer disposed beneath each of the first and second trenches.

[0166] The first metal layer may be disposed in each of the first and second trenches and may be adjacent to side surfaces of some of the plurality of insulating layers, and the first metal layer and the second metal layer may be adjacent to each other.

[0167] The first metal layer may be disposed on the same layer and made of the same material as the first source electrode and the first drain electrode, and the second metal layer may be disposed on the same layer and made of the same material as the first gate electrode.

[0168] The display device may further comprise a light-blocking layer disposed under the first active layer so as to overlap the first gate electrode, the first metal layer may be made of the same material as the first source electrode and the first drain electrode, and the second metal layer may be made of the same material as the light-blocking layer.

[0169] The second metal layer may be disposed in each of the first and second trenches and adjacent to surfaces of the plurality of insulating layers, and the first metal layer may be disposed in each of the first and second trenches and adjacent to surfaces of the second metal layer.

[0170] The first metal layer may be arranged on the same layer and made of the same material as the second source electrode and the second drain electrode, and the second metal layer may be arranged on the same layer and made of the same material as the first source electrode and the first drain electrode.

[0171] The display device may further comprise an optical electronic device arranged to overlap the optical region.

[0172] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are merely illustrative and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should therefore be understood that the exemplary embodiments described above are illustrative in all aspects and do not limit the present disclosure. The scope of the present disclosure should be interpreted based on the following claims.

Claims

[1] Display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) with: a substrate (110) having a display region (DA), an optical region (OA) disposed in the display region (DA) and having a through-hole (TH), and a non-display region (NDA) configured to surround the display region (DA); a plurality of insulating layers (111, 112a, 113a, 112b, 113b) arranged on the substrate (110); at least one dam (301, 302) disposed on the plurality of insulating layers (111, 112a, 113a, 112b, 113b); and at least one connection protection part (200) arranged on the plurality of insulating layers (111, 112a, 113a, 112b, 113b) and arranged to be closer to the through-hole (TH) than the at least one dam (301, 302); wherein a first trench (T1) is arranged in some of the plurality of insulating layers (111, 112a, 113a, 112b, 113b) and overlaps the at least one connection protection part (200) in the optical region (OA). [2] The display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to claim 1, wherein the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114) comprises at least one of a first buffer layer (111), a first gate insulating layer (112a), a first interlayer insulating layer (113a), a second buffer layer (114), a second gate insulating layer (112b), and a second interlayer insulating layer (113b) disposed on the substrate (110); and wherein the first trench (T1) is arranged in some insulating layers (112a, 113a, 113b, 114) arranged on a top side of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114). [3] The display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to claim 1 or 2, further comprising a second trench (T2) arranged in some of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114) and overlapping the at least one dam (301, 302) in the optical region (OA). [4] The display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to claim 2, further comprising: a first thin-film transistor (TR1) arranged on the substrate (110) in the display area (DA) and having a first active layer (A1), a first gate electrode (G1), a first source electrode (S1) and a first drain electrode (D1); at least one insulating layer (113a, 114) arranged on the first gate electrode (G1); and a second thin-film transistor (TR2) disposed on the at least one insulating layer (113a, 114) and having a second active layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2); a first planarization layer (115a) disposed over the first source electrode (S1) and the first drain electrode (D1) of the first thin-film transistor (TR1) and the second source electrode (S2) and the second drain electrode (D2) of the second thin-film transistor (TR2), and a second planarization layer (115b) disposed above the first planarization layer (115a), wherein at least one of the first planarization layer (115a) and the second planarization layer (115b) is disposed in the first trench (T1) to fill the first trench (T1). [5] The display device (1400, 1500, 1600, 1700) according to claim 3, further comprising a first metal layer (410, 510, 610, 710) disposed in each of the first and second trenches (T1, T2) and disposed along the surfaces of some of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114). [6] The display device (1400, 1500, 1600) according to claim 5, wherein the first metal layer (410, 510, 610) disposed in each of the first and second trenches (T1, T2) is adjacent to the surfaces of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114). [7] The display device (1400, 1500, 1600) according to claim 6, further comprising: a first thin-film transistor (TR1) arranged on the substrate (110) in the display area (DA) and having a first active layer (A1), a first gate electrode (G1), a first source electrode (S1) and a first drain electrode (D1); at least one insulating layer (113a, 114) arranged on the first gate electrode (G1); and a second thin-film transistor (TR2) disposed on the at least one insulating layer (113a, 114) and having a second active layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2). [8] The display device (1400, 1500, 1600) according to claim 7, wherein the first metal layer (410, 510, 610) is made of the same material as the first source electrode (S1) and the first drain electrode (D1). [9] The display device (1500, 1600) according to claim 7 or 8, further comprising a second metal layer (520, 620) disposed under each of the first and second trenches (T1, T2). [10] The display device (1500, 1600) according to claim 9, wherein the first metal layer (510, 610) disposed in each of the first and second trenches (T1, T2) is adjacent to side surfaces of some of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114), and the first metal layer (510, 610) and the second metal layer (510, 620) are adjacent to each other. [11] The display device (1500) according to claim 10, wherein the first metal layer (510) is arranged on the same layer and is made of the same material as the first source electrode (S1) and the first drain electrode (D1), and the second metal layer (520) is arranged on the same layer and is made of the same material as the first gate electrode (G1). [12] The display device (1600) of claim 10, further comprising: a light-blocking layer (125) disposed below the first active layer (A1) so as to overlap the first gate electrode (G1), wherein the first metal layer (610) is made of the same material as the first source electrode (S1) and the first drain electrode (D1), and wherein the second metal layer (620) is made of the same material as the light-blocking layer (125). [13] The display device (1700) of claim 5, further comprising a second metal layer (720) disposed in each of the first and second trenches (T1, T2) and adjacent to surfaces of the plurality of insulating layers (111, 112a, 113a, 112b, 113b, 114), wherein the first metal layer (710) disposed in each of the first and second trenches (T1, T2) is adjacent to surfaces of the second metal layer (720). [14] The display device (1700) of claim 13, wherein the first metal layer (710) is disposed on the same layer and is made of the same material as the second source electrode (S2) and the second drain electrode (D2), and the second metal layer (720) is disposed on the same layer and is made of the same material as the first source electrode (S1) and the first drain electrode (D1). [15] A display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to any one of claims 1 to 14, further comprising an optical electronic device arranged to overlap the optical area (OA). [16] The display device (100, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700) according to claim 15, wherein the through-hole (TH) is shaped to correspond to the optical electronic device.

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