HEAT SIGNAL GENERATION CIRCUIT AND HEAT SIGNAL GENERATION METHOD FOR IT

Abstract

Clock signal generation circuit comprising the following: a receiver circuit (102) configured to receive an input clock signal (CLK1): a clock path circuit (104) which is coupled to an output terminal of the receiver circuit (102); an oscillator circuit (110) configured to provide an oscillator signal (CLK2) with the same frequency as the input clock signal (CLK1); a multiplexer circuit (108) whose input terminal is coupled to the clock path circuit (104) and the oscillator circuit (110), wherein the input clock signal (CLK1) is sent through the clock path circuit (104) to the input terminal of the multiplexer circuit (108); an analog clock signal generator circuit (112) coupled to the oscillator circuit (110) to provide an output clock signal (CLK3), wherein an input terminal of the oscillator circuit (110) is coupled to an input terminal of the clock path circuit (104) or an output terminal of the analog clock signal generator circuit (112) to generate the oscillator signal (CLK2) based on the input clock signal (CLK1) or the output clock signal (CLK3); and a control circuit (106) which is coupled to the clock path circuit (104) and the multiplexer circuit (108) and is configured to control the multiplexer circuit (108), to selectively output the oscillator signal (CLK2) to the analog clock signal generator circuit (112), and wherein when the analog clock signal generator circuit (112) enters a sleep mode or a switched-off mode, the control circuit (106) determines that the analog clock signal generator circuit (112) does not supply the output clock signal (CLK3), and to control the clock path circuit (104), to stop sending the input clock signal (CLK1).

Description

BACKGROUND Technical area

[0001] The disclosure relates to a clock signal generation device and in particular to a multi-phase clock signal generation circuit and a clock signal generation method therefor. Description of the related area

[0002] In general, storage devices often use polyphase clock signals supplied by polyphase clock circuits to serialize or deserialize data signals to achieve high-speed read / write operations. The polyphase clock circuit might be, for example, an analog four-phase clock generator circuit used to generate four-phase clock signals. When the analog four-phase clock generator circuit does not need to output clock signals and is in off mode, the clock signals must still be continuously supplied to the four-phase clock generator via the clock path circuit so that the four-phase clock generator circuit can return to normal mode and continue operating normally. However, since the clock path circuit typically contains relatively power-consuming circuit components such as...If it contains a buffer, it will cause significant power consumption by continuously configuring the clock path circuit to supply the clock signals to the four-phase clock generator.

[0003] EP 0 316 943 A2 describes an integrated semiconductor circuit, in particular a microcomputer, which includes a clock generation circuit. The operation of the clock generation circuit is stopped once when the oscillation output signals are to be selectively transmitted to the clock generation circuit via a multiplexer.

[0004] US 5 126 695 A describes an integrated semiconductor circuit comprising a first oscillator circuit driven by a first voltage to generate a first clock signal used as an internal system clock signal for an internal circuit in the integrated circuit, and a second oscillator circuit driven by a second voltage lower than the first voltage to generate a second clock signal.

[0005] US 2021 / 0111727A1 describes a system comprising a digital phase-locked loop (DPLL) with a loop filter and a digitally controlled oscillator. The system also includes a clock generator coupled to an output of the DPLL and several clock domains coupled to the clock generator.

[0006] US 5 982 241 A describes a monolithic oscillator with two programmable fixed-frequency outputs, comprising a crystalless oscillator circuit that uses frequency-coupled feedback to generate an AI signal at a selected frequency, the frequency being stabilized over temperature and voltage by a compensation circuit connected to the crystalless oscillator circuit. SUMMARY

[0007] The invention relates to a clock signal generation circuit and a clock signal generation method that can effectively and substantially reduce the power consumption of the clock signal generation circuit.

[0008] The problem is solved by the features of the independent claims. Further embodiments are given in the dependent claims.

[0009] A clock signal generation circuit of the invention comprises a receiver circuit, a clock path circuit, an oscillator circuit, a multiplexer circuit, an analog clock signal generator circuit, and a control circuit. The receiver circuit receives an input clock signal. The clock path circuit is coupled to the receiver circuit and transmits the input clock signal. The oscillator circuit provides an oscillator signal with the same frequency as the input clock signal. An input terminal of the multiplexer circuit is coupled to the clock path circuit and the oscillator circuit. The analog clock signal generator circuit is coupled to the oscillator circuit and provides an output clock signal. The control circuit is coupled to the clock path circuit and the multiplexer circuit.If the analog clock signal generator circuit does not supply the output clock signal, the multiplexer circuit is controlled to selectively output the oscillator signal to the analog clock signal generator circuit, and the clock path circuit is controlled to stop sending the input clock signal.

[0010] In one embodiment of the invention, an input terminal of the oscillator circuit is coupled to an input terminal of the clock path circuit or an output terminal of the analog clock signal generator circuit in order to generate the oscillator signal based on the input clock signal or the output clock signal.

[0011] In one embodiment of the invention, the oscillator circuit can include a ring oscillator circuit or an injection detent oscillator circuit.

[0012] In one embodiment of the disclosure, the analog clock signal generator circuit may include an analog four-phase clock signal generator circuit.

[0013] In one embodiment of the invention, when the analog clock signal generator circuit enters a sleep mode or a switched-off mode, the control circuit determines that the analog clock signal generator circuit does not supply the output clock signal.

[0014] The invention also provides a clock signal generation method for a clock signal generation circuit. The clock signal generation circuit comprises a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to an input terminal of the multiplexer circuit. An output terminal of the oscillator circuit is coupled to the analog clock signal generator circuit. The clock path circuit is configured to send an input clock signal. The clock signal generation method of the clock signal generation circuit comprises the following steps: It is determined whether the analog clock signal generator circuit provides an output clock signal. In response to the analog clock signal generator circuit providing the output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal to the analog clock signal generator circuit.In response to the fact that the analog clock signal generator circuit does not supply the output clock signal, the multiplexer circuit is controlled to selectively output an oscillator signal to the analog clock signal generator circuit, and the clock path circuit is controlled to stop sending the input clock signal.

[0015] In one embodiment of the invention, an input terminal of the oscillator circuit receives the input clock signal or the output clock signal in order to generate the oscillator signal based on the input clock signal or the output clock signal.

[0016] In one embodiment of the invention, the oscillator circuit includes a ring oscillator circuit or an injection detent oscillator circuit.

[0017] In one embodiment of the disclosure, the analog clock signal generator circuit may include an analog four-phase clock signal generator circuit.

[0018] In one embodiment of the invention, when the analog clock signal generator circuit enters a sleep mode or a switched-off mode, it is determined that the analog clock signal generator circuit does not supply the output clock signal.

[0019] Based on the above description, the control circuit of the embodiment of the invention controls the multiplexer circuit to selectively output the oscillator signal supplied by the oscillator circuit to the analog clock signal generator circuit when the analog clock signal generator circuit does not supply the output clock signal, and to control the clock path circuit to stop sending the input clock signal. In this way, when the analog clock signal generator circuit does not supply the output clock signal, the oscillator circuit is used instead of the clock path circuit to supply the oscillator signal to the analog clock signal generator circuit at the same frequency as the input clock signal, thereby effectively reducing the power consumption of the clock signal generation circuit.

[0020] To make the above-mentioned features and advantages of the invention clearer and easier to understand, the following embodiments are given and described in detail with accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1, Fig. 2 to Fig. Figure 3 are schematic diagrams of a clock signal generation circuit according to embodiments of the disclosure. Fig. Figure 4 is a flowchart of a clock signal generation method of a clock signal generation circuit according to an embodiment of the invention. DESCRIPTION OF THE EXECUTION FORMS

[0021] Fig. 1 is a schematic diagram of a clock signal generation circuit according to an embodiment of the disclosure. With reference to Fig. 1. The clock signal generation circuit can comprise a receiver circuit 102, a clock path circuit 104, a control circuit 106, a multiplexer circuit 108, an oscillator circuit 110, and an analog clock signal generator circuit 112. The clock path circuit 104 is coupled to input terminals of the control circuit 106 and the multiplexer circuit 108. The oscillator circuit 110 is coupled to another input terminal of the multiplexer circuit 108. A control terminal of the oscillator circuit 110 is coupled to the control circuit 106. An output terminal of the multiplexer circuit 108 is coupled to the analog clock signal generator circuit 112. The analog clock signal generator circuit 112 can, for example, be an analog four-phase clock signal generator circuit, but the disclosure is not limited to this.In further embodiments, the analog clock signal generator circuit 112 can also be an analog clock signal generator with a different number of phases. The receiver circuit 102, the clock path circuit 104, the control circuit 106, the multiplexer circuit 108, the oscillator circuit 110, and the analog clock signal generator circuit 112 can, for example, be applied to a storage device and implemented as integrated circuits, systems-on-chip (SoCs), chipsets, or a chip array.

[0022] The receiver circuit 102 can receive an input clock signal CLK1, which is to be sent by the clock path circuit 104 to the input terminal of the multiplexer circuit 108. The oscillator circuit 110 is configured to receive an input clock signal CLK0 and to output an oscillator signal CLK2 at the same frequency as the input clock signal CLK1. The oscillator circuit 110 can be, for example, an injection detent oscillator (ILO) circuit or a ring oscillator circuit, but the disclosure is not limited to these. For example, as in Fig. As shown in Figure 2, the oscillator circuit 110 can be coupled to an output terminal of the analog clock signal generator circuit 112 to receive an output clock signal CLK3, supplied by the analog clock signal generator circuit 112, as the input clock signal CLK0, and to supply the oscillator signal CLK2 based on the output clock signal CLK3, which is output by the analog clock signal generator circuit 112. Alternatively, the oscillator circuit 110 can be coupled to an input terminal of the clock path circuit 104, as shown in Figure 2. Fig. Figure 3 shows how to supply the oscillator signal CLK2 according to the input clock signal CLK1. In further embodiments, the input clock signal CLK0, which is received by the oscillator circuit 110, can also come from other circuits, without referring to the embodiments of Fig. 2, Fig. to be limited to 3.

[0023] The control circuit 106 can determine whether the analog clock signal generator circuit 112 provides the output clock signal CLK3, for example, by determining whether the analog clock signal generator circuit 112 enters a sleep mode or a switched-off mode. If the analog clock signal generator circuit 112 enters a sleep mode or a switched-off mode, it is determined that the analog clock signal generator circuit 112 does not provide the output clock signal; otherwise, it is determined that the analog clock signal generator circuit 112 provides the output clock signal. If the control circuit 106 determines that the analog clock signal generator circuit 112 does not provide the output clock signal, the control circuit 106 can control the multiplexer circuit 108 to selectively output the oscillator signal CLK2 to the analog clock signal generator circuit 112, and control the clock path circuit 104 to stop sending the input clock signal CLK1.In this way, when the analog clock signal generator circuit 112 does not need to supply the output clock signal, the oscillator circuit 110 is used instead of the clock path circuit 104 to supply the oscillator signal CLK2 at the same frequency as the input clock signal CLK1 to the analog clock signal generator circuit 112, and the clock path circuit 104 is configured to stop sending the input clock signal CLK1, thereby effectively reducing the power consumption of the clock signal generation circuit without affecting the normal operation of the clock signal generation circuit.

[0024] Fig.Figure 4 is a flowchart of a clock signal generation method for a clock signal generation circuit according to one embodiment of the invention. The clock signal generation circuit comprises the clock path circuit, the oscillator circuit, the multiplexer circuit, and the analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to the input terminal of the multiplexer circuit. The output terminal of the multiplexer circuit is coupled to the analog clock signal generator circuit. The oscillator circuit can be implemented as a ring oscillator circuit or an injection detent oscillator circuit, but the disclosure is not limited thereto. The clock path circuit is configured to send the input clock signal. From the embodiments described above, it is evident that the clock signal generation method of the clock signal generation circuit can include at least the following steps.First, it is determined whether the analog clock signal generator circuit provides the output clock signal (step S402). For example, it can be determined whether the analog clock signal generator circuit enters the idle mode or the off mode. If the analog clock signal generator circuit enters the idle mode or the off mode, it is determined that the analog clock signal generator circuit does not provide the output clock signal. The analog clock signal generator circuit can be, for example, an analog four-phase clock signal generator circuit, but the disclosure is not limited to this. If the analog clock signal generator circuit provides the output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal to the analog clock signal generator circuit. The multiplexer circuit can be implemented, for example, as a multiplexer circuit, but the invention is not limited to this.If it is determined that the analog clock signal generator circuit provides the output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal supplied by the clock path circuit to the analog clock signal generator circuit (step S404). If it is determined that the analog clock signal generator circuit does not provide the output clock signal, the multiplexer circuit is controlled to selectively output the oscillator signal to the analog clock signal generator circuit (step S406), and the clock path circuit is controlled to stop sending the input clock signal (step S408). The oscillator circuit can receive either the input clock signal or the output clock signal supplied by the analog clock signal generator circuit to generate the oscillator signal based on either the input clock signal or the output clock signal.

[0025] In summary, the control circuit of the embodiment of the disclosure can control the multiplexer circuit to selectively output the oscillator signal supplied by the oscillator circuit to the analog clock signal generator circuit when the analog clock signal generator circuit does not supply the output clock signal, and control the clock path circuit to stop sending the input clock signal. In this way, when the analog clock signal generator circuit does not supply the output clock signal, the oscillator circuit is used instead of the clock path circuit to supply the oscillator signal to the analog clock signal generator circuit at the same frequency as the input clock signal, thereby effectively reducing the power consumption of the clock signal generation circuit. Reference symbol list 102 Receiver circuit 104 Clock path circuit 106 Control circuit 108 Multiplexer circuit 110 Oscillator circuit 112 Analog Clock Signal Generator Circuit CLK0 input clock signal CLK1~CLK3 Clock signal S402~A408 Steps of the clock signal generation procedure of the clock signal generation circuit

Claims

Clock signal generation circuit comprising: a receiver circuit (102) configured to receive an input clock signal (CLK1); a clock path circuit (104) coupled to an output terminal of the receiver circuit (102); an oscillator circuit (110) configured to provide an oscillator signal (CLK2) at the same frequency as the input clock signal (CLK1); a multiplexer circuit (108) whose input terminal is coupled to the clock path circuit (104) and the oscillator circuit (110), the input clock signal (CLK1) being sent through the clock path circuit (104) to the input terminal of the multiplexer circuit (108);an analog clock signal generator circuit (112) coupled to the oscillator circuit (110) to provide an output clock signal (CLK3), wherein an input terminal of the oscillator circuit (110) is coupled to an input terminal of the clock path circuit (104) or an output terminal of the analog clock signal generator circuit (112) to generate the oscillator signal (CLK2) based on the input clock signal (CLK1) or the output clock signal (CLK3);and a control circuit (106) coupled to the clock path circuit (104) and the multiplexer circuit (108) and configured to control the multiplexer circuit (108) to selectively output the oscillator signal (CLK2) to the analog clock signal generator circuit (112), wherein when the analog clock signal generator circuit (112) enters a sleep mode or a switched-off mode, the control circuit (106) determines that the analog clock signal generator circuit (112) does not supply the output clock signal (CLK3), and to control the clock path circuit (104) to stop sending the input clock signal (CLK1). Clock signal generation circuit according to claim 1, wherein the oscillator circuit (110) comprises a ring oscillator circuit or an injection detent oscillator circuit. Clock signal generation circuit according to one of the preceding claims, wherein the analog clock signal generator circuit (112) comprises an analog four-phase clock signal generator circuit (112). Clock signal generation method of a clock signal generation circuit, wherein the clock signal generation circuit comprises a clock path circuit (104), an oscillator circuit (110), a multiplexer circuit (108) and an analog clock signal generator circuit (112), the clock path circuit (104) and the oscillator circuit (110) being coupled to an input terminal of the multiplexer circuit (108), an output terminal of the multiplexer circuit (108) being coupled to the analog clock signal generator circuit (112) and the clock path circuit (104) being configured to send an input clock signal (CLK1), wherein the clock signal generation method of the clock signal generation circuit comprises: determining whether the analog clock signal generator circuit (112) enters a sleep mode or a switched-off mode, wherein, if the analog clock signal generator circuit (112) enters a sleep mode or a switched-off mode, determiningthat the analog clock signal generator circuit (112) does not supply the output clock signal (CLK3); in response to the analog clock signal generator circuit (112) supplying the output clock signal (CLK3), control the multiplexer circuit (108) to selectively output the input clock signal (CLK1) to the analog clock signal generator circuit (112); and in response to the fact that the analog clock signal generator circuit (112) does not supply the output clock signal (CLK3), the multiplexer circuit (108) is controlled to selectively output an oscillator signal (CLK2) to the analog clock signal generator circuit (112), and the clock path circuit (104) is controlled to stop sending the input clock signal (CLK1), wherein an input terminal of the oscillator circuit (110) receives the input clock signal (CLK1) or the output clock signal (CLK3) in order to generate the oscillator signal (CLK2) based on the input clock signal (CLK1) or the output clock signal (CLK3). Clock signal generation method of the clock signal generation circuit according to claim 4, wherein the oscillator circuit (110) comprises a ring oscillator circuit or an injection detent oscillator circuit. Clock signal generation method of the clock signal generation circuit according to claim 4 or 5, wherein the analog clock signal generator circuit (112) comprises an analog four-phase clock signal generator circuit (112).

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