Programmable processing array supporting multidimensional interpolation calculations

Abstract

Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a lookup table (LUT) according to a fused single instruction stream, multiple data stream (SIMD) instruction. The LUT may include segment entries corresponding to a result of evaluating a function using corresponding index values ​​representing an independent variable of the function. The index values ​​are used to map data sample values ​​in a data array configured to be interpolated to the segment entries.By using an iterative process of mapping data samples to valid segment entries contained in each LUT section, the architecture advantageously facilitates scaling to support larger LUTs and can thus be extended to enable linear interpolation on multiple dimensions.

Description

TECHNICAL FIELDTechniques are described that relate generally to programmable processor array architectures, and more particularly, to techniques for using such architectures to perform linear interpolation in multiple dimensions using a single instruction stream, multiple data streams (SIMD) instruction set.BACKGROUNDProgrammable processing array architectures may utilize multidimensional look-up tables (LUTs) as part of the computations performed for various signal processing tasks. Typically, the values stored in the LUTs are used to perform some type of interpolation according to the signal processing calculations. The most common of these interpolations is linear interpolation, which significantly and cost-effectively increases the uniformity of signal representation. Multi-dimensional LUTs can also be used to effectively model non-linear relationships between different signals, a practical example of multiband digital pre-distortion.Previous solutions for implementing table lookups (table lookups) include the use of a SIMD instruction set for a large 1D LUT implementation. Moreover, previous solutions use parallel processing, but are limited to only 1D table lookups and require a large number of instructions. Other techniques that implement multi-dimensional table lookups with interpolation have been implemented, but are based on memory access and require special memories as well as a special memory addressing scheme. Thus, current techniques for performing multi-dimensional table lookups are insufficient for programmable processing array architectures.BRIEF DESCRIPTION OF THE DRAWINGS / FIGURESThe accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the aspects of the present disclosure and, together with the description, further serve to explain the principles of the aspects and enable those skilled in the relevant art to make and use the aspects. FIG. 1 illustrates an example of a conventional vector processor architecture. FIG. 2 illustrates another example of a conventional vector processor architecture. FIG. 3 illustrates a block diagram of a programmable processing array architecture in accordance with the disclosure. FIG. 4 illustrates the use of 1-dimensional (1D) linear interpolation from stored look-up table values, in accordance with the disclosure; FIG. 5 illustrates the use of 2-dimensional (2D) linear interpolation from stored look-up table values, in accordance with the disclosure; FIG. 6A illustrates a look-up table (LUT) in accordance with the disclosure; FIG. 6B illustrates a look-up table (LUT) that is larger than the LUT of FIG. 6A, in accordance with the disclosure; FIG. 7 illustrates a conventional architecture and computational flow for performing linear 1D interpolation using accessed table values; FIG. 8 illustrates an architecture and computational flow for performing linear interpolation using accessed table values, in accordance with the disclosure; FIG. 9 illustrates a wireless device according to the disclosure; and FIG. 10 illustrates a process flow in accordance with the disclosure.The exemplary aspects of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element appears for the first time is typically indicated by the leftmost digit(s) in the corresponding reference numeral.DETAILED DESCRIPTIONIn the following description, numerous specific details are set forth in order to provide a thorough understanding of aspects of the present disclosure. However, it will be apparent to one skilled in the art that the aspects, including structures, systems, and methods, may be practiced without these specific details. The description and presentation herein are the usual means used by skilled artisans in the art to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuitry have not been described in detail in order to avoid unnecessarily obscuring aspects of the disclosure.The disclosure proposes a new instruction and hardware (HW) architecture to support efficient execution that can be implemented to perform linear interpolation using table lookups according to any suitable number of interpolation dimensions. An internal state selector is used to accumulate the result and reduce overhead. Several instructions and HW improvements are also introduced, and a procedure is provided to use proposed SIMD instructions to effectively expand the 1D case to compute multi-dimensional table lookups.The proposed microarchitecture and specialized fused instructions for 1D LUTs make large LUTs with interpolation substantially more efficient than conventional solutions. Moreover, the additional extensions for multi-dimensional LUTs with interpolation enable efficient multi-dimensional LUTs computation with a reduced set of instructions and without special storage requirements, such as those implemented in conventional solutions.1. Programmable Processing Array Operational SummaryThe programmable processing arrays, as discussed in more detail herein, may be implemented as vector processors or any other suitable type of array processors, of which vector processors are considered a specialized type. Such array processors may represent a central processing unit (CPU) that implements an instruction set including instructions that operate on one-dimensional arrays of data referred to as data "vectors". This is in contrast to scalar processors having instructions that operate on individual data elements. Vector processors may substantially improve performance at certain workloads, particularly numerical simulation and similar tasks, by utilizing a number of execution units, alternatively referred to herein as cores, execution units, processing units, functional units, or processing elements (PEs), that independently perform specific functions on incoming data streams to achieve a processing flow.Generally, conventional CPUs manipulate one or two data simultaneously. Conventional CPUs may, for example, receive an instruction essentially specifying: "add A to B and place the result in C", where "C" is an address in memory (memory). Typically, the data is rarely sent in raw form, but is "referenced" by passing an address to a location that holds the actual data. Decoding this address and retrieving the data from that particular memory location takes some time during which a conventional CPU idle waits for the requested data to be retrieved. As CPU speeds have increased, this memory latency has evolved to a large obstacle to performance in the past.To reduce the amount of time consumed for these steps, most modern CPUs use a technique known as instruction pipetting, in which the instructions sequentially pass through multiple subunits. The first subunit reads and decodes the address, the next subunit "interrogates" the values at these addresses (fetches), while the next subunit performs the actual mathematical operations. Vector processors continue this concept. For example, not only are the instructions pipelined, but the vector processors also pipelined the data itself. For example, instructions may be provided to a vector processor that indicate not only the addition of A to B, but the addition of all numbers within a particular range of address positions in memory to all numbers at a different set of address positions in memory. Rather than continuously decoding the instructions and querying the data required to complete each individual instruction, a vector processor may thus read a single instruction from memory. This first instruction is defined such that the instruction itself indicates that the instruction is repeatedly executed on another data item at an address that is one increment greater than the last. This allows a considerable saving in time during decoding.Vector processors may be implemented according to various architectures, and the various programmable processing array architectures as discussed throughout the disclosure may be implemented according to any of these architectures or combinations of these architectures as well as alternative processing array architectures distinct from vector processors. Figures 1 and 2 provide two different implementations of a vector processor architecture. FIG. 1 illustrates an attached vector processor attached to a general purpose computer to increase and improve the performance of this computer in numerical computing tasks. The attached vector processor achieves high performance by parallel processing with multiple functional units.In contrast, FIG. 2 shows an example of a single instruction stream, Single Instruction Stream (SIMD) vector processor architecture. The vector processor architecture 200 shown in FIG. 2 may include an architecture that consists of one or more execution units 204.1-204.N. Each execution unit is capable of executing an instruction. Each instruction may be a control, load / store, scalar, or vector instruction. Thus, a processor architecture having N execution units 204.1-204.N as shown in FIG. 2 may issue up to N instructions per clock cycle. The execution units 204.1-204.N operate under the control of a common control unit (such as a processor or processing circuitry) such that a single instruction stream is provided to control each of the execution units 204.1-204.N. The I / O data as shown in FIG. 2 is typically identified with data communicated between the vector processor 200 and another data source or processor (which may be the common controller or other processor) depending on the particular application. Thus, vector data store 201 stores data received as input to be processed by execution units 204.1-204.N, as well as data output or read from vector data store 201 after processing the data.Vector processor architecture 200 as shown in FIG. 2 is an example of a load / store (load store) architecture used by vector processors and is an instruction set architecture that divides instructions into two categories: memory access (load and store data between vector data store 201 and vector registers 202.1-202.N), and the vector processing operations performed by execution units 204.1-204.N using the data retrieved from vector registers 202.1-202.N and the results stored in the vector registers.Thus, the load / store instruction architecture enables data stored in vector data store 201 to be loaded into vector registers 202.1-202.N using load operations, transferred to execution units 204.1-204.N, processed, written back into vector registers 202.1-202.N, and subsequently written back into vector data store 201 using store operations. The position (address) of the data and the type of processing operation to be performed by each execution unit 204.1-204.N is part of an instruction stored as part of the instruction set in the program memory 206. The movement of data between these various components may be scheduled according to a decoder accessing the instruction sets from the program memory, which is not shown in more detail in FIG. 2 for the sake of brevity. The interconnect network that supports the transfer of data between the various components of vector processor architecture 200 as shown in FIG. 2 is generally implemented as a collection of data buses and may be shared among a set of different components, ports, etc. In this manner, multiple execution units 204.1-204.N may write to a single vector register 202, and the data loaded into multiple vector registers 202.1-202.N may be read and processed by multiple execution units 204.1-204.N. The use of instruction sets according to vector processor architecture 200 is well known, so that for brevity additional description of this operation is not provided.Each of the digital data streams may include a set of N discrete data samples that form the digital data to be subjected to the various processing operations, as discussed in more detail herein. In some scenarios, the discrete data samples may correspond to data configured to be modulated and transmitted. Regardless of the particular implementation, the processing operations may include performing one or more mathematical functions for each of the N samples within a digital data stream. The specific mathematical functions may depend on the particular implementation, such as a digital pre-distortion (DPD) function that may be used by a particular transmitter architecture. The mathematical functions can be distilled into a table of coarse values having the table entries representing a set of stored discrete data points. Each table entry may thus represent the result of evaluating a particular mathematical function using a respective discrete data sample as an independent variable of the continuous function.This discrete data point table may thus represent a range of function output values corresponding to specific points of discrete samples within a range of data samples. For example, if the DPD function f(x)=x is 2 and the data samples are expected to vary between 0 to 4000, then the table may store values within a range of addressable memory such that each table entry contains an evaluated result corresponding to a discrete digital data sample x. For example, the first entry in the table may correspond to the evaluated result f( 0) (i.e., the minimum value of the range of digital data stream samples), whereas the last entry in the table may correspond to the evaluated result f( 4000) (i.e., the maximum value of the range of digital data stream samples).However, to save memory space, it is preferable to condense the table entries stored in memory into a coarser representation of a smaller subset of data stream samples. For example, storing each evaluated value of f(x) incrementally by successive integer values f(0), f(1), f(2)...f(4000) using the example provided above would require a table of 4001 entries. Thus, it is advantageous to condense the size of this table into a coarser representation, such as per increments of 10, 25, 50, 100, 250, etc., and then use linear interpolation to calculate the corresponding function outputs from the next set of discrete data points stored in the table into which a received data sample falls. Determination of the granularity or coarseness of a table may be determined based on an accepted trade-off between accuracy and available memory.Moreover, and as discussed further below, the techniques implemented herein may use a programmable processing array architecture, from which the vector processors, as discussed herein, are considered a specialized manner. This architecture may be used to perform the linear interpolation calculations as discussed herein to evaluate a function according to specific data samples. Thus, unless otherwise indicated, the term "linear interpolation" should not be limited to a single dimension or interpreted according to a single variable. Instead, linear interpolation computations as used herein may be applicable to one or more dimensional linear interpolations according to any suitable number of dimensions and / or variables (e.g., bi-linear and tri-linear interpolation). The architecture and functionality of this overall interpolation process will be discussed further below.Programmable Processing Array ArchitectureFIG. 3 illustrates a block diagram showing details of a portion of a programmable processing array architecture in accordance with the disclosure. The architecture 300 as shown in FIG. 3 may also be referred to herein simply as a processing array and may form part of a hybrid architecture that implements dedicated hardware blocks, or as a stand-alone processing component. The programmable processing array architecture 300, when implemented as a vector processor architecture, may operate in the same manner as the vector processor architecture 200 shown and discussed above with respect to FIG. 2. However, the programmable processing array architecture 300 is not limited to a vector processor architecture and may be implemented in accordance with any suitable type of array-based processor architecture.In either case, the processing array, as shown in FIG. 3, may comprise any suitable number N of ports, each port comprising any suitable number M of processing elements (PEs). Although each port is shown in FIG. 3 as comprising 8 PEs, this is for ease of explanation and brevity, and the processing array may comprise any suitable number of such PEs per port. Thus, the processing array may comprise a network of PEs whose number is equal to the number of PEs per port (M) multiplied by the total number of ports (N). Thus, for an illustrative scenario in which the processing array includes 8 ports and 8 PEs per port, the processing array would implement (MxN)=(8x8)=64 PEs. Moreover, according to such a configuration, when implemented to perform wireless processing functions, each port may be identified with a respective antenna used as part of a multiple-input multiple-output (MIMO) communication system. Thus, the number of antennas used according to such a system may be equal to the number N of ports, each port dedicated to a data stream transmitted and received per antenna.Each of the PEs per port of the processing array may be coupled to the data interfaces 302.1, 302.2, and each PE may perform processing operations on an array of data samples that are retrieved via the data interfaces 302.1, 302.2. Access to the array of data samples by the PEs may be facilitated by any suitable configuration of switches (SWs), as indicated in FIG. 3 via the SW blocks. The switches within each of the ports of the processing array may also be coupled together via connections 306.1, 306.2, two shown in Figure 3 for the illustrative scenario of each port comprising 8 PEs. Thus, connections 306.1, 306.2 serve to mediate the operation and corresponding data flow of each grouping of 4 PEs within each port, each coupled to each local port switch. The flow of data to a particular grouping of PEs and the selection of a particular port may be performed according to any suitable technique, including known techniques. In an illustrative scenario, this may be controlled by reference to a global system clock or other suitable clock via a system on a chip (SoC), network, system, etc., of which the processing array forms part.Thus, at any particular time, one or more of the PEs may be provided with and / or access an array of data samples provided on one of the data buses to perform processing operations, the results then being provided (i.e., transmitted) on another respective data bus. In other words, any number and combination of the PEs per port may sequentially or simultaneously perform processing operations to provide an array of processed (i.e., output) data samples to another PE or data interfaces 302.1, 302.2 via any suitable data bus. The decisions as to which PEs perform the processing operations may be controlled via the operation of the switches, which may include using control signals according to any suitable technique for this, including known techniques.Data interfaces 302.1, 302.2 serve as "fabric interfaces" (fabric interfaces) to couple the processing array to other components of the architecture in which the processing array is implemented. Thus, data interfaces 302.1, 302.2 are configured to facilitate the exchange of data between the PEs of the processing array, one or more hardware components such as memory 310, hardware accelerators, an RF front end, and / or a data source. The data interfaces 302.1, 302.2 may thus be configured to provide data to the processing array configured to be processed and, when implemented as part of a transmitter, data configured to be transmitted. The data interfaces 302.1, 302.2 are configured to convert received data samples into arrays of data samples on which the processing operations are then performed via the PEs of the processing array. The data interfaces 302.1, 302.2 are also configured to reverse this process, i.e., to convert the arrays of data samples back into a block or stream of data samples, if appropriate, which are then provided to one or more hardware components such as the memory 310, hardware accelerators, an RF front end and / or a data source, etc.Data interfaces 302.1, 302.2 may represent any suitable number and / or type of data interface configured to transfer data samples between any suitable data source and other components of the device in which the processing array is implemented. Thus, data interfaces 302.1, 302.2 may be implemented as any suitable type of data interface for this purpose, such as a standardized serial interface used by data converters (ADCs and DACs) and logic devices (FPGAs or ASICs), and which may include a standard JESD-based interface and / or a chip-to-chip (C2C) interface. The data samples provided from the data source, as shown in FIG. 3, may be in a data array format or provided as streaming (i.e., serial) data bit streams. In the latter case, data interfaces 302.1, 302.2 may implement any suitable type and / or number of hardware and / or software components, digital logic, etc., to manage the translation of the streams of data bit samples into an array of data samples that are acknowledged and implemented via the processing array, and vice versa.In a scenario where the processing array is implemented as part of a wireless communication device, each of the PEs in the processing array may be coupled to the data interfaces 302.1, 302.2 via any suitable number and / or type of data connections, which may include wired buses, ports, etc. Data interfaces 302.1, 302.2 may thus be implemented as a collection of data buses that couple each port (which may represent an individual channel or a grouping of individual PEs in the processing array) to a data source via a dedicated data bus. Although not shown in detail in the figures, according to such scenarios, each data bus may be adapted for use in a digital front end (DFE) used for wireless communications, and thus the dedicated buses may include a per-port TX and RX data buses in this non-limiting scenario.The various techniques, as discussed in more detail herein, which may use SIMD instructions to perform linear interpolation on any suitable number of dimensions may be implemented with any suitable type of programmable processing array architecture. This may include the programmable processing array 300 as shown in FIG. 3, or alternatively the vector processing array architectures as shown in FIGS. 1 and 2. In any case, various techniques, as discussed in more detail herein, may be implemented according to any suitable type of application that uses data interpolation (not limited to only linear interpolation) according to any suitable predefined function that may be represented via entries stored in an addressable lookup table (LUT).The data associated with the LUT entries, as discussed in more detail herein, may also be stored in any suitable portion of the processing architecture that is implemented. In a non-limiting and illustrative scenario, the LUTs may be stored in any suitable memory accessed by the processing elements of the programmable processing array to perform the various operations as discussed herein. This memory may include the vector data memory 201, as shown in Fig. 2. For other types of programmable processing array architectures, the LUT data may be stored in any suitable type of memory accessed via the processing elements of the programmable processing array. Thus, for programmable processing array 300, as shown in FIG. 3, the LUT data entries may be stored in memory 310 accessed by the PEs via communications over data interfaces 302.1, 302.2. Alternatively, the LUTs may be stored in one or more register files that may form part of memory 310 or a separate component, not shown in FIG. 3 for brevity, which may additionally be coupled to data interfaces 302.1, 302.2 to enable the PEs to access data via read and write operations. Memory 310 may thus represent any suitable type of memory having any suitable addressable format for this purpose.Regardless of the particular architecture, the processing elements of the programmable processing architecture may perform interpolation calculations using the retrieved lookup values. The function being evaluated in this manner may form part or all of a DPD function or other suitable function that provides the desired evaluated values for a particular application. To provide an illustrative and non-limiting scenario, if the DPD function is the expression f(x)=f(|x n|) ·x n then the interpolation calculation may result in the processing elements calculating the portion f(|x n|). Continuing with this example, the processing elements may additionally calculate the overall function score f(x) by performing a multiplication of the interpolated result with the received data sample(s) associated with a particular digital data stream / s.Such functions may be implemented as part of digital signal processing operations for wireless communications, digital pre-distortion (DPD) coefficient calculations, average signal measurement calculations over time, digital signal processing of signals transmitted or received over individual antenna data streams for multiple-input multiple-output (MIMO) antenna systems, filter tap calculations, etc.It is noted that although the disclosure is described herein with respect to a programmable processing array architecture, this is a non-limiting and illustrative scenario. The techniques as described herein may be performed according to any suitable type of processing architecture including known types of processors, processor circuitry, and / or other suitable components. Moreover, although reference is made to the use of linear interpolation in this disclosure, this is also a non-limiting and illustrative scenario, and the interpolation operations as described herein may be performed according to any suitable type of linear or non-linear interpolation calculations.Overview of the Use of Linear Interpolation Look-Up TablesFIG. 4 illustrates a diagram demonstrating the use of linear interpolation from discrete values, in accordance with the disclosure. The diagram 400 represents a continuous function f(x), where x represents a real valued number. The diagram 400 defines a linear interpolation process according to a plurality of defined terms, referred to in more detail below as part of the interpolation process. The linear interpolation process is discussed in more detail below and may be implemented via a programmable processing array such as that discussed above with respect to FIG. 3.Referring to the diagram 400, the function f(x) according to Equation 1 below may be represented as follows:Referring to both Equation 1 and Diagram 400, the following are defined as follows:x represents a real valued number;Δ represents the size of a look-up table segment;N seg represents the number of look-up table segments;θ j represents the jth look-up table value; generally j ∈ [0, N seg];j sel represents the selection of the index j sel of the lower value of the segment; andrepresents the distance from the lower value.The techniques described in more detail herein may be extended to any suitable number of dimensions of linear interpolation. A 2-dimensional (2D) linear interpolation is illustrated in FIG. 5 and the accompanying diagram 500. For the diagram 500, two functions are defined according to equations 2-4 below as follows:x 1, x 2 are real valued numbers;Δ 1, Δ 2 represent the sizes of a look-up table bin in two directions;θ j1,j2 represents the look-up table value at the 2D grid position j 1, j 2selecting the index j sel of the lower value of the segment in the direction i; andrepresents the distance from the lower value in the direction i.The formulas can be extended to any N-dimensional look-up tables with linear interpolation. The data is thus retrieved from the LUT (such as from a memory via a processing element as mentioned above) and interpolated along the first dimension, and the further dimensions are then used for further interpolations.FIG. 6A illustrates a sample LUT format as a non-limiting and illustrative scenario to provide further clarity with respect to the interpolation operations as discussed herein. The LUT 600 as shown in FIG. 6A includes any suitable number of N segments 602.1-602.N, which may alternatively be referred to herein as bins. Each segment 602.1-602.N includes two entries that include a lower segment entry and an upper segment entry. Using segment 602.1 as a non-limiting and illustrative scenario, the lower segment entry comprises the evaluation of the real valued number j sel( i.e., θ[j sel]), whereas the upper segment entry comprises the evaluation of the real valued number j sel+1( i.e., θ[jsel+1]). The real valued numbers j sel and j sel+1 may be referred to herein as an upper index value (or entry) and a lower index value (or entry), respectively. For brevity, subscript "sel" may be omitted throughout the disclosure.In other words, the diagram 400 illustrates that the LUT index values j and j+1 correspond to respective real valued numbers x, which may represent the independent variables of a function, such as a continuous function. The LUT 600 also contains additional real valued numbers corresponding to the evaluation of these index values according to the function f(x). Thus, the evaluation of these real valued numbers for index values j and j+1 is shown in FIG. 4 as f(x)=θ j and θ j+1 respectively. The evaluated values θ j and θ j+1 may be referred to herein as the lower and upper segment entries, respectively, because each segment of the LUT has stored two entries in this manner. Thus, to perform the linear interpolation process, a determination is first made with respect to the upper and lower index values j and j+1 that extend over a data sample that thus identifies the range of segment entries, i.e., the lower and upper segment entries, between which the sample falls. This is represented in FIG. 4 as the value expressed in terms of a proportion of the size of the LUT segment and is a distance from the lower index value j. Once the values for the segment entries θ j and θ j+1 are obtained via the corresponding index values, the unknown value for f(x) can be calculated as shown in FIG. 4 using linear interpolation between the points (j, θ j) and (j+1, θ j+1) assuming linearity between these two points.Thus, referring now to FIG. 6A, the range of evaluated values f(x) (i.e., the segment entries) stored in each segment 602.1-602.N corresponds to the function outputs between the respective lower and upper index values j and j+1, as shown. The interpolation operation, as discussed in more detail herein, may be performed between each respective lower segment entry θ j and upper segment entry θ j+1 based on the value of x, which may be expressed as an offset value from the lower index value j with respect to a portion of the segment size Δ, as shown. In other words, the value δ is expressed with respect to the real valued number x as shown in FIG. 6A, and represents the fraction of the evaluated function f(x) within the range of values θ j and θ j+1. To provide a non-limiting and illustrative scenario for segment 602.1 as shown in FIG. 6A, the lower index value j may be sel0 while the upper index value j may be sel+11. Thus, a value x of 0.75 may represent the fraction (in this case three quarters) of the size of the segment 602.1, where the segment size Δ is 1, and a linear interpolation may then be performed to determine the value f(0.75) = θ[δ].Conventional Use of Merged SIMD Instructions to Use a 1D Table Lookup Procedure with Linear InterpolationFIG. 7 illustrates a conventional architecture for performing linear interpolation using an N vector element SIMD operation. The conventional architecture includes three computational blocks that can be identified with HW blocks that perform their respective operations. The HW blocks as shown in FIG. 7 may be implemented as the execution units 204.1 discussed above with respect to FIG. 2.With continued reference to FIG. 7, x represents a real valued number having a number N of elements, which may alternatively be referred to herein as data samples or simply samples. Thus, x may be an array of samples (such as a vector) that together form a real valued number for which a linear interpolation operation is to be performed. The architecture 700 as shown in FIG. 7 includes a dedicated index-obtained HW block 702 configured to calculate the look-up table indices j sel, j sel+1 for each sample of the array x. This may be performed using the lower index j sel as an example according to the relationship j sel= as noted above to select the lower index value of the respective segment, as Δ may be a predefined and static value based on the LUT format and the design configuration.Thus, the index-get HW block 702 may be pre-configured using knowledge of the size of each segment of the LUT. In this way, index-obtained HW block 702 may use the size Δ of the LUT segments and the value of x to calculate the lower index value j sel for each sample in array x. Once known, this index value can be used to determine the upper index value j sel+1 as well. Thus, the index-obtained HW block 702 may receive a data vector x having N samples and calculate a corresponding left index value j sel and right index value j sel+1. for each of the N samples. Again, these left and right index values may correspond to the lower and upper index values of a segment that extends across the value of the data sample, as discussed above with respect to LUT 600.From each LUT segment, the index-obtained HW block 702 also calculates, for each sample in the array x, a corresponding value δ, which in turn represents the fraction of the evaluated function f(x) within the range of values for a particular segment. Index-obtained HW block 702 may do so using the relationship as noted above, for example, where values j sel and Δ are calculated and / or known as noted above. Thus, as shown in FIG. 7, index-obtained HW block 702 also outputs an array of N data samples, each representing a corresponding value δ for each respective data sample of array x.Typically, the architecture 700 also implements further processing to provide the j sel-, j sel+1- and δ value for each respective element of the array x. This may comprise, for example, "clipping" values to fall within a certain predetermined range. An example snippet of python code, which may be implemented for arrays of data, is inserted directly below for ease of explanation. The XBAR HW block 704 may be implemented as a common random access HW block. For the present application, a suitable size may include an M-to-2N mapping block that can select any sample from the M inputs for any of the 2N outputs. The input of this block comprises the look-up table values, i.e. the segment values and index values, which corresponds to accessing M values from a LUT table of any suitable size. The XBAR HW block 704 is thus configured to map, for each of the N samples in the array x, the indices j sel, j sel+1 to corresponding upper and lower segment entries that are stored in and retrieved from the LUT. Thus, the XBAR HW block 704 is configured to fetch any suitable number of M entries included within the segments of the LUT 600, as mentioned above. The number of entries that are retrieved in this manner is typically a function of the hardware configuration in which the architecture 700 is implemented. Thus, the XBAR HW block 704 may retrieve a number of LUT entries that are used to match the index values with the index values of each respective segment of the LUT and, in turn, map the lower and upper index values j sel, j sel+1 for each segment to the respective lower and upper segment entries θ jsel, θ jsel+1 output by the XBAR HW block 704, as shown in FIG. 7.The output samples, i.e., the segment values (i.e., segment entries) θ jsel, θ jsel+1, as shown in FIG. 7, must finally be interpolated. Thus, the interpolating HW block 706 is configured to receive these values for each of the N samples in the array x, which may have a size of 2N compared to the size of the data array x, as well as the calculated δ for each sample. The interpolating HW block 706 is configured to then perform interpolation per sample, such as by the relationship of Equation 1 above, i.e.In particular, the interpolating HW block 706 is configured to receive, for each of the samples of the x array, the lower and upper index values θ jsel, θ jsel+1 associated with the lower and upper segment entries of a respective segment of the LUT, as discussed above with respect to the LUT 600. Again, for each set of lower and upper segment entries θ jsel, θ jsel+1 the interpolating HW block 706 receives a respective δ value representing the fraction of the x array element to be calculated via interpolation. The interpolating HW block 706 is configured to output a "final" interpolated function f(x) for each respective sample of the array x, which represents the linear interpolation calculation for each sample in the array x.The operations described above may be merged into a single SIMD instruction to perform a 1D table lookup with interpolation into an LUT of a maximum of 2N entries. Such a SIMD instruction may be represented as follows: wherein the 2N table values are passed as two N element vectors theta_0_to_N-1, theta_N_to_2N-1, holding the lower N and higher N elements, respectively.V. Extending the use of a 1D table lookup with SIMD instructions to handle larger tablesThe architecture as shown and discussed above with respect to FIG. 7 may use stored LUT segment entries to perform linear interpolation. However, the number of LUT segments M accessed by the XBAR HW block 704 to perform the mapping processes is limited by the architecture of the programmable processing array. Thus, for typical systems, M=2N and, therefore, the data (i.e., index values and segment entries) for only 2N segments (i.e., twice the number of data samples) of the LUT may be accessed by the XBAR HW block 704 at a time to perform the mapping process, as discussed above.However, due to the limited number of LUT segments that can be accessed in this manner, the lower and upper index values identified by the index-obtained HW block 702 may not be included within the range of the LUT segments being accessed. To provide an illustrative and non-limiting scenario, LUT 600 may include a total of 256 segments, although only 64 LUT segments may be accessed by XBAR HW block 704. Assuming that the size of each segment is 0.1, the index values for the first 64 LUT segments may cover a range of x values between 0 and 6.4. For data samples having a value greater than 6.4, the index obtained HW block 702 is unable to map the index values because the data sample is not included within the 64 segments accessed by the XBAR HW block 704. Thus, the conventional architecture 700 as described with respect to FIG. 7 is not well suited for performing interpolation with larger LUT tables.To address this issue, FIG. 8 illustrates an architecture and computational flow for performing linear interpolation using accessed table values, in accordance with the disclosure. The architecture 800 as shown in FIG. 8 includes multiple dedicated HW blocks that may operate in a similar manner to the respective HW blocks shown and discussed above with respect to the conventional architecture 700 of FIG. 7. However, and as discussed further below, the "base" implementation of the architecture 700 may be extended with limited HW cost to handle LUTs with a larger number of segments. In particular, the architecture 800 may use any suitable number of K clock cycles of throughput (K=1 for a merged instruction), which may be extended to a multi-instruction implementation where each 2N additional samples require additional K clock cycles and typically an additional instruction. However, the additional instruction may be avoided through the use of an internal state machine.Thus, architecture 800 may operate in a similar manner to architecture 700 as described above, although architecture 800 may include additional and alternative operations to accommodate the use of a larger LUT to perform linear interpolation operations in an efficient manner. The various hardware blocks as shown and discussed with respect to architecture 800 may be identified with any suitable hardware components, processing components, processing circuitry, etc. In a non-limiting and illustrative scenario, the architecture 800 may be implemented as part of a programmable processing array, such as the programmable processing array as shown and discussed herein with respect to FIG. 3, and may operate using any suitable instruction set architecture, such as the SIMD-based instruction set as discussed herein.However, the architecture 800 is not limited to such implementations and may be implemented in accordance with any suitable processor-based architecture and / or instruction sets that may include processor array architectures or non-array-based processor architectures. The hardware blocks as shown and described with respect to FIG. 8 may be identified with any suitable dedicated hardware components and collectively referred to herein as processing circuitry. The hardware blocks of architecture 800 may be identified in some non-limiting and illustrative scenarios with any suitable portion of programmable processing array 300, such as the various PEs shown and described herein. The connections between the hardware blocks of architecture 800 may be identified with any suitable number of buses, connections, wires, etc., such as data interfaces 302.1, 302.2 discussed above with respect to FIG. 3.Thus, reference is now made to FIG. 6B, which illustrates a larger LUT 650 compared to the LUT 600 as shown in FIG. 6A. The LUT 650 may have the same format as the LUT 600 as shown in FIG. 6A. That is, the LUT 650 may include any suitable number of segments 650, 652, 654, 656, 658, etc., each segment including lower and upper index values identified with an independent variable of a function, as well as respective lower and upper segment entries identified with the evaluation of the independent variables according to that function. In other words, the lower segment entry and the upper segment entry of each of the segments 602.1-602.N of the LUT 600 correspond to the result of evaluating a function using a respective lower index value and upper index value stored in each respective segment of the LUT 650, which represent an independent variable of the function.Alternatively, each segment 602.1-602.N of LUT 650, as shown in FIG. 6B, may include a single segment entry, such that duplication of entries across segments is avoided and less memory is needed. To provide an illustrative scenario, the "odd" segments 602.1, 602.3, etc. may include a lower segment entry that includes the evaluation of the real valued number j sel( i.e., θ[ jsel]) whereas the "even" segments 602.2, 602.4, etc. may include an upper segment entry that includes the evaluation of the real valued number j sel+1( i.e., θ[ jsel+1]) as discussed above with respect to FIG. 6A. In other words, the values corresponding to the evaluation of theta for each index value may be individually assigned to the segments of the LUT 650 or grouped into the various segments, the latter resulting in nearly doubling of the memory for the LUT 650 due to the repetition of the index values and the corresponding segment values. Again, the LUT 650 as shown in FIG. 6B includes a larger number of segments compared to the LUT 600 as shown in FIG. 6A. Thus, the LUT 650 may include any suitable number of segment portions each including at most a number of M segments. The LUT 650 may include a last portion of segments that is less than M, as shown in FIG. 6B. Each segment portion, such as segments 650.1-650.M, 652.1-652.M, etc., may correspond to a different range of index values and segment entries. Thus, the LUT 650 may store segments 650.1-656.P that cover an overall range of index values (i.e., lower and upper index values) and corresponding segment entries (i.e., lower and upper segment entries). The last set of segments 658.1-658.P may include a number of segments equal to (i.e., P=M) or less than (i.e., P<M) the number of segments in the other portions of the LUT 650. The portions of the LUT segments will be further referenced below with respect to the architecture 800 as shown in FIG. 8.XBAR HW block 804 may operate in a similar manner as XBAR HW block 704 discussed above with respect to architecture 700. However, the XBAR HW block 804 may repeatedly access another portion of the LUT 650 that includes a number of M segments (or less for the last portion of the LUT 650), and thus access the index values and segment entries for each of the segments in each LUT portion. It is noted that the XBAR HW block 804 may be implemented as any suitable type of selection network and the inputs may be coupled to the selection network in any suitable manner to facilitate the XBAR HW block 804 to retrieve the required data from the LUT as discussed herein. Since the segments of the LUT may include individual segment and index values or multiple segment and index values, the XBAR HW block 804 may still retrieve all data needed in both cases. However, if individual segment and index values are stored per segment, XBAR HW block 804 may retrieve M-1 segments instead of M segments.In any case, the number of M segments may include any suitable number of segments, which may be a function of the hardware and / or data path width in which the architecture 800 is implemented. Each portion of the LUT 650 accessed in this manner, i.e., each number of M segments or P segments, if any, is processed individually (i.e., portion-by-portion), and the results output by the XBAR HW block 804 are then accumulated, which is discussed in more detail below. That is, the total number of segments for a LUT may be represented as a size of K segments. Thus, the total number of sections is represented as ceil(K / (M)). If K is not a multiple of M, then the last section will have P<M segments.Index obtained HW block 802 may also function in a similar manner as index obtained HW block 702 described above. Thus, index-obtained HW block 802 may receive a number of N data samples that form part of an array x. Index-obtained HW block 802 may then determine, for each data sample, a corresponding lower index value j sel-2 N*iand a corresponding upper index value j sel+1-2 N*icorresponding to a respective segment of the portion of LUT 650 that extends across the value of each determined data sample. The index-obtained HW block 802 may also output a corresponding value δ for each data sample, which in turn represents the fraction of the evaluated function f(x) within the range of values for a particular segment.This process of determining the lower and upper index values and the corresponding value δ may be performed in the same manner as discussed above for the index-obtained HW block 702. However, the notation "2N*i" is provided with respect to the current iteration and the portion of the LUT 650 processed by the XBAR HW block 804, and is provided for ease of explanation, as will be referred to in more detail below as part of the pseudo code.Thus, and as mentioned above with respect to architecture 700, XBAR HW block 804 is configured to map each of the data samples in array x to a corresponding LUT lower segment entry and upper segment entry (i.e., the θ mapped values as shown in FIG. 8). To do so, the XBAR HW block 804 determines, for each of the data samples, the lower segment entry θ[j sel] and the upper segment entry θ[j sel+1] based on the corresponding lower index value j sel and upper index value j sel+1 of a respective segment of the LUT 650 that extend over a range within which the data sample falls.However, for a given array x of data samples, the corresponding indices j and j+1 may correspond to different segments of the LUT 650, and these different segments may extend over different portions of the LUT 650 than those currently accessed by the XBAR HW block 804. Thus, when the XBAR HW block 804 operates based on the instruction on a portion of segments of the LUT 650, each index j and j+1 generated by the index obtaining block 802 may or may not be included within this particular range of segments. It should be noted that XBAR HW block 804 is only capable of mapping the data samples to the correct corresponding segment entries (i.e., lower and upper segment entries) if the data sample value is within the range of lower and upper index values for one of the segments in the current portion of LUT 650. Otherwise, the XBAR HW block 804 calculates any (i.e., invalid) values when the data sample is outside the range of any of the segments of the portion of the LUT currently being processed.Thus, for each iteration (i.e., each portion of the M segments of LUT 650 being processed at any time), XBAR HW block 804 may map each of the data samples in the array to corresponding segment entries, but only a portion of these data samples may be within the range of segments covered by the currently processed portion of LUT 650. Thus, for each iteration, i.e., for each portion of the LUT 650 that the XBAR HW block 804 uses to perform the mapping function, only a portion of the samples may be mapped correctly (i.e., valid) to lower and upper segment entries.Therefore, index-obtained HW block 802 also calculates a set of validity indicators for each sample in array x mapped to a corresponding lower segment entry and upper segment entry of a respective segment in the LUT. The set of validity indicators may include a number 2N (i.e., one per calculated index value per sample in the data array) of samples, each representing a binary indication of whether the corresponding lower index value and upper index value are valid. The validity indicator may indicate validity when a data sample is spanned by a lower index value and upper index value of the respective segment in the LUT, and otherwise indicate that the resulting mapped(s) lower(n) segment entry and upper segment entries are invalid. The set of validity indicators may thus be used by the combine HW block 705 to accumulate the correctly mapped (i.e., valid) segment values for each of the data samples in the array x while iteratively traversing all portions of the LUT.In other words, the XBAR HW block 804 performs an initial mapping of the samples in the array x onto a first portion of the LUT 650, which may include a first number M of segments. The XBAR HW block 804 may then output the mapped lower and upper segment entries for each data sample in the array x using the range of values covered by the first M segments. Some of these mapped values may be valid while others may be invalid, and thus the combine HW block 705 uses the set of validity indicators to store and maintain (i.e., not subsequently overwrite) the valid mapped lower and upper segment entries, at an appropriate storage location, which may include the memory 310, a register file, etc.During each subsequent iteration, the XBAR HW block 804 outputs the mapped lower and upper segment entries for each data sample in the array x using the range of values covered by the second M segments, the third M segments, and so forth. After each iteration, the combine HW block 705 stores the valid mapped lower and upper segment entries for each data sample (i.e., θ mapped as shown in FIG. 8 ), while in subsequent iterations, previously stored mapped values that were invalid are overwritten with valid mapped values. Thus, the combine HW block 705 is configured to store, after each iteration, a corresponding lower segment entry and upper segment entry for each of the data samples for that specific portion of the LUT that are valid based on the set of validity indicators. Moreover, by referring to the set of validity indicators after each iteration, the combine HW block 705 also maintains previously stored valid mapped values when subsequently mapped values are identified as invalid while previously stored invalid entries are overwritten with valid. Thus, the "loop" of storing valid mapped segment entries and overwriting previously identified invalid mapped segment entries with valid maps (i.e., valid maps of θ[j sel], θ[j sel+1]) continues until all portions of LUT 650 have been processed by XBAR HW block 804.In this manner, upon iterative processing of each portion of the LUT 650, the combine HW block 805 obtains valid mapped lower and upper segment entries for each data sample in the array x. In other words, upon completion of all iterations, i.e., all portions of the LUT 650 being processed, the combine HW block 805 is configured to provide a corresponding lower segment entry and upper segment entry for each of the data samples in the array x as a result of combining the valid mapped data samples from each iteration. Thus, due to the iterative nature of the XBAR HW block 804 and the combine HW block 805, the entire set of valid mapped lower and upper segments is output from the LUT 650 for each of the data samples in the array x by the combine HW block 805 at the final portion of the LUT 650 being processed.At this time, the interpolating HW block 806 is able to perform the linear interpolation operation for each data sample in the array x, because each data sample now has a valid mapped lower and upper segment value and a corresponding value δ. The interpolate HW block 806 is therefore configured to receive a control signal indicated as the "final LUT segment processor indicator" in FIG. 8. The control signal may represent a binary identifier that indicates whether the current portion of the LUT 650 processed by the XBAR HW block 804 includes the last portion of segments, i.e., the final portion of the LUT 650 processed by the XBAR HW block 804. In other words, the interpolating HW block 806 is configured to perform the linear interpolation operation in response to receiving the control signal indicating that the portion of the LUT 650 used to map the data samples of the array x includes the last segment of the LUT 650.This control signal may be generated by any suitable component, such as a processor, an ASIC, one of the PEs of the programmable processing array, etc., within which the architecture 800 forms a part and has knowledge of the operations performed by the programmable processing array. Thus, the control signal, when activated, identifies to the interpolate HW block 806 that each mapped segment entry is now valid, and the interpolate HW block 806 performs only the linear interpolation operations, if so. Otherwise, the interpolate HW block 806 may be disabled and / or inactive and not perform operations on the 2N data samples received at its input.As noted above for architecture 700, architecture 800 may also be implemented as part of a SIMD processor-based architecture, and thus perform the operations as described herein based on a merged SIMD instruction having any suitable format and / or number of fields. That is, the merged SIMD instruction may instruct each of the index-get HW block 802, the XBAR HW block 804, the combine HW block 805, and the interpolate HW block 806 to perform their respective operations as discussed herein. This may include XBAR HW block 804 repeatedly mapping the data samples to segment values of different portions of LUT 650, combining HW block 805 combining the valid mapped segments from each of the iterations, interpolating HW block 806 performing the linear interpolation operations, etc.Thus, the pseudo code of the overall process with reference to the "i" indices as shown in Figure 8 may be provided as follows: Thus, for a SIMD-based processor architecture, as a non-limiting and illustrative scenario, the SIMD instructions may be implemented as follows: Again, due to the use of the control signal, the instruction updates the theta_selected (i.e., theta mapped values) each time for a new segment, and the final interpolated value f is valid only once all segments are processed.The theta_selected values (i.e., the mapped theta values) may be submitted to the instruction as above or maintained within the HW as an internal state variable. It is also noted that passing the index and LUT segment values may be handled by internal states and a state machine performing the entire iterative procedure as described above.Multi-dimensional look-up tables with interpolationThe iterative process described above with respect to linear interpolation of data samples of an array x is with respect to one-dimensional linear interpolation. In other words, the segment entries of LUT 650 correspond to the evaluation of a single function f(x). However, this is not limiting and provided as an illustrative scenario for ease of explanation. Given the use of processing portions of the larger LUT 650 in an iterative manner, the architecture 800 is well suited for performing linear interpolation using larger LUTs, and this concept can be exploited to extend the linear interpolation to any suitable number of additional dimensions. Thus, it is noted that since a multi-dimensional LUT is likely to have a larger number of segments, the truncated LUT access as described above may be particularly useful for multi-dimensional linear interpolation, although multi-dimensional linear interpolation may also be performed in a single iteration in other alternative implementations.In either case, the LUT 650 may be extended to store segment entries and corresponding index values for additional functions to be evaluated, i.e., one function per interpolation dimension. Such an LUT may be referred to herein as a multi-dimensional LUT, and the architecture 800 as described herein may implement such a multi-dimensional LUT to perform linear interpolation using any suitable number of 1D LUT functions. In other words, the data samples forming part of array x may be from any suitable number of data arrays, with architecture 800 performing linear interpolation as mentioned above on each of the data arrays as part of a multi-dimensional interpolation operation. To do so, the same components of the architecture 800 as described above may be implemented, with some extensions as described in more detail below.Again, as described above with respect to FIG. 6B, each segment of the LUT 650 may include individually assigned index and segment entry values or a set of such values (e.g., the upper and lower index values and corresponding segment entries). Moreover, in any event, a multi-dimensional function may be represented by corresponding multi-dimensional LUT values included in such LUT as represented. If the number of points along each of the multiple dimensions is represented as K 1, K 2,..., etc., then the LUT 650 may be accessed segments per K dimension as a number of 1D-sized arrays having a size of K=K1*K2*...speichern which may then be accessed via the portions of segments of size M as described above.However, if each segment includes upper and lower index values and corresponding segment entries, the segments defined along the last dimension become K-1 segments. In this case, the boundaries of the multi-dimensional arrays have segments that contain the segment entries for different parts (i.e., different dimensions) and thus must be corrected. Thus, it may be particularly advantageous to implement the single index value and the corresponding segment value per segment format for the 1D arrays when implementing a multi-dimensional LUT, as this results in a memory saving while reducing the complexity of the interpolation calculations. For this implementation, a notation called a dot representation is used.Thus, in extending the process described above to multi-dimensional linear interpolation scenarios, each of the N-dimensional indices may be calculated and then converted to equivalent 1D indices. That is, an index in a multi-dimensional array may be converted into a linear index. To provide a non-limiting and illustrative scenario, for a 2D index j 1 based on x 1 and j 2 based on x 2, where j 1 is in the range 0,.., N_ seg_D 1- 1 and j 2 is in the range 0,..., N_ seg_D 2- 1, the linear index may be calculated as:The range of the linear index j_lin is 0,..., N_seg_D1*N_seg_D2-1.Thus, using the dot representation for ease of explanation, the linear index for the second dimension may be calculated as:j_lin=j1*K2+j2 where K2 is the number of points in dimension 2, and so on.For the multidimensional linear interpolation scenario, 2^N_dimensional points must be retrieved per iteration. Thus, for the 2D case, 4 theta values (i.e., 4 mapped segment values, a lower and upper segment value for each data sample x) are needed to perform the interpolation of the first dimension according to Equations 5 and 6 below as follows:This yields 4 linear index values, 2 for the first interpolation: and 2 for the second interpolation:The architecture 800 as discussed above may be implemented to perform these equivalent 1D lookups and interpolations along the second dimension. The indices may be calculated in a dedicated HW block as part of the operation of the index-obtained HW block 802, or alternatively, externally by regular processor instructions.Finally, the final step for the 2D linear interpolation LUT is interpolation between the first interpolated values according to Equation 7 below as follows:This operation may be performed by the interpolating HW block 806.Alternatively, the calculation of the multi-dimensional translation into a linear table may include the calculation of an equivalent 1D-xvalue as follows:Using these two values and the corresponding 2D LUT portion, the original instruction may be used to retrieve the data that would be used to perform the first interpolation. That is, the portions of the first dimension LUT may be accessed in a similar manner as described above for the case of a single dimension, i.e., by iteratively processing each portion of the first dimension LUT 650. However, instead of performing the interpolation, this process may then be repeated for the second dimensions as well as any other dimensions. Thus, at the end of the processing iterations for each dimension, each of the valid theta mapped values is stored in an appropriate location, such as one or more register files. After this iterative process is completed for each dimension, the interpolating HW block 806 may then perform the final multi-dimensional interpolation according to Equation 7 above.VII. AN ELECTRONIC DEVICEFIG. 9 illustrates an example device according to the present disclosure. The device 900 may be identified with one or more devices implementing a programmable processing array architecture to perform processing operations, such as the programmable processing array 300 as shown and discussed herein with reference to FIG. 3. The device 900 may be identified with a wireless device, a user equipment (UE), or other suitable device configured to perform wireless communications, such as a mobile phone, a laptop computer, a cellular base station, a tablet, etc., which may include one or more components configured to transmit and receive radio signals. The programmable processing array 300 as discussed herein, by its operation as discussed herein, may facilitate the execution of any suitable number and / or type of processing operations that may be used as part of the transmission and / or reception of wireless signals via the electronic device 900. Thus, the processing operations may include any suitable type of digital signal processing according to wirelessly transmitted and / or received data, which may include filter processing, digital front-end (DFE) processing, etc. Alternatively, the device 900 may be identified with a graphics processing unit (GPU) that may perform graphics processing on streams of graphics data.As will be discussed further below, the device 900 may perform the functions as discussed herein with respect to the programmable processing array 300 as shown and discussed herein with reference to FIG. 3. The apparatus 900 may perform processing operations by receiving processor instructions, such as SIMD instructions, with any suitable number of fields. These processing operations may be performed to receive data samples and output the result of performing data processing on the sets of data samples. To do so, the device 900 may include one or more processors 902, a transceiver 904, a programmable processing array architecture 906, and a memory 908. The components shown in FIG. 9 are provided for simplicity of explanation, and the apparatus 900 may implement additional, fewer, or alternative components than those shown in FIG. 9. In one scenario, transceiver 904 may be omitted when device 900 is implemented as a GPU.The processor(s) 902 may be formed as any suitable number and / or type of computer processors that may function to control the device 900 and / or other components of the device 900. Processor(s) 902 may / may be identified with one or more processors (or suitable portions thereof) implemented by device 900. The processor(s) 902 may / may be identified with one or more processors, such as a host processor, a digital signal processor, one or more microprocessors, graphics processors, baseband processors, microcontrollers, an application-specific integrated circuit (ASIC), a portion (or the entirety) of a field programmable gate array (FPGA), etc.In any case, the processor(s) 902 may be configured to execute instructions to perform arithmetic, logical, and / or input / output (I / O) operations and / or to control operation of one or more components of the device 900 to perform various functions, as described herein. The processor(s) 902 may include one or more microprocessor cores, memory registers, buffers, clocks, etc., and may / may generate electronic control signals associated with the components of the device 900 to control and / or modify the operation of these components. The processor(s) 902 may communicate with and / or control functions associated with the transceiver 904, the programmable processing array architecture 906, and / or the memory 908.The transceiver 904 (if present) may be implemented as any suitable number and / or type of components configured to transmit and / or receive data (such as data packets) and / or wireless signals in accordance with any suitable number and / or type of communication protocols. Transceiver 904 may include any suitable type of components to enable this functionality, including components associated with known transceiver, transmitter, and / or receiver operations, configurations, and implementations. Although depicted as a transceiver in FIG. 9, transceiver 904 may include any suitable number of transmitters, receivers, or combinations thereof, which may be integrated into a single transceiver or as multiple transceivers or transceiver modules. The transceiver 904 may include components typically identified with an RF front end, and include antennas, ports, power amplifiers (PAs), RF filters, mixers, local oscillators (LOs), low noise amplifiers (LNAs), up converters, down converters, channel tuners, etc.Thus, the transceiver 904 may be configured as any suitable number and / or type of components configured to enable the reception and / or transmission of data and / or signals in accordance with one or more communication protocols. The transceiver 904 may be implemented as any number and / or type of components to support wireless communication, such as analog-to-digital converters (ADCs), digital-to-analog converters, intermediate frequency (IF) amplifiers and / or filters, modulators, demodulators, baseband processors, etc. The linear interpolation operations as discussed herein may be part of the digital signal processing operations implemented by the apparatus 900 to facilitate the transceiver 904 transmitting data that has undergone such processing operations. These processing operations may include, as various non-limiting and illustrative scenarios, digital pre-distortion (DPD) coefficient calculations, average signal measurement calculations over time, digital signal processing of signals transmitted or received over individual antenna data streams for multiple-input multiple-output (MIMO) antenna systems, filter tap calculations, etc. Thus, the data received via the transceiver 904 (e.g., wireless signal data streams), data provided to the transceiver 904 for transmission (e.g., data streams for transmission), and / or data used in connection with the transmission and / or reception of data via the transceiver 904 (e.g., digital filter coefficients, digital pre-distortion (DPD) terms, etc.) may be processed as data streams via the programmable processing array architecture 906 as part of its processing operations as discussed herein.Thus, programmable processing array architecture 906 may be identified with programmable processing array 300 as well as programmable processing array architecture 800 as shown and described herein with reference to FIGS. 3 and 8. In this manner, transceiver 904 may be configured to transmit and / or receive data signals based on digital signal processing operations performed via programmable processing array architecture 800, which in turn may be identified with programmable processing array architecture 906.The memory 908 is configured to store data and / or instructions such that, when the instructions are executed by the processor(s) 902, the device 900 is caused to perform various functions as described herein with respect to the programmable processing array architecture 906, such as controlling, monitoring, and / or regulating the flow of data through the programmable processing array architecture 906. The memory 908 may be implemented as any suitable volatile and / or nonvolatile memory including read-only memory (ROM), random access memory (RAM), flash memory, a magnetic storage medium, an optical disk, erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), etc. The memory 908 may be non-removable, removable, or a combination of both. For example, the memory 908 may be implemented as a non-transitory computer readable medium storing one or more executable instructions, such as logic, algorithms, code, etc.As will be discussed further below, the instructions, logic, code, etc. stored in the memory 908 are represented by the various modules as shown, which may enable the functionality disclosed herein to be functionally realized. Alternatively, the modules as shown in FIG. 9 associated with the memory 908 may include instructions and / or code to enable control and / or monitoring of operation of hardware components implemented via the device 900. In other words, the modules shown in FIG. 9 are provided for ease of explanation with respect to functional mapping between hardware and software components for the sake of simplicity. Thus, the processor(s) 902 may execute the instructions stored in these respective modules, in conjunction with one or more hardware components, for performing the various functions as discussed herein.The processing control engine 910 may represent the functionality described herein, as discussed with respect to controlling and / or monitoring the programmable processing array architecture 906. The processing control engine 910 may represent program memory (and stored instruction sets), decoder, and / or memory, as discussed herein with reference to FIG. 3, and may alternatively or additionally include any suitable number of register files. Additionally or alternatively, one or more of the program memory, decoder, and / or register files may form a portion of the processor / s 902, memory 908, programmable processing array architecture 906, or separate components not shown in FIG. 9.The executable instructions stored in the instruction management module 911, in conjunction with execution via the processor(s) 902 of the device 900, may facilitate receiving and decoding processor instructions (which may be sent via the processor(s) 902 or other suitable component of the device 900 or a component external to the device 900) and providing data samples to the programmable processing array architecture 906.This may include determining each specific processor instruction to perform specific types of processing operations, such as the processing operations discussed herein that are executed by the architecture 800 to perform linear interpolation of data samples, and / or any of the functionalities discussed herein with respect to the programmable processing array 300, such as reading data samples from and writing data samples to memory and / or register files, generating processor instructions and / or control signals, the computations identified with different processing operations, etc.The executable instructions stored in the processing data management module 913, in conjunction with execution via the processor / s) 902, may facilitate determining when the calculated results of interpolation operations are complete and when to store those results. This may include writing the results to one or more register files to be used by the appropriate components of device 900 or other suitable device.VIII. A Process FlowFIG. 10 illustrates a process flow. Referring to FIG. 10, the process flow 1000 may be performed by and / or otherwise associated with processing circuitry and / or memory devices. These processors and / or storage devices may be associated with one or more components of the programmable processing array 300, one or more components of the architecture 800, and / or one or more components of the device 900, as discussed herein. To provide an illustrative and non-limiting scenario, the process flow 1000 may be performed via the dedicated HW blocks of the architecture 800 as discussed in more detail herein with respect to FIG. 8. Additionally or alternatively, the processors and / or memory devices may be identified with the one or more PEs of the programmable processing array 300 and / or the processing circuitry 902 as discussed above. The flow 1000 may include alternative or additional steps, not shown in FIG. 10 for brevity, and may be performed in a different order than the steps shown in FIG. 10.The flow 1000 may begin by receiving (block 1002) one or more instructions. These instructions may be received in a non-limiting and illustrative scenario as a merged SIMD instruction having any suitable number of fields and / or format as discussed herein. The merged SIMD instruction may include the data that instructs each dedicated HW block to perform the various functions as discussed herein, which may additionally or alternatively form part of the process flow 1000.The flow 1000 may include receiving (block 1004) an array of data samples that may form part of an array x, as discussed above with respect to FIG. 8.The process 1000 may include computing (block 1006), for each data sample in the array, a corresponding lower and upper index value j, as discussed above with respect to FIG. 8.The flow 1000 may include mapping (block 1008), for each data sample and for a portion of segments of the LUT, each lower and upper index value to a corresponding lower and upper segment entry of the portion of the LUT. This may include, in a non-limiting and illustrative scenario, the operations performed by the XBAR HW block 804 as shown and discussed above with respect to FIG. 8.The flow 1000 may include one or more processors that store (block 1010) the valid mapped segment values for the currently processed portion of the LUT at an appropriate storage location, such as one or more register files. This may include, in a non-limiting and illustrative scenario, the operations performed by the combine HW block 805 as shown and discussed above with respect to FIG. 8.The flow 1000 may include one or more processors that determine (block 1012) whether the last portion of the LUT has been processed. This may include, in a non-limiting and illustrative scenario, the interpolating HW block 806 determining whether it is based on the received control signal as shown and discussed above with respect to FIG. 8. If not, then the process flow 1000 may include mapping (block 1008) the lower and upper index values to corresponding segment values included in segments of the next portion of the LUT. However, if the last portion of the LUT has been processed (i.e., the last segments), then it is assumed that all currently mapped segment values are now valid, and thus the linear interpolation operation is performed on the data array (block 1014) using the mapped upper and lower segment values for each data sample as well as the corresponding δ value, as shown and discussed above with respect to FIG. 8.IX. General Operation of a Programmable Processor ArrayA programmable processing array is provided. The programmable processing array includes a memory configured to store a plurality of segments identified with a look-up table (LUT); and processing circuitry configured to: for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly map each of a received plurality of data samples for additional portions of the LUT, thereby mapping each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, that are stored in a respective segment of the LUT and that represent an independent variable of the function. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to determine, for each of the plurality of data samples, a respective upper index value and lower index value of a respective segment of the portion of the LUT that extends over the value of the respective data sample. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array includes a last segment of the plurality of segments identified with the LUT. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to determine whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators that indicate a binary indication for each of the plurality of data samples. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to provide a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the processing circuitry is configured to repeatedly map the plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the plurality of data samples is part of a data array originating from a plurality of data arrays, and the processing circuitry is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.X. General Operation of a Wireless DeviceA wireless device is provided. The wireless device includes a programmable processing array configured to: store a plurality of segments identified with a look-up table (LUT); and for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly map each of a received plurality of data samples for additional portions of the LUT, thereby mapping each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries; and a transceiver configured to transmit data processed based on the linear interpolation operation. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, that are stored in a respective segment of the LUT and that represent an independent variable of the function. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to determine, for each of the plurality of data samples, a respective upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array includes a last segment of the plurality of segments identified with the LUT. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to determine whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the plurality of data samples. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to provide a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the programmable processing array is configured to repeatedly map the plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction. Additionally or alternatively to, and in any combination with the optional features discussed above in this paragraph, the plurality of data samples is part of a data array originating from a plurality of data arrays, and the programmable processing array is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.ExamplesThe following examples relate to further aspects.An example (e.g., example 1) is directed to a programmable processing array, comprising: a memory configured to store a plurality of segments identified with a look-up table (LUT); and processing circuitry configured to: for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly mapping each of a received plurality of data samples for additional portions of the LUT to thereby map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries.Another example (e.g., Example 2) is directed to a previously described example (e.g., Example 1), wherein the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, that are stored in a respective segment of the LUT and that represent an independent variable of the function.Another example (e.g., Example 3) is directed to a previously described example (e.g., one or more of Examples 1-2), wherein the processing circuitry is configured to determine, for each of the plurality of data samples, a corresponding upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.Another example (e.g., Example 4) is directed to a previously described example (e.g., one or more of Examples 1-3), wherein the processing circuitry is configured to map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.Another example (e.g., example 5) is directed to a previously described example (e.g., one or more of examples 1-4), wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.Another example (e.g., example 6) is directed to a previously described example (e.g., one or more of examples 1-5), wherein the processing circuitry is configured to determine whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the plurality of data samples.Another example (e.g., example 7) is directed to a previously described example (e.g., one or more of examples 1-6), wherein the processing circuitry is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators.Another example (e.g., example 8) is directed to a previously described example (e.g., one or more of examples 1-7), wherein the processing circuitry is configured to provide a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration.Another example (e.g., example 9) is directed to a previously described example (e.g., one or more of examples 1-8), wherein the processing circuitry is configured to repeatedly map the plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.Another example (e.g., example 10) is directed to a previously described example (e.g., one or more of examples 1-9) where the plurality of data samples is part of a data array originating from a plurality of data arrays, and where the processing circuitry is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.An example (e.g., example 11) is directed to a wireless device, comprising: a programmable processing array configured to: store a plurality of segments identified with a look-up table (LUT); and for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly map each of a received plurality of data samples for additional portions of the LUT, thereby mapping each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries; and a transceiver configured to transmit data processed based on the linear interpolation operation.Another example (e.g., example 12) is directed to a previously described example (e.g., example 11) wherein the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, stored in a respective segment of the LUT and representing an independent variable of the function.Another example (e.g., example 13) is directed to a previously described example (e.g., one or more of examples 11-12), wherein the programmable processing array is configured to determine, for each of the plurality of data samples, a corresponding upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.Another example (e.g., example 14) is directed to a previously described example (e.g., one or more of examples 11-13), wherein the programmable processing array is configured to map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.Another example (e.g., example 15) is directed to a previously described example (e.g., one or more of examples 11-14) wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.Another example (e.g., example 16) is directed to a previously described example (e.g., one or more of examples 11-15), wherein the programmable processing array is configured to determine whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the plurality of data samples.Another example (e.g., example 17) is directed to a previously described example (e.g., one or more of examples 11-16), wherein the programmable processing array is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators.Another example (e.g., example 18) is directed to a previously described example (e.g., one or more of examples 11-17), wherein the programmable processing array is configured to provide a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration.Another example (e.g., example 19) is directed to a previously described example (e.g., one or more of examples 11-18), wherein the programmable processing array is configured to repeatedly map the plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.Another example (e.g., example 20) is directed to a previously described example (e.g., one or more of examples 11-19), wherein the plurality of data samples is part of a data array originating from a plurality of data arrays, and wherein the programmable processing array is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.An example (e.g., example 21) is directed to a programmable processing array, comprising: a memory configured to store a plurality of segments identified with a look-up table (LUT); and processing means for: for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, mapping the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly mapping each of a received plurality of data samples for additional portions of the LUT to thereby map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries.Another example (e.g., example 22) is directed to a previously described example (e.g., example 21) where the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, stored in a respective segment of the LUT and representing an independent variable of the function.Another example (e.g., example 23) is directed to a previously described example (e.g., one or more of examples 21-22), wherein the processing means determines, for each of the plurality of data samples, a corresponding upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.Another example (e.g., example 24) is directed to a previously described example (e.g., one or more of examples 21-23), wherein the processing means maps each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.Another example (e.g., example 25) is directed to a previously described example (e.g., one or more of examples 21-24), wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.Another example (e.g., example 26) is directed to a previously described example (e.g., one or more of examples 21-25), wherein the processing means determines whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the plurality of data samples.Another example (e.g., example 27) is directed to a previously described example (e.g., one or more of examples 21-26), wherein after each iteration, the processing means stores a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators.Another example (e.g., example 28) is directed to a previously described example (e.g., one or more of examples 21-27), wherein the processing means provides a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration.Another example (e.g., example 29) is directed to a previously described example (e.g., one or more of examples 21-28), wherein the processing means repeatedly maps the plurality of data samples and performs the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.Another example (e.g., example 30) is directed to a previously described example (e.g., one or more of examples 21-29), wherein the plurality of data samples is part of a data array originating from a plurality of data arrays, and wherein the processing means performs the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.An example (e.g., Example 31) is directed to a wireless device, comprising: a programmable processing array configured to: store a plurality of segments identified with a look-up table (LUT); and for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly map each of a received plurality of data samples for additional portions of the LUT, thereby mapping each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries; and a transceiver means for transmitting data processed based on the linear interpolation operation.Another example (e.g., example 32) is directed to a previously described example (e.g., example 31) where the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, stored in a respective segment of the LUT and representing an independent variable of the function.Another example (e.g., example 33) is directed to a previously described example (e.g., one or more of examples 31-32), wherein the programmable processing array is configured to determine, for each of the plurality of data samples, a corresponding upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.Another example (e.g., example 34) is directed to a previously described example (e.g., one or more of examples 31-33), wherein the programmable processing array is configured to map each of the plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.Another example (e.g., example 35) is directed to a previously described example (e.g., one or more of examples 31-34), wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.Another example (e.g., example 36) is directed to a previously described example (e.g., one or more of examples 31-35), wherein the programmable processing array is configured to determine whether each of the plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the plurality of data samples.Another example (e.g., example 37) is directed to a previously described example (e.g., one or more of examples 31-36), wherein the programmable processing array is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the plurality of data samples for the portion of the LUT based on the set of validity indicators.Another example (e.g., example 38) is directed to a previously described example (e.g., one or more of examples 31-37), wherein the programmable processing array is configured to provide a corresponding upper segment entry and a lower segment entry of each of the plurality of data samples to the LUT by combining the mapped data samples from each iteration.Another example (e.g., example 39) is directed to a previously described example (e.g., one or more of examples 31-38), wherein the programmable processing array is configured to repeatedly map the plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.Another example (e.g., example 40) is directed to a previously described example (e.g., one or more of examples 31-39), wherein the plurality of data samples is part of a data array originating from a plurality of data arrays, and wherein the programmable processing array is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.An apparatus as shown and described.A method as shown and described.SummaryThe foregoing description of the specific aspects will fully disclose the general spirit of the disclosure such that others, by applying knowledge within the art, may readily modify and / or adapt such specific aspects for various applications without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed aspects based on the teachings and instructions set forth herein. It is to be understood that the terminology or terminology herein is for the purpose of description and not of limitation, and therefore the terminology or terminology of the present description is to be interpreted in the light of the teachings and instructions by one skilled in the art.References in the specification to "one aspect", "a single aspect", "an example aspect", etc., indicate that the described aspect may include a particular feature, structure, or characteristic, but each aspect does not necessarily include the particular feature, structure, or characteristic. Further, such phrases are not necessarily referring to the same aspect. Further, when a particular feature, structure, or characteristic is described in connection with an aspect, it is disclosed that it is within the knowledge of one skilled in the art to perform such feature, structure, or characteristic in connection with other aspects whether or not expressly described.The example aspects described herein are provided for illustrative purposes and are not limiting. Other example aspects are possible, and modifications may be made to the example aspects. Therefore, the description is not intended to limit the disclosure. Rather, the scope of the disclosure is defined only in accordance with the following claims and their equivalents.Aspects may be implemented in hardware (e.g., circuitry), firmware, software, or any combination thereof. Aspects may also be implemented as instructions stored on a machine readable medium that may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM), random access memory (RAM), magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other types of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, and instructions may be described herein as executing certain actions. It should be understood, however, that such descriptions are for clarity only and that such acts are actually taken from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc. Further, any of the implementation variants may be executed by a general purpose computer.For purposes of this discussion, the term "processing circuitry" or "processor circuitry" is to be understood as being one or more circuit(s), processor(s), logic, or a combination thereof. For example, a circuit may include analog circuitry, digital circuitry, state machine logic, other structural electronic hardware, or a combination thereof. A processor may include a microprocessor, a digital signal processor (DSP), or another hardware processor. The processor may be "hard-coded" with instructions to perform one or more corresponding function(s) according to aspects described herein. Alternatively, the processor may access internal and / or external memory to fetch instructions stored in the memory that, when executed by the processor, execute the corresponding function(s) associated with the processor and / or one or more functions and / or operations related to operation of a component having the processor included therein.In one or more of the example aspects described herein, processing circuitry may include memory storing data and / or instructions. The memory may be any known volatile and / or nonvolatile memory including, for example, read-only memory (ROM), random access memory (RAM), flash memory, a magnetic storage medium, an optical disk, erasable programmable read-only memory (EPROM), and programmable read-only memory (PROM). The memory may not be removable, removable, or a combination of both.

Claims

A programmable processing array comprising: a memory configured to store a plurality of segments identified with a look-up table (LUT); and processing means for: for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, mapping the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly mapping each of the received plurality of data samples to additional portions of the LUT, thereby mapping each of the received plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the received plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries.The programmable processing array of claim 1, wherein the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, stored in a respective segment of the LUT and representing an independent variable of the function.The programmable processing array of claim 1 or claim 2, wherein the processing means determines, for each of the received plurality of data samples, a respective upper index value and lower index value of a respective segment of the portion of the LUT that extends over the value of the respective data sample.The programmable processing array of claim 3, wherein the processing means maps each of the received plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the received plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.The programmable processing array of any of claims 1-4, wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.The programmable processing array of any of claims 1-5, wherein the processing means determines whether each of the received plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the received plurality of data samples whether each data sample is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT.The programmable processing array of claim 6, wherein the processing means stores, after each iteration, a corresponding upper segment entry and lower segment entry of each of the received plurality of data samples for the portion of the LUT based on the set of validity indicators.The programmable processing array of claim 7, wherein the processing means provides a corresponding upper segment entry and a lower segment entry of each of the received plurality of data samples to the LUT by combining the mapped data samples from each iteration.The programmable processing array of any of claims 1-8, wherein the processing means repeatedly maps the received plurality of data samples and performs the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.The programmable processing array according to any of claims 1-9, wherein the received plurality of data samples is part of a data array originating from a plurality of data arrays, and wherein the processing means performs the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.A wireless device, comprising: a programmable processing array configured to: store a plurality of segments identified with a look-up table (LUT); and for each of a received plurality of data samples having a value that is within a range of values stored in segments of a portion of the LUT, map the data sample to an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT that extends across the data sample; repeatedly map each of the received plurality of data samples for additional portions of the LUT, thereby mapping each of the received plurality of data samples to a corresponding upper segment entry and a lower segment entry of a respective segment in the LUT; and performing, for each of the received plurality of data samples, a linear interpolation operation based on the respective upper segment entries and lower segment entries; and a transceiver configured to transmit data processed based on the linear interpolation operation.The wireless device of claim 11, wherein the upper segment entry and the lower segment entry of each of the segments of the LUT correspond to a result of evaluating a function using a corresponding upper index value and lower index value, respectively, that are stored in a respective segment of the LUT and that represent an independent variable of the function.The wireless device of claim 11 or claim 12, wherein the programmable processing array is configured to determine, for each of the received plurality of data samples, a corresponding upper index value and lower index value of a respective segment of the portion of the LUT that extends across the value of the respective data sample.The wireless device of claim 13, wherein the programmable processing array is configured to map each of the received plurality of data samples to a corresponding upper segment entry and a lower segment entry of the LUT by determining, for each of the received plurality of data samples, the upper segment entry and the lower segment entry based on the corresponding upper index value and lower index value of each respective segment of the LUT.The wireless device of any of claims 11-14, wherein the linear interpolation operation is performed in response to receiving a control signal indicating that the portion of the LUT used to map the data samples of the array comprises a last segment of the plurality of segments identified with the LUT.The wireless device of any of claims 11-15, wherein the programmable processing array is configured to determine whether each of the received plurality of data samples is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT based on a set of validity indicators indicating a binary indication for each of the received plurality of data samples whether each data sample is spanned by an upper segment entry and a lower segment entry of a respective segment in the portion of the LUT.The wireless device of claim 16, wherein the programmable processing array is configured to store, after each iteration, a corresponding upper segment entry and lower segment entry of each of the received plurality of data samples for the portion of the LUT based on the set of validity indicators.The wireless device of claim 17, wherein the programmable processing array is configured to provide a corresponding upper segment entry and a lower segment entry of each of the received plurality of data samples to the LUT by combining the mapped data samples from each iteration.The wireless device of any of claims 11-18, wherein the programmable processing array is configured to repeatedly map the received plurality of data samples and perform the linear interpolation operation based on receiving a single instruction stream, multiple data stream (SIMD) instruction.The wireless device of any of claims 11-19, wherein the received plurality of data samples is part of a data array originating from a plurality of data arrays, and wherein the programmable processing array is configured to perform the linear interpolation operation as part of a multi-dimensional interpolation operation on the plurality of data arrays.

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