INTEGRATED SELF-TESTING KIT FOR A DIGITAL-TO-ANALOGUE CONVERTER

Abstract

A built-in self-test, BIST, arrangement (100) for a digital-to-analog converter, DAC, comprising a main DAC (10) configured to convert a digital input signal received at its input into an analog output signal provided at its output, a sub-DAC (20) configured to convert a digital input signal received at its input into an analog output signal provided at its output, a comparator (30) coupled to the output of the main DAC (10) and the output of the sub-DAC (20) and configured to compare the analog output signal of the main DAC (10) with the analog output signal of the sub-DAC (20), and a processing unit (40) coupled to an output of the comparator (30), the input of the main DAC (10), and the input of the sub-DAC (20).The processing unit (40) is configured to determine a coupling factor between the main DAC (10) and the sub-DAC (20) by performing a measurement of a plurality of least significant bits (LSBs) of the main DAC (10) by the sub-DAC (20), where the coupling factor reflects a ratio of the LSB of the main DAC (10) and the LSB of the sub-DAC (20); to determine a difference between two sets of bits of the main DAC (10) for N sets of bits by performing a measurement of the main DAC (10) by the sub-DAC (20) based on the coupling factor, where N is the number of bits of the main DAC (10), thereby determining a linear system; to determine a bit value for each bit of the main DAC (10) by resolving the linear system; and to determine a performance of the main DAC (10) using the determined bit values. to determine.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a built-in self-test (BIST) arrangement for a digital-to-analog converter (DAC), in particular a switching capacitor (SC), successive approximation register (SAR), analog-to-digital converter (ADC) comprising the BIST arrangement, and a method for performing the BIST. BACKGROUND

[0002] Data converters typically use a type of digital-to-analog converter (DAC), which can be affected by manufacturing defects or damaged during its lifetime. Detecting these defects is crucial in production testing and safety-critical applications, making a self-testing procedure for such DACs essential.

[0003] Currently, DAC circuits can be tested in different ways depending on the system in which they are implemented. Some well-known methods are the following: An initial test is called a ramp / sine wave test: In this test, the DAC's characteristics are checked against a precise reference signal. This approach is usually time-consuming and requires a measuring device with higher precision than the device under test.

[0004] A second test is called Delta-BIST: This approach uses an auxiliary circuit to determine the difference between the DAC's bits and then calculates the ratio of the bits, thus determining the DAC's static performance. While attractive, this approach requires additional circuitry, typically exhibits variable execution time due to PVT (process voltage-temperature) fluctuations, and can be highly susceptible to interference, potentially leading to sporadic false alarms.

[0005] Therefore, there is a need for an improved BIST arrangement for a DAC. SUMMARY

[0006] According to one aspect of the invention, a built-in self-test (BIST) arrangement for a digital-to-analog converter (DAC) comprises: a main DAC configured to convert a digital input signal received at its input into an analog output signal provided at its output; a sub-DAC configured to convert a digital input signal received at its input into an analog output signal provided at its output; and a comparator coupled to the output of the main DAC and the output of the sub-DAC, configured to compare the analog output signal of the main DAC with the analog output signal of the sub-DAC.A processing unit coupled to a comparator output, the main DAC input, and the sub-DAC input, configured to determine a coupling factor between the main DAC and the sub-DAC by performing a measurement of a plurality of least significant bits (LSBs) of the main DAC by the sub-DAC, where the coupling factor reflects a ratio of the LSB of the main DAC to the LSB of the sub-DAC. The processing unit is further configured to determine a difference between two sets of bits of the main DAC for N sets of bits by performing a measurement of the main DAC by the sub-DAC based on the coupling factor, where N is the number of bits of the main DAC, thereby determining a linear system. The processing unit is further configured to determine a bit value for each bit of the main DAC by resolving the linear system.The processing unit is also designed to determine the performance of the main DAC using the specified bit values.

[0007] In other words, the performance and functionality of a DAC, the main DAC, are evaluated using a sub-DAC to resolve a difference between the DAC bits and calculate the ratio of its bits. This is essentially achieved by determining a coupling factor between the main DAC and the sub-DAC, resolving the difference between two sets of the main DAC bits using the sub-DAC, repeating the aforementioned measurement for N sets of linearly independent bits, where N is the number of bits in the DAC, resolving the linear system and determining the individual bit size of the main DAC, and estimating the functionality and performance of the main DAC.

[0008] The coupling factor, which represents the ratio between the LSB of the main DAC and the LSB of the sub-DAC, allows the sub-DAC to measure the main DAC.

[0009] A digital-to-analog converter (DAC) is an electronic component that generally converts a digital input signal, comprising a number of input lines, into an analog output signal. The number of input lines can indicate the resolution of the DAC. The analog output signal can be a current or a voltage, especially when a high output impedance is desired. The voltage range of the DAC can depend on its specified purpose. An example of an output voltage range might be from 0 V to 5 V, or, for a differential output, from -5 V to +5 V.

[0010] A comparator is an electronic component that compares two input voltages or currents and outputs a digital signal indicating which is larger.

[0011] Determining the performance of the main DAC can involve checking a pass / fail criterion for specific bit values. In other words, for each specific bit value, it is determined whether the bit value lies within a predetermined, and especially expected, range of values.

[0012] The two sets of bits of the main DAC can comprise a first set consisting of only 1 bit of the main DAC and a second set of bits consisting of the equivalent sum of bits with lower significance. In general, the two sets of bits can comprise any set of bits that allows the overall system of equations to be linearly independent and where the difference between the two sets lies within the range of the sub-DAC.

[0013] Solving the linear system can involve multiplying known bit values ​​of the main DAC by the determined differences between the sets of bits in the main DAC. In particular, the system can be solved by multiplying an inverse matrix of the set of bits used, or in other words, sets of equations, by a difference estimated by the sub-DAC, especially normalized by the coupling factor.

[0014] The BIST arrangement can be implemented without additional components, particularly analog circuitry. In other words, the BIST arrangement can be implemented in any system that includes a main DAC, a sub-DAC (which could also be implemented using the least significant bits, LSB, of the main DAC), and a comparator. An example of such a system is a switching capacitor (SC), a successive approximation register (SAR), and an analog-to-digital converter (ADC). In an SC-SAR ADC, a main DAC and a comparator are used for ADC conversion, along with a sub-DAC used for calibration purposes.

[0015] Furthermore, the BIST configuration does not require any additional precise measuring equipment. The relationship between the main DAC and the sub-DAC is accurate enough to estimate the functionality and performance of the main DAC.

[0016] Additionally, the self-test can be implemented using a relatively simple digital method. Determining the coupling factor, the number of bits in the main DAC, the resolution of the linear system, and the performance of the main DAC require only a relatively simple control logic for the processing unit.

[0017] Furthermore, due to its design, the self-test has a relatively constant and therefore predictable execution time. Compared to known methods, the self-test also has a faster execution time, in particular a significantly faster time than known methods.

[0018] Due to its fast execution time and relatively simple digital implementation, the processing unit can be implemented on the chip. This provides greater resistance to measurement noise.

[0019] Consequently, the BIST arrangement provides a very fast, precise and cost-effective way to detect defects and failures of a main DAC circuit, especially after its manufacture and during its lifetime.

[0020] This provides an improved BIST configuration of a DAC.

[0021] In a preferred embodiment, the processing unit is configured to measure the sub-DAC using the main DAC, thereby evaluating the functionality and performance of the sub-DAC.

[0022] In other words, the main DAC is used to measure and evaluate the sub-DAC to determine if it is of the correct size. Thus, the DAC is used to assess the functionality and performance, particularly its basic performance, of the sub-DAC.

[0023] Typically, the resolution of the main DAC is lower than that of the sub-DAC. Therefore, it becomes clear that the main DAC can only perform a coarse measurement of the sub-DAC. Consequently, measuring the sub-DAC using the main DAC preferentially identifies a sub-DAC with larger defects.

[0024] This ensures with a relatively high degree of probability that the sub-DAC is functioning correctly. This is important because the sub-DAC is used to measure and test the main DAC.

[0025] This provides an improved BIST configuration of a DAC.

[0026] In a preferred embodiment, the measurement of the main DAC is performed by the sub-DAC in two directions, thereby ignoring any offset of the comparator.

[0027] Generally, a comparator includes an offset value, also called an offset voltage, which must be applied to the comparator's input to produce a 0V output voltage. To provide an offset-free comparator output voltage, the sub-DAC performs measurements of the main DAC—namely, determining the coupling factor and the difference between two sets of the main DAC bits—in two directions, or in other words, in reverse directions. In other words, each measurement of the main DAC is performed twice with the inputs to the main DAC reversed. The results of these measurements are then added together and divided by two to obtain an offset-free result. Consequently, the comparator's offset does not need to be measured or considered separately in the measurements and calculations.

[0028] This provides an improved BIST configuration of a DAC.

[0029] In a preferred embodiment, performing the measurement of the main DAC by the sub-DAC includes performing a successive approximation register (SAR) search.

[0030] The SC-SAR-ADC naturally includes a main DAC and a comparator used for ADC conversion, as well as a sub-DAC used for calibration purposes. Consequently, the described BIST arrangement can be implemented in an SC-SAR-ADC circuit without additional components.

[0031] Thus, a BIST arrangement of a DAC is provided with improved measurement accuracy of the main DAC.

[0032] In a preferred embodiment, determining the difference between two sets of bits of the main DAC comprises performing an averaging of the determined difference.

[0033] Averaging, also known as signal averaging or averaging algorithm, refers to a process that reduces the noise component of a signal or, in other words, improves the signal-to-noise ratio. In other words, averaging reduces the influence of noise on a measured signal, in this case, the difference between two sets of bits from the main DAC.

[0034] In particular, averaging reduces noise caused by mismatch in digital-to-analog conversion.

[0035] Thus, a BIST arrangement of a DAC is provided with improved measurement accuracy of the main DAC.

[0036] In a preferred embodiment, determining the performance of the main DAC includes estimating a differential nonlinearity, DNL, ​​or an integral nonlinearity, INL, of the main DAC.

[0037] Although the performance of the main DAC can only be determined based on the specific bit values ​​of the main DAC, the DNL or DAC provide measurement methods that can be used to determine the performance of a DAC.

[0038] The DNL describes a deviation between pairs of bit values ​​compared to an ideal LSB step.

[0039] The DAC describes a deviation between an ideal DAC transfer function, which is a straight line, and the DAC transfer function determined by the bit values ​​of the main DAC.

[0040] In a preferred embodiment, the sub-DAC includes a higher resolution than the main DAC.

[0041] The difference between two sets of bits from the main DAC for N sets of bits is determined by performing a measurement of the main DAC using the sub-DAC. Thus, due to the relatively high resolution of the sub-DAC, which is higher than that of the main DAC, a relatively high accuracy of the measurement of the main DAC can be achieved.

[0042] Particularly due to the relatively small value range that the sub-DAC must exhibit, a sub-DAC focusing on high resolution can be chosen for the BIST arrangement without significantly increasing the cost of the BIST arrangement.

[0043] Thus, a BIST arrangement of a DAC with improved measurement accuracy of the main DAC is provided.

[0044] By providing a BIST setup with a sub-DAC with relatively high resolution and using an averaging method when measuring the main DAC using the sub-DAC, the accuracy of the measurement of the main DAC is further improved.

[0045] In a preferred embodiment, the sub-DAC covers a smaller value range than the main DAC.

[0046] For the measurement of the main DAC, the sub-DAC does not need to have the same value range as the main DAC, particularly due to the determination of the coupling factor. This allows the sub-DAC to have a higher resolution than a sub-DAC with a wider value range.

[0047] Thus, a BIST arrangement of a DAC is provided with improved measurement accuracy of the main DAC.

[0048] In a preferred embodiment, the sets of bits of the main DAC are linearly independent.

[0049] To solve a linear system with N variables, at least N linearly independent equations are required. In this system, the equations are the sets of bits used for the measurements, and the variables are the bits to be determined.

[0050] In a preferred embodiment, the sub-DAC is implemented using a plurality of LSBs of the main DAC.

[0051] In other words, without the need for a structural sub-DAC, a variety of LSBs of the main DAC can be used to perform the measurement of the main DAC.

[0052] Thus, a BIST configuration of a DAC with reduced components is provided.

[0053] In a preferred embodiment, the BIST arrangement is integrated into a semiconductor chip.

[0054] Due to the simplicity of the procedure for performing the BIST, the processing unit can be implemented directly on the chip.

[0055] This provides a compact implementation of the BIST arrangement.

[0056] According to one aspect of the invention, a switching capacitor, SC, successive approximation register, SAR, analog-to-digital converter, ADC, comprising the BIST arrangement described herein is provided.

[0057] An example of this is an SC SAR ADC. In this particular circuit, a main DAC and a comparator are used for the ADC conversion, as well as a sub-DAC used for calibration purposes.

[0058] According to one aspect of the invention, a method for performing a built-in self-test (BIST) for a digital-to-analog converter (DAC) is provided, comprising a main DAC configured to convert a digital input signal received at its input into an analog output signal provided at its output, and a sub-DAC configured to convert a digital input signal received at its input into an analog output signal provided at its output, wherein the sub-DAC covers a smaller range than the main DAC, wherein a comparator is coupled to the output of the main DAC and the output of the sub-DAC and is configured to compare the analog output signal of the main DAC with the analog output signal of the sub-DAC.The method compares the analog output signal of the main DAC with the analog output signal of the sub-DAC, wherein a processing unit is coupled to an output of the comparator, the input of the main DAC, and the input of the sub-DAC. The method comprises the following steps: Determining a coupling factor between the main DAC and the sub-DAC by performing a measurement of a plurality of least significant bits (LSBs) of the main DAC by the sub-DAC, where the coupling factor reflects a ratio of the LSB of the main DAC to the LSB of the sub-DAC. Determining a difference between two sets of bits of the main DAC for N sets of bits by performing a measurement of the main DAC by the sub-DAC, where N is the number of bits of the main DAC, thereby determining a linear system. Determining a bit value for each bit of the main DAC, resolving the linear system. Determining the performance of the main DAC using the specified bit values.

[0059] Experts will recognize further features and advantages when reading the following detailed description and examining the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The present disclosure is illustrated by means of examples and not by limitations in the figures of the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale with one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. Figure 1 illustrates a BIST arrangement for the DAC; Fig. 2 illustrates a procedure for performing a BIST for a DAC; Fig. Figure 3 illustrates the determination of a coupling factor in a BIST configuration for a DAC; and Fig. Figure 4 illustrates how to determine the difference between two sets of bits from the main DAC. DETAILED DESCRIPTION

[0061] Fig. Figure 1 illustrates a built-in self-test (BIST) arrangement 100 for a digital-to-analog converter (DAC) comprising: a main DAC 10 configured to convert a digital input signal received at its input into an analog output signal provided at its output; a sub-DAC 20 configured to convert a digital input signal received at its input into an analog output signal provided at its output; and a comparator 30 coupled to the output of the main DAC 10 and the output of the sub-DAC 20, configured to compare the analog output signal of the main DAC 10 with the analog output signal of the sub-DAC. The comparator 30 comprises a positive input (+) and a negative input (-), with the main DAC connected to the positive input (+) and the sub-DAC to the negative input (-).A processing unit 40 is coupled to an output of the comparator 30, the input of the main DAC 10, and the input of the sub-DAC 20. The processing unit 40 is configured to control the main DAC and the sub-DAC.

[0062] The processing unit 40 is configured to determine a coupling factor between the main DAC 10 and the sub-DAC 20 by performing a measurement of a multitude of Least Significant Bits (LSBs) of the main DAC 10 by the sub-DAC 20, where the coupling factor reflects a ratio of the LSB of the main DAC 10 and the LSB of the sub-DAC 20; to determine a difference between two sets of bits of the main DAC 10 for N sets of bits by performing a measurement of the main DAC 10 by the sub-DAC 20 based on the coupling factor, where N is the number of bits of the main DAC 10, thereby determining a linear system; to determine a bit value for each bit of the main DAC 10; to resolve the linear system; and to determine a performance of the main DAC 10 using the determined bit values.

[0063] Fig. Figure 2 illustrates a method for performing a BIST for a digital-to-analog converter, DAC, comprising a main DAC 10 configured to convert a digital input signal received at its input into an analog output signal provided at its output, a sub-DAC 20 configured to convert a digital input signal received at its input into an analog output signal provided at its output, wherein the sub-DAC 20 has a smaller value range than the main DAC 10, wherein a comparator 30 is coupled to the output of the main DAC 10 and the output of the sub-DAC 20 and is configured to compare the analog output signal of the main DAC 10 with the analog output signal of the sub-DAC 20, and wherein a processing unit is coupled to an output of the comparator, wherein the input of the main DAC 10 and the input of the sub-DAC 20, the method comprising the following steps includes.

[0064] Step S10 involves determining a coupling factor between the main DAC 10 and the sub-DAC 20 by performing a measurement of a multitude of least significant bits (LSBs) of the main DAC 10 through the sub-DAC 20, where the coupling factor reflects a ratio of the LSB of the main DAC 10 to the LSB of the sub-DAC 20. Step S20 involves determining a difference between two sets of bits of the main DAC 10 for N sets of bits by performing a measurement of the main DAC 10 through the sub-DAC 20, where N is the number of bits of the main DAC 10, thereby determining a linear system. Step S30 involves determining a bit value for each bit of the main DAC 10, resolving the linear system. Step S40 involves determining a power rating of the main DAC using the determined bit values.

[0065] Fig. Figure 3 illustrates how to determine a coupling factor in a BIST configuration for a DAC.

[0066] In general, the structure of the BIST arrangement corresponds to the BIST arrangement of Fig. 1. The BIST order of Fig. However, the second component is implemented in an SC-SAR ADC, where the comparator 30 sequentially compares an input voltage with the output of an internal DAC using switching capacitors. Consequently, the main DAC 10 and the sub-DAC 20 comprise a plurality of capacitors connected in parallel. Each of the capacitors can be connected to either a positive reference or ground. In this case, the main DAC 10 has a value range of 13 bits and the sub-DAC 20 a value range of 7 bits. The comparator 30 comprises a positive input (+) and a negative input -. The negative input - is connected between ground (GND) and a common-mode voltage (Vcm). A second common-mode switch (Sc2) is arranged between the common-mode voltage (Vcm) and the negative input -. A capacitor is arranged between the negative input - and ground (GND).The positive input + is connected to the outputs of the main DAC 10 and the sub-DAC 20, which are connected to the common-mode voltage Vcm via a first common-mode switch Sc1.

[0067] The coupling factor between the main DAC 10 and the sub-DAC 20 is determined by measuring a large number of LSBs of the main DAC 10 through the sub-DAC 20. In one step, the so-called sampling phase, a capacitor of the main DAC 10, for example the LSB+2 capacitor, is connected to the ground reference voltage. The first and second common-mode switches Sc1 and Sc2 are closed.

[0068] In a further step, the so-called conversion phase, the common-mode switches Sc1 and Sc2 are opened and the capacitor of the main DAC 10 is connected to a reference voltage. A SAR search is performed on the main DAC 10 by the sub-DAC 20, or in other words, the sub-DAC 20 measures the main DAC 10.

[0069] The search is then performed N times, where N is the number of desired conversions to be averaged, and an averaged result of the search determines a positive coupling factor.

[0070] In a further step, another sampling phase is carried out, with the capacitor of the main DAC 10 connected to the reference voltage.

[0071] In a further step, the conversion phase is then performed, with the capacitor of the main DAC 10 connected to the ground reference voltage. A SAR search is performed on the main DAC 10 by the sub-DAC 20, or in other words, the sub-DAC 20 measures the main DAC 10.

[0072] The search is then performed N times, where N is the number of desired conversions to be averaged, and an averaged result of the search determines a negative coupling factor.

[0073] By subtracting the negative coupling factor from the positive coupling factor and dividing the results by 2, or in the case of the LSB+2 capacitor by 2 times 2 2 The offset-free coupling factor is determined.

[0074] Fig. Figure 4 illustrates the determination of a difference between two sets of bits of the main DAC.

[0075] In this example, each bit of the main DAC and the sub-DAC is represented by a capacitor. Consequently, the difference between a first set of capacitors Ca and a second set of capacitors Cb is determined. Preferably, the first set of capacitors Ca comprises a single capacitor, and the second set of capacitors Cb comprises the equivalent sum of smaller capacitors.

[0076] Thus, the difference between the first set of capacitors Ca and the second set of capacitors Cb is determined in the following way.

[0077] In one step, the so-called sampling phase, the first set of capacitors Ca of the main DAC 10 is connected to a ground reference voltage, and the second set of capacitors Cb of the main DAC 10 is also connected to a reference voltage. Common-mode switches Sc1 and Sc2, which connect a common-mode voltage Vcm to the positive input (+) and negative input -, respectively, of comparator 30, are closed. Thus, the capacitors of the main DAC 10 are charged to the input voltage.

[0078] In a further step, the so-called conversion phase, the common-mode switches Sc1 and Sc2 are opened, and the first set of capacitors Ca of the main DAC 10 is connected to the reference voltage, and the second set of capacitors Cb of the main DAC 10 is connected to the ground reference voltage. A SAR search is performed on the main DAC 10 by the sub-DAC 20; in other words, the sub-DAC 20 measures the main DAC 10.

[0079] The search is then performed N times, where N is the number of desired conversions to be averaged and an averaged result of the search determines a positive difference.

[0080] In a further step, another sampling phase is carried out, with the first set of capacitors Ca of the main DAC 10 connected to the ground reference voltage and the second set of capacitors Cb of the main DAC 10 connected to the reference voltage.

[0081] In a further step, the conversion phase is performed, whereby the first set of capacitors Ca of the main DAC 10 is connected to the ground reference voltage and the second set of capacitors Cb of the main DAC 10 is also connected to the reference voltage. A SAR search is performed on the main DAC 10 by the sub-DAC 20, or in other words, the sub-DAC 20 measures the main DAC 10.

[0082] The search is then performed N times, where N is the number of desired conversions to be averaged, and an averaged result of the search determines a negative difference.

[0083] By subtracting the negative difference from the positive difference and dividing the results by 2, the offset-free difference between the two sets of bits of the main DAC 10 is determined.

[0084] Although specific examples have been illustrated and described here, it will be clear to those skilled in the art that a multitude of alternative and / or equivalent implementations can be used in place of the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover all adaptations or variations of the specific examples discussed herein. Therefore, this invention is intended to be limited only by the claims and their equivalents.

[0085] It should be noted that the methods and arrangements, including their preferred embodiments, as described in this document, can be used alone or in combination with the other methods and arrangements disclosed herein. Furthermore, the features described in connection with an arrangement are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and arrangements described in this document can be combined as desired. In particular, the features of the claims can be combined as desired.

[0086] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are contained within its spirit and scope. Furthermore, all examples and embodiments presented in this description are provided for illustrative purposes only, to facilitate the reader's understanding of the principles of the proposed methods and systems. Moreover, all statements contained herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof. Reference symbol list 10 Main DAC 20 Sub-DAC 30 Comparator 40 processing units S10 Determining a coupling factor between the main DAC and the sub-DAC S20 Determining a difference between two sets of bits of the main DAC for N sets of bits S30 Determining a bit value for each bit of the main DAC S40 Determining the performance of the main DAC using the determined bit values Ca first set of capacitors Cb second set of capacitors Vcm common mode voltage Sc1 first common-mode switch Sc2 second common-mode switch

Claims

Built-in self-test, BIST, arrangement (100) for a digital-to-analog converter, DAC, comprising: a main DAC (10) configured to convert a digital input signal received at its input into an analog output signal provided at its output; a sub-DAC (20) configured to convert a digital input signal received at its input into an analog output signal provided at its output; a comparator (30) coupled to the output of the main DAC (10) and the output of the sub-DAC (20) and configured to compare the analog output signal of the main DAC (10) with the analog output signal of the sub-DAC (20);and a processing unit (40) coupled to an output of the comparator (30), the input of the main DAC (10), and the input of the sub-DAC (20), and configured to determine a coupling factor between the main DAC (10) and the sub-DAC (20) by performing a measurement of a plurality of least significant bits (LSBs) of the main DAC (10) by the sub-DAC (20), wherein the coupling factor reflects a ratio of the LSB of the main DAC (10) and the LSB of the sub-DAC (20); to determine a difference between two sets of bits of the main DAC (10) for N sets of bits by performing a measurement of the main DAC (10) by the sub-DAC (20) based on the coupling factor, wherein N is the number of bits of the main DAC (10), thereby determining a linear system; a bit value for each To determine the bit of the main DAC (10) by solving the linear system;and to determine the performance of the main DAC (10) using the specified bit values. BIST arrangement according to claim 1, wherein the processing unit is configured to measure the sub-DAC (20) using the main DAC (10), thereby evaluating the functionality and performance of the sub-DAC (20). BIST arrangement according to one of the preceding claims, wherein the measurement of the main DAC (10) is performed by the sub-DAC (20) in two directions, thereby ignoring an offset of the comparator. BIST arrangement according to one of the preceding claims, wherein performing the measurement of the main DAC (10) by the sub-DAC (20) comprises: performing a successive approximation register, SAR, search. BIST arrangement according to one of the preceding claims, wherein determining the difference between two sets of bits of the main DAC (10) comprises: performing an averaging of the determined difference. BIST arrangement according to any of the preceding claims, wherein determining a performance of the main DAC (10) comprises: estimating a differential nonlinearity, DNL, ​​or an integral nonlinearity, INL, of the main DAC (10). BIST arrangement according to one of the preceding claims, wherein the sub-DAC (20) comprises a higher resolution than the main DAC (10). BIST arrangement according to one of the preceding claims, wherein the sub-DAC (20) covers a smaller range of values ​​than the main DAC (10). BIST arrangement according to one of the preceding claims, wherein the sets of bits of the main DAC (10) are linearly independent. BIST arrangement according to one of the preceding claims, wherein the sub-DAC (20) is implemented using a plurality of LSBs of the main DAC. BIST arrangement according to one of the preceding claims, wherein the BIST arrangement is integrated into a semiconductor chip. Switching capacitor, SC, successive approximation register, SAR, analog-to-digital converter, ADC, comprising the BIST arrangement (100) of any one of the preceding claims. A method for performing a built-in self-test (BIST) for a digital-to-analog converter (DAC), comprising a main DAC (10) configured to convert a digital input signal received at its input into an analog output signal provided at its output, a sub-DAC (20) configured to convert a digital input signal received at its input into an analog output signal provided at its output, wherein the sub-DAC (20) covers a smaller range of values ​​than the main DAC (10), wherein a comparator (30) is coupled to the output of the main DAC (10) and the output of the sub-DAC (20) and is configured to compare the analog output signal of the main DAC (10) with the analog output signal of the sub-DAC (20), and wherein a processing unit is coupled to an output of the comparator, wherein the input of the main DAC (10) and the input of the sub-DAC (20) are coupled,wherein the procedure comprises: Determining (S10) a coupling factor between the main DAC (10) and the sub-DAC (20) by performing a measurement of a plurality of least significant bits, LSBs, of the main DAC (10) by the sub-DAC (20), wherein the coupling factor reflects a ratio of the LSB of the main DAC (10) and the LSB of the sub-DAC (20); Determining (S20) a difference between two sets of bits of the main DAC (10) for N sets of bits by performing a measurement of the main DAC (10) by the sub-DAC (20), wherein N is the number of bits of the main DAC (10), thereby determining a linear system; Determining (S30) a bit value for each bit of the main DAC (10), resolving the linear system; and Determine (S40) a performance of the main DAC (10) using the determined bit values.

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