SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device having highly integrated memory cells and a method for manufacturing the semiconductor device are disclosed. A semiconductor device includes a memory cell array; a dummy region including a dummy stack horizontally spaced from the memory cell array; a peripheral circuit region arranged at a lower level than the memory cell array and the dummy region; a stack-level connector extending through the dummy stack; and a stack-level spacer formed on a sidewall of the stack-level connector.

Description

BACKGROUND1. Field of InterestEmbodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including three-dimensional (3D) memory cells and a method of manufacturing the semiconductor device.2. Description of the Related ArtIn order to meet the requirements of large capacity and miniaturization of memory devices, a technology for providing a three-dimensional (3D) memory device in which a plurality of memory cells are stacked has recently been disclosed.SUMMARYEmbodiments of the present disclosure are directed to a semiconductor device having highly integrated memory cells and a method of manufacturing the semiconductor device.According to an embodiment of the present disclosure, a semiconductor device includes a memory cell array; a dummy region including a dummy stack horizontally spaced apart from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and the dummy region; a stack level plug passing through the dummy stack; and a stack level spacer formed on a sidewall of the stack level plug.According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device includes forming a memory cell array and a dummy stack over a first substrate, the memory cell array and the dummy stack being horizontally spaced apart from each other; forming a stack-level via to penetrate the dummy stack; forming a stack-level spacer on a sidewall of the stack-level via; and forming a stack-level plug over the stack-level spacer to fill the stack-level via.According to another embodiment of the present disclosure, a semiconductor device includes a memory cell array disposed over a first substrate; a second substrate having a front side and a back side and turned over to face the memory cell array; a peripheral circuit formed on the front side of the second substrate; and a back side interconnect structure passing through the second substrate from the back side of the second substrate and coupled to the peripheral circuit.According to another embodiment of the present disclosure, a semiconductor device includes a peripheral circuit portion; a memory cell array including a vertical conductive line disposed over the peripheral circuit portion, a plurality of data storage elements, and a common plate line coupled in common to the data storage elements. The semiconductor device further includes a substrate formed over an upper portion of the common plate line; a nano-via configured to penetrate the substrate to expose an upper portion of the common plate line; a nano-level spacer formed on a sidewall of the nano-via; a nano-silicon via configured to fill the nano-via over the nano-level spacer; an upper-level interconnect over the nano-silicon via; a lower-level interconnect coupled to a lower portion of the vertical conductive line; a first bonding pad coupled to the lower-level interconnect; and a second bonding pad coupled to the first bonding pad while coupled to the peripheral circuit region. The semiconductor device may include a dummy region including a dummy stack horizontally spaced from the memory cell array; a stack level plug configured to penetrate the dummy stack; and a stack level spacer formed on a sidewall of the stack level plug.According to another embodiment of the present disclosure, a semiconductor device includes a memory cell array disposed over a front side of a first substrate; a back side interconnect structure disposed at a higher level than the memory cell array; a second substrate having a front side facing the memory cell array and a back side facing the back side interconnect structure; a control circuit including one or more transistors disposed over the front side of the second substrate; and a multi-level metal line including one or more metal lines coupled to the control circuit. The back side interconnect structure may include a power interconnect line embedded internally on the front side side of the second substrate; a power via configured to penetrate the back side of the second substrate to be coupled to the power interconnect line; a power contact plug coupled to the power interconnect line and the control circuit; and a power level spacer formed on the sidewalls of the power interconnect line and the power via.According to an embodiment of the present invention, a semiconductor device may include a first substrate; a memory cell array including memory cells vertically stacked above the first substrate; a second substrate including a front side facing the memory cell array and a back side at a higher level than the front side and including a plurality of control circuits for controlling the memory cells; a back side power distribution network passing through the second substrate and supplying power to the control circuits from the back side of the second substrate, the back side power distribution network including a buried bus bar embedded in the front side of the second substrate; a nano-silicon via passing through the back side of the second substrate and coupled to the buried bus bar; a power level spacer formed on a sidewall of the nano-silicon via and the buried bus bar; and a buried bus bar via disposed on the front side of the second substrate and coupled to the buried bus bar.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a schematic perspective view illustrating a memory cell according to an embodiment of the present disclosure. FIG. 1B is a schematic cross-sectional view illustrating the memory cell shown in FIG. 1A. FIG. 1C is a plan view illustrating a switching element shown in FIG. 1A. FIG. 1D is a schematic cross-sectional view illustrating a memory cell according to another embodiment of the present disclosure. FIG. 2A is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 2B is a schematic perspective view illustrating a memory cell array MCA shown in FIG. 2A. FIG. 2C is a schematic cross-sectional view taken along a line A-A' shown in FIG. 2A. FIG. 2D is a schematic cross-sectional view taken along a line B-B' shown in FIG. 2A. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device 200 according to another embodiment of the present disclosure. FIGS. 4 to 22 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIGS. 23 to 27 illustrate a method of manufacturing a pad portion according to an embodiment of the present disclosure. FIGS. 28 to 33 illustrate a method of manufacturing the semiconductor device shown in FIG. 3. FIGS. 34 to 36 illustrate a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. FIGS. 37 to 39 are perspective views illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 40 is a cross-sectional view illustrating a memory cell array according to another embodiment of the present disclosure. FIGS. 41 to 45 illustrate a semiconductor device according to another embodiment of the present disclosure.DETAILED DESCRIPTIONVarious embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present disclosure.Hereinafter, the various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.The drawings are not necessarily to scale, and in some instances, proportions may be exaggerated to clearly illustrate features of embodiments of the present disclosure. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers to not only a case where the first layer is directly formed on the second layer or the substrate but also a case where a third layer is present between the first layer and the second layer or the substrate.The following embodiments of the present disclosure relate to three-dimensional memory cells that can increase the memory cell density and decrease the parasitic capacitance by vertically stacking memory cells.FIG. 1A is a schematic perspective view illustrating a memory cell MC according to an embodiment of the present disclosure. FIG. 1B is a schematic cross-sectional view illustrating the memory cell MC of FIG. 1A. FIG. 1C is a plan view illustrating a switching element of FIG. 1A.Referring to FIGS. 1A to 1C, the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.The first conductive line BL may be vertically oriented in a first direction D 1. The first conductive line BL may include a bit line. The first conductive line BL may be referred to as a vertical conductive line, a vertically oriented bit line, a vertically extending bit line, or a pillar-shaped bit line. The first conductive line BL may include a conductive material. The first conductive line BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductive line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL may include a stack of titanium nitride and tungsten (TiN / W).The switching element TR may have a function of controlling the voltage (or current) supply to the data storage element CAP in a data write operation and a data read operation for the data storage element CAP. The switching element TR may include a horizontal layer HL, an inter-level dielectric layer GD, and a second conductive line DWL. The second conductive line DWL may include a horizontal conductive line or a horizontal word line. The horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second conductive line DWL may serve as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second conductive line DWL may be referred to as a horizontal gate electrode or a horizontal word line.The horizontal layer HL may extend in a second direction D 2 intersecting with the first direction D 1. The second conductive line DWL may extend in a third direction D 3 intersecting with the first direction D 1 and the second direction D 2. The first direction D 1 may be a vertical direction, the second direction D 2 may be a first horizontal direction, and the third direction D 3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D 2) and the second conductive line DWL may extend in the second horizontal direction (i.e., the third direction D 3).The horizontal layer HL may be horizontally oriented in the second direction D 2 from the first conductive line BL. The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G 1 and a lower horizontal line G 2 facing each other with a horizontal layer HL interposed therebetween. An inter-level dielectric layer GD may be formed on an upper surface and a lower surface of the horizontal layer HL. The upper horizontal line G 1 may be disposed above the horizontal layer HL and the lower horizontal line G 2 may be disposed below the horizontal layer HL. The second conductive line DWL may include a pair of the upper horizontal line G 1 and the lower horizontal line G 2. In the second conductive line DWL, the same driving voltage may be applied to the upper horizontal line G 1 and the lower horizontal line G 2. For example, the upper horizontal line G 1 and the lower horizontal line G 2 may form a pair to be coupled to a single memory cell MC. According to another embodiment of the present disclosure, different driving voltages may be applied to the upper horizontal line G 1 and the lower horizontal line G 2. In this case, a horizontal line of the upper horizontal line G 1 and the lower horizontal line G 2 may serve as a back gate or a shield gate (shield gate).Referring back to FIG. 1C, each of the upper horizontal line G 1 and the lower horizontal line G 2 may have a width in the second direction D 2, for example, a width of an overlapping portion that overlaps with the horizontal layer HL to be larger than a width of a non-overlapping portion that does not overlap with the horizontal layer HL. Due to this difference in width, the second conductive line DWL may have a notch-shaped side wall. The second conductive line DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping section WLP may refer to a section that overlaps with the channel CH of the horizontal layer HL. The channel non-overlapping portion NOL may refer to a portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a diamond shape.From the perspective of a plan view, the horizontal layer HL can have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surfaces of the horizontal layer HL may have a curved shape or a rounded shape.The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polysilicon, monocrystalline silicon, germanium or silicon germanium. According to another embodiment of the present disclosure, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present disclosure, the horizontal layer HL may include a conductive metal oxide.The upper surface and the lower surface of the horizontal layer HL may have a flat surface. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D 2.The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first and second doped regions SR and DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body. The channel CH and the channel overlapping portion WLP of the second conductive line DWL may overlap each other. The channel CH may have a cross shape or a diamond shape. The size of the channel overlap portion WLP of the second conductive line DWL may be larger than that of the channel CH. The channel overlapping portion WLP of the second conductive line DWL may completely overlap with the channel CH.The first doped region SR and the second doped region DR may be doped with impurities of the same conductive type. The first doped region SR and the second doped region DR may be doped with an N-type conductive impurity or a P-type conductive impurity. The first doped region SR and the second doped region DR may include at least one impurity selected from the group consisting of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first conductive line BL and the second doped region DR may be coupled to the data storage element CAP. The first and second doped regions SR and DR may be referred to as first and second source / drain regions, respectively.The inter-level dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The inter-level dielectric layer GD may also be referred to as a gate dielectric layer. The inter-level dielectric layer GD may also be referred to as a horizontal layer side dielectric layer. The inter-level dielectric layer GD may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an antiferromagnetic material, or a combination thereof. The inter-level dielectric layer GD may include SiO 2, Si 3 N 4, HfO 2, Al 2 O 3, ZrO 2, AlON, HfON, HfSiO, HfSiON, HfNbO, or a combination thereof. The inter-level dielectric layer GD may be formed by a thermal oxidation process of a semiconductor material.The second conductive line DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductive line DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive line DWL may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less. The P-type work function material may have a high work function of about 4.5 eV or more. The second conductive line DWL may include a stack of a low work function material and a high work function material.The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be arranged horizontally in the second direction D 2 from the switching element TR. The data storage element CAP may include a first electrode SN horizontally extending from the horizontal layer HL in the second direction D 2. The data storage element CAP may further include a second electrode PN over the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D 2. The first electrode SN may include an internal space and a plurality of outer surfaces. The inner space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN may extend vertically in the first direction D 1, and the horizontal outer surfaces of the first electrode SN may extend horizontally in the second direction D 2 or the third direction D 3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed in the inner space of the first electrode SN over the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to a common disk PL.The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, which may be a horizontal three-dimensional structure oriented in the second direction D 2. In an example of the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include inner cylindrical surfaces and outer cylindrical surfaces. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surfaces of the first electrode SN.According to another embodiment of the present disclosure, the first electrode SN may have a columnar shape or a cylindrical shape. The cylinder shape may refer to a structure in which a columnar shape and a cylindrical shape are united.The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2), iridium (Ir), iridium oxide (IrO 2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / titanium silicon nitride (TiSiN) stack, a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inside of the first electrode SN, titanium nitride (TiN) may serve as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO 2), zirconium oxide (ZrO 2), aluminum oxide (Al 2 O 3), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), tantalum oxide (Ta 2 O 5), niobium oxide (Nb 2 O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.The dielectric layer DE may be formed of a zirconium-based oxide. The dielectric layer DE may have a stack structure including zirconia (ZrO 2). The dielectric layer DE may include a ZA (ZrO 2 / Al 2 O 3)- stack or a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2)- stack. The ZA stack may have a structure in which alumina (Al 2 O 3) is stacked over zirconia (ZrO 2). The ZAZ stack may have a structure in which zirconia (ZrO 2), alumina (Al 2 O 3) and zirconia (ZrO 2) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as layers based on zirconium oxide (ZrO 2)-. According to another embodiment of the present disclosure, the dielectric layer DE may be formed of hafnium (Hf)-based oxide. The dielectric layer DE may be a stack structure including hafnium oxide (HfO 2). The dielectric layer DE may include an HA (HfO 2 / Al 2 O 3)- stack or an HAH (HfO 2 / Al 2 O 3 / HfO 2)- stack. The HA stack may have a structure in which alumina (Al 2 O 3) is stacked over hafnium oxide (HfO 2). The HAH stack may have a structure in which hafnium oxide (HfO 2), aluminum oxide (Al 2 O 3) and hafnium oxide (HfO 2) are sequentially stacked. The HA stack and the HAH stack may be referred to as hafnium oxide (HfO 2)- based layers. In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al 2 O 3) may have a larger band gap energy than zirconia (ZrO 2) and hafnia (HfO 2). Alumina (Al 2 O 3) may have a lower dielectric constant than zirconia (ZrO 2) and hafnia (HfO 2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a band gap energy larger than the high-k material. In addition to aluminum oxide (Al 2 O 3) the dielectric layer DE may include silicon oxide (SiO 2) as another high band gap material. By including the high band gap material, the dielectric layer DE may be capable of suppressing the leakage current. The high band gap material may be thinner than the high k material. According to another embodiment of the present disclosure, the dielectric layer DE may include a stacked structure in which high-k materials and high-band gap materials are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3)- stack, a ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al2O3 / ZrO2) stack, an HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3)- stack, an HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al2O3 / HfO2) stack, an HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2)- stack, a ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O3 / ZrO2 / HfO2 / ZrO2) stack, HZHZ(HfO 2 / ZrO 2 / HfO 2 / ZrO 2)- stack or an AHZAZHA(Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO2 / HfO2 / Al2O3) stack. In the above stacked structure, the alumina (Al 2 O 3) may be thinner than the zirconia (ZrO 2) and the hafnium oxide (HfO 2).According to another embodiment of the present disclosure, the dielectric layer DE may include a high-k material and a high-band gap material. The dielectric layer DE may have a laminated structure in which a plurality of high-k materials and a plurality of high band gap materials are stacked, or a mixed structure in which the high-k material and the high band gap material are mixed.According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferromagnetic material, or a combination thereof. For example, the dielectric layer DE may include HfNbO.According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferromagnetic material, a high-k material, or a combination of a ferroelectric material and an antiferromagnetic material. According to another embodiment of the present disclosure, the dielectric layer DE may include a perovskite dielectric material. The perovskite dielectric material may include SrTiO 3, ( Ba,Sr)TiO 3, BaTiO 3, PbTiO 3, PZT, PLZT, or PbTiO 3.Further, according to another embodiment of the present disclosure, an interfacial control layer for reducing the leakage current may be formed between the first electrode SN and the dielectric layer DE. The interfacial control layer may include titanium oxide (TiO 2), tantalum oxide (Ta 2 O 5), niobium oxide (Nb 2 O 5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced by another data storage material. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.For example, the memory cell MC may include a thyristor, the first conductive line BL may be a cathode line, and the data storage element CAP may be replaced with an anode line. The horizontal layer HL may include four semiconductor layers stacked in the second direction D 2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias voltage of the same voltage is applied to the thyristor, the thyristor may have a high conductivity state in which a large amount of current flows or a low conductivity state in which a small amount of current flows or no current flows. The memory cell MC according to the embodiment of the present disclosure may have a "1" state and a "0" state according to the high conductivity state and the low conductivity state of the thyristor, respectively.Referring back to FIGS. 1A and 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first and second contact nodes BLC and SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first and second contact nodes BLC and SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.FIG. 1D is a schematic cross-sectional view illustrating a memory cell MC 1 according to another embodiment of the present disclosure. The memory cell MC 1 of FIG. 1D may be similar to the memory cell MC of FIGS. 1A to 1C. Here, detailed description of the constituent elements that also appear in FIGS. 1A to 1C may be omitted.The memory cell MC 1 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include the horizontal layer HL, an inter-level dielectric layer GD, and a second conductive line DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.The memory cell MC 1 may further include a first contact node BLC between the first conductive line BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first and second contact nodes BLC and SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.The second conductive line DWL may include an upper horizontal line G 1 and a lower horizontal line G 2. The upper horizontal line G 1 and the lower horizontal line G 2 may each include a first work function electrode G 11 (an electrode G 11 having a first work function), a second work function electrode G 12 (an electrode G 12 having a second work function), and a third work function electrode G 13 (an electrode having a third work function). The first work function electrode G 11, the second work function electrode G 12, and the third work function electrode G 13 may be arranged horizontally in the second direction D 2. The first work function electrode G 11, the second work function electrode G 12, and the third work function electrode G 13 may directly contact each other. The second work function electrode G 12 may be disposed adjacent to the first conductive line BL, and the third work function electrode G 13 may be disposed adjacent to the data storage element CAP. The horizontal layer HL may have a thickness less than the thickness of the first, second, and third work function electrodes G 11, G 12, and G 13.The first work function electrode G 11, the second work function electrode G 12, and the third work function electrode G 13 may be formed of different work function materials. The first work function electrode G 11 may have a work function larger than the work functions of the second and third work function electrodes G 12 and G 13. The first work function electrode G 11 may include a material having a high work function. The first work function electrode G 11 may have a work function larger than the middle-gap work function of silicon. The second and third work function electrodes G 12 and G 13 may include a material having a low work function. The second and third work function electrodes G 12 and G 13 may have a work function lower than the middle gap work function of silicon. More specifically, the high work function material may have a work function greater than about 4.5 eV and the low work function material may have a work function less than about 4.5 eV. The first work function electrode G 11 may include a metal-based material, and the second and third work function electrodes G 12 and G 13 may include a semiconductor material.The second and third work function electrodes G 12 and G 13 may include polysilicon doped with an N-type dopant, i.e., an N-type dopant doped with polysilicon. The first work function electrode G 11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G 11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may be further formed between the second and third work function electrodes G 12 and G 13 and the first work function electrode G 11.According to the embodiment of the present disclosure, each of the upper and lower horizontal lines G 1 and G 2 of the second conductive line DWL may include the second work function electrode G 12, the first work function electrode G 11, and the third work function electrode G 13 arranged sequentially and horizontally in the second direction D 2. The first work function electrode G 11 may include a metal, and the second work function electrode G 12 and the third work function electrode G 13 may include polysilicon.Each of the upper and lower horizontal lines G 1 and G 2 of the second conductive line DWL may have a poly-Si metal-poly-Si (PMP) structure in which polysilicon, a metal, and polysilicon are horizontally arranged in the second direction D 2. In the PMP structure, the first work function electrode G 11 may be a metal-based material, and the second and third work function electrodes G 12 and G 13 may be an N-type dopant doped with polysilicon. The N-type dopant may include phosphorus or arsenic.A first barrier layer G 12L may be disposed between the first work function electrode G 11 and the second work function electrode G 12. A second barrier layer G 13L may be disposed between the first work function electrode G 11 and the third work function electrode G 13. The first and second barrier layers G 12L and G 13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G 13L may cover the upper surface, the lower surface, and a side surface of the first work function electrode G 11.The first work function electrode G 11 may have a volume larger than that of the second and third work function electrodes G 12 and G 13, and accordingly, the second conductive line DWL may have a low resistance. The first work function electrodes G 11 of the upper and lower horizontal lines G 1 and G 2 may vertically overlap each other in the first direction D 1 with the horizontal layer HL interposed therebetween. The second and third work function electrodes G 12 and G 13 of the upper and lower horizontal lines G 1 and G 2 may also vertically overlap each other in the first direction D 1 with the horizontal layer HL interposed therebetween. The overlap portion of the first work function electrode G 11 and the horizontal layer HL may be larger than the overlap portion of the second and third work function electrodes G 12 and G 13 and the horizontal layer HL. The first work function electrode G 11 may extend in the third direction D 3, and the second and third work function electrodes G 12 and G 13 may have an independent structure overlapping with the horizontal layer HL. For example, the first work function electrode G 11 may include a channel overlap portion WLP and a channel non-overlap portion NOL, and the second and third work function electrodes G 12 and G 13 may be part of the channel overlap portion WLP. The second and third work function electrodes G 12 and G 13 and the first work function electrode G 11 may directly contact each other.As described above, each of the upper and lower horizontal lines G 1 and G 2 may have a triple work function electrode structure including the first, second, and third work function electrodes G 11, G 12, and G 13. The second conductive line DWL may include a pair of first work function electrodes G 11, a pair of second work function electrodes G 12, and a pair of third work function electrodes G 13 extending across the horizontal layer HL in the third direction D 3 with the horizontal layer HL interposed therebetween. The first work function electrodes G 11, the second work function electrodes G 12, and the third work function electrodes G 13 may vertically overlap the channel CH.Each of the second conductive lines DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL, as illustrated in FIG. 1C. The channel overlapping portions WLP may have a cross shape or a diamond shape. The channel overlapping portions WLP may completely overlap the channel CH. The second conductive line DWL extending in the third direction D 3 may have notch-shaped side walls due to the channel overlapping portions WLP and the channel non-overlapping portions NOL. From the perspective of a plan view, the notch-shaped side walls may be provided by protruding portions formed by the channel overlapping portions WLP and recessed portions formed by the channel non-overlapping portions NOL. The channel overlapping portion WLP may include first work function electrodes G 11, second work function electrodes G 12, and third work function electrodes G 13. The first work function electrodes G 11, the second work function electrodes G 12, and the third work function electrodes G 13 may vertically overlap the channel CH.In the second direction D 2, the first work function electrode G 11 having a high work function may be disposed at the center of the second conductive line DWL, and the second and third work function electrodes G 12 and G 13 having a low work function may be disposed at both end portions of the second conductive line DWL, thereby reducing leakage current such as gate induced drain leakage (GIDL).The threshold voltage of the switching element TR can be increased by disposing the first work function electrode G 11 having a high work function in the center of the second conductive line DWL. Since the second work function electrode G 12 of the second conductive line DWL has a low work function, a low electric field may be formed between the first conductive line BL and the second conductive line DWL. Since the third work function electrode G 13 of the second conductive line DWL has a low work function, a low electric field may be formed between the data storage element CAP and the second conductive line DWL.As described above, the memory cell MC 1 may include a second conductive line DWL having an electrode structure with triple work function. Each of the upper and lower horizontal lines G 1 and G 2 of the second conductive line DWL may include the first work function electrode G 11, the second work function electrode G 12, and the third work function electrode G 13. The first work function electrode G 11 may overlap the channel CH. The second work function electrode G 12 may be disposed adjacent to the first conductive line BL and the first doped region SR. The third work function electrode G 13 may be disposed adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G 12, a low electric field may be formed between the second conductive line DWL and the first conductive line BL, which may alleviate the leakage current. Due to the low work function of the third work function electrode G 13, a low electric field may be formed between the second conductive line DWL and the data storage element CAP, which may mitigate the leakage current. Due to the high work function of the first work function electrode G 11, the threshold voltage of the switching element TR may be increased. In addition, due to the high work function of the first work function electrode G 11, the height of the memory cell MC 1 may be reduced, which is advantageous in terms of integration.FIG. 2A is a schematic plan view illustrating a semiconductor device 100 according to an embodiment of the present disclosure. FIG. 2B is a schematic perspective view illustrating a memory cell array MCA of FIG. 2A. FIG. 2C is a schematic cross-sectional view taken along a line A-A' shown in FIG. 2A. FIG. 2D is a schematic cross-sectional view taken along a line B-B' shown in FIG. 2A.Referring to FIGS. 2A, 2B, 2C, and 2D, the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. Each of the memory cells MC may be described with reference to FIGS. 1A to 1C. Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. According to another embodiment of the present disclosure, each of the memory cells MC may be the same as the memory cell MC 1 of FIG. 1D. The switching element TR may include a second conductive line DWL and a horizontal layer HL.The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may be a region in which memory cells MC are formed, and the second region CTA may be a region in which cell contact plugs WC coupled to the second conductive lines DWL of the memory cells MC are formed.The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. For example, the memory cell array MCA may include a plurality of column arrays. The column array of the memory cells MC may include a plurality of memory cells MC stacked in the first direction D 1. The row array of the memory cells MC may include a plurality of memory cells MC horizontally arranged in the second direction D 2 and the third direction D 3.The memory cell array MCA may include a plurality of first mirror-like subcell arrays and a plurality of second mirror-like subcell arrays. The first mirror-like sub-cell array may include a mirror-like structure in which two memory cells MC adjacent in the second direction D 2 share a first conductive line BL. The second mirror-like sub-cell array may include a mirror-like structure in which two memory cells MC share the second electrode PN of the data storage element CAP in the second direction D 2.Inter-cell dielectric layers IL may be disposed between the memory cells MC stacked in the first direction D 1. Cell isolation layers ISOA and ISOB may be disposed between the memory cells MC adjacent to each other in the third direction D 3. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers may include first cell isolation layers ISOA and second cell isolation layers ISOB. The first cell isolation layers ISOA and the second cell isolation layers ISOB may extend vertically in the first direction D 1. The first cell insulating layers ISOA and the second cell insulating layers ISOB may be alternately and repeatedly arranged in the second direction D 2. The first cell isolation layers ISOA may be disposed between the data storage elements CAP in the third direction D 3. The second cell insulating layers ISOB may be disposed between the first conductive lines BL in the third direction D 3. The second conductive lines DWL may be disposed between the first cell insulating layers ISOA and the second cell insulating layers ISOB in the second direction D 2.The memory cell array MCA may be disposed over a first substrate W 1.The memory cell array MCA may include a plurality of first conductive lines BL vertically extending in the first direction D 1. The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in the first direction D 1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D 1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D 1. The memory cell array MCA may include an alternating stack of the second conductive lines DWL and the inter-cell dielectric layers IL stacked in the first direction D 1.Each of the second conductive lines DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G 1 and a lower horizontal line G 2 facing each other with a horizontal layer HL interposed therebetween. An inter-level dielectric layer GD may be formed on an upper surface and a lower surface of the horizontal layer HL. The upper horizontal line G 1 may be disposed above the horizontal layer HL and the lower horizontal line G 2 may be disposed below the horizontal layer HL. The second conductive line DWL may include a pair of the upper horizontal line G 1 and the lower horizontal line G 2. Each of the second conductive lines DWL may include a channel overlapping portion WLP as illustrated in FIG. 1C. The channel overlapping portion WLP may have a cross shape or a diamond shape. The channel overlapping portion WLP may completely overlap with the channel CH. The second conductive line DWL extending in the third direction D 3 may include a plurality of channel overlapping portions WLP. The second conductive line DWL may have a notch-shaped side wall due to the channel overlapping portions WLP.A plurality of first passivation layers BF 1 may be disposed between the lowermost second conductive line DWL among the second conductive lines DWL and the first substrate W 1. A second passivation layer BF 2 may be disposed between the first conductive line BL and the first substrate W 1. Third passivation layers BF 3 may be disposed between the data storage element CAP and the first substrate W 1. The first to third passivation layers BF 1, BF 2, and BF 3 may include a dielectric material. The first to third passivation layers BF 1, BF 2, and BF 3 may include silicon oxide. The first to third passivation layers BF 1, BF 2, and BF 3 may electrically separate the first conductive line BL, the second conductive lines DWL, and the data storage elements CAP from the first substrate W 1.The first conductive line BL may extend vertically in the first direction D 1 from the upper portion of the first substrate W 1. The horizontal layers HL may extend in the second direction D 2 intersecting with the first direction D 1. The second conductive lines DWL may extend in the third direction D 3 intersecting with the first direction D 1 and the second direction D 2.The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. From the perspective of a plan view, the horizontal layers HL can have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surfaces of the horizontal layer HL may have a curved shape or a rounded shape. As illustrated in FIGS. 1B and 2C, the horizontal layer HL may include a channel CH.A first cover layer BC may be disposed between the second conductive line DWL and the first conductive line BL. A second cap layer CC may be disposed between the second conductive line DWL and the first electrode SN of the data storage element CAP. The first cover layer BC may be disposed between the upper horizontal line G 1 and the first conductive line BL, and also the first cover layer BC may be disposed between the lower horizontal line G 2 and the first conductive line BL. The second cap layer CC may be disposed between the upper horizontal line G 1 and the first electrode SN of the data storage element CAP, and also the second cap layer CC may be disposed between the lower horizontal line G 2 and the first electrode SN of the data storage element CAP.The first and second capping layers BC and CC may include a dielectric material. The first and second capping layers BC and CC may include silicon oxide, silicon nitride, silicon carbon oxide, an air gap, or a combination thereof. The first and second capping layers BC may include a stack of silicon oxide and silicon nitride.The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D 3 may share a second conductive line DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D 3 may be coupled to different first conductive lines BL. The switching elements TR stacked in the first direction D 1 may share a first conductive line BL. The switching elements TR horizontally arranged in the third direction D 3 may share a second conductive line DWL.The first cell isolation layers ISOA may be disposed between the first electrodes SN of the data storage elements CAP in the third direction D 3. The first electrodes SN may be separated from each other by the first cell insulating layers ISOA. The second electrodes PN of the data storage elements CAP may be coupled to a common disk PL. The second electrodes PN of the data storage elements CAP may be united to become a common disk PL.The first cell isolation layers ISOA may be disposed between the data storage elements CAP in the third direction D 3. The second cell isolation layers ISOB may be disposed between the vertical conductive lines BL in the third direction D 3. The second conductive line DWL may be disposed between the first cell insulating layers ISOA and the second cell insulating layers ISOB in the second direction D 2.The first substrate W 1 may be a material suitable for semiconductor processing. The first substrate W 1 may include one or more of conductive materials, dielectric materials, and semiconducting materials. Various materials may be formed over the first substrate W 1. The first substrate W 1 may include a semiconductor substrate. The first substrate W 1 may be formed of a material including silicon. The first substrate W 1 may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The first substrate W 1 may include other semiconductor materials such as germanium. The first substrate W 1 may include a III-V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The first substrate W 1 may include a silicon-on-insulator (SOI) substrate.According to another embodiment of the present disclosure, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND, a ferroelectric random access memory (FeRAM), a spin transfer torque random access memory (STT-RAM), a phase change RAM (PCRAM), or a resistive RAM (ReRAM).Referring to FIG. 2D, the second conductive lines DWL may be disposed in the first region CA, and portions of the second conductive lines DWL may extend to the second region CTA. The portions of the second conductive lines DWL disposed in the second region CTA may be referred to as a pad portion WLE, a peripheral portion, or a pad stack. The stack of the second conductive lines DWL may include a first stack and a second stack. The first stack may be a portion formed in the first region CA, and the second stack may be a portion formed in the second region CTA. One side of the pad portion WLE of FIG. 2A may be covered by an interlayer dielectric layer ILD.The pad portion WLE of the second conductive lines DWL may include a plurality of levels L 1, L 2, L 3, and L 4. In the pad portion WLE, each of the horizontal conductive lines DWL of the planes L 1 to L 4 may include a pair of the upper horizontal line G 1 and the lower horizontal line G 2. In the pad portion WLE, the planes L 1 to L 4 may further include pads GP. The pads GP may be disposed between the upper horizontal line G 1 and the lower horizontal line G 2. Each of the pads GP may be electrically connected to the upper horizontal line G 1 and the lower horizontal line G 2.The lateral lengths of the pads GP in the third direction D 3 may be different from each other. For example, the lateral lengths of the pads GP may be gradually decreased as they go from the fourth plane L 4 to the first plane L 1 in the first direction D 1.The pads GP and the horizontal layers HL may be spaced apart from each other. The pads GP may not be disposed in the first region CA.The pads GP, the upper horizontal lines G 1, and the lower horizontal lines G 2 may include the same material. The pads GP, the upper horizontal lines G 1, and the lower horizontal lines G 2 may include a metal-based material. For example, the pads GP, the upper horizontal lines G 1, and the lower horizontal lines G 2 may include titanium nitride, tungsten, or a combination thereof.The second region CTA may include contact plugs WC 1, WC 2, WC 3, and WC 4 coupled to the second conductive lines DWL of the pad portion WLE, respectively.The second region CTA may include the pad portion WLE in which the first conductive lines DWL and the inter-cell dielectric layers IL are alternately stacked. The second region CTA may include an array of contact plugs WC 1, WC 2, WC 3, and WC 4 disposed in the pad portion WLE, laterally spaced apart from each other in the second horizontal direction (i.e., the third direction D 3), and having different heights. The upper surfaces of the contact plugs WC 1, WC 2, WC 3, and WC 4 may be disposed on the same horizontal plane, and the lower portions of the contact plugs WC 1, WC 2, WC 3, and WC 4 may be adjacent to the second conductive lines DWL, respectively.The first contact plug WC 1 may be electrically connected to the second conductive line DWL of the first plane L 1. The first contact plug WC 1 may be electrically connected to the upper horizontal line G 1 of the first plane L 1. The second contact plug WC 2 may be electrically connected to the second conductive line DWL of the second plane L 2. The second contact plug WC 2 may be electrically connected to the upper horizontal line G 1 of the second plane L 2 by passing through the cell insulating layer IL. The third contact plug WC 3 may be electrically connected to the second conductive line DWL of the third level L 3. The third contact plug WC 3 may be electrically connected to the upper horizontal line G 1 of the third level L 3 by passing through the cell insulating layer IL. The fourth contact plug WC 4 may be electrically connected to the second conductive line DWL of the fourth level L 4. The fourth contact plug WC 4 may be electrically connected to the upper horizontal line G 1 of the fourth level L 4 by passing through the cell insulating layer IL.The vertical height of the fourth contact plug WC 4 may be greater than the vertical height of the third contact plug WC 3, and the vertical height of the third contact plug WC 3 may be greater than the vertical height of the second contact plug WC 2. The vertical height of the second contact plug WC 2 may be greater than the vertical height of the first contact plug WC 1. Here, the vertical height may refer to the height in the first direction D 1.As described above, the pad portion WLE of the second conductive lines DWL may have a staircase structure.FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device 200 according to another embodiment of the present disclosure.Referring to FIG. 3, the semiconductor device 200 may include a memory cell array MCA, a peripheral circuit region PA 1, and a dummy region PA 2. The memory cell array MCA may be disposed at a higher level than the peripheral circuit area PA 1. The dummy region PA 2 may be horizontally spaced apart from the memory cell array MCA. For the detailed description of the memory cell array MCA of FIG. 3, reference may be made to FIGS. 2A to 2D.The memory cell array MCA and the dummy region PA 2 may be formed on a first substrate W 1. The peripheral circuit region PA 1 may be formed on a second substrate W 2. The memory cell array MCA may include a three-dimensional array of memory cells MC, which may include a column array of memory cells MC and a row array of memory cells MC. For the detailed description of the memory cells MC, reference may be made to FIGS. 1A to 1C. Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. According to another embodiment of the present disclosure, each memory cell MC may be identical to the memory cell MC 1 of FIG. 1D. The memory cell array MCA may include a plurality of first conductive lines BL vertically extending in the first direction D 1. The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in the first direction D 1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D 1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D 1. The memory cell array MCA may include an alternating stack of the second conductive lines DWL and the inter-cell dielectric layers IL stacked in the first direction D 1.The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may include memory cells MC formed therein, and the second region CTA may include cell contact plugs WC formed therein. In the second region CTA, a pad portion WLE of the second conductive lines DWL may be disposed, and the second conductive lines DWL of the pad portion WLE may be coupled to the cell contact plugs WC. The second conductive lines DWL of the pad portion WLE may have a staircase structure. An interlayer dielectric layer ILD may be formed over the pad portion WLE, and the cell contact plugs WC pass through the interlayer dielectric layer ILD.The peripheral circuit region PA 1 may include a semiconductor substrate, a metal interconnection structure, an insulation structure, a conductive structure, another memory, or a peripheral circuit portion.Referring to FIG. 3, the peripheral circuit region PA 1 may be disposed at a lower level than the memory cell array MCA. This may be referred to as a cellover PERI structure (cell-on-PERI structure or COP structure). The first substrate W 1 is reversed to connect the memory cell array MCA and the peripheral circuit region PA 1.The peripheral circuit region PA 1 may be coupled to the memory cell array MCA. The peripheral circuit portion PA 1 may include one or more control circuits for driving the memory cell array MCA. The one or more control circuits of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The one or more control circuits of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, and the like. The one or more control circuits of the peripheral circuit portion may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.For example, the peripheral circuit region PA 1 may include a plurality of control circuits formed over the second substrate W 2. For example, the peripheral circuit region PA 1 may include sub word line drivers SWD and a sense amplifier SA. The second conductive lines DWL of the memory cell array MCA may be coupled to the sub-wordline drivers SWD. The first conductive lines BL of the memory cell array MCA may be coupled to the sense amplifier SA. The peripheral circuit portion PA 1 may further include a peripheral control circuit CL.The peripheral circuit region PA 1 and the memory cell array MCA may be coupled to each other through a bonding pattern WBD. The peripheral circuit region PA 1 and the dummy region PA 2 may be coupled to each other through a bonding pattern WBD and a first multilayer-level interconnection LML. The bonding pattern WBD may include a plurality of bonding pads CBD and PBD. The peripheral circuit region PA 1 and the memory cell array MCA may be coupled to each other through the bonding pattern WBD and the first multilayer-level interconnection LML.The bonding pads CBD and PBD may include first bonding pads CBD and second bonding pads PBD. The first bonding pads CBD and the second bonding pads PBD may be coupled to each other by wafer bonding. First bonding contact plugs CBC may be coupled to the first bonding pads CBD. Second bonding contact plugs PBC may be coupled to the second bonding pads PBD.The first conductive lines BL of the memory cell array MCA may be coupled to the first bonding pads CBD and the first bonding contact plugs CBC through the front-level interconnection FM 1. A front-level connector F 1B may be disposed between the first conductive lines BL and the front-level interconnect FM 1.The cell contact plugs WC of the memory cell array MCA may be coupled to the first bonding pads CBD and the first bonding contact plugs CBC through the front-level interconnection FM 1.The common plate PL of the data storage elements CAP of the memory cell array MCA may be coupled to a second multilayer-level interconnect UML through a nano-silicon via PC and a post-level interconnect PM (post-level interconnect). The nano-silicon vias PC may penetrate the back side of the first substrate W 1. Nanolevel spacers SP 2 may be formed on the sidewalls of the nano-silicon vias PC. The nanolevel spacers SP 2 may be disposed between the nano-silicon vias PC and the first substrate W 1. The nano-silicon vias PC may be coupled to the common plate line PL extending through the first substrate W 1 from the back side of the first substrate W 1. The nano-silicon vias PC are embedded in the first substrate W 1, and sidewalls of the nano-silicon vias PC are completely surrounded by and insulated from the first substrate W 1 by the nano-level spacers SP 2.The dummy region PA 2 may be disposed at a higher level than the peripheral circuit region PA 1. The dummy region PA 2 may include a dummy stack SG, a stack level plug FC passing through the dummy stack SG, and a stack level spacer SP 1 formed on the sidewall of the stack level plug FC. The stack level spacer SP 1 may include a dielectric material. The dummy stack SG may include silicon layers S 1 and S 3 and silicon germanium layers S 2 and S 4.The stack level spacers SP 1 may be disposed between the stack level connectors FC and the dummy stack SG. A stack of the silicon layers S 1 and S 3 and the silicon-germanium layers S 2 and S 4 may be disposed around the stack level plugs FC and the stack level spacers SP 1.The vertical height of the stack-level plug FC may be greater than the vertical height of the nano-silicon via PC.The second multi-layer level interconnect UML and the post-level interconnect PM may be coupled to an upper portion of the stack-level plug FC. The front-level interconnect FM 1 may be coupled to a lower portion of the stack-level connector FC. The stack-level plug FC may be coupled to the second multilayer-level interconnect UML through the nano-silicon via PC and the post-level interconnect PM. The front-level interconnect FM 1 may be coupled to the first bonding contact plugs CBC and the first bonding pads CBD. The peripheral control circuit CL may be coupled to the second bonding contact plugs PBC and the second bonding pads PBD through the first multilayer-level interconnection LML. The nano-silicon vias PC are embedded in the first substrate W 1, and sidewalls of the nano-silicon vias PC are completely surrounded by and insulated from the first substrate W 1 by the nano-level spacers SP 2.The sub-wordline drivers SWD and the sense amplifier SA may be coupled to the second bonding contact plugs PBC and the second bonding pads PBD through the first multilayer level interconnection LML.The nano-silicon via PC, the post-level interconnect PM, and the second multi-layer level interconnect UML may be the back side interconnect structure. The peripheral control circuit CL may be electrically coupled to the back side interconnect structure through a vertical path of the first multilayer-level interconnect LML, the bonding pattern WBD, and the stack-level connector FC.The semiconductor device 200 of FIG. 3 may have a COP structure, and the memory cell array MCA and the dummy region PA 2 may be disposed at a higher level than the peripheral circuit region PA 1. As described above, since the spacers SP 1 and SP 2 are formed on the sidewalls of the stack-level plug FC and the nano-silicon via PC, it is possible to prevent short-circuit between the stack-level plug FC and the nano-silicon via PC and the first substrate W 1. In addition, it is possible to prevent a short circuit between the stack-level connector FC and the nano-silicon via PC.FIGS. 4 to 22 illustrate a method of manufacturing a semiconductor device according to embodiments of the present disclosure.Referring to FIG. 4, a stack body SB may be formed over a first substrate 11. The first substrate 11 may include a semiconductor substrate. The stack body SB may include a plurality of sub-stacks that are alternately stacked. Each of the sub-stacks may include a first layer 12A, a second layer 13, a third layer 12B, and a provisional horizontal layer 14 stacked in the mentioned order. The first layer 12A and the third layer and 12B may be formed of the same material and may include silicon germanium. The second layers 13 may include monocrystalline silicon. The preliminary horizontal layers 14 may include monocrystalline silicon. The second layers 13 and the preliminary horizontal layers 14 may be made of the same material. The first layer 12A, the second layer 13, the third layer 12B, and the provisional horizontal layer 14 may be formed by an epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the provisional horizontal layer 14 may be thicker than the second layer 13.The stack body SB may include a plurality of preliminary horizontal layers 14, a first sacrificial layer stack SB 1, a second sacrificial layer stack SB 2, a third sacrificial layer stack SB 3, a fourth sacrificial layer stack SB 4, and a fifth sacrificial layer stack SB 5. The stack body SB may include the first sacrificial layer stack SB 1, the provisional horizontal layer 14, the second sacrificial layer stack SB 2, the provisional horizontal layer 14, the third sacrificial layer stack SB 3, the provisional horizontal layer 14, the fourth sacrificial layer stack SB 4, the provisional horizontal layer 14, and the fifth sacrificial layer stack SB 5 stacked in the mentioned order. The uppermost layer of the stack body SB may be the second layer 13. Each of the first to fifth sacrificial layer stacks SB 1 to SB 5 may be a three-layer stack of the first layer 12A, the second layer 13, and the third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a monocrystalline silicon layer, the first to fifth sacrificial layer stacks SB 1 to SB 5 may include a stack of a first silicon germanium layer, a monocrystalline silicon layer, and a second silicon germanium layer (SiGe / Si / SiGe). The fifth sacrificial layer stack SB 5 may be a quadruple layer of the first layer 12A / the second layer 13 / the third layer 12B / the second layer 13. The fifth sacrificial layer stack SB 5 may be used as a hard mask.The second layer 13 may include a first monocrystalline silicon layer and the preliminary horizontal layer 14 may include a second monocrystalline silicon layer. Accordingly, the stack body SB may include the first sacrificial layer stack SB 1 disposed below the second monocrystalline silicon layer and the second sacrificial layer stack SB 2 disposed above the second monocrystalline silicon layer. Each of the first and second sacrificial layer stacks SB 1 and SB 2 may include a stack of a first silicon-germanium layer, a first monocrystalline silicon layer, and a second silicon-germanium layer. The second monocrystalline silicon layer may be thicker than the first monocrystalline silicon layer.As described above with reference to the embodiments of the present disclosure, when the memory cells are stacked, the first sacrificial layer stack SB 1, the provisional horizontal layer 14, the second sacrificial layer stack SB 2, the provisional horizontal layer 14, the third sacrificial layer stack SB 3, the provisional horizontal layer 14, the fourth sacrificial layer stack SB 4, the provisional horizontal layer 14, and the fifth sacrificial layer stack SB 5 may be alternately stacked a plurality of times.According to another embodiment of the present disclosure, the preliminary horizontal layer 14 may include amorphous silicon or polysilicon.Referring to FIG. 5, portions of the stack body SB may be etched. As a result, a plurality of vertical openings 15 and 16 can be formed in the stack body SB. The vertical openings 15 and 16 may include first vertical openings 15 and second vertical openings 16. From the perspective of a plan view, the first vertical openings 15 and the second vertical openings 16 may be hole-shaped vertical openings. According to another embodiment of the present disclosure, the first vertical openings 15 and the second vertical openings 16 may be linear vertical openings.As described above, a hard mask layer pattern HM 1 may be formed to form the vertical openings 15 and 16, and the hard mask layer pattern HM 1 may be formed using a double patterning process.Referring to FIG. 6, a portion HT of the hard mask layer pattern HM 1 may be trimmed.Subsequently, the first layers 12A and the third layers 12B of FIG. 5 may be selectively removed through the vertical openings 15 and 16.In order to selectively remove the first layers 12A and the third layers 12B, the difference between the etch selectivities of the second layers 13 and the preliminary horizontal layers 14 and the etch selectivities of the first layers 12A and the third layers 12B may be used. The first layers 12A and the third layers 12B may be removed by a wet etching process or a dry etching process. For example, when the first layers 12A and the third layers 12B include a silicon germanium layer and the second layers 13 and the preliminary horizontal layers 14 include a silicon layer, the silicon germanium layers may be etched using an etchant or etching gas having selectivity with respect to the silicon layers.The second layers 13 can then be removed. The second layers 13 may be removed by a wet etching process or a dry etching process. According to an embodiment of the present disclosure, the preliminary horizontal layers 14 may be partially removed while the second layers 13 are removed. As a result, the second layers 13 can be removed and the preliminary horizontal layers 14 can become thin as indicated by a reference sign "14A". The recess process for forming the temporary horizontal sheets 14A, i.e., the temporary horizontal sheet patterns 14A, may be referred to as a thinning process or a trimming process of the temporary horizontal sheets 14. The preliminary horizontal layer patterns 14A may be referred to as an active layer of a thin body. The preliminary horizontal layer patterns 14A may include a monocrystalline silicon layer. While the preliminary horizontal layer patterns 14A are formed, the surface of the first substrate 11 may be recessed to a predetermined depth. The recess process for forming the preliminary horizontal layer patterns 14A may use Hot SC- 1 (HSC 1). HSC1may include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2) and water (H 2 O) are mixed in a ratio of about 1:4:20. The second layers 13 and the preliminary horizontal layers 14 may be selectively etched using the HSC1.As a result of the above-described recess process, the preliminary horizontal layer patterns 14A and wide recesses 17 can be formed. Each of the upper surface and the lower surface of the preliminary horizontal layer patterns 14A may include a flat surface.From the perspective of a plan view, the temporary horizontal layer patterns 14A may have a cross shape. The side surfaces of the temporary horizontal layer patterns 14A may have a curved shape or a rounded shape.After the preliminary horizontal layer patterns 14A are formed, the vertical openings 15 and 16 may be widened.Referring to FIG. 7, first dielectric layers 18 may be formed to completely cover the preliminary horizontal layer patterns 14A. The first dielectric layers 18 may include silicon nitride.While the first dielectric layers 18 are formed, a dummy dielectric layer 18D may be formed on the surface of the first substrate 11.Subsequently, a second dielectric layer 19 may be formed over the first dielectric layers 18. The second dielectric layer 19 may fill between the vertically adjacent first dielectric layers 18. The second dielectric layer 19 may include silicon oxide. Portions of the second dielectric layer 19 may be conformally formed on the surfaces of the vertical openings 15 and 16. Each of the wide recesses 17 of FIG. 6 may be filled with the first dielectric layer 18 and the second dielectric layer 19.The first dielectric layers 18 may surround the preliminary horizontal layer pattern 14A, and the second dielectric layers 19 may surround the first dielectric layers 18.Sacrificial columns 20 may then be formed over the second dielectric layers 19 disposed in the vertical openings 15 and 16. The sacrificial columns 20 may contain amorphous carbon. Further, according to another embodiment of the present disclosure, a pillar capping layer may be formed over the sacrificial pillars 20. The pillar covering layer may include a metal-based material. The pillar cap layer may include titanium nitride.The second dielectric layers 19 and the sacrificial pillars 20 may form first and second sacrificial pillar structures SV 1 and SV 2 filling the vertical openings 15 and 16. The first sacrificial pillar structure SV 1 may fill the first vertical openings 15, and the second sacrificial pillar structure SV 2 may fill the second vertical openings 16. The sacrificial pillars 20 may not be formed between the first dielectric layers 18 that are vertically stacked. According to another embodiment of the present disclosure, each of the first and second sacrificial pillar structures SV 1 and SV 2 may include a dielectric material, a carbonaceous material, a metal-based material, or a combination thereof. Each of the first and second sacrificial pillar structures SV 1 and SV 2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.As the preliminary horizontal layer patterns 14A, the first dielectric layers 18 and the second dielectric layers 19 are formed, and a cell shape structure MD may be formed. The cell form structure MD may include a variety of cell forms. Each cell form may include a plurality of forming layers. For example, each cell shape may include a first shape layer, a second shape layer, a third shape layer, a fourth shape layer, and a fifth shape layer, which are sequentially stacked. The first mold layer and the fifth mold layer may correspond to the second dielectric layers 19. The second mold layer and the fourth mold layer may correspond to the first dielectric layers 18. The third shape layer may correspond to the preliminary horizontal layer pattern 14A. Each cell form may include an ONSNO stack. Here, the ONSNO stack may refer to a structure in which a first oxide, a first nitride, a monocrystalline silicon layer, a second nitride, and a second oxide are sequentially stacked. First and second silicon oxides may correspond to the second dielectric layers 19, and first and second silicon nitrides may correspond to the first dielectric layers 18. The monocrystalline silicon layer may correspond to the preliminary horizontal layer patterns 14A.By a series of the processes illustrated in FIGS. 4 to 7 described above, the sub-stacks SB 1 to SB 5 of the stack body SB may be replaced with cell shapes. The first layer 12A, the second layer 13, and the third layer 12B of each of the sub-stacks SB 1 to SB 5 may be replaced with the first dielectric layers 18 and the second dielectric layers 19. The provisional horizontal layer 14 may become the provisional horizontal layer pattern 14A.Referring to FIG. 8, the hard mask layer pattern HM 1 of FIG. 7 may be removed to form a hard mask layer level opening HM'.Referring to FIG. 9, the upper dielectric layers HM may fill the hard mask layer level opening HM' of FIG. 8. The upper dielectric layers HM may include silicon oxide.Referring to FIG. 10, the second sacrificial pillar structures SV 2 of FIG. 9 may be removed to form first hole-shaped vertical openings 21. The first hole-shaped vertical openings 21 may be formed by selectively etching the second dielectric layer 19 and the sacrificial pillars 20.Subsequently, the second dielectric layers 19 may be horizontally recessed. Subsequently, the first dielectric layers 18 may be horizontally recessed. The recess amount of the first dielectric layers 18 may be larger than the recess amount of the second dielectric layers 19. A portion of the first dielectric layers 18 may be recessed to form a dummy dielectric layer 18D on the substrate 11.As a result of the recess process of the first dielectric layers 18, the first dielectric layer level recesses 22 may be formed. Portions of the preliminary horizontal layer patterns 14A may be exposed by the first dielectric layer level recesses 22.Referring to FIG. 11, first vertical sacrificial structures 23 may be formed to fill the first dielectric layer level recesses 22 and the first hole-shaped vertical openings 21 of FIG. 10. The first vertical sacrificial structure 23 may include a dielectric material. The first vertical sacrificial structure 23 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. Each of the first sacrificial vertical structures 23 may include a body portion filling the first hole-shaped vertical openings 21 and extended portions 23A filling the first dielectric layer-level recesses 22.Referring to FIG. 12, the sacrificial column 20 of the first sacrificial column structure SV 1 of FIG. 11 may be removed to form a vertical plane path 24.Subsequently, to form a bottom level gap 25, the dummy dielectric layer 18D under the vertical level path 24 of FIG. 11 may be removed.Referring to FIG. 13, a portion of the second dielectric layers 19 may be cut to form second hole-shaped vertical openings 26.Subsequently, a first passivation layer BF 1 may be formed to fill the lower level gap 25 of FIG. 12. The first passivation layer BF 1 may include silicon oxide. Forming the first passivation layer BF 1 may include depositing silicon oxide to fill the lower level gap 25 and etching the silicon oxide. Subsequently, a second passivation layer BF 2 may be formed by oxidizing the surface of the first substrate 11.Referring to FIG. 14, the first dielectric layers 18 of FIG. 13 may be removed to form horizontal plane recesses 27. Portions of the temporary horizontal layer patterns 14A may be exposed by the horizontal plane recesses 27. A portion of a preliminary horizontal layer pattern 14A may be exposed by a pair of the horizontal plane recesses 27.Referring to FIG. 15, an inter-level dielectric layer 28 may be formed over the exposed portions of the preliminary horizontal layer patterns 14A. The inter-level dielectric layer 28 may be formed by oxidizing the surface of the preliminary horizontal layer patterns 14A. According to another embodiment of the present disclosure, the inter-level dielectric layer 28 may be formed by a deposition process of silicon oxide.The inter-level dielectric layer 28 may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an antiferromagnetic material, or a combination thereof. The inter-level dielectric layer 28 may include SiO 2, Si 3 N 4, HfO 2, Al 2 O 3, ZrO 2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.Referring to FIG. 16, a horizontal conductive line 29 may be formed over the inter-level dielectric layer 28 to fill the horizontal level recesses 27. Forming the horizontal conductive line 29 may include depositing a conductive material to fill the horizontal level recesses 27 over the inter-level dielectric layer 28 and performing an etch back process of the conductive material. The horizontal conductive line 29 may include a pair of first and second horizontal conductive lines 29A and 29B facing each other with the semiconductor layer pattern 14A interposed therebetween. The first and second horizontal conductive lines 29A and 29B may include a metal-based material, a semiconductor material, or a combination thereof. The first and second horizontal conductive lines 29A and 29B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first and second horizontal conductive lines 29A and 29B may include a titanium nitride and tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The first and second horizontal conductive lines 29A and 29B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less. The P-type work function material may have a high work function of about 4.5 eV or more. As illustrated in FIGS. 1A to 1C, each of the first and second horizontal conductive lines 29A and 29B may have a cross shape and include a channel overlapping portion WLP. The horizontal conductive line 29 may correspond to the second conductive line DWL as illustrated in FIGS. 1A to 3. The first and second horizontal conductive lines 29A and 29B may correspond to the upper and lower horizontal lines G 1 and G 2, as illustrated in FIGS. 1A to 2D.Referring to FIG. 17, a vertical conductive line 33 commonly coupled to the preliminary horizontal layer patterns 14A may be formed. The vertical conductive line 33 may fill the second hole-shaped vertical openings 26 of FIG. 16. The vertical conductive line 33 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive line 33 may include a bit line. The vertical conductive line 33 may correspond to the first conductive line BL as illustrated in FIGS. 1A to 3B.Before the vertical conductive line 33 is formed, a first contact node 31 may be formed. The first contact node 31 may include a metal-based material or a semiconductor material. The first contact node 31 may include doped polysilicon. Impurities may be diffused from the first contact node 31, thereby forming first doped regions 32 on one side of the preliminary horizontal layer patterns 14A.Before the first contact node 31 is formed, a first capping layer 30 may be formed. The first cover layer 30 may be formed on one side of the horizontal conductive line 29. The first capping layer 30 may include silicon oxide, silicon nitride, or a combination thereof.Referring to FIG. 18, the body portion of the first vertically sacrificial structure 23 of FIG. 17 may be removed to form the enlarged hole-shaped openings 34'. Subsequently, a third passivation layer BF 3 may be formed on the surface of the first substrate 11. The third passivation layer BF 3 may include silicon oxide.Subsequently, to form memory openings 35, the extended portion of the first sacrificial vertical structure 23 and the preliminary horizontal layer patterns 14A may be trimmed, i.e., trimmed, horizontally from the extended hole-shaped openings 34'. The extended portion of the first vertically sacrificial structure 23 remaining after the memory openings 35 are formed may be referred to simply as the first capping layer 34, and the remaining preliminary horizontal layer patterns 14A may be referred to simply as the horizontal layer HL. The horizontal layer HL may have a cross shape from the perspective of a plan view.Referring to FIG. 19, a second contact node 36 may be formed over a second edge of the horizontal layer HL. The second contact node 36 may include doped polysilicon. Impurities may be diffused from the second contact node 36, thereby forming second doped regions 37 on a second side of the horizontal layer HL. The second contact node 36 may be referred to as an inner contact node.The horizontal layer HL may include a first doped region 32, a second doped region 37, and a channel 38. The channel 38 may be defined between the first doped region 32 and the second doped region 37. The channel 38 may vertically overlap the horizontal conductive line 29. The channel 38 may correspond to the channel CH, as illustrated in FIGS. 1A to 2D.Referring to FIG. 20, a first electrode 39 of a data storage element may be formed over the second contact node 36. The first electrode 39 may have a horizontally oriented cylindrical shape.Referring to FIG. 21, the second dielectric layers 19 may be horizontally recessed (see a reference sign "40"). As a result, the outer walls of the first electrodes 39 may be exposed.Referring to FIG. 22, a dielectric layer 41 and a second electrode 42 may be sequentially formed over the first electrodes 39. The first electrode 39, the dielectric layer 41, and the second electrode 42 may become a data storage element CAP.The first electrode 39 may include an interior space and a plurality of outer surfaces. The interior of the first electrode 39 may include a plurality of inner surfaces. The outer surfaces of the first electrode 39 may include vertical outer surfaces and a plurality of horizontal outer surfaces. The inner space of the first electrode 39 may be a three-dimensional space. The dielectric layer 41 may conformally cover the inner surfaces and the outer surfaces of the first electrode 39. The second electrode 42 may be disposed in the inner space of the first electrode 39 over the dielectric layer 41. Some of the outer surfaces of the first electrode 39 may be coupled to the horizontal layer HL.The first electrode 39 may have a cylindrical shape. The cylindrical shape of the first electrode 39 may include inner cylindrical surfaces and outer cylindrical surfaces. The dielectric layer 41 and the second electrode 42 may be disposed on the cylindrical inner surfaces of the first electrode 39.Each of the first electrode 39 and the second electrode 42 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, each of the first electrode 39 and the second electrode 42 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2), iridium (Ir), iridium oxide (IrO 2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a titanium nitride / titanium silicon nitride (TiN / TiSiN) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 42 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 42 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the interior of the first electrode 39, titanium nitride (TiN) may serve as the second electrode 42 of the data storage element CAP, and tungsten nitride may be a low resistance material.The dielectric layer 41 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 41 may include silicon oxide, silicon nitride, a high-k material, a perovskite material, a ferroelectric material, an antiferromagnetic material, or a combination thereof. The dielectric layer 41 may include a high-k material such as hafnium oxide (HfO 2), zirconium oxide (ZrO 2), aluminum oxide (Al 2 O 3), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), tantalum oxide (Ta 2 O 5), niobium oxide (Nb 2 O5), or strontium titanium oxide (SrTiO3). The dielectric layer 41 may include a ZA (ZrO 2 / Al 2 O 3)- stack, a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2)- stack, a ZAZA (ZrO 2 / Al 2 O 3 / ZrO2 / Al2O3) stack, A ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2)- stack, an HA (HfO 2 / Al 2 O 3)- stack, an HAH (HfO2 / Al2O3 / HfO2) stack, an HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3)- stack, an HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al2O3 / HfO2) stack, an HZAZH(HfO 2 / ZrO 2 / Al2O 3 / ZrO 2 / HfO 2)- stack, a ZHZAZHZ(ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO2 / HfO2 / ZrO2) stack, HZHZ(HfO 2 / ZrO2 / HfO 2 / ZrO 2)- stack or an AHZAZHA(Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO2 / Al2O3) stack.Further, according to another embodiment of the present disclosure, an interfacial control layer may be formed between the first electrode 39 and the dielectric layer 41 to alleviate the leakage current. The interfacial control layer may include titanium oxide (TiO 2), tantalum oxide (Ta 2 O 5), niobium oxide (Nb 2 O 5), niobium nitride (NbN), or a combination thereof. The interfacial control layer may also be formed between the second electrode 42 and the dielectric layer 41.FIGS. 23 to 27 illustrate a method of forming a pad portion according to an embodiment of the present disclosure. FIGS. 23 to 27 illustrate a method of forming a pad portion according to the line B-B' shown in FIG. 2A. The pad portion forming process may be performed after the vertical conductive line 33 illustrated in FIG. 17 is formed.Referring to FIGS. 4 to 17, after the horizontal conductive lines 29 and the vertical conductive line 33 are formed, the pad portion may be formed at an edge of one side of the horizontal conductive lines 29.Referring to FIG. 23, the horizontal conductive lines 29 may include a pair of a first horizontal conductive line 29A and a second horizontal conductive line 29B. A plurality of horizontal conductive lines 29 may be stacked in the first direction D 1. The preliminary horizontal layer pattern 14A and the inter-plane dielectric layer 28 may be formed in the first region CA and the second region CTA, respectively. Second dielectric layers 19 may be formed between the horizontal conductive lines 29.Referring to FIG. 24, the horizontal conductive lines 29 and the second dielectric layers 19 may be etched to form a pad isolation slot WSM in the second region CTA.The inter-level dielectric layer 28 and the preliminary horizontal layer patterns 14A of FIG. 23 may be removed by the pad isolation slot WSM. As a result, pad-shaped recesses PD' can be formed between the first horizontal conductive line 29A and the second horizontal conductive line 29B.Referring to FIG. 25, pads GP filling the pad-shaped recesses PD' of FIG. 24 may be formed.Each horizontal conductive line 29 may include a pair of the first horizontal conductive line 29A and the second horizontal conductive line 29B. Each pad GP may be electrically connected to the first horizontal conductive line 29A and the second horizontal conductive line 29B.The pads GP, the first horizontal conductive lines 29A, and the second horizontal conductive lines 29B may include the same material. The pads GP, the first horizontal conductive lines 29A, and the second horizontal conductive lines 29B may include a metal-based material. For example, the pads GP, the first horizontal conductive lines 29A, and the second horizontal conductive lines 29B may include titanium nitride, tungsten, or a combination thereof. The pads GP, the first horizontal conductive lines 29A, and the second horizontal conductive lines 29B may include a metal-based material.After the pads GP are formed, a slot WSL filling the pad isolation slot WSM may be formed. The slot WSL may include a dielectric material.Referring to FIG. 26, the pads GP, the first horizontal conductive lines 29A, and the second horizontal conductive lines 29B may be etched to form a staircase structure STP.Referring to FIG. 27, after an interlayer dielectric layer ILD covering the staircase structure STP is formed, cell contact plugs WC coupled to the horizontal conductive lines 29 of the respective planes may be formed. The cell contact plugs WC may include a metal-based material.A memory cell array may be formed in the first substrate 11 by a series of processes illustrated in FIGS. 4 to 27. Hereinafter, for the detailed description of the constituent elements of the memory cell array, reference may be made to FIGS. 1A to 27.FIGS. 28 to 33 illustrate a method of manufacturing the semiconductor device shown in FIG. 3.Referring to FIG. 28, a first substrate W 1 including a memory cell array MCA and a dummy stack SG may be prepared. The dummy stack SG may include silicon layers and silicon-germanium layers. The dummy stack SG may correspond to the stack body SB as illustrated in FIG. 4. Hereinafter, for the detailed description of the constituent elements of the memory cell array MCA and the dummy stack SG, reference may be made to FIGS. 1A to 27. The memory cell array MCA may include a first region CA and a second region CTA.A plurality of contact holes C 1 and C 2 may be formed. The contact holes may include a first contact hole C 1 and second contact holes C 2. The first contact hole C 1 may be formed in the first region CA of the memory cell array MCA, and the second contact holes C 2 may be formed in the second region CTA of the memory cell array MCA. The first contact hole C 1 may expose an upper portion of a first conductive line BL of the memory cell array MCA. The second contact holes C 2 may expose the steps of the second conductive lines DWL of the pad portion.A front plane plug F 1B may be formed in the first contact hole C 1, and cell contact plugs WC may be formed in the second contact holes C 2.After forming the front plane plug F 1B and the cell contact plugs WC, a third contact hole C 3 may be formed in the dummy region PA 2. The third contact hole C 3 may pass through the dummy stack SG of the dummy region PA 2 and may extend into the inside of the first substrate W 1. The third contact hole C 3 may be referred to as a stack-level contact hole.Referring to FIG. 29, a stack-level plug FC may be formed in the third contact hole C 3. Before the stack-level plug FC is formed, a stack-level spacer SP 1 may be formed on a sidewall of the third contact hole C 3 of FIG. 28.Referring to FIG. 30, front-level interconnects FM 1 may be formed over the front-level connector F 1B and the cell contact connector WC. The front level interconnects FM1 may be formed over the stack level connector FC. The front-level interconnections FM 1 may be formed over the memory cell array MCA and the dummy region PA 2.First bonding contact plugs CBC and first bonding pads CBD may be sequentially formed over the front-level interconnections FM 1.Referring to FIG. 31, a peripheral circuit region PA 1 may be prepared. The peripheral circuit region PA 1 may be formed with a peripheral control circuit CL, a sub-word line driver SWD, and a sense amplifier SA over a second substrate W 2. The peripheral control circuit CL, the sub word line driver SWD, and the sense amplifier SA may include transistors.A first multilayer level interconnection LML may be formed over the peripheral control circuit CL, the sub word line driver SWD, and the sense amplifier SA.Second bonding contact plugs PBC and second bonding pads PBD may be sequentially formed over the first multilayer-level interconnection LML.Referring to FIG. 32, a wafer bonding process may be performed to bond the memory cell array MCA and the peripheral circuit region PA 1. For example, the first substrate W 1 may be reversed to connect the memory cell array MCA and the peripheral circuit region PA 1 to each other. In addition, the first substrate W 1 may be turned over to connect the dummy region PA 2 and the peripheral circuit region PA 1. The memory cell array MCA and the peripheral circuit portion PA 1 may be connected through the bonding pattern WBD of the first bonding pads CBD and the second bonding pads PBD. The dummy region PA 2 and the peripheral circuit region PA 1 may be connected through the bonding pattern WBD of the first bonding pads CBD and the second bonding pads PBD.Subsequently, a plurality of nano through holes NT may be formed on the back surface of the first substrate W 1. The nano through holes NT may be formed by partially etching the back surface of the first substrate W 1.The nano through holes NT may expose the back surfaces of the common plates PL and the stack-level connectors FC.Referring to FIG. 33, a nano-silicon via PC and post-level interconnects PM may be formed. The nano-silicon via PC may fill the nano-vias NT. Before the nano-silicon vias PC are formed, a nano-level spacer SP 2 may be formed on the sidewalls of the nano-vias NT.A second multi-layer level interconnect UML may be formed over the post-level interconnects PM.The common plate PL of the data storage elements CAP of the memory cell array MCA may be coupled to the second multilayer-level interconnect UML through the nano-silicon via PC and the post-level interconnect PM. The nano-silicon via PC may penetrate the back surface of the first substrate W 1. The nanolevel spacers SP 2 may be formed on the sidewalls of the nano-silicon vias PC.The stack-level plug FC may be coupled to the second multilayer-level interconnect UML through the nano-silicon via PC and the post-level interconnect PM.FIGS. 34 to 36 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.Referring to FIG. 34, a stack body SB 10 may be formed over the first substrate 11. The stack body SB 10 may include an alternating stack of first semiconductor layers and second semiconductor layers. For example, the alternating stack may include a plurality of silicon-germanium layers 12 and a plurality of monocrystalline silicon layers 14' alternately stacked by an epitaxial growth process. The silicon-germanium layers 12 may be sacrificial layers, and the monocrystalline silicon layers 14' may be recess target layers. The silicon-germanium layers 12 may correspond to the first layers 12A or the third layers 12B of FIG. 4, and the monocrystalline silicon layers 14' may correspond to the fourth layers 14 of FIG. 4. Unlike the stack body SB of FIG. 4, the stack body SB 10 may include an alternating stack of the silicon-germanium layers 12 and the monocrystalline silicon layers 14'.Referring to FIG. 35, a hard mask layer pattern HM 1 may be formed over the stack body SB 10.Subsequently, the stack body SB 10 may be etched using the hard mask layer pattern HM 1 as an etching barrier. As a result, a plurality of first and second vertically sacrificial openings 15 and 16 may be formed in the stack body SB 10.Referring to Fig. 36, preliminary horizontal layers 14A' and horizontal recesses 17 may be formed. The preliminary horizontal layers 14A' and the horizontal recesses 17 may be formed by a recess process of the silicon-germanium layers 12 and the monocrystalline silicon layers 14' of FIG. 35. After the silicon-germanium layers 12 are removed, a recess process of the monocrystalline silicon layers 14' may be performed. The preliminary horizontal layers 14A' may correspond to the preliminary horizontal layers 14A of FIG. 6.The silicon-germanium layers 12 may be recessed by a wet etching process or a dry etching process. The silicon-germanium layers 12 may be etched using an etchant or etching gas with selectivity with respect to the monocrystalline silicon layers 14'.The recess process of the monocrystalline silicon layers 14' for forming the preliminary horizontal layers 14A' may use, for example, Hot SC-1 (HSC1). HSC1may include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2) and water (H 2 O) are mixed in a ratio of about 1:4:20. The monocrystalline silicon layers 14' can be selectively etched using the HSC1.While the preliminary horizontal layers 14A' are formed, the surface of the first substrate 11 may be recessed to a predetermined depth (see a reference numeral "11A"). As a result, the depths of the first and second vertically sacrificial openings 15 and 16 can be increased.Subsequently, a series of the processes illustrated in FIGS. 8 to 22 may be performed.FIGS. 37 to 39 are perspective views illustrating memory cell arrays according to other embodiments of the present disclosure. The memory cell arrays MCA 100, MCA 200, and MCA 300 may be similar to the memory cell array MCA of FIG. 2C. Hereinafter, for detailed description of the constituent element that also appears in FIG. 2C, reference may be made to the above-described embodiments of the present disclosure.Referring to FIG. 37, the memory cell array MCA 100 may include a plurality of memory cells MC 10.The memory cell array MCA 100 may include a three-dimensional array of the memory cells MC 10, which may include a column array of memory cells MC 10 and a row array of memory cells MC 10. The column array of the memory cells MC 10 may include a plurality of memory cells MC 10 stacked in the first direction D 1. The row array of the memory cells MC 10 may include a plurality of memory cells MC 10 horizontally arranged in the second direction D 2 and the third direction D 3.Each memory cell MC 10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For the detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above-described embodiments of the present disclosure.The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D 2. The second conductive line DWL may extend in the third direction D 3.The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G 1 and a lower horizontal line G 2 facing each other with the horizontal layer HL interposed therebetween. As illustrated in FIG. 1B, an inter-level dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL.Each of the upper horizontal line G 1 and the lower horizontal line G 2 may include a pair of flat side walls FSW extending in the third direction D 3. The flat side walls FSW may refer to the vertical side walls. The flat side walls FSW may have a linear shape extending in the third direction D 3.Referring to FIG. 38, the memory cell array MCA 200 may include a plurality of memory cells MC 20.The memory cell array MCA 200 may include a three-dimensional array of memory cells MC 20. The three-dimensional array of memory cells MC 20 may include a column array of memory cells MC 20 and a row array of memory cells MC 20. The column array of the memory cells MC 20 may include a plurality of memory cells MC 20 stacked in the first direction D 1. The row array of the memory cells MC 20 may include a plurality of memory cells MC 20 horizontally arranged in the second direction D 2 and the third direction D 3.Each memory cell MC 20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For the detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above-described embodiments of the present disclosure.The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D 2. The second conductive line SWL may extend in the third direction D 3.The second conductive line SWL may be a single structure. For example, the second conductive line SWL may be disposed over the horizontal layer HL. As illustrated in FIG. 3, an inter-level dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. According to another embodiment of the present disclosure, the second conductive line SWL may be disposed below the horizontal layer HL.The second conductive line SWL may include a pair of flat side walls FSW extending in the third direction D 3. The flat side walls FSW may refer to the vertical side walls.According to another embodiment of the present disclosure, the second conductive line SWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL, as illustrated in FIG. 1C.Referring to FIG. 39, the memory cell array MCA300 may include a plurality of memory cells MC30.The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC 30 may include a column array of memory cells MC 30 and a row array of memory cells MC 30. The column array of the memory cells MC 30 may include a plurality of memory cells MC 30 stacked in the first direction D 1. The row array of the memory cells MC 30 may include a plurality of memory cells MC 30 horizontally arranged in the second direction D 2 and the third direction D 3.Each memory cell MC 30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For the detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above-described embodiments of the present disclosure.The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D 2. The second conductive line GAA-WL may extend in the third direction D 3.The second conductive line GAA-WL may be a gate all around structure GAA (a gate all around structure GAA). For example, the second conductive line GAA-WL may extend in the third direction D 3 while surrounding the horizontal layers HL. An inter-level dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The inter-level dielectric layer GD may surround each of the horizontal layers HL.The second conductive line GAA- WL may include a pair of flat side walls FSW extending in the third direction D 3. The flat side wall FSW may refer to a vertical side wall.According to another embodiment of the present disclosure, each memory cell may include a first conductive line BL horizontally extending in the third direction D 3, a second conductive line DWL vertically extending in the first direction D 1, and a horizontal layer HL horizontally extending in the second direction D 2. The second conductive line DWL may have a double structure and may be replaced with a single structure or a gate all around structure.FIG. 40 is a cross-sectional view illustrating a memory cell array MCA 400 according to another embodiment of the present disclosure.The memory cell array MCA400 of FIG. 40 may be similar to the memory cell array MCA of FIGS. 2A to 2D. Hereinafter, detailed description of the constituent elements of the memory cell array MCA400 that also appear in the memory cell array MCA of FIGS. 2A to 2D may be omitted.Referring to FIG. 40, a buried buffer layer BBF may completely cover the upper surface of a first substrate W 1. The buried buffer layer BBF may include an oxide such as silicon oxide. The first substrate W 1 and the buried buffer layer BBF may have a silicon-on-insulator (SOI) structure.FIGS. 41 to 44 schematically illustrate a semiconductor device according to another embodiment of the present disclosure.Referring to FIGS. 41 to 44, each of the semiconductor devices 300, 310, 300A, and 310A may include a memory cell array MCA, a peripheral circuit PERI, and a back side interconnection structure BSPDN. The semiconductor device 300, 310, 300A, and 310A may further include a bonding pattern WBD disposed between the memory cell array MCA and the peripheral circuit PERI. The semiconductor device 300 of FIG. 41 and the semiconductor device 310 of FIG. 42 may include the same constituent elements except for the buffer layer BF and the buried buffer layer BF 10. The semiconductor device 300A of FIG. 43 and the semiconductor device 310A of FIG. 44 may include the same constituent elements except for the buffer layer BF and the buried buffer layer BF 10. The semiconductor device 300, 310, 300A, and 310A may exclude the dummy stack SG illustrated in FIG. 3.The memory cell array MCA may be similar to the memory cell array MCA of FIGS. 2A to 2D. Hereinafter, for the detailed description of the constituent elements of the memory cell array MCA, reference may be made to FIGS. 2A to 2D. The memory cell array MCA may include a first substrate W 10, a plurality of memory cells MC, and a front multilevel metal line FMLM.The memory cell array MCA may include a first region R 1 and a second region R 2. The first region R 1 may be a region in which memory cells MC are formed, and the second region R 2 may be a region in which cell contact plugs coupled to the memory cells MC are formed. The second region R 2 of the semiconductor devices 300 and 310 may include a staircase pad portion. The second region R 2 of the semiconductor devices 300A and 310A may include a staircaseless pad portion.The memory cells MC may be disposed over the first substrate W 10. The front multilevel metal line FMLM may be disposed over the memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of the memory cells MC may include a plurality of memory cells MC stacked in the first direction D 1. The row array of the memory cells MC may include a plurality of memory cells MC horizontally arranged in the second direction D 2 and the third direction D 3. The memory cell arrays may be vertically stacked in the first direction D 1 over the first substrate W 10. According to another embodiment of the present disclosure, the memory cell arrays may be horizontally arranged in the second direction D 2 above the first substrate W 10. The memory cell arrays may include a buried gate-based dynamic random access memory (DRAM), a three-dimensional (3D) DRAM, a 3D NAND, a flash memory, a spin transfer torque random access memory (STT-RAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a thyristor, a vertical gate-based DRAM, and the like. The front multilevel metal line FMLM may include a plurality of metal lines and a plurality of vias. The memory cell array MCA may include a plurality of upper dielectric layers TIL 1, TIL 2, and TIL 3. The upper surfaces of the first conductive line BL and the common plate PL may be disposed on the same plane as the upper surface of the upper dielectric layer TIL 2. The front multiple plane metal line FMLM of the memory cell array MCA may include front plane connectors F 1B, front plane interconnects FM 1, front plane connectors F 2C, and front plane interconnects FM 2. The front-level connectors F 1B may penetrate the upper dielectric layer TIL 3 to be coupled to the first conductive line BL and the common plate PL, respectively. The front-level interconnections FM 2 may be coupled to the first bonding contact plugs CBC and the first bonding pads CBD, respectively.Referring to FIGS. 41 and 42, in the second region R 2 of the memory cell array MCA, a respective pad portion of the staircase-shaped pad portion may include an upper horizontal line G 1, a lower horizontal line G 2, and a pad GP between the upper horizontal line G 1 and the lower horizontal line G 2. The pad portions of the staircase pad portion may have different horizontal lengths. Inter-cell dielectric layers IL may be disposed between the pad portions. The inter-cell dielectric layers IL may include silicon oxide. The inter-cell dielectric layers IL may be referred to as horizontal inter-cell dielectric layers. The staircase pad portion upper horizontal lines G 1 may be coupled to the first front contact plugs F 1C and the first front plane interconnect FM 1, respectively. The front contact plugs F 1C may be referred to as cell contacts. The first front contact plugs F 1C may penetrate the upper dielectric layers TIL 1, TIL 2, and TIL 3 and the interlayer dielectric layer ILD. The first front contact plugs F 1C may correspond to the cell contact plugs WC of FIG. 3.Referring to FIGS. 43 and 44, in the second region R 2 of the memory cell array MCA, a respective pad portion of the staircaseless pad portion may include an upper horizontal line G 1, a lower horizontal line G 2, and a pad GP between the upper horizontal line G 1 and the lower horizontal line G 2. The pad portions of the staircaseless pad portion may have the same horizontal length. The staircaseless pad portion upper horizontal lines G1 may be coupled to the first front contact plugs F1C and front plane interconnects FM1, respectively. Sidewall spacers F 1S may be formed on the sidewalls of the first front contact plugs F 1C. The sidewall spacers F 1S may include a dielectric material.A buffer layer BF may be disposed on the lower surface of the first conductive line BL and the lower surface of the common plate PL. The buffer layer BF may include an oxide such as silicon oxide. The semiconductor device 310 of FIG. 42 may include a buried buffer layer BF 10 completely covering the upper surface of the first substrate W 10. The buried buffer layer BF 10 may include an oxide such as silicon oxide. The first substrate W 10 and the buried buffer layer BF 10 may have a silicon-on-insulator (SOI) structure.The peripheral circuit CL may include a second substrate W 20, a plurality of control circuits CL, SA, and SWD disposed on a lower-level surface of the second substrate W 20, and a multi-level metal line MLM coupled to the control circuits CL, SA, and SWD. The multi-level metal line MLM may include a plurality of metal lines MT 1 to MT 5 and a plurality of metal contact plugs M 1C to M 5C. The multi-level metal line MLM may include at least a first level metal line MT 1 and a first level metal contact plug M 1C. The first level metal line MT 1 and the first level metal contact plug M 1C may be coupled to the control circuits CL, SA, and SWD.The peripheral circuit PERI may include at least one or more control circuits for driving the memory cell array MCA. The one or more control circuits of the peripheral circuit PERI may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The one or more control circuits of the peripheral circuit PERI may include an address decoder circuit, a read circuit, a write circuit, and the like. The one or more control circuits of the peripheral circuit PERI may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.For example, the peripheral circuit PERI may include a common plate control circuit CL, sub word line drivers SWD, and a sense amplifier SA. A first conductive line BL of the memory cell array MCA may be coupled to the sense amplifier SA. Second conductive lines DWL may be coupled to the sub-wordline drivers SWD. The common plates PL may be coupled to the common plate control circuit CL. Each of the transistors for the common plate control circuit CL, the sub-word line drivers SWD, and the sense amplifier SA may include a gate, a gate spacer, and source / drain.The back side interconnect structure BSPDN may include the second substrate W 20, a power interconnect line PIL embedded in the second substrate W 20, a power contact plug PILC coupled to a first surface of the power interconnect line PIL, a power via PM 1C coupled to a second surface of the power interconnect line PIL, and a post-multilevel metal line PMLM disposed over the power via PM 1C. The post-multilevel metal line PMLM may include a plurality of metal lines PM 1, TMT, and RDA, and a plurality of vias TMC and RDV. The power interconnection line PIL and the power via PM 1C may have an integral structure. A sidewall of the power interconnect line PIL and a sidewall of the power via PM 1C may be surrounded by a power level spacer SP. The power interconnection line PIL is embedded in the second substrate W 20, and sidewalls of the power interconnection line PIL are completely surrounded by and insulated from the second substrate W 20 by the power level spacer SP. The second substrate W 20 may include a front side FS and a back side BS. The second substrate W 20 may be inverted by wafer inversion so that the back surface BS is disposed above the front surface FS. Accordingly, the front side FS of the second substrate W 20 may refer to a surface facing the multilevel metal line MLM and the memory cell array MCA, and the back side BS of the second substrate W 20 may refer to a surface facing the post multilevel metal line PMLM.A post-interlayer dielectric layer PILD may be formed on the back surface BS of the second substrate W 20. The power via PM 1C may expand into the inside of the second substrate W 20 by passing through the post-interlayer dielectric layer PILD. The power via PM 1C may have a low aspect ratio. The power via PM 1C may be referred to as a "nano-silicon via NTSC.". The power interconnection line PIL may be referred to as a buried bus bar BPR. The power contact plug PILC may be referred to as a buried bus bar via landing on the power interconnect line PIL, i.e., a "via-to-buried bus bar (via-to-BPR) VBPR.". The vertical structure of the power via PM 1C, the power interconnection line PIL, and the power contact plug PILC may be a structure passing through the post-interlayer dielectric layer PILD and the second substrate W 20. The power contact plug PILC may be coupled to a multilevel metal line MLM. The power contact plug PILC may be coupled to a first level metal line MT 1 of the multi-level metal line MLM. The first level metal contact plug M 1C and the power contact plug PILC may be disposed on the same level.The back side interconnection structure BSPDN may be a back side power distribution network that directly supplies power from the back side of the second substrate W 20. The back side interconnect structure BSPDN may supply the power to the control circuits CL, SA, and SWD of the peripheral circuit PERI. The back side interconnect structure BSPDN and the peripheral circuit PERI may share the second substrate W 20. The back side interconnect structure BSPDN may be coupled to the peripheral circuit PERI passing through the second substrate W 20 from the back side BS of the second substrate W 20.The wafer bonding structure WBD may include a first bonding pad CBD coupled to the memory cell array MCA and a second bonding pad PBD coupled to the peripheral circuit PERI. The wafer bonding structure WBD may further include a first bonding contact plug CBC and a second bonding contact plug PBC. The first bonding contact plug CBC may be coupled to the front multilevel metal line FMLM of the memory cell array MCA and the first bonding pad CBD. The second bonding contact plug PBC may be coupled to the multilevel metal line MLM of the peripheral circuit PERI and the second bonding pad PBD. Bonding dielectric layers may be disposed between the first bonding pads CBD of the same plane, and the bonding dielectric layers may be disposed between the second bonding pads PBD of the same plane. The first bonding pad CBD and the second bonding pad PBD may be coupled by direct bonding or hybrid bonding. Direct bonding may mean that the first bonding pad CBD and the second bonding pad PBD are directly bonded, for example, may refer to metal-metal bonding. Hybrid bonding may refer to a combination of metal-metal bonding and dielectric-to-dielectric bonding, referred to briefly as dielectric-to-dielectric bonding. Dielectric-to-dielectric bonding may refer to bonding of the bonding dielectric layers.As described above, the semiconductor device 300, 310, 300A, and 310A may include: a memory cell array MCA disposed over the front side of the first substrate W 10; a back side interconnect structure BSPDN disposed on a higher level than the memory cell array MCA; a second substrate W 20 having a front side FS facing the memory cell array MCA and a back side BS facing the back side interconnect structure BSPDN; a control circuit including at least one or more transistors disposed over the front side FS of the second substrate W 20; and a multilevel metal line MLM including at least one or more metal lines coupled to the control circuit. The back side interconnect structure BSPDN includes: a power interconnect line PIL embedded inside on the front side FS side of the second substrate W 20; a power via PM 1C passing through the back side BS of the second substrate W 20 to be coupled to the power interconnect line PIL; a power contact plug PILC coupled to the power interconnect line PIL and the control circuit; and a power plane spacer SP formed on the sidewall of the power interconnect line and the power via.As described above, the semiconductor device 300, 310, 300A, and 310A may have a structure in which the memory cell array MCA, the peripheral circuit PERI, and the back side interconnection structure BSPDN are vertically stacked. The memory cell array MCA may be disposed at a lower level than the control circuits CL, SA, and SWD. The post-multilevel metal line PMLM of the back side interconnect structure BSPDN may be disposed at a higher level than the control circuits CL, SA, and SWD. Power may be directly supplied from the back side interconnect structure BSPDN to the control circuits CL, SA, and SWD. Accordingly, a path for supplying the power from the back side interconnection pattern BSPDN to the control circuits CL, SA, and SWD may become short. The power supply path may include the post-multilevel metal line PMLM, the power via PM 1C, the power contact plug PILC, the power interconnection line PIL, the first level metal line MT 1, and the first level metal contact plug M 1C. The method of supplying power to the control circuits CL, SA, and SWD of the peripheral circuit PERI may be a top-down power supply.The memory cell array MCA and the peripheral circuit PERI may be connected by a wafer bonding process. The memory cell array MCA and the peripheral circuit PERI may be connected by a wafer bonding pattern WBD. The wafer bonding structure WBD may improve the degree of integration, such as overcoming the process constraints and maximizing the net die.When the wafer bonding process is applied, the back side interconnection pattern BSPDN may be disposed on the back side BS of the second substrate W 20. Therefore, power consumption and current resistance of the semiconductor device 300, 310, 300A, and 310A can be reduced.FIG. 45 schematically illustrates a semiconductor device according to another embodiment of the present disclosure. The semiconductor device 200A of FIG. 45 may be similar to the semiconductor device 200 of FIG. 3. Hereinafter, overlapping descriptions of components identical to those shown in FIG. 3 will be simplified or omitted.Referring to FIG. 45, the semiconductor device 200A may include a memory cell array MCA, a peripheral circuit region PA 1, and a dummy region PA 2. The memory cell array MCA and the dummy region PA 2 may be disposed at a higher level than the peripheral circuit region PA 1. The dummy region PA 2 may be horizontally spaced apart from the memory cell array MCA. For the detailed description of the memory cell array MCA of FIG. 3, reference may be made to FIGS. 2A to 2D.The memory cell array MCA and the dummy region PA 2 may be formed on a first substrate W 1.The peripheral circuit region PA 1 may be formed on a second substrate W 2. The memory cell array MCA may include a three-dimensional array of memory cells MC. For the detailed description of the memory cells MC, reference may be made to FIGS. 1A to 1C. Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may include memory cells MC formed therein, and the second region CTA may include cell contact plugs WC formed therein. In the second region CTA, a staircaseless pad portion WLE of the second conductive lines DWL may be disposed, and the second conductive lines DWL of the staircaseless pad portion WLE may be coupled to the cell contact plugs WC. The staircase pad portion WLE may include a vertical stack of pad portions, and a respective pad portion of the staircase pad portion WLE may include an upper horizontal line G 1, a lower horizontal line G 2, and a pad GP between the upper horizontal line G 1 and the lower horizontal line G 2. The pad portions of the staircase pad portion WLE may have the same horizontal length. The semiconductor device 200 of FIG. 3 may include a staircase pad portion, and the semiconductor device 200A of FIG. 45 may include a staircase pad portion.The peripheral circuit region PA 1 may be coupled to the memory cell array MCA. The peripheral circuit region PA 1 may be disposed at a lower level than the memory cell array MCA. The first substrate W 1 is turned over to bond the memory cell array MCA and the peripheral circuit region PA 1. The peripheral circuit portion PA 1 may include one or more control circuits for driving the memory cell array MCA. For example, the peripheral circuit region PA 1 may include sub word line drivers SWD, a sense amplifier SA, and a peripheral control circuit CL. The first conductive lines BL of the memory cell array MCA may be coupled to the sense amplifier SA.The peripheral circuit region PA 1 and the memory cell array MCA may be coupled to each other through a bonding pattern WBD. The peripheral circuit region PA 1 and the dummy region PA 2 may be coupled to each other through a bonding pattern WBD and a first multilayer-level interconnection LML. The bonding pattern WBD may include a plurality of bonding pads CBD and PBD. The peripheral circuit region PA 1 and the memory cell array MCA may be coupled to each other through the bonding pattern WBD and the first multi-layer level interconnection LML. The bonding pads CBD and PBD may include first bonding pads CBD and second bonding pads PBD. The first bonding pads CBD and the second bonding pads PBD may be coupled to each other by wafer bonding. First bonding contact plugs CBC may be coupled to the first bonding pads CBD. Second bonding contact plugs PBC may be coupled to the second bonding pads PBD.The first conductive lines BL of the memory cell array MCA may be coupled to the first bonding pads CBD and the first bonding contact plugs CBC through the front-level interconnection FM 1. The cell contact plugs WC of the memory cell array MCA may be coupled to the first bonding pads CBD and the first bonding contact plugs CBC through the front-level interconnection FM 1. Sidewall spacers F 1S may be formed on the sidewalls of the first front contact plugs F 1C. The sidewall spacers F 1S may include a dielectric material. The common plate PL of the data storage elements CAP of the memory cell array MCA may be coupled to a second multi-layer interconnection UML through a nano-silicon via PC and a post-layer interconnection PM. The nano-silicon vias PC may penetrate the back side of the first substrate W 1. Nanolevel spacers SP 2 may be formed on the sidewalls of the nano-silicon vias PC. The nanolevel spacers SP 2 may be disposed between the nano-silicon vias PC and the first substrate W 1.The dummy region PA 2 may include a dummy stack SG, a stack level plug FC passing through the dummy stack SG, and a stack level spacer SP 1 formed on the sidewall of the stack level plug FC. The stack level spacer SP 1 may include a dielectric material. The dummy stack SG may include silicon layers S 1 and S 3 and silicon germanium layers S 2 and S 4.The stack level spacers SP 1 may be disposed between the stack level connectors FC and the dummy stack SG. A stack of the silicon layers S 1 and S 3 and the silicon-germanium layers S 2 and S 4 may be disposed around the stack level plugs FC and the stack level spacers SP 1. The vertical height of the stack-level plug FC may be greater than the vertical height of the nano-silicon via PC.The second multi-layer level interconnect UML may be coupled to an upper portion of the stack level connector FC. The front-level interconnect FM 1 may be coupled to a lower portion of the stack-level connector FC. The front-level interconnect FM 1 may be coupled to the first bonding contact plugs CBC and the first bonding pads CBD. The peripheral control circuit CL may be coupled to the second bonding contact plugs PBC and the second bonding pads PBD through the first multilayer-level interconnection LML.The sub-wordline drivers SWD and the sense amplifier SA may be coupled to the second bonding contact plugs PBC and the second bonding pads PBD, respectively, through the first multilayer level interconnect LML.According to the embodiment of the present disclosure, spacers may be formed on the sidewalls of the stack-level connectors disposed in the dummy region, thereby preventing short circuits between the adjacent structures.Although the embodiments of the present disclosure have been described with reference to the specific embodiments of the present disclosure, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the following claims. Further, the embodiments may be combined to form additional embodiments.

Claims

A semiconductor device, comprising: a memory cell array; a dummy region including a dummy stack horizontally spaced from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and the dummy region; a stack level plug passing through the dummy stack; and a stack level spacer formed on a sidewall of the stack level plug.The semiconductor device of claim 1, wherein the dummy region further comprises: a substrate including a front side and a back side; a nano-silicon via that passes through the substrate and is coupled to an upper portion of the stack-level plug; and a nano-level spacer that is formed on a sidewall of the nano-silicon via, wherein the dummy stack is formed on the front side of the substrate and the substrate is inverted such that the dummy stack and the peripheral circuit region face each other.The semiconductor device of claim 2, wherein a vertical height of the stack-level plug is greater than a vertical height of the nano-silicon via.The semiconductor device of claim 1, wherein the dummy stack comprises: a plurality of silicon layers and a plurality of silicon-germanium layers that are alternately stacked.The semiconductor device according to claim 1, wherein the peripheral circuit portion comprises: a plurality of control circuits for driving the memory cell array.The semiconductor device of claim 1, wherein the memory cell array comprises a plurality of memory cells that are vertically stacked, and wherein each of the memory cells comprises: a horizontal layer that is horizontally oriented; a first conductive line that is vertically oriented while coupled to a first side of the horizontal layer; a second conductive line that is horizontally oriented while crossing the horizontal layer; and a data storage element that is coupled to a second side of the horizontal layer.The semiconductor device of claim 6, wherein second conductive lines of the memory cell array include: a staircase pad portion.The semiconductor device of claim 7, wherein the pad portion comprises: an upper horizontal line; a lower horizontal line; and a pad between the upper horizontal line and the lower horizontal line.The semiconductor device of claim 6, wherein second conductive lines of the memory cell array comprise: a staircaseless pad portion.The semiconductor device of claim 1, further comprising: a bonding structure disposed between the peripheral circuit region and the memory cell array, and between the peripheral circuit region and the dummy region.The semiconductor device of claim 10, wherein the bonding structure comprises: first bonding pads coupled to the memory cell array and the stack-level connector, respectively; and a second bonding pad coupled to the peripheral circuit portion.A method of manufacturing a semiconductor device, the method comprising: forming a memory cell array and a dummy stack over a first substrate, wherein the memory cell array and the dummy stack are horizontally spaced apart from each other; forming a stack-level via to penetrate the dummy stack; forming a stack-level spacer on a sidewall of the stack-level via; and forming a stack-level plug over the stack-level spacer to fill the stack-level via.The method of claim 12, wherein the memory cell array comprises a plurality of memory cells that are vertically stacked, and wherein each of the memory cells comprises: a horizontal layer that is horizontally oriented; a first conductive line that is vertically oriented while coupled to a first side of the horizontal layer; a second conductive line that is horizontally oriented while crossing the horizontal layer; and a data storage element that is coupled to a second side of the horizontal layer.The method of claim 12, wherein forming the memory cell array and the dummy stack horizontally spaced apart from each other over the first substrate comprises: forming a stack body over the first substrate; and replacing a first portion of the stack body with a cell shape, and wherein a second portion of the stack body remains as the dummy stack.The method of claim 12, further comprising: forming a plurality of control circuits over a second substrate; forming first bonding pads respectively coupled to the memory cell array and the stack-level connector; forming second bonding pads coupled to the control circuits; and wafer bonding the first bonding pads and the second bonding pads by inverting the first substrate.The method of claim 15, further comprising: after wafer bonding the first bonding pads and the second bonding pads, forming a nano-via to penetrate a back side of the first substrate and expose the stack-level plug; forming a nano-level spacer on a sidewall of the nano-via; forming a nano-silicon via to fill the nano-via over the nano-level spacer; and forming an upper-level interconnect over the nano-silicon via.The method of claim 15, further comprising: prior to forming the first bonding pads respectively coupled to the memory cell array and the stack-level connector, forming a lower-level interconnect to be coupled to the stack-level connector; and forming a first bonding contact connector over the lower-level interconnect.A semiconductor device, comprising: a memory cell array disposed over a first substrate; a second substrate having a front side and a back side and turned over to face the memory cell array; a peripheral circuit formed on the front side of the second substrate; and a back side interconnect structure extending through the second substrate from the back side of the second substrate and coupled to the peripheral circuit.The semiconductor device of claim 18, wherein the back side interconnect structure comprises: a power interconnect line embedded in the second substrate; a power contact plug coupled to a bottom surface of the power interconnect line; a power via coupled to a top surface of the power interconnect line; and a post-multi-layer level interconnect coupled to a top surface of the power via.The semiconductor device of claim 18, further comprising: a power level spacer formed on the sidewall of the power interconnect line and the power via.The semiconductor device of claim 20, wherein the energy interconnect line is embedded in the second substrate, and sidewalls of the energy interconnect line are completely surrounded by and insulated from the second substrate by the energy level spacer.The semiconductor device of claim 18, further comprising: a first bonding pad coupled to the memory cell array; and a second bonding pad coupled to the peripheral circuit.The semiconductor device according to claim 18, wherein the peripheral circuit comprises: a plurality of control circuits for driving the memory cell array.The semiconductor device of claim 18, wherein the memory cell array comprises a plurality of memory cells that are vertically stacked, and wherein each of the memory cells comprises: a horizontal layer that is horizontally oriented; a first conductive line that is vertically oriented while coupled to a first side of the horizontal layer; a second conductive line that is horizontally oriented while crossing the horizontal layer; and a data storage element that is coupled to a second side of the horizontal layer.

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