LOW-DROPOUT VOLTAGE CONTROL WITH ADAPTIVE LOAD BALANCE

Abstract

Load balancing techniques for voltage regulators. In one example, the techniques can be implemented in an LDO voltage regulator designed to provide load balancing with a single driver for an internal and external pass-through element using a pair of variable voltage dividers to adjust the load balance based on the load current. In other examples, a calibrated voltage source can be used to replace one of the variable voltage dividers. A calibration circuit arrangement and methods for determining the value of the calibrated voltage source are also described. In still other examples, a single variable voltage divider can be used without a calibrated voltage source by restricting the external pass-through element so that it is weaker than the internal pass-through element.In any such example, the internal and external pass-through element can be implemented, for example, with either n-type or p-type power transistors and with similar or different transistor technologies (e.g., FETs and BJTs).

Description

TECHNICAL AREA

[0001] The present description refers to linear voltage regulators and in particular to low-dropout (LDO) voltage regulators. BACKGROUND

[0002] The direct current (DC) output voltage provided to a load by a standard power supply can vary due to any number of factors, such as transient conditions, environmental conditions, and changing load conditions. In such cases, a linear voltage regulator can be coupled between the power supply and the load and used to provide a regulated DC output voltage to the load. This way, the output voltage of the linear voltage regulator remains unaffected by abrupt or otherwise transient changes in the input supply voltage and load current. One type of linear regulator is a low-dropout (LDO) voltage regulator, which generally incorporates a stable reference voltage (e.g., a bandgap voltage reference), a differential amplifier (sometimes simply called an amplifier), and a pass-through element (e.g., a voltage regulator).A field-effect transistor (sometimes called a power FET or forward-pass FET) is included. An LDO voltage regulator is a relatively simple and inexpensive way to derive a stable, small-scale power supply from an unregulated input supply voltage (such as a battery output). In response to the input supply voltage dropping below the dropout-mode threshold voltage, the regulator enters dropout mode and ceases to regulate against further reductions in the input supply voltage. Thus, during dropout mode, the output voltage is generally equal to the input supply voltage minus the voltage drop across the forward element. Dropout mode ends in response to the input supply voltage ramping up to a level above the dropout-mode threshold. The LDO voltage regulator circuitry can be implemented within an integrated circuit chip.The passband element can be located on the chip or external to the chip and can be of the p-type or n-type type. A number of non-trivial problems remain with LDO voltage regulators. SUMMARY

[0003] An example circuit includes an input voltage terminal, an output voltage terminal, a feedback voltage terminal, and an output signal terminal. The circuit further includes a passband element coupled between the input voltage terminal and the output voltage terminal, which has a control terminal. The passband element is an n-type passband element. The circuit also includes an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to the feedback voltage terminal. The circuit further includes a load balancing circuit with an input, a first output, and a second output. The input of the load balancing circuit is coupled to the amplifier output.The first output of the load balancing circuit is coupled to the control terminal of the pass-through element, and the second output of the load balancing circuit is coupled to the output signal terminal.

[0004] Another exemplary circuit includes an input voltage terminal, an output voltage terminal, a feedback voltage terminal, and an output signal terminal. The circuit further includes a passband element coupled between the input voltage terminal and the output voltage terminal, which has a control terminal. The passband element is an n-type passband element. The circuit further includes an error amplifier designed to generate an error amplifier output voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage. The circuit further includes a first impedance divider, which includes a first variable impedance and is designed to generate a first drive voltage at the control terminal of the passband element based on the error amplifier output voltage.The circuit also includes a second impedance divider, which incorporates a second variable impedance and is designed to generate a second drive voltage at the output signal terminal based on the error amplifier output voltage.

[0005] An exemplary system includes a first n-type passband coupled between an input voltage terminal and an output voltage terminal, and having a control terminal. The system further includes a second n-type passband coupled between the input voltage terminal and the output voltage terminal, and having a control terminal. The system further includes an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to a feedback voltage terminal. The system further includes a first impedance divider coupled between the amplifier output and a ground terminal, and having an output coupled to the control terminal of the first n-type passband.The first impedance divider further includes a first variable impedance coupled between its output and ground. The system further includes a second impedance divider coupled between the amplifier output and ground, with an output coupled to the control terminal of the second n-type pass-through element. The second impedance divider further includes a second variable impedance coupled between the amplifier output and the output of the second impedance divider.

[0006] Another example circuit includes an input voltage terminal, an output voltage terminal, a feedback voltage terminal, and an output signal terminal. The circuit further includes a passband element coupled between the input voltage terminal and the output voltage terminal, which has a control terminal. The passband element is a p-type passband element. The circuit also includes an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to the feedback voltage terminal. The circuit further includes a load balancing circuit with an input, a first output, and a second output. The input of the load balancing circuit is coupled to the amplifier output.The first output of the load balancing circuit is coupled to the control terminal of the pass-through element, and the second output of the load balancing circuit is coupled to the output signal terminal.

[0007] Another exemplary circuit includes an input voltage terminal, an output voltage terminal, a feedback voltage terminal, and an output signal terminal. The circuit further includes a passband element coupled between the input voltage terminal and the output voltage terminal, which has a control terminal. The passband element is a p-type passband element. The circuit further includes an error amplifier designed to generate an error amplifier output voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage. The circuit further includes a first impedance divider, which includes a first variable impedance and is designed to generate a first drive voltage at the control terminal of the passband element based on the error amplifier output voltage.The circuit also includes a second impedance divider, which incorporates a second variable impedance and is designed to generate a second drive voltage at the output signal terminal based on the error amplifier output voltage.

[0008] Another exemplary system includes a first p-type passband coupled between an input voltage terminal and an output voltage terminal, and having a control terminal. The system further includes a second p-type passband coupled between the input voltage terminal and the output voltage terminal, and having a control terminal. The system further includes an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to a feedback voltage terminal. The system further includes a first impedance divider and a second impedance divider.The first impedance divider is coupled between the amplifier output and the input voltage terminal and includes an output coupled to the control terminal of the first p-type pass-through element. The first impedance divider also includes a first variable impedance coupled between its output and the input voltage terminal. The second impedance divider is coupled between the amplifier output and the input voltage terminal and includes an output coupled to the control terminal of the second p-type pass-through element. The second impedance divider also includes a second variable impedance coupled between its amplifier output and the output of the second impedance divider.

[0009] Another example circuit includes an input voltage terminal, an output voltage terminal, and an output signal terminal. The circuit further includes an error amplifier with an amplifier output. The circuit also includes a passband element coupled between the input voltage terminal and the output voltage terminal, which has a control terminal and a threshold voltage. The circuit further includes a calibration circuit designed to determine the difference between the threshold voltage of the passband element and the threshold voltage of an external passband element.

[0010] Another exemplary circuit includes an input voltage terminal, an output voltage terminal, a feedback voltage terminal, and an output signal terminal. The circuit further includes a pass-through element coupled between the input voltage terminal and the output voltage terminal, and has a control terminal. The circuit also includes an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to the feedback voltage terminal. The circuit further includes a load balancing circuit with one input, a first output, and a second output.The input of the load balancing circuit is coupled to the amplifier output, the first output of the load balancing circuit is coupled to the control terminal of the pass-through element, and the second output of the load balancing circuit is coupled to the output signal terminal. The load balancing circuit includes an impedance divider coupled between the amplifier output and either a ground terminal or the input voltage terminal, with the impedance divider having an output coupled to the first output of the load balancing circuit.

[0011] An exemplary procedure includes a method for calibrating a voltage regulator system. The procedure includes: disabling a first pass-through element coupled between an input voltage terminal and an output voltage terminal of the voltage regulator system. The procedure further includes generating a load current at the output voltage terminal, the load current passing through a second pass-through element coupled between the input voltage terminal and the output voltage terminal. The procedure further includes determining a voltage difference between a threshold voltage of the first pass-through element and a threshold voltage of the second pass-through element. The procedure further includes applying the voltage difference to a control terminal of the first pass-through element or a control terminal of the second pass-through element. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of a circuit that includes a low-dropout (LDO) voltage regulator configured for load balancing, in an example. Fig. Figures 2A-D each graphically represent a load balancing scheme implemented by the LDO voltage regulator. Fig. 1 is executed, in an example. Fig. Figure 3 is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in an example. Fig. Figure 4 is a schematic diagram of an n-type LDO voltage regulator configured for load balancing in another example. Fig. Figures 5A-D are each a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in another example. Fig. Figure 6 is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in another example. Fig. Figure 7 is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in an example. Fig. Figure 8 is a schematic diagram of a p-type LDO voltage regulator configured for load balancing in another example. Fig. Figures 9A-D are each a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in another example. Fig. Figure 10 is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in another example. Fig. Figure 11 is a flowchart of a load balancing procedure in an LDO voltage regulator, in an example. Fig. Figure 12A is a schematic diagram of an n-type LDO voltage regulator configured for load balancing using a calibrated voltage source, in an example. Fig.Figure 12B is a schematic diagram of a p-type LDO voltage regulator configured for load balancing using a calibrated voltage source, in an example. Fig. 13A is a flowchart of a procedure for calibrating an LDO voltage regulator configured for load balancing, in an example. Fig. Figure 13B is a flowchart of a procedure for determining the voltage difference between threshold voltages of an external and internal pass-through element for the method of Fig. 13A, for example. Fig. Figure 14A is a schematic diagram of an n-type LDO voltage regulator configured for load balancing using a calibrated voltage source, wherein the LDO voltage regulator is in a calibration mode and includes a calibration circuit arrangement designed to determine the value of the calibrated voltage source, in an example. Fig. Figure 14B is a schematic diagram of a p-type LDO voltage regulator configured for load balancing using a calibrated voltage source, wherein the LDO voltage regulator is in a calibration mode and includes a calibration circuit arrangement designed to determine the value of the calibrated voltage source, in an example. Fig. 14C is a flowchart of a procedure for calibrating an LDO voltage regulator configured for load balancing, as in Fig. 14A-B shown, in an example. Fig. Figure 14D is a schematic diagram of an n-type LDO voltage regulator configured for load balancing using a calibrated voltage source, wherein the LDO voltage regulator is in a voltage regulation mode utilizing the calibrated voltage source, which is provided using the calibration circuit arrangement of Fig.14A is determined, in an example. Fig. Figure 14E is a schematic diagram of a p-type LDO voltage regulator configured for load balancing using a calibrated voltage source, wherein the LDO voltage regulator is in a voltage regulation mode utilizing the calibrated voltage source, which is provided using the calibration circuit arrangement of Fig. 14B is determined, in an example. Fig. Figure 15 is a schematic diagram of the calibration circuit arrangement designed to determine the value of the calibrated voltage source, in another example. Fig. Figure 16 is a schematic diagram of an LDO voltage regulator configured for load balancing using a calibrated voltage source, in another example. Fig.Figures 17A-C each represent a schematic diagram of an LDO voltage regulator configured for load balancing using an external n-type pass-through element constrained with respect to an internal n-type pass-through element, in an example. Fig. Figures 18A-C each represent a schematic diagram of an LDO voltage regulator configured for load balancing using an external p-type pass-through element constrained with respect to an internal p-type pass-through element, in an example. Fig. Figure 19 is a block diagram of an electronic system that includes an LDO voltage regulator configured for load balancing, in an example. DETAILED DESCRIPTION

[0012] Load balancing techniques for linear voltage regulator applications are described here. In one example, the techniques can be implemented in an LDO voltage regulator designed to provide load balancing with a single driver (error amplifier) ​​for an internal and external pass-through element using a complementary pair of variable voltage dividers to automatically adjust the load balance based on the load current. In other examples, a calibrated voltage source can be used to replace one of the variable voltage dividers. A calibration circuit arrangement and methods for determining the value of the calibrated voltage source are also described here. In still other examples, a single variable voltage divider can be used without a calibrated voltage source by restricting the external pass-through element so that it is weaker than the internal pass-through element.In any of these examples, the internal and external passband can be implemented using either n-type or p-type power transistors and similar transistor technologies (e.g., FETs or BJTs) or different transistor technologies (e.g., FET and BJT). Many variations and configurations become apparent from this revelation. General overview

[0013] As described above, a number of non-trivial problems remain with LDO voltage regulators. For example, the power dissipated in the forward-biased FET is proportional to the product of the load current and the difference between the input and output voltage (I). LOAD -[V IN -V OUT]) and can lead to a temperature increase as the load current increases. The increased heat can damage the die, thus imposing an inherent current limit and / or requiring thermal management. For example, one possible solution is to design the LDO voltage regulator to accommodate the higher current and larger thermal budget. For instance, a large on-chip forward-biased MOSFET can be used, along with wider metal leads and a package with low thermal resistance between the junction and the environment (low-theta JA, possibly in conjunction with a heatsink). However, such a solution increases the chip area and leaves less thermal budget for other power modules in the circuit arrangement. Another solution is to use an external forward-biased MOSFET, which increases the current-carrying capability of the LDO voltage regulator, provides better (lower) on-resistance (e.g., RDS(on)). DSonof the external pass-through FET) and allows for a relatively wide range of user-programmable load current. However, such regulators are less flexible because they cannot be powered on without the connected pass-through FET. Furthermore, such regulators suffer from low bandwidth because the gate capacitance of the external pass-through FET adds a pole, which in turn requires compensation. Consequently, external compensation components and / or a high quiescent current are required to shift the pole to higher frequencies, as a load-tracking zero cannot be added. Yet another solution could be to use parallel LDO voltage regulators, but such a solution would require a system-level current balancing loop as well as the cost of multiple LDO voltage regulators.

[0014] This section describes LDO voltage regulator techniques for adaptively balancing load current between an internal and external pass-through element. One example describes an LDO voltage regulator configured with an integrated or internal pass-through element that provides stable start-up and low-load current support. The LDO voltage regulator further incorporates a load-balancing circuit (or circuit, used interchangeably) designed to adaptively transfer high load current to an external pass-through element. The load-balancing circuit receives a control or drive voltage from an error amplifier of the LDO voltage regulator and generates a first control signal to control the internal pass-through element and a second control signal to control the external pass-through element.In such an example, the load balancing circuit arrangement is, in response to the fact that the load current is less than or equal to a first current threshold (herein referred to as I. STB The internal pass-through element (Iw, which represents the current level that the internal pass-through element can handle without requiring any load balancing and without stability issues) is designed to ensure that the entire load current is supplied through the internal pass-through element. In this case, the external pass-through element (if present) can be kept in its off state or otherwise disabled by the load balancing circuitry. Furthermore, the load balancing circuitry, in response to the load current being greater than Iw, STBis designed to ensure that a first part of the load current is supplied via the internal pass-through element and a second or remaining part of the load current is supplied via the external pass-through element. Furthermore, the load balancing circuit arrangement is designed to respond when the load current exceeds a second current threshold (here denoted as I). LIM_INT (designated as the maximum current level that the internal pass-through element can safely handle), designed to reduce the first part of the load current supplied by the internal pass-through element to I LIM_INT to limit, and to cause a second or remaining part of the load current to be provided via the external pass-through element.

[0015] In some cases, both the internal and external passband elements are n-type transistor devices (e.g., NMOS power FET or NPN power BJT). In other cases, both the internal and external passband elements are p-type transistor devices (e.g., PMOS power FET or PNP power BJT). In still other cases, the internal and external passband elements can be of different transistor technologies, such as the example where one of the internal and external passband elements is a power FET and the other is a power BJT.

[0016] In any such case, the load balancing circuit arrangement may include a variable impedance divider designed to adaptively adjust the voltage at the control terminal of a given pass-through element based on the load current. In some such cases, there is a first variable impedance divider whose output is coupled to the control terminal of the internal pass-through element, and a second variable impedance divider whose output is coupled to the control terminal of the external pass-through element (or otherwise coupled to a terminal that can be coupled to the control terminal of the external pass-through element). The variable impedance dividers can be controlled to effect the load balancing described above and below.

[0017] In other cases, there may only be a variable impedance divider. In such an exemplary case, the output of the variable impedance divider is coupled to the control terminal of the internal pass-through element, and the control terminal of the external pass-through element may be directly coupled to the error amplifier output (or otherwise without an intervening impedance divider). Since one of the internal and external pass-through elements may be more powerful than the other, one of the pass-through elements will conduct more (or less) current than the other without any further intervention.Thus, and according to one example, a voltage source designed to compensate for the difference in strength between the internal and external pass-through element can be applied to one of the pass-through elements, thereby enabling the internal and external pass-through elements to be controlled in such a way as to effect adaptive load balancing, as described in various ways here. In some such examples, a calibration circuit can be used to determine the difference between the threshold voltage of the internal pass-through element and the threshold voltage of a given external pass-through element. The determined voltage difference can then be applied (e.g., as a voltage source) to the control terminal of the internal or external pass-through element to compensate for the difference in strength.Alternatively, if the internal pass-through element is so restricted that it is stronger than the given external pass-through element, then no such calibration or voltage source is required.

[0018] The techniques described here can provide a number of advantages or benefits. For example, an LDO voltage regulator configured for load balancing between an internal and external pass-through element, as described in various ways here, can provide a low quiescent current because the external pass-through element does not draw a current below the threshold of the stability current (Ist). STB). Furthermore, the bandwidth is improved at such lower load currents because the gate capacitance of the external pass-through element is not occupied. Additionally, the voltage regulator can start and support light loads without requiring any external pass-through element to be connected. Moreover, the voltage regulator does not need to be internally configured for high temperature (saving die area and reducing the need for thermal management) because higher load currents can be handled by the external pass-through element. Numerous variations and configurations are evident from the exemplary embodiments described here. Circuit architecture

[0019] Fig.Figure 1 is a block diagram of a circuit 10 that includes a low-dropout (LDO) voltage regulator 100 configured for load balancing, in an example. As shown, the voltage regulator 100 includes an error amplifier (EA) 101, a load balancing circuit arrangement 103, and an internal pass-through element 105, all of which can be located on a given substrate, such as on or otherwise as part of an integrated circuit die within an integrated circuit package (e.g., ceramic flat pack with leads, dual in-line, ball grid array, pin grid array, land grid array, wired chip carrier, quad flat without leads, to name a few examples), or on or otherwise as part of a printed circuit board (e.g.,(single-sided, double-sided, multi-layer, flexible, to name just a few examples), or on or otherwise part of any other suitable substrate on which a circuit arrangement may be formed and / or located. As further shown, an external pass-through element 107, a resistor network including R1 and R2, and an output capacitor C are included. EXT operationally coupled to the voltage regulator 100. The pass-through element 107 is referred to as the external pass-through element 107 because it is located external to the voltage regulator 100 (e.g., external to the integrated circuit package of the regulator 100). The resistors R1 and R2 and / or the output capacitor C EXTThese components can also be located externally to the controller 100, as shown, but in other examples they can be integrated into the controller 100. Both the internal pass-through element 105 and the external pass-through element 107 are coupled between the input voltage terminal and the output voltage terminal and include a control terminal. A power-hung electronic system can also be coupled to the output voltage terminal, here as the load current I. LOAD The electronic system can be designed to be suitable for any number of applications (e.g., automotive systems, computing systems, communication systems, gaming systems, household appliances and consumer electronics systems, mobile electronic systems such as smartphones, or any other application that utilizes regulated power). Other examples of circuit 10 may include additional components not shown and / or be configured differently.

[0020] More specifically, the voltage regulator 100 receives an input voltage V IN at an input voltage terminal 100A and a feedback voltage V FB at a feedback voltage connection 100b and provides a regulated output voltage V OUT at an output voltage terminal 100c. The resistor network, including R1 and R2, is coupled between the output voltage terminal 100c and a ground terminal 100d and provides V FB Ready. The error amplifier 101 receives V FB at one of its input terminals and a reference voltage (V REF ) at its other input terminal and provides a control voltage (VDRV) at its output. V FB is a scaled-down version of the voltage at the output voltage terminal. REFcan be generated, for example, by a bandgap voltage reference or other stable voltage source and can be integrated with or coupled to the voltage regulator 100. As further described in Fig. As shown in Figure 1, the first and second current terminals 105a and 105b of the internal pass-through element 105 (e.g., source / drain terminals for a FET pass-through element, or emitter / collector terminals for a BJT pass-through element) are coupled to terminals 100a and 100c, respectively, of the voltage regulator 100; and a first and second current terminal 107a and 107b of the external pass-through element 107 (e.g., source / drain terminals for a FET pass-through element, or emitter / collector terminals for a BJT pass-through element) are coupled to terminals 100a and 100c, respectively, of the voltage regulator 100. The load balancing circuit arrangement 103 receives VDRV at its input terminal 103a and is designed to supply a first drive voltage VDRV. INTand a second control voltage VDRV EXT to generate at its first output terminal 103b or its second output terminal 103c. As further shown, the first control circuit VDRV INT applied to the control terminal 105c of the internal passage element 105, and the second control circuit VDRV EXT is applied to an output signal terminal 100e of the voltage regulator 100, which in turn is coupled to the control terminal 107c of the external pass-through element 107.

[0021] For the sake of clarity and to reduce the clutter of the figures, some of the ones in Fig.The numerical reference terms used in Figure 1 are not repeated in subsequent figures. More generally, reference terms used in one figure may not be used in another figure, but may still be valid. This detailed description may refer to descriptive phrases instead of the corresponding numerical term, as further detailed in Table 1. Similar expressions not listed in Table 1, but conveying the same meaning, may also be used. Table 1: Index for numerical reference designation and corresponding descriptive phrases Numerical designation Appropriate descriptive phrases that can be used instead 100a Input voltage connection or V IN -connection or V IN -Node 100b Feedback voltage connection or V FB -connection or V FB -Node 100c Output voltage connection or V OUT -connection or V OUT -Node 100d Ground connection, ground node or ground or V RTN 100e Output signal connection of the voltage regulator or VDRV EXT -connection or VDRV EXT -Node 103a Input terminal of the load balancing circuit arrangement 103 (LSC) or LSC input or input of the LSC or VDRV input of the LSC 103b 1. LSC output port or 1. LSC output or 1. output of the LSC or VDRV INT -Exit of the LSC 103c 2. LSC output port or 2nd LSC output or 2nd output of the LSC or VDRV EXT -Exit of the LSC 105a 1. Power connection of the internal pass-through element 105 / 105n / 105p (IPE) or 1. Connection of the IPE or Source connection of the IPE or Drain connection of the IPE or Emitter connection of the IPE or Collector connection of the IPE or Source of the IPE or Drain of the IPE or Emitter of the IPE or Collector of the IPE 105b 2. Power connection of the IPE or 2nd connection of the IPE or Source connection of the IPE or Drain connection of the IPE or Emitter connection of the IPE or Collector connection of the IPE or Source of the IPE or Drain of the IPE or Emitter of the IPE or Collector of the IPE 105c Control connection of the IPE or gate connection of the IPE or base connection of the IPE or gate of the IPE or base of the IPE 107a 1. Power connection of the external pass-through element 107 / 107n / 107p (EPE) or 1. Connection of the EPE or Source connection of the EPE or Drain connection of the EPE or Emitter connection of the EPE or Collector connection of the EPE or Source of the EPE or Drain of the EPE or Emitter of the EPE or Collector of the EPE 107b 2. Power connection of the EPE or 2nd connection of the EPE or Source connection of the EPE or Drain connection of the EPE or Emitter connection of the EPE or Collector connection of the EPE or Source of the EPE or Drain of the EPE or Emitter of the EPE or Collector of the EPE 107c Control connection of the EPE or gate connection of the EPE or base connection of the EPE or gate of the EPE or base of the EPE

[0022] The load balancing circuit arrangement 103 is designed to implement a load balancing scheme based on the load current I LOAD to implement. Fig. Figures 2A-D graphically illustrate an example of such a load balancing scheme. With reference to Fig.1 and Fig. 2A is the load balancing circuit arrangement 103, in response to the fact that the load current I LOAD less than or equal to a first current threshold I STB is designed to cause the entire (or substantially the entire) load current I LOAD is provided via the internal passage element 105. The threshold I STB can be fixed for a given application or can be user-configurable and represents the current level that the internal pass-through element 105 can handle without any required load balancing and without stability issues. In this case, the external pass-through element 107 (if present) can be kept in its off state or otherwise deactivated by the load balancing circuit arrangement 103. For example, in such an exemplary case, the load balancing circuit arrangement 103 represents VDRV. INTto a value that fully activates the internal pass-through element 105, and sets VDRV EXT to a value that completely switches off the external pass-through element 107. In this state or operating mode, the current I supplied by the internal pass-through element 105 is INT equal (or substantially equal) to the load current I LOAD , and the current I provided by the external passage element 105 EXT is equal to (or essentially equal to) zero (e.g., I INT = I LOAD ; I EXT = 0). As used in this context, the expressions “essentially all” and “essentially equal” refer to the possibility that small or otherwise acceptable amounts of load current I LOAD leaked or otherwise obtained through the external passage element 107 (e.g. less than 2% or 1% of I LOADOther applications may exhibit different amounts of such a leakage current, or none at all.

[0023] With further reference to Fig. 1 and Fig. 2A is the load balancing circuit arrangement 103 in response to the fact that the load current I LOAD greater than I STB is designed to cause a first part of the load current I LOAD is provided via the internal passage element 105 (where this part is referred to as I INT (is designated) and a second or remaining part of the load current I LOAD is provided via the external passage element 107 (where this part is referred to as I EXT (is designated). For example, in such an exemplary case, the load balancing circuit arrangement 103 VDRV represents INT to a value that partially switches on the internal passage element 105, which in turn allows the internal passage element 105 I INT allows through, and VDRV EXTsets to a value that partially switches on the external pass-through element 107, which in turn allows the external pass-through element 107 I EXT allows the current I provided by the internal pass-through element 105 to pass through. In this state or operating mode, the current I is INT plus the current I provided by the external passage element 105 EXT equal (or substantially equal) to the load current I LOAD (e.g. I INT + I EXT = I LOAD As used in this context, the phrase "essentially the same" refers to the possibility that a small or otherwise acceptable amount(s) of I INT and / or I EXT leaks or can otherwise be supplied to the given load (e.g. less than 2% or 1% of I LOADAs described above, other applications may exhibit other parasitic scenarios and / or amounts of such leakage current, or otherwise tolerate or not exhibit such leakage current.

[0024] With further reference to Fig. 1 and Fig. 2A the load balancing circuit arrangement 103 is further designed to distribute the current provided by the internal pass-through element 105 to I LIM_INT to limit and to ensure that any remaining part of the load current I LOAD is provided via the external passage element 107. The threshold I LIM_INT can be fixed for a given application or can be user-configurable and represents the maximum current level that the internal pass-through element 105 can safely handle. For example, in such an exemplary case, the load balancing circuit arrangement 103 VDRV limits INTto a value which, in turn, reduces the current flowing through the internal passage element 105 to I LIM_INT limited, and represents VDRV EXT on a value which in turn the external passage element 107 I EXT targets to extract a residual amount of the load current I LOAD to provide. In this state or operating mode, the current I flowing through the internal pass-through element 105 is INT equal (or essentially equal) I LIM_INT , and the external pass-through element 105 represents a residual of the load current I LOAD ready (e.g. I) INT = ~I LIM_INT , I EXT = I LOAD - I LIM_INT As used in this context, the phrase "essentially the same" refers to the possibility of a small or otherwise acceptable deviation from I LIM_INT can be tolerated (e.g., within 2% or 1% of I) LIM_INT ). Furthermore, I can LIM_INTa built-in margin (e.g., 10 microamps to 100 microamps) is provided, which favors a current limit just below the actual maximum rated current, as indicated by the tilde. Other applications may have different margins and maximum currents.

[0025] Fig. 2B illustrates plots of the currents I INT , I EXT and I LOAD according to some examples. As shown, if I LOAD smaller than I STB The gradients (ascent / run) of I follow. LOAD - and I INT -Plots essentially overlap, since the internal passage element 105 covers the entire I LOAD provides and the external pass-through element 107 remains switched off (and thus I EXT is equal to zero, and the slope of I EXT -plots are zero or flat). After I LOAD the I STB -threshold is exceeded, the external passage element 107 begins to form part of I LOADto direct and to refer to, so that the slope of the I EXT -plots increase, while the slope of the I INT -plots decrease. As further stated in Fig. 2B shown after I LOAD the I LIM_INT -If the threshold is exceeded, the slope of the corresponding I flattens out. INT -plots off (goes to zero), and any further increase of I LOAD is by means of I EXT provided. This example shows that each of the streams I INT and I EXT with a rate of change relative to changes in the load current I LOAD is associated and that the rate of change of the current I INT decreases, while the rate of change of the current I EXT increases. Exemplary current values ​​are shown, where I LOAD in a range from less than 17.2 microamperes (µA) to more than 956.7 milliamperes (mA), where I STB is set to approximately 1.5 mA and I LIM_INTis set to approximately 15 mA. Other examples may have a different operating range and / or different thresholds.

[0026] Fig. 2C illustrates plots of the voltages VDRV, VDRV INT and VDRV EXT according to some examples. As shown, if I LOAD smaller than I STB The slopes of the plots for the corresponding VDRV and VDRV follow. INT -Control voltages essentially correspond to each other, since the internal pass-through element 105 carries the entire I LOAD provides and the external pass-through element 107 remains switched off (e.g., VDRV indicates EXT a slope from zero to and is equal to 0 volts for n-type or V IN for p-type). Since I LOAD about the I STB -threshold increased and VDRV correspondingly increases in control strength (e.g. away from 0 volts for n-type and to 0 volts for p-type), the slope of the VDRV EXT -Plots to, while the slope of the VDRVINT -plots decrease. As further stated in Fig. 2C shown after I LOAD the I LIM_INT -If the threshold is exceeded, the slope of the corresponding VDRV flattens out. INT -plots off (goes to zero), and any further increase of I LOAD is achieved by increasing the control strength of VDRV EXT provided. This example shows that each of the control voltages VDRV INT and VDRV EXT associated with a rate of change relative to changes in VDRV generated by the error amplifier 101, and that the rate of change of VDRV INT decreases, while the rate of change of VDRV EXT increases. Exemplary control voltage ranges are shown for n-type and p-type forward devices, where an n-type control voltage ranges from 0 volts (fully off state) to V IN (fully on state) and wherein a p-type control voltage is in a range of V IN(fully off state) to 0 volts (fully on state). Other examples may have a different operating range and / or different thresholds.

[0027] Fig. 2D illustrates plots of the VDRV amplification INT -path (from the output of the error amplifier 101 to the control terminal of the internal pass-through element 105, referred to as a gain plot VDRV) INT / NDRV) and the strengthening of the VDRV EXT -path (from the output of the error amplifier 101 to the control terminal of the external pass-through element 107, referred to as gain plot VDRV) EXT / VDRV), according to some examples. As shown, if I LOAD smaller than I STB is, is the plot for the reinforcement of the VDRV EXT -path flat or zero, since the internal passage element 105 covers the entire I LOAD provides and the external pass-through element 107 remains switched off. If I LOAD about the I STB-threshold increased beyond, the reinforcement of the VDRV takes EXT -path to, while the reinforcement of the VDRV INT -path decreases. This example shows that the gain from the output of the error amplifier 101 to the internal pass-through element 105 decreases, while the gain from the output of the error amplifier 101 to the external pass-through element 107 increases, in each case relative to increases in I. LOAD (or relative to increases in VDRV generated by the error amplifier 101), as soon as I LOAD the I STB -threshold is exceeded, at least for a period of time.

[0028] In one example, the transition from the internal pass-through element 105 can only be used for load balancing between the internal pass-through element 105 and the external pass-through element 107 if the load current I LOAD I STBexceeds, in the analog domain. Likewise, any adaptive load balancing between the internal pass-through element 105 and the external pass-through element 107 can be performed when the load current I exceeds a certain threshold. LOAD between I STB and I LIM_INT lies or if the load current I LOAD I LIM_INT exceeding the limit, operations are performed in the analog domain. For example, in some such examples, the load balancing circuit arrangement 103 is configured with a pair of analog impedance dividers, enabling a seamless adaptive and stable transfer of the load current I. LOADbetween the internal pass-through element 105 and the external pass-through element 107. Other examples may only use an analog impedance divider in conjunction with a calibrated voltage source. Still other examples may only use an analog impedance divider in conjunction with the restriction that the internal pass-through element 105 is stronger than the external pass-through element 107. Such examples are described further below. In all such cases, the analog-based load balancing schemes, which are described here in various forms, are inherently stable.

[0029] The output capacitor C EXTThe capacitor can be any suitable capacitor for a given application. The internal and external forward junctions 105 and 107 can be any suitable forward junctions, such as n-type metal-oxide-semiconductor field-effect transistors (NMOS FETs), p-type metal-oxide-semiconductor field-effect transistors (PMOS FETs), n-type bipolar transistors (NPN BJTs), or p-type bipolar transistors (PNP BJTs). In some examples, the internal and external forward junctions 105 and 107 are different transistor technologies. For example, one of the internal and external forward junctions 105 and 107 is a BJT, and the other of the internal and external forward junctions 105 and 107 is a FET. In such a hybrid configuration, the two different transistors would either be of the p-type (e.g., PMOS and PNP) or n-type (e.g., NMOS and NPN).More generally, the pass-through elements 105 and 107 can be implemented using any suitable transistor or pass-through element technology. The error amplifier 101 can be any suitable error amplifier circuit designed to provide a drive voltage for a pass-through element. The coupling of the inputs to the error amplifier depends on the type of pass-through elements as well as the internal configuration of the error amplifier 101. For example, for a voltage regulator 100 with n-type pass-through elements, V. REF at the non-inverting input (+), and V FB can be applied to the inverting input (-) of the error amplifier. These inputs can be inverted for a voltage regulator 100 with p-type pass-through elements (V REF is applied at the inverting input, and V FB(applied to the non-inverting input). If the error amplifier 101 also includes an odd number of inversion stages, then these couplings described above can be reversed. Any error amplifier technology can be used. N-type LDO voltage regulator with load balancing circuit arrangement

[0030] Fig. Figure 3 is a schematic diagram of an n-type LDO voltage regulator 100n configured for load balancing, in an example. As shown, the voltage regulator 100n is an example voltage regulator 100 of Fig. 1, wherein the voltage regulator 100n is an n-type voltage regulator. In particular, the voltage regulator 100n includes an n-type load balancing circuit arrangement 103n and an internal n-type pass-through element 105n and is coupled to an external n-type pass-through element 107n. Other components, such as the error amplifier 101, the resistors R1 and R2, and the capacitor CEXT , can be the same as above with reference to Fig. 1 described. The above relevant description of the Fig. 1 and 2A-D apply equally here.

[0031] With further reference to the example of Fig. 3 will be V REF and V FB The signal is applied to the non-inverting or inverting input of the error amplifier 101, which in turn generates a control signal VDRV from these inputs. The V REF - and V FB -Inputs can be inverted depending on how many inverting stages are configured in amplifier 101 (V REF and V FB(applied to the inverting or non-inverting input, respectively). Both the internal pass diode 105n and the external pass diode 107n can be, for example, any type of n-type power transistor, such as an NMOS FET, a gallium nitride (GaN) FET, or an NPN BJT, or any other type of power device suitable for an n-type pass diode. The pass diode configuration can be homogeneous or a hybrid configuration. An example of a homogeneous pass diode configuration is one in which both the internal pass diode 105n and the external pass diode 107n are NMOS FETs. An example of a hybrid pass diode configuration is one in which one of the internal pass diode 105n and the external pass diode 107n is an NMOS FET and the other is an NPN BJT.

[0032] As above, similarly with reference to Fig.As described in section 1, the load balancing circuit arrangement 103n receives VDRV from the error amplifier 101 and is designed to provide a first control voltage VDRV INT and a second control voltage VDRV EXT to generate. In this example of Fig. 3. The load balancing circuit arrangement 103n generates the first control voltage VDRV. INT and the second control voltage VDRV EXT from VDRV using a complementary pair of variable voltage dividers, also referred to here as variable impedance dividers (used interchangeably). Each voltage divider is coupled between the output of the error amplifier 101 and the ground terminal, and its output is coupled to the control terminal of one of the internal pass-through element 105n and the external pass-through element 107n. More precisely, a first impedance divider includes a resistor R LIML and a variable resistor R INT, which are coupled serially between the output of amplifier 101 and the ground connection, and represent the first control voltage VDRV INT at its exit (node ​​between R LIML and R INT ) ready, which in turn is coupled to the control terminal of the internal pass-through element 105n. Furthermore, a second impedance divider includes a resistor R. EXT and a pull-down impedance circuit Z PD , which are coupled serially between the output of amplifier 101 and the ground connection, and represent the second control voltage VDRV EXT at its exit (node ​​between R EXT and Z PD) ready, which in turn is coupled to the control terminal of the external pass-through element 107n via an output signal terminal of the voltage regulator 100. In general, the first and second impedance dividers can be implemented with any passive and / or active components. Such a configuration advantageously enables single-loop control for two uncorrelated outputs by dividing one output (VDRV) into two outputs (VDRV) using load-dependent voltage dividers. INT and VDRV EXT ) is divided. Compensation is relatively simpler using one control loop instead of multiple control loops, as further explained below with reference to Fig. 5A-D and 6 are described.

[0033] As further in Fig. As shown in Figure 3, the location of the variable resistance is different in each divider, and therefore the dividers can be considered complementary to each other. More precisely, the variable resistance RINT of the first divider coupled between the output of the first divider and the ground connection (lower position of the divider), and the variable resistor R EXT The output of the second divider is coupled between the output of amplifier 101 and the output of the second divider (upper position of the divider). The resistance values ​​(or impedance values, used interchangeably) of R INT and R EXT are load-dependent. More precisely, the resistances are determined by R. EXT and R INT reduced, while I LOAD increases. While I LOAD As the current increases, the external passage element 107n becomes stronger and the internal passage element 105n becomes weaker.

[0034] To put it in more detail, if the load current I LOAD As the voltage increases, the output voltage VDRV of the error amplifier 101 also increases, and the resistances of R EXT and R INTtransition from high impedance to low impedance (e.g., in a relatively linear manner). While the variable resistance R INT As the current through R changes from a relatively high impedance to a relatively low impedance, it decreases. LIML to, which increases the voltage drop across R LIML increases, which in turn decreases the gain from the output of the error amplifier 101 to the control terminal of the internal pass-through element 105n. In contrast, while a variable resistor R EXT as the current through Z changes from a relatively high impedance to a relatively low impedance PD to, which increases the voltage drop across Z PD This increases the gain from the output of the error amplifier 101 to the control terminal of the external pass-through element 107n. In this way, the slope of a plot of VDRV for the n-type voltage regulator 100n increases. INTitself, or the slope of a plot of gain associated with the VDRV INT -control path is associated, while VDRV increases in control strength (as in Fig. 2C or 2D shown); furthermore, the slope of a plot of VDRV EXT itself, or the slope of a plot of gain associated with the VDRV EXT -control path is associated with, while VDRV increases in control strength (as in Fig. 2C or 2D shown). Z PD It could be, for example, a resistor, a current source, a degenerated natural transistor, or a degenerated depletion transistor, to name a few examples.

[0035] Fig. Figure 4 is a schematic diagram of an n-type LDO voltage regulator 100nF configured for load balancing, in another example. As shown, this example is similar to the example of Fig. 3, with the exception that the variable resistors R EXT and R INTThe load balancing circuit arrangement 103n is implemented with p-type FETs MP1 and MP2. The above relevant description of the Fig. Paragraphs 1-3 apply equally here. In one example, the FETs MP1 and MP2 can be PMOS FETs, although other transistor technologies can be used. The drain of MP1 is coupled to the ground terminal, and the source of MP1 is coupled to the control terminal of the internal passband 105n, and the drain of MP2 is coupled to the control terminal of the external passband 107n, and the source of MP2 is coupled to the output of amplifier 101. The gate (control terminal) of MP1 is coupled to a node where V PINT is provided (the output of the first divider), and the gate of MP2 is coupled to a node at which V PEXT is provided (the output of the second divisor). In this example, V PINT and V PEXTFor a given application, the voltage should be fixed and not vary with the load current; instead, it is the source voltage of the FETs MP1 and MP2 that varies with the load current in this example. Both V PINT as well as V PEXT can be set theoretically or empirically, for example, to overcome the limitations of the fixed current thresholds I STB and I LIM_INT to reflect the given application, as above with reference to Fig. 2A described.

[0036] In the operation of such an n-type configuration, when the load current I LOAD As the output voltage VDRV of the error amplifier 101 increases, so do the source-to-drain resistors (R). SD_ON The FETs MP1 and MP2 transition from high impedance to low impedance (e.g., in a relatively linear manner). During R SD_ON As the impedance of FET MP1 transitions from a relatively high impedance to a relatively low impedance, the current through R LIMLto, which increases the voltage drop across R LIML increases, which in turn decreases the gain from the output of the error amplifier 101 to the control terminal of the internal pass-through element 105n. In contrast, while R SD_ON As the impedance of FET MP2 transitions from a relatively high impedance to a relatively low impedance, the current through Z PD to, which increases the voltage drop across Z PD This increases the gain from the output of the error amplifier 101 to the control terminal of the external pass-through element 107n. In this way, the slope of a plot of VDRV for the n-type voltage regulator 100n increases. INT itself, or the slope of a plot of gain associated with the VDRV INT -The control path is associated with it, while VDRV increases (as in Fig. 2C or 2D shown); furthermore, the slope of a plot of VDRV EXT itself, or the slope of a plot of gain associated with the VDRVEXT -The control path is associated with it, while VDRV increases (as in Fig. 2C or 2D shown).

[0037] Fig. Figure 5A is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in another example. As shown, this example is similar to the example of Fig. 4, with the exception that an active control circuit in the load balancing circuit arrangement 103n is used to generate the V PINT and V PEXT is provided, and the error amplifier 101 is configured with a load-dependent zero for pole-zero compensation. Each of these different features is described in more detail below. Additionally, in this example, the internal passband 105n is implemented with an NMOS FET, and the external passband 107n is implemented with an NPN BJT. The drain of the internal passband 105n is connected to the V IN-connection coupled, and the source of the internal pass-through element 105n is connected to the V OUT -connection coupled, and the gate (control terminal) of the internal pass-through element 105n is connected to the output of the error amplifier 101 via the resistor R LIML coupled. The collector of the external pass-through element 107n is connected to the V IN -connection coupled, and the emitter of the external pass-through element 107n is connected to the V OUT -connection coupled, and the base (control connection) of the external pass-through element 107n is connected to the output of the error amplifier 101 via the variable resistor R EXT coupled (which in this example is implemented with the FET MP2). The exemplary n-type LDO voltage regulator of Fig. 5B is similar to the example of Fig.5A with the exception that the internal passband 105n is implemented with an NPN BJT instead of an NMOS FET. In this example, the collector of the internal passband 105n is V IN -connection coupled, and the emitter of the internal pass-through element 105n is connected to the V OUT -connection coupled, and the base (control connection) of the internal pass-through element 105n is connected to the output of the error amplifier 101 via the resistor R LIML coupled. The above relevant description with reference to Fig. 1-4 applies equally here.

[0038] As shown in this example, the active control circuit for generating V includes PINT and V PEXTthe comparators 501 and 503, wherein the inverting inputs of the comparators 501 and 503 are coupled to the control terminal of the internal pass-through element 105n and the non-inverting inputs of the comparators 501 and 503 are coupled to a bias or voltage source node, respectively, which are connected to threshold (turn-on) voltages V LIMH and V LIML are set up. An example operation is as follows. If I LOAD smaller than I STB VDRV is smaller than V LIMH and V LIML , and the output signals V PINT and V PEXT Both are high, which disables or turns off each of the p-type FETs MP1 and MP2, so that VDRV equals VDRV INT is and the entire I LOAD is provided by the internal passage element 105n. If I LOAD As VDRV increases, so does VDRV, and when VDRV INT The voltage threshold V is set at the control terminal of the internal pass-through element 105n. LIMHexceeds the output signal V PINT The comparator 501 switches from high to low, causing the p-type FET MP1 to turn on. This allows current to flow through R LIML flows, causing a voltage drop across R LIML This generates a gain that, in turn, reduces the gain from the output of the error amplifier 101 to the internal pass-through element 105n. The opposite occurs for the external pass-through element 107n. More precisely, when VDRV INT The voltage threshold (switch-on) V is set at the control terminal of the internal pass-through element 105n. LIML exceeds the output signal V PEXT The comparator 503 switches from high to low, causing the p-type FET MP2 to turn on. This allows current to flow through Z PD flows, causing a voltage drop across Z PDThis generates a gain that, in turn, increases the gain from the output of the error amplifier 101 to the external pass-through element 107n. This complementary action of the dividers allows for a relatively small impedance transfer of current between the two pass-through elements, thus ensuring system stability. In this example, instead of V PINT and V PEXT are fixed LIMH and V LIML They must be fixed for the given application and do not vary with the load current. Both V LIMH as well as V LIML can be set theoretically or empirically, for example, to overcome the limitations of the fixed current thresholds I STB and I LIM_INT to reflect the given application, as above with reference to Fig. 2A described.

[0039] As further in Fig.As shown in 5A-B, the error amplifier 101 in this example comprises an error amplifier stage A1, an inverting amplifier stage A2, and a low-impedance buffer stage B. In this example, amplifier stage A1 is connected to V IN pre-biased, and both the amplifier stage A2 and the buffer stage B are powered via a charging pump voltage or boost stage (V CP ) pre-tensioned. V CP can be any voltage level high enough to meet the overload requirement of the n-type pass-through elements 105n and 107n (e.g. V CP = V OUT + ΔV GS Such a bias voltage allows, for example, the gate of the internal passband element 105n to be pulled higher than a drain, thereby broadening the input range of the LDO voltage regulator. If such a range of output voltage is not required, then V IN also for levels A2 and B, instead of V CPcan be used. As further shown in this example, a pole-zero compensation network that includes the capacitor C is PZ and includes the FET MP3, which are coupled in series from the input of stage A2 to the output of stage A2. In this example, MP3 is a PMOS FET whose drain is connected to C PZ is coupled and its source is coupled to the output of stage A2. The gate of the MP3 receives a load-tracking control voltage V. ZERO_LOAD In operation, when I LOAD increases, takes V ZERO_LOAD off, which in turn reduces the resistance of FET MP3 (or otherwise pushes MP3 towards its low impedance or on state) and C PZ enables compensation to be provided. In contrast, if I LOAD decreases, V ZERO_LOADto, which in turn increases the resistance of MP3 (or otherwise pushes MP3 towards its high-impedance or on-state), ultimately opening the compensation path so that C PZ not with C EXT competes and causes instability at lower load currents (and lower switching frequencies).

[0040] Fig. Figure 5C is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in another example. The load balancing concept is similar to the examples in the Fig. 5A-B, with some differences in bias and operation, as described here. The description relevant above applies equally. As shown in this example, both the internal passband 105n and the external passband 107n are NMOS FETs, and the first and second impedance dividers of the load balancing circuit arrangement 103n are effectively controlled by R LIMand MP1 (first divider) and R LIM2 and MPLIM EXT (second divisor) provided. The source of the p-type FET MPLIM EXT is coupled to the control terminal of the external pass-through element 107n, and its drain is coupled to the ground terminal. R LIM2 is coupled between the output of amplifier 101 and the control terminal of external pass-through element 107n. FET MP1 is controlled by comparator 505, whose inverting input in this example is connected to the node between resistor R. LIM and is coupled to the control terminal of the pass-through element 105n, whose non-inverting input is coupled to the gate and drain of the FET MN1, so that it sets the threshold voltage V LIM_INT receives, and its output is coupled to the control terminal of FET MP1. The FET MPLIM EXT is controlled by the comparator 507, whose non-inverting input is connected to the node between the resistor R LIMand is coupled to the control terminal of the pass-through element 105n, whose inverting input is on V STB is set (which corresponds to the desired I STB corresponds) and its output connected to the control terminal of the FET MPLIM EXT is coupled. As further shown, V LIM_INT by controlling the maximum current I LIM_INT (scaled by N) set by the FET MN1. The FET MN1 is a replica (e.g., correlated or tuned) of the internal passband 105n, which is N times larger than the FET MN1 (where N is an integer of 2 or more). For example, in some such examples, the width-to-length (W / L) ratio of the internal passband 105n is N times larger than the W / L ratio of the FET MN1, where the width W and the length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors. LIM2This could be, for example, a resistor, as shown, or another resistive element (e.g., a transistor that has a control terminal voltage providing a source-to-drain resistance).

[0041] An example of a business is as follows. If VDRV INT at the gate of the internal pass-through element 105n smaller than V STB If the output of comparator 507 is low, it switches MPLIM. EXT This, in turn, pulls the gate of the external passband element 107n low, thus keeping the FET 107n switched off. This allows the internal passband element 105n to carry the load current I. LOAD to lead until the threshold I STB is fulfilled. As soon as VDRV INT greater than V STB When this happens, the output of comparator 507 goes high and MPLIM EXTis switched off, which in turn allows the gate voltage of the FET 107n to rise, thus enabling the FET 107n to be switched on (so that it can start to conduct part of the load current I). LOAD to lead). If VDRV INT about V LIM_INT When the output of comparator 505 goes low, FET MP1 is switched on, which in turn causes FET MP1 to draw current through R. LIM refers to. This allows V LIM_INT is maintained at the gate of the internal pass-through element 105n, which in turn reduces the current through the internal pass-through element 105n to I LIM_INT limited.

[0042] Fig. Figure 5D is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in another example. The load balancing concept is similar to the examples in the Fig.5A-C, with some differences in bias and operation, as described here. The description relevant above applies equally. As shown in this example, the internal pass-through element 105n is an NMOS FET, the external pass-through element 107n is an NPN BJT, and the first and second impedance dividers of the load balancing circuit arrangement 103n are effectively controlled by R LIM and MP1 (first divider) and R LIM2 and MPLIM EXT (second part) provided. Similar to the example of Fig. 5C becomes V LIM_INT by controlling the maximum current I LIM_INT(scaled by N) set by the FET MN1. The FET MN1 is a replica (e.g., correlated or tuned) of the internal passband 105n, which is N times larger than the FET MN1 (where N is an integer of 2 or more). For example, in some such examples, the width-to-length (W / L) ratio of the internal passband 105n is N times larger than the W / L ratio of the FET MN1, where the width W and the length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors. LIM2 It can be, for example, a resistor, as shown, or another resistive element, and is located between the current source I LIM_INT / N and the gate and drain of FET MN1. Furthermore, in this example, the control terminal of FET MP1 is coupled to the gate and drain of FET MN1, so that it directly controls the threshold voltage V. LIM_INT receives. The source of the p-type FET MPLIM EXTis coupled to the output of amplifier 101, its drain is coupled to the control terminal of external pass-through element 107n, and its control terminal is coupled to the node between R LIM2 and the power source I LIM_INT / N coupled, so that it V LIM_INT2 receives.

[0043] An example operation is as follows. At low I LOAD (connected to V) OUT ), if VDRV is less than (V LIM_INT + V TH of MP1) is, then MPLIM is EXT switched off and I LOAD is only supported by the internal pass-through element 105n. While I LOAD As the number of people affected increases, VDRV increases, and eventually MPLIM becomes more prevalent. EXT switched on, thereby directing VDRV to the base of the external pass-through element 107n to support higher current. At the same time, MP1 is also switched on (since V LIM_INT2 >V LIM_INT ), thereby increasing the reinforcement of VDRV to VDRV INTThis is reduced, which in turn allows the external pass-through element 107n to carry a higher current. In this way, the variable-gain divider circuit arrangement, which is defined by R, reduces LIM , MP1, R LIM2 and MPLIM EXT is provided, the reinforcement for the internal passage element 105n, while I LOAD increases, and increases the gain for the external pass-through element 107n, while I LOAD increases. More precisely: while I LOAD As the signal increases, VDRV, provided by amplifier 101, goes upwards, and both MP1 and MPLIM EXT will be switched on; when MPLIM EXT When switched on, it increases the amplification (VDRV) EXT / VDRV) of the VDRV EXT -path; and when MP1 is turned on, it reduces the gain (VDRV) INT / VDRV) of the VDRV INT -path. The complementary gain adjustment at the respective paths is further in Fig.Illustrated in 2D. As further explained in Fig. As shown in 5D, a relatively small power source I BIAS3 through the resistor R LIM The DC bias voltage (in parallel to the gate / base driver, amplifier 101) is provided, which can be used to provide an additional bias voltage for the internal pass-through element 105n, which is useful, for example, at very low load currents (e.g., I LOAD < 100 microamperes) can be helpful. A similar advantage can be achieved by the current source I BIAS2 A connection is provided between the control terminal of the external pass-through element 107n and the ground terminal. Other examples may be configured differently.

[0044] Fig. Figure 6 is a schematic diagram of an n-type LDO voltage regulator configured for load balancing, in an example. As shown, this example is similar to the examples in the Fig.5A-B, with the exception that the active comparator-based control circuit is used to generate V PINT and V PEXT effectively replaced by resistors and current sources in the load balancing circuit arrangement 103n. More specifically, in the example of Fig. 5A V LIMH and V LIML more like turn-on thresholds in a comparator representation. In contrast, in this example, Fig. 6 the resistors R LIML and R LIMH and the power sources I BIAS1 and I BIAS2 used to adaptively adjust the trigger points so that the FETs MP1 and MP2 are switched on at the desired setpoints. In this context, the PMOS FETs MP4, MP5, and MP6 and the NMOS FETs MN1 and MN2 enable detection and tracking. Each of these different features is described in more detail below. The above relevant description with reference to Fig. 1-5D applies equally here.

[0045] With further reference to Fig. 6 is the FET MN1 between the V OUT -connection and the V CP -connection (or the V) IN (Connection in other examples that do not require a higher charging pump voltage) is coupled, and its gate is coupled to its drain and its source is coupled to the V OUT-terminal coupled. The FET MN1 is a scaled-down replica of the internal passband 105n, where the internal passband 105n is N times larger, and N is an integer of 2 or more. For example, in some such examples, the width-to-length (W / L) ratio of the internal passband 105n is N times larger than the W / L ratio of the FET MN1, where the width W and the length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors. The gate of the FET MP4 is coupled to its drain, and the gate and source of the FET MP1 are coupled to the gate and drain of the FET MN1. The current source I BIAS1 is coupled between the drain of FET MP4 and the ground terminal. FET MP5 is coupled between the ground terminal and the V CP -connection (or V) IN -terminal) coupled, and its gate is connected to its drain via resistor R LIMH coupled, its source is linked to the VCP -connection (or V) IN -terminal) is coupled, and its drain is coupled to the gate of FET MP2. The current source I BIAS2 is coupled between the ground connection and the gate of the FET MP5 (so that R LMH between I BIAS2 and the drain of FET MP5). In some such examples, FET MP1 and FET MP4 may be matched or correlated, and FET MP2 and FET MP5 may be matched and correlated. The current source I BIAS3 through the resistor R LIML forms a DC bias voltage (in parallel to the gate / base driver, amplifier 101) which can be used to provide an additional bias voltage for the internal pass-through element 105n, which is useful, for example, at very low load currents (e.g., I LOAD < 100 microamperes) can be helpful. Other examples may be configured differently.

[0046] Referring to the example of Fig.6 are the expressions for the control voltages V PINT and V PEXT for the FETs MP1 and MP2 as follows. VPINT=VLIM_INT−VGS_MP4 K=(W / LMP1) / (W / LMP4) VPEXT=VLIM_INT−VGS_MP5+IBIAS2∗RLIMH V LIM_INT is a replica bias, referenced to V OUT , and which depend on the I LIM_INT for the given application, and effectively ensures that the internal pass-through element 105n carries only a current less than or equal to I LIM_INT is. It is important to remember that I LIM_INT The maximum current level that the internal passband element 105n can safely handle is represented. Furthermore, W / L represents the respective width-to-length ratio of the FETs MP1 and MP4, where the width W and the length L are the dimensions of the current-carrying channel area of ​​the respective transistors.

[0047] More specifically, the charging pump voltage V CPused to create a scaled-down version of the maximum current I LIM_INT to provide in the replica FET MN1, which provides a replica bias V LIM _ INT referenced to V OUT generated and those produced by the I LIM_INT depends on the given application. For example, if the FET MN1 is N times smaller than the forward element 105n (e.g., based on W / L ratios as described above), then the pumped current is equal to I. LIM _ INT / N. The resulting preload V LIM_INT is then used to V PINT via the resistor R LIML , the FET MP4 and I BIAS1 to provide and V PEXT via the resistor R LIMH , the FET MP5 and I BIAS2 to provide. When FETs MP1 and MP4 are matched, FET MP4 effectively cancels the process variation of FET MP1 (so that V LIM_INT(subjected to a PMOS down-through via MP4 and a PMOS up-through via MP1), so that the corresponding bias voltage at the gate of the internal pass-through element 105n I LIM_INT accurately reflects this. Similarly, if the FETs MP2 and MP5 are matched, the FET MP5 effectively cancels out the process variation of the FET MP2 (so that V LIM_INT (subjected to a PMOS down via MP5 and a PMOS up via MP2), so that the corresponding bias voltage at the gate of the external pass-through element 107n I LIM_INT accurately reflects.

[0048] With further reference to the example of Fig. Section 6 provides a load sensing circuit arrangement to enable pole-zero compensation and load tracking. More specifically, a replica buffer stage B2 receives a signal V2 provided at the output of the A2 stage of the error amplifier 101. Like buffer stage B1, buffer stage B2 can be connected to V CP or V INThe gate of the PMOS FET MP6 is coupled to its drain, and its source is coupled to the output of the buffer stage B2. The NMOS FET MN2 is a scaled-down replica of the internal passband 105n (e.g., 105n is K times larger than MN2, where K is an integer of 2 or more, and similarly to 105n being N times larger than MN1, as described above, with that relevant discussion applying equally here), and its gate is coupled to the gate of the internal passband 105n, its drain is coupled to the drain of the FET MP6, and its source is coupled to the V OUT -connection coupled. Such a configuration represents a scaled-down version of the load current I. LOAD Ready for load recording. As described above, if I LOAD increases, takes V ZERO_LOADat the drains of FETs MP6 and MN2, which in turn reduces the resistance of FET MP3 (or otherwise pushes MP3 towards its low impedance or on state) and C PZ This allows compensation for higher load currents. In contrast, if I LOAD decreases, V ZERO_LOAD to, which in turn increases the resistance of MP3 (or otherwise pushes MP3 towards its high-impedance or on-state), ultimately opening the compensation path so that C PZ not with C EXT competes and causes instability at lower load currents. P-type LDO voltage regulator with load balancing circuit arrangement

[0049] Fig. Figure 7 is a schematic diagram of a p-type LDO voltage regulator 100p configured for load balancing, in an example. As shown, the voltage regulator 100p is an example voltage regulator 100 of Fig.1, wherein the voltage regulator 100p is a p-type voltage regulator. In particular, the voltage regulator 100p includes a p-type load balancing circuit arrangement 103p and an internal p-type pass-through element 105p and is coupled to an external p-type pass-through element 107p. Other components, such as the error amplifier 101, the resistors R1 and R2, and the capacitor C EXT The above relevant description of the Fig. 1 and 2A-D apply equally here.

[0050] With further reference to the example of Fig. 7 will be V REF and V FB The signal is applied to the inverting or non-inverting input of the error amplifier 101, which in turn generates a control signal VDRV from these inputs. REF - and V FB -Inputs can be inverted depending on how many inverting stages are configured in amplifier 101 (V REF and V FB(applied to the non-inverting or inverting input, respectively). Both the internal pass diode 105p and the external pass diode 107p can be, for example, any type of p-type power transistor, such as a PMOS FET or a PNP BJT, or any other type of power device suitable for a p-type pass diode. The pass diode configuration can be homogeneous or a hybrid configuration. An example of a homogeneous pass diode configuration is one in which both the internal pass diode 105p and the external pass diode 107p are PMOS FETs. An example of a hybrid pass diode configuration is one in which one of the internal pass diode 105p and the external pass diode 107p is a PMOS FET and the other is a PNP BJT.

[0051] As above, similarly with reference to Fig. As described in section 1, the load balancing circuit arrangement 103p receives VDRV from the error amplifier 101 and is designed to provide a first control voltage VDRV INT and a second control voltage VDRV EXT to generate. In this example of Fig. 7 The load balancing circuit arrangement 103p generates the first control voltage VDRV INT and the second control voltage VDRV EXT from VDRV using a complementary pair of variable voltage dividers, also referred to here as variable impedance dividers (used interchangeably). Each voltage divider is connected between the output of the error amplifier 101 and the input voltage terminal V. IN coupled, and its output is coupled to the control terminal of one of the internal pass-through element 105p and the external pass-through element 107p. More precisely, a first impedance divider includes a resistor R LIML and a variable resistor R INT, which are connected serially between the output of amplifier 101 and the V IN -connection are coupled, and represents the first control voltage VDRV INT at its exit (node ​​between R LIML and R INT ) ready, which in turn is coupled to the control terminal of the internal pass-through element 105p. Furthermore, a second impedance divider includes a resistor R. EXT and a pull-up impedance circuit Z PU , which are connected serially between the output of amplifier 101 and the V IN -connection are coupled, and provides the second control voltage VDRV EXT at its exit (node ​​between R EXT and Z PU) ready, which in turn is coupled to the control terminal of the external pass-through element 107p via an output signal terminal of the voltage regulator 100. In general, the first and second impedance dividers can be implemented with any passive and / or active components. As with the exemplary n-type configuration of Fig. 3. Such a configuration advantageously enables single-loop control for two uncorrelated outputs as well as relatively easier compensation by splitting one output (VDRV) into two outputs (VDRV) using load-dependent voltage dividers. INT and VDRV EXT ) is shared.

[0052] As further in Fig. As shown in Figure 7, the location of the variable resistance is different in each divider, and therefore the dividers can be considered complementary to each other. More precisely, the variable resistance R INTof the first divisor between the outcome of the first divisor and the V IN -Connection coupled (upper position of the divider), and the variable resistance R EXT The output of the second divider is coupled between the output of amplifier 101 and the output of the second divider (lower position of the divider). The resistance values ​​(or impedance values, used interchangeably) of R INT and R EXT are load-dependent. More precisely, the resistances are determined by R. EXT and R INT reduced, while I LOAD increases. While I LOAD As the current increases, the external passage element 107p becomes stronger and the internal passage element 105p becomes weaker.

[0053] In the operation of such a p-type configuration, when the load current I LOAD As the voltage increases, the output voltage VDRV of the error amplifier 101 decreases, and the resistances of R EXT and R INTtransition from high impedance to low impedance (e.g., in a relatively linear manner). While the variable resistance R INT As the current through R changes from a relatively high impedance to a relatively low impedance, it decreases. LIML to, which increases the voltage drop across R LIML increases, which in turn decreases the gain from the output of the error amplifier 101 to the control terminal of the internal pass-through element 105p. In contrast, while a variable resistor R EXT as the current through Z changes from a relatively high impedance to a relatively low impedance PU to, which increases the voltage drop across Z PU This increases the gain from the output of the error amplifier 101 to the control terminal of the external pass-through element 107p. In this way, the slope of a plot of VDRV for the p-type voltage regulator 100p increases. INTitself, or the slope of a plot of gain associated with the VDRV INT -control path is associated, while VDRV increases in control strength (as in Fig. (2C or 2D shown), which in this case means a reduction in the absolute value of VDRV; furthermore, the slope of a plot of VDRV decreases EXT itself, or the slope of a plot of gain associated with the VDRV EXT -control path is associated with, while VDRV increases in control strength (as in Fig. 2C or 2D shown). Z PU It could be, for example, a resistor, a current source, a degenerated natural transistor, or a degenerated depletion transistor, to name a few examples.

[0054] Fig. Figure 8 is a schematic diagram of a p-type LDO voltage regulator 100pF configured for load balancing, in another example. As shown, this example is similar to the example of Fig. 7, with the exception that the variable resistors R EXT and R INT The load balancing circuit arrangement 103p is implemented with n-type FETs MN1 and MN2. The above relevant description of the Fig. 1-2D and 7 apply equally here. In one example, the FETs MN1 and MN2 could be PMOS FETs, although other transistor technologies could be used. The drain of MN1 is connected to the V IN The -terminal is coupled, and the source of MN1 is coupled to the control terminal of the internal pass-through element 105p, and the drain of MN2 is coupled to the control terminal of the external pass-through element 107p, and the source of MN2 is coupled to the output of amplifier 101. The gate (control terminal) of MN1 is coupled to a node where V NINT is provided, and the gate of MN2 is coupled to a node where V NEXT is provided. In this example, V NINT and V NEXTFor a given application, the voltage should be fixed and not vary with the load current; instead, it is the source voltage of the FETs MN1 and MN2 that varies with the load current in this example. Both V NINT as well as V NEXT can be set theoretically or empirically, for example, to overcome the limitations of the fixed current thresholds I STB and I LIM_INT to reflect the given application, as above with reference to Fig. 2A described.

[0055] In the operation of such a p-type configuration, when the load current I LOAD As the voltage increases, the output voltage VDRV of the error amplifier 101 decreases, and the source-to-drain resistors (R) SD_ON The FETs MN1 and MN2 transition from high impedance to low impedance (e.g., in a relatively linear manner). During R SD_ON As the impedance of FET MN1 transitions from a relatively high impedance to a relatively low impedance, the current through R LIMLto, which increases the voltage drop across R LIML increases, which in turn decreases the gain from the output of the error amplifier 101 to the control terminal of the internal pass-through element 105p. In contrast, while R SD_ON As the impedance of the FET MN2 transitions from a relatively high impedance to a relatively low impedance, the current through Z PU to, which increases the voltage drop across Z PU This increases the gain from the output of the error amplifier 101 to the control terminal of the external pass-through element 107p. In this way, the slope of a plot of VDRV for the p-type voltage regulator 100p increases. INT itself, or the slope of a plot of gain associated with the VDRV INT -Control path is associated, while VDRV increases in control strength (decreases in amount) (as in Fig. 2C or 2D shown); furthermore, the slope of a plot of VDRV EXTitself, or the slope of a plot of gain associated with the VDRV EXT -control path is associated with, while VDRV increases in control strength (as in Fig. 2C or 2D shown).

[0056] Fig. Figure 9A is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in another example. As shown, this example is similar to the example of Fig. 8, with the exception that an active control circuit in the load balancing circuit arrangement 103p is used to generate the V NINT and V NEXTis provided, and the error amplifier 101 is configured with a load-dependent zero for pole-zero compensation. Each of these different features is described in more detail below. Additionally, in this example, the internal passband 105p is implemented with a PMOS FET, and the external passband 107p is implemented with a PNP BJT. The source of the internal passband 105p is connected to the V IN -connection coupled, and the drain of the internal pass-through element 105p is connected to the V OUT -connection coupled, and the gate (control terminal) of the internal pass-through element 105p is connected to the output of the error amplifier 101 via the resistor R LIML coupled. The emitter of the external pass-through element 107p is connected to the V IN -connection coupled, and the collector of the external pass-through element 107p is connected to the V OUT-connection coupled, and the base (control connection) of the external pass-through element 107p is connected to the output of the error amplifier 101 via the variable resistor R EXT coupled (which in this example is implemented with the FET MN2). The exemplary n-type LDO voltage regulator of Fig. 9B is similar to the example of Fig. 9A, with the exception that the internal passband 105p is implemented with a PNP-BJT instead of a PMOS-FET. In this example, the emitter of the internal passband 105p is connected to the V IN -connection coupled, and the collector of the internal pass-through element 105p is connected to the V OUT -connection coupled, and the base (control connection) of the internal pass-through element 105p is connected to the output of the error amplifier 101 via the resistor R LIML coupled. The above relevant description with reference to Fig. 1-2 and 7-8 apply equally here.

[0057] As shown in this example, the active control circuit for generating V includes NINT and V NEXT the comparators 901 and 903, wherein the inverting inputs of the comparators 901 and 903 are coupled to the control terminal of the internal pass-through element 105p and the non-inverting inputs of the comparators 901 and 903 are coupled to a bias or voltage source node to measure the voltages V LIMH and V LIML to subject it to a threshold value (to be switched on). An example operation is as follows. If I LOAD smaller than I STB VDRV is greater than V LMH and V LIML , and the output signals V PINT and V PEXT Both are low, thus disabling or turning off each of the n-type FETs MN1 and MN2, so that VDRV equals VDRV INT is and the entire I LOAD is provided by the internal passage element 105p. If I LOADVDRV decreases when VDRV increases, and when VDRV INT at the control terminal of the internal pass-through element 105p below the voltage threshold V LIMH If the output signal V falls, it NINT The comparator 901 switches from low to high, causing the n-type FET MN1 to turn on. This allows current to flow through R LIML flows, causing a voltage drop across R LIML This generates a gain that, in turn, reduces the gain from the output of the error amplifier 101 to the internal pass-through element 105p. The opposite occurs for the external pass-through element 107p. More precisely, when VDRVINT at the control terminal of the internal pass-through element 105p falls below the voltage threshold (switch-on) V LIML If the output signal V falls, it NEXT The comparator 903 switches from low to high, causing the n-type FET MN2 to turn on. This allows current to flow through Z PU flows, causing a voltage drop across ZPU This generates a gain that, in turn, increases the gain from the output of the error amplifier 101 to the external pass-through element 107p. This complementary action of the dividers allows for a relatively small impedance transfer of current between the two pass-through elements, thus ensuring system stability. In this example, instead of V NINT and V NEXT are fixed LIMH and V LIML They must be fixed for the given application and do not vary with the load current. Both V LIMH as well as V LIML can be set theoretically or empirically, for example, to overcome the limitations of the fixed current thresholds I STB and I LIM_INT to reflect the given application, as above with reference to Fig. 2A described.

[0058] As further in Fig. As shown in 9A-B, the error amplifier 101 in this example includes an error amplifier stage A1 and an amplifier stage A2. In this example, both the amplifier stage A2 and the buffer B are connected to V IN biased. As further shown in this example, a pole-zero compensation network is used, which includes the capacitor C. PZ and includes the FET MP3, which are coupled in series between the input of stage A2 and the V IN -terminal coupled. In this example, MP3 is a scaled-down replica of the internal pass-through element 105p to aid load tracking. More specifically, MP3 is a PMOS FET whose drain is connected to C PZ is coupled and whose source is connected to the V IN -connection is coupled. The MP3's gate receives VDRV. INT In operation, when I LOAD as increases, VDRV takes INToff, which in turn reduces the resistance of FET MP3 (or otherwise pushes MP3 towards its low impedance or on state) and C PZ enables compensation to be provided. In contrast, if I LOAD VDRV decreases INT to, which in turn increases the resistance of MP3 (or otherwise pushes MP3 towards its high-impedance or on-state), ultimately opening the compensation path so that C PZ not with C EXT competes and causes instability at lower load currents (and lower switching frequencies).

[0059] Fig. Figure 9C is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in another example. The load balancing concept is similar to the examples in the Fig. 9A-B, with some differences in bias and operation, as described here. The description relevant above applies equally. As shown in this example, the internal passband 105p is implemented with a PMOS FET and the external passband 107p is implemented with a PNP BJT, and the first and second impedance dividers of the load balancing circuit arrangement 103p are effectively provided by R LIM and MN1 (first divisor) and R LIM2 and MNLIM EXT (second divisor) provided. The source of the n-type FET MNLIM EXT is coupled to the control port of the external pass-through element 107p, and its drain is coupled to the V IN -Connection coupled. R LIM2is coupled between the output of amplifier 101 and the control terminal of the external pass-through element 107p and can be, for example, a resistor, as shown, or another resistive element (e.g., a transistor with a control terminal voltage providing a source-to-drain resistance). The FET MN1 is controlled by the comparator 905, whose inverting input in this example is connected to the node between the resistor R LIM and is coupled to the control terminal of the pass-through element 105p, whose non-inverting input is coupled to the gate and drain of the FET MP1, so that it sets the threshold voltage V LIM_INT receives, and its output is coupled to the control terminal of FET MN1. The FET MNLIM EXT is controlled by the comparator 907, whose non-inverting input is connected to the node between the resistor R LIMand is coupled to the control terminal of the pass-through element 105p, whose inverting input is on V STB is set (which corresponds to the desired I STB corresponds) and its output connected to the control terminal of the FET MPLIM EXT is coupled. As further shown, V LIM_INT by controlling the maximum current I LIM_INT (scaled by N) set by the FET MP1, whose source is connected to the V IN -connection is coupled and its gate and drain are connected to the ground connection via the current source I LIM_INT / N is coupled. The FET MP1 is a replica (e.g., correlated or tuned) of the internal passband 105p, which is N times larger than the FET MP1 (where N is an integer of 2 or more). For example, in some such examples, the width-to-length (W / L) ratio of the internal passband 105p is N times larger than the W / L ratio of the FET MP1, where the width W and the length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors.

[0060] An example of a business is as follows. If VDRV INT at the gate of the internal pass-through element 105p greater than V STB If the output of comparator 907 is high, it switches MNLIM. EXT This, in turn, pulls the base of the external pass-through element 107p high, thus keeping the BJT 107p switched off. This allows the internal pass-through element 105p to carry the load current I. LOAD to lead until the threshold ISTB is fulfilled. As soon as VDRV INT smaller than V STB When this happens, the output of comparator 907 goes low and MNLIM. EXT is switched off, which in turn allows the base current to flow from the BJT 107p, thus enabling the BJT 107p to be switched on (so that it can start drawing part of the load current I). LOAD to lead). If VDRV INT under V LIM_INT When the output of comparator 905 goes high, FET MN1 is switched on, which in turn causes FET MN1 to draw current through R. LIM presses. This allows V LIM_INT is maintained at the gate of the internal pass-through element 105p, which in turn reduces the current through the internal pass-through element 105p to I LIM_INT limited.

[0061] Fig. Figure 9D is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in another example. The load balancing concept is similar to the examples in the Fig. 9A-C, with some differences in bias and operation, as described here. The description relevant above applies equally. As shown in this example, the internal passband 105p is a PMOS FET, the external passband 107p is a PNP BJT, and the first and second impedance dividers of the load balancing circuit arrangement 103p are effectively controlled by R LIM and MN1 (first divisor) and R LIM2 and MNLIM EXT (second part) provided. Similar to the example of Fig. 9C will be V LIM_INT by controlling the maximum current I LIM_INT(scaled by N) is set by the FET MP1, and the FET MP1 is a replica (e.g., correlated or tuned) of the internal passband 105p, which is N times larger than the FET MP1 (where N is an integer of 2 or more). The current source I BIAS , the resistance R LIM2 and the n-type FET MN3 are in series between the V IN -connection and the V LIM_INT -Node (drain and gate of MP1) coupled. R LIM2 is between I BIAS and the drain of MN3, and is further coupled between the gate and drain of MN3. The source of MN3 is coupled to the drain and gate of MP1. The FET MN3 can be a replica of MN1 to account for the process variation of MN1 (so that V LIM_INT (subjected to an NMOS up via MN3 and an NMOS down via MN1), so that the corresponding bias voltage at the gate of the internal pass-through element 105p I LIM_INTThis is reflected exactly. More precisely, the control terminal of FET MN1 is coupled to the gate of FET MN3, so that it directly controls the threshold voltage V. LIM_INT + V TH_MN3 receives, which is through V TH_MN1 (V TH_MN1 = V TH_MN3 ) is adjusted downwards before being applied to the control terminal of the internal pass-through element 105p. The source of the n-type FET MPLIM EXT is coupled to the output of amplifier 101, its drain is coupled to the control terminal of external pass-through element 107p, and its control terminal is coupled to the node between R LIM2 and coupled to the drain of MN3, so that it V LIM_INT2 receives.

[0062] An example operation is as follows. At low I LOAD (connected to V) OUT ), if VDRV is greater than (V LIM _ INT2 - V TH by MNLIM EXT ) is, then MNLIM is EXT switched off and I LOADis only supported by the internal pass-through element 105p. While I LOAD As the number of VDRV increases, it decreases, and finally MNLIM becomes the target. EXT switched on, thereby directing VDRV to the base of the external pass-through element 107p to support higher current. At the same time, MN1 is also switched on (since V LIM_INT2 <V LIM_INT + V TH_MN3 ), thereby increasing the reinforcement of VDRV to VDRV INT This is reduced, which in turn allows the external pass-through element 107p to carry a higher current. In this way, the variable-gain divider circuit arrangement, which is defined by R, reduces LIM , MN1, R LIM2 and MNLIM EXT is provided, the amplification for the internal passage element 105p, while I LOAD increases, and increases the gain for the external pass-through element 107p, while I LOAD increases. More precisely: while I LOADAs the VDRV signal increases, the signal provided by amplifier 101 decreases, and both MN1 and MNLIM decrease. EXT will be switched on; when MPLIM EXT When switched on, it increases the amplification (VDRV) EXT / VDRV) of the VDRV EXT -path; and when MN1 is switched on, it reduces the gain (VDRV) INT / VDRV) of the VDRV INT -path. The complementary gain adjustment at the respective paths is further in Fig. Illustrated in 2D. As further explained in Fig. As shown in 9D, a relatively small current source I BIAS3 through resistance P LIM The DC bias voltage (in parallel to the gate / base driver, amplifier 101) is provided, which can be used to provide an additional bias voltage for the internal pass-through element 105p, which is useful, for example, at very low load currents (e.g., I LOAD< 100 microamperes) can be helpful. A similar advantage can be achieved by the current source I BIAS2 A connection is provided between the control terminal of the external pass-through element 107p and the ground terminal. Other examples may be configured differently.

[0063] Fig. Figure 10 is a schematic diagram of a p-type LDO voltage regulator configured for load balancing, in an example. As shown, this example is similar to the example of Fig. 9A or Fig. 9B, with the exception that the active comparator-based control circuit is used to generate V NINT and V NEXT effectively replaced by resistors and a current source in the load balancing circuit arrangement 103p. More specifically, in the example of Fig. 9A V LIMH and V LIML more like turn-on thresholds in a comparator representation. In contrast, in this example, Fig. 10 the resistors R LIML and R EXTB and the power source I BIAS1 used to adaptively adjust the trigger points so that the FETs MN1 and MN2 are switched on at the desired setpoints. In this context, the PMOS FET MP1 and the NMOS FET MN3 enable detection and tracking. Each of these different features is described in more detail below. The above relevant description with reference to Fig. The same applies to 1-2 and 7-9D.

[0064] With further reference to Fig. 10 is the FET MP1 between the V IN -connection and the V OUT -connection coupled, and its gate is coupled to its drain, which is further coupled to the V OUT -connection is coupled, and its source is connected to the V IN-terminal coupled. The FET MP1 is a scaled-down replica of the internal passband 105p, where the internal passband 105p is N times larger, and N is an integer of 2 or more. For example, in some such examples, the width-to-length (W / L) ratio of the internal passband 105p is N times larger than the W / L ratio of the FET MP1, where the width W and the length L are the channel parameters (actual dimensions of the current-carrying region) of the respective transistors. The current source I BIAS1 is between the V IN -connection and the V OUT -connection coupled. The FET MN3 is connected between the current source I BIAS1 and the V OUT -terminal coupled, and its gate is connected to its drain via resistor R EXTB coupled, its source is linked to the V OUT -terminal coupled, and its drain is connected to the power source I BIAS1 coupled, so that R EXTB between the power source IBIAS1 and the drain of MN3. In some such examples, the FETs MN1, MN2, and MN3 may be matched or correlated with each other. The current source I BIAS2 through the resistor R LIML forms a DC bias voltage (in parallel with the amplifier 101) which can be used to provide an additional bias voltage for the internal pass-through element 105p, which is useful, for example, at very low load currents (e.g., I LOAD < 100 microamperes) can be helpful. Other examples may be configured differently.

[0065] Referring to the example of Fig. 10 are the expressions for the control voltages V NINT and V NEXT for the FETs MN1 and MN2 as follows. VNINT=VLIM_INT+VGS_MN3 VNEXT=VNINT−(IBIAS1∗REXTB) V LIM_INT is a replica preload that depends on the I LIM_INTfor the given application, and effectively ensures that the internal pass-through element 105p carries only a current less than or equal to I LIM_INT is. LIM_INT represents the maximum current level that the internal pass-through element 105p can safely handle.

[0066] More specifically, a scaled-down version of the maximum current I LIM_INT provided in the replica FET MP1, which provides a replica bias V LIM_INT referenced to V OUT generated and those produced by the I LIM_INT depends on the given application. For example, if the FET MP1 is N times smaller than the forward element 105p (e.g., based on W / L ratios as described above), then the current through MP1 is equal to I LIM_INT / N. The resulting preload V LIM_INT is then used to V NINT and V NEXT about the resistors R LIML and R EXTB , the FET MN3 and I BIAS1to provide. When FETs MN1 and MN3 are matched, FET MN3 effectively cancels the process variation of FET MN1 (so that V LIM_INT (subjected to an NMOS up via MN3 and an NMOS down via MN1), so that the corresponding bias voltage at the gate of the internal pass-through element 105p I LIM_INT accurately reflects this. Similarly, if the FETs MN2 and MN3 are matched, the FET MN3 effectively cancels out the process variation of the FET MN2 (so that V LIM_INT (subjected to an NMOS up via MN3 and an NMOS down via MN2), so that the corresponding bias voltage at the gate of the external pass element 107p I LIM_INT accurately reflects.

[0067] With further reference to the example of Fig. A load sensing circuit arrangement is provided in section 10 to enable pole-zero compensation and load tracking. As described above, if I LOAD as increases, VDRV takes INToff, which in turn reduces the resistance of the replica FET MP3 (or otherwise pushes MP3 towards its low impedance or on state) and C PZ enables compensation to be provided. In contrast, if I LOAD VDRV decreases INT to, which in turn increases the resistance of MP3 (or otherwise pushes MP3 towards its high-impedance or on-state), ultimately opening the compensation path so that C PZ not with C EXT competes and causes instability at lower load currents. Load balancing method

[0068] Fig. Figure 11 is a flowchart of a load balancing procedure in an LDO voltage regulator, in an example. The method can be implemented, for example, in the analog domain using the load balancing circuit arrangement of any of the voltage regulators described herein with reference to Fig. 1-10 and 12A-19 are described. Other examples of voltage regulators designed to adaptively balance load current between an internal and external pass-through element can be used to provide similar functionality.

[0069] As shown, the procedure includes a determination at 1101 as to whether the load current I LOAD smaller than the current threshold I STB This determination can be carried out, for example, in the analog domain using a load balancing circuit arrangement designed to maintain a given I STB to implement, as described in various ways here. It should be considered from the above that the threshold I STB is fixed for a given application and represents the current level that the internal pass-through element can handle without any required load balancing and without stability problems.

[0070] In response to the fact that the load current I LOAD smaller than the current threshold I STB If the procedure continues at 1103 with the setting of VDRV INT , to encompass the entire (or substantially the entire) I LOAD to provide via the internal passage element, and the setting of VDRV EXT , to switch off or otherwise disable the external pass-through element. This is achieved dynamically in the analog domain via the load balancing circuit arrangement, as described in various ways here. As further described above, the phrase "essentially all" in this context refers to the exemplary case where small or otherwise acceptable amounts of load current I LOAD leaked or otherwise obtained through the external passage element 107 (e.g. less than 1% of I LOADIn some examples, for instance, each of the internal and external pass-through elements has a control terminal (e.g., gate or base), and in response to the load current I LOAD smaller than the current threshold I STBThe procedure involves applying a first voltage to the control terminal of the internal pass-through element, causing the internal pass-through element to supply the entire load current, and applying a second voltage to the control terminal of the external pass-through element, effectively switching off the external pass-through element or otherwise providing no load current (or otherwise only a negligible amount of the load current). The procedure transitions from step 1103 to step 1111, where a determination is made as to whether or not monitoring should continue. If continued monitoring is desired, the procedure continues to step 1101. If continued monitoring is not desired (e.g., the system is switched off or offline), the procedure can stop.

[0071] In response to the fact that the load current I LOAD not smaller than the current threshold I STBIf the procedure continues at 1105 with the setting of VDRV INT , to complete the first part of the I LOAD to provide via the internal passage element, and the setting of VDRV EXT , to obtain a second part (or remaining part) of the I LOAD to provide the current via the external pass-through element. The amount of current handled by each pass-through element varies, as the total load current I LOAD varies, with such transitions occurring dynamically and in the analog domain through the operation of the load balancing circuit arrangement, as described here in various ways.

[0072] The procedure also includes a determination at 1107 as to whether the load current I LOAD greater than the current threshold I LIM_INT is. As described above, the threshold I LIM_INTfor a given application, it is fixed and represents the maximum current level that the internal pass-through element can safely handle. In response to the load current I LOAD not greater than the current threshold I LIM_INT is, the procedure continues to determine the load current I LOAD to monitor by returning to 1101 for repetition.

[0073] In response to the fact that the load current I LOAD greater than the current threshold I LIM_INT If the procedure continues at 1109 with the restriction of the first part of I LOAD , which is provided by the internal passage element, on I LIM_INT and the provision of the second part (or remaining part) of I LOAD via the external pass-through element. In some examples, for instance, each of the internal and external pass-through elements has a control terminal (e.g., gate or base), and in response to the load current I LOADgreater than the current threshold I LIM_INT The procedure involves applying an initial voltage to the control terminal of the internal pass-through element, so that the internal pass-through element provides the first part of the load current (which is based on the current threshold I). LIM_INT It may be limited if the total load current I LOAD (this threshold is exceeded), and applying a second voltage to the control terminal of the external pass-through element so that the external pass-through element provides no load current (or a negligible amount of the load current). The procedure transitions from step 1109 to step 1113, where a determination is made as to whether or not monitoring should continue. If continued monitoring is desired, the procedure proceeds to step 1101 and continues. If continued monitoring is not desired (e.g., the system is switched off or offline), the procedure can stop.

[0074] As described above, the method can be implemented in the analog domain using the load balancing circuit arrangement of any of the various voltage regulators described here. For example, in the n-type examples of Fig. 1, as with reference to Fig. As described in 3-6, the impedance divider, which is R UML and R INT (for Fig. 3-5B and 6) or R LIM and R INT (for Fig. 5C-D) includes, operated to control the VDRV control voltage INT to adjust the internal pass-through element, and the impedance divider, which R EXT and Z PD (for Fig. 3-5B and 6) or R LIM2 and MPLIM EXT (for Fig. 5C-D) is operated to control the VDRV control voltage. EXT to adjust the external pass-through element; in the p-type examples of Fig. 1, as with reference to Fig. As described in 7-10, the impedance divider, which is R LIML and R INT (for Fig. 7-9B and 10) or R LIM and MN1 (for Fig. 9C-D) includes, operated to control the VDRV control voltage INT to adjust the internal pass-through element, and the impedance divider, which R EXT and Z PU (for Fig. 7-9B and 10) or R LIM2 and MNLIM EXT (for Fig. 9C-D) is operated to control the VDRV control voltage. EXT to adjust the external passage element; in the examples of Fig. 1, as with reference to Fig. As described in sections 12A to 16, the impedance divider, which is R LIM and R INT includes, operated to control the VDRV control voltage INT to adjust the internal pass-through element, and the voltage source V CAL is operated to control the VDRV EXTto adapt the external passage element; and in examples relating to Fig. As described in sections 17A to 18C, the impedance divider, which is R LIM and R INT includes, operated to control the VDRV control voltage INT to adjust the internal pass-through element, and the error amplifier 101 is operated to adjust the control voltage VDRV EXT to adjust the external passage element, in conjunction with the restriction that the external passage element is weaker than the internal passage element.

[0075] As further described above, the internal and external passband can be p-type or n-type and can be the same or different power transistor technologies (e.g., FETs, BJTs, or a hybrid configuration including a FET and a BJT). As further described above, the internal passband can be contained within an integrated circuit chip that includes an LDO voltage regulator, and the external passband can be located external to the integrated circuit chip. In other examples, the internal passband can be contained on a printed circuit board (PCB) or be part of a system that includes an LDO voltage regulator, and the external passband can be located external to the PCB or system.In other examples, both an n-type and a p-type circuit arrangement, as described here, can be contained within an integrated circuit chip or chipset, or on a PCB or PCB assembly, and external n-type and p-type pass-through elements can be coupled to it. Other such internal-external configurations can be used. Load balancing with calibrated voltage source

[0076] Fig. Figure 12A is a schematic diagram of an n-type LDO voltage regulator, 100nc, configured for load balancing using a calibrated voltage source, in an example. As shown, this example is similar to the example of Fig. 4, except that in the load balancing circuit arrangement 103nc the variable impedance divider, whose output is coupled to the control terminal of the external pass-through element 107n, is connected to a calibrated voltage source V CALwas replaced. In such a load balancing scheme, the control voltage VDRV INT , which is provided to the control terminal of the internal pass-through element 105n, by the operation of the variable impedance divider (e.g. R LIM and R INT , together with a bias circuit arrangement), as described above in various ways, and the control voltage VDRV EXT , which is provided to the control terminal of the external pass-through element 107n, is the voltage supplied by the error amplifier 101, as measured by the calibrated voltage source V CAL adapted. The above relevant description with reference to Fig. 1-6 and 11 apply equally here.

[0077] The value of the voltage source V CAL can be adjusted to compensate for a difference in the threshold voltage of the internal pass-through element 105n and the external pass-through element 107n. The voltage source V CALIt can be located in different places in the circuit, as shown in the dashed highlighted circle. Other locations can also be used. In each such case, the voltage source V can be CAL The circuit must be serially coupled between the output of the error amplifier 101 and the control terminal of either the internal pass-through element 105n or the external pass-through element 107n. The polarity of the voltage source V CAL The effect shown can be reversed, depending on which of the passage elements 105n and 107n is stronger (e.g., lower V). TH(GS) for FETs or lower V TH(BE) (for BJTs), and the location of the voltage source V CALto adjust the control voltage at the corresponding control terminal either upwards or downwards, as required to enable load balancing. In some examples, a configurable voltage source may be provided at the control terminal or node of both pass-through elements 105n and 107n, and one of these configurable voltage sources may be set and switched into the circuit after a calibration process has been performed to determine the threshold voltage difference of the internal pass-through element 105n and the external pass-through element 107n.

[0078] For example, if the internal passband 105n is an NMOS FET with a threshold voltage of approximately 1.0 volt, and the external passband 107n is an NMOS FET or an NPN BJT with a threshold voltage of approximately 0.7 volts, then the external passband 107n has a threshold voltage approximately 0.3 volts higher than the internal passband 105n. Therefore, the external passband 107n will activate and deliver more current to the load. Applying a voltage source V CAL with a value of 0.3 volts, where the negative terminal of the voltage source V CAL coupled to the control connection of the external pass-through element 107n, it neutralizes or otherwise compensates for the difference in strength and enables load balancing.

[0079] In some examples, a margin can be added to the actual threshold voltage difference to make the internal 105nΩ pass-through element slightly stronger than the external 107nΩ pass-through element. Such a margin will vary from one example to the next, based on factors such as the transistor technology used (e.g., silicon versus germanium) and the absolute value of the threshold difference, but in some examples it is in the range of 10–100 millivolts. For example, continuing the example above, the voltage source V could CAL be set to 0.4 volts, which corresponds to the 0.3-volt V TH -Difference and a 0.1-volt margin are represented.

[0080] Fig. Figure 12B is a schematic diagram of a p-type LDO voltage regulator 100pc configured for load balancing using a calibrated voltage source, in an example. As shown, this example is similar to the example of Fig. 7, except that in the load balancing circuit arrangement 103pc the variable impedance divider, the output of which is coupled to the control terminal of the external pass-through element 107p, is connected to a calibrated voltage source V CAL was replaced. In such a load balancing scheme, the control voltage VDRV INT , which is provided to the control terminal of the internal pass-through element 105p, by the operation of the variable impedance divider (e.g. R LIM and R INT , together with a bias circuit arrangement), as described above in various ways, and the control voltage VDRV EXT , which is provided to the control terminal of the external pass-through element 107p, is the voltage supplied by the error amplifier 101, as measured by the calibrated voltage source V CAL adapted. The above relevant description with reference to Fig. 1-2 and 7-11 apply equally here.

[0081] The value of the voltage source V CAL can be adjusted to compensate for a difference in the threshold voltage of the internal pass-through element 105p and the external pass-through element 107p. The voltage source V CAL It can be located in different places in the circuit, as shown in the dashed highlighted circle. Other locations can also be used. In each such case, the voltage source V can be CAL The output of the error amplifier 101 is coupled in series to the control terminal of either the internal pass-through element 105p or the external pass-through element 107p. The polarity of the voltage source VCAL can be reversed from that shown, depending on which of the pass-through elements 105p and 107p is stronger (e.g., lower V). TH(GS) or lower V TH(BE)), and the location of the voltage source VCAL to adjust the control voltage at the corresponding control terminal either up or down, as required to enable load balancing. In some examples, a configurable voltage source may be provided at the control terminal or node of both pass-through elements 105p and 107p, and one of these configurable voltage sources may be set and switched into the circuit after a calibration process has been performed to determine the threshold voltage difference of the internal pass-through element 105p and the external pass-through element 107p.

[0082] For example, if the internal passband 105p is a PMOS FET with a threshold voltage of approximately 1.0 volt, and the external passband 107p is a PMOS FET or a PNP BJT with a threshold voltage of approximately 0.7 volts, then the external passband 107p has a threshold voltage approximately 0.3 volts higher than the internal passband 105p. Therefore, the external passband 107p will activate and deliver more current to the load. Applying a voltage source V CAL with a value of 0.3 volts, where the positive terminal of the voltage source V CAL coupled with the control connection of the external pass-through element 107p, neutralizes or otherwise compensates for the difference in strength and enables load balancing.

[0083] As just above with reference to Fig. As described in section 12A, a margin can be added to the actual threshold voltage difference to make the internal forward element 105pF slightly stronger than the external forward element 107pF. Such a margin will vary from one example to the next, based on factors such as the transistor technology used and the absolute value of the threshold difference, but in some examples it is in the range of 10–100 millivolts. For example, continuing the example above, the voltage source could be set to 0.4 volts, representing the 0.3-volt difference and a 0.1-volt margin. Calibration method and circuit arrangement

[0084] Fig. Figure 13A is a flowchart of a procedure for calibrating an LDO voltage regulator configured for load balancing, in an example. The LDO voltage regulator can be of the n-type or p-type type. Fig. Figure 13B is a flowchart of a procedure for determining the voltage difference between threshold voltages of an external and internal pass-through element for the method of Fig. 13A, in an example. In describing the method of Fig. 13A-B makes brief reference to the exemplary n-type LDO voltage regulator, which is described in Fig. 14A is shown, and the exemplary p-type LDO voltage regulator shown in Fig. Figure 14B shows the components that are further described below. Other voltage regulators designed to adaptively balance load current between an internal and external pass-through element can also benefit from this method.

[0085] As shown, when both an internal passage element and an external passage element are located between the V IN - and V OUTSince the voltage regulator's terminals are coupled, the method involves switching off or otherwise disabling the internal pass-through element 1301. This can be achieved, for example, with one or more switching elements, such as a switch coupled between the output of the error amplifier 101 and the control terminal of the internal pass-through element (e.g., S1 of the voltage regulator). Fig. 14A or Fig. 14B), and / or a switch from the control terminal of the internal pass-through element to ground for n-type pass-through elements (e.g., S3 of Fig. 14A) or from the control terminal of the internal pass-through element to a supply terminal (e.g. V IN -connection) for p-type pass-through elements (e.g. S3 from Fig. 14B).

[0086] The process starts with generating a load current at V 1303 OUT-connection continues, with the load current flowing through the external pass-through element. The load current can be, for example, an on-chip or other built-in load (e.g., Ic). LOAD_INT from Fig. 14A or Fig. 14B), which is designed to provide a previously set (known) load current value. In other examples, the known load current can be supplied to a terminal of the voltage regulator via an external power source while the calibration process is being performed.

[0087] The procedure continues by determining a voltage difference between a threshold voltage of the internal pass-through element and a threshold voltage of the external pass-through element. This determination effectively establishes which of the pass-through elements is stronger, meaning which of the pass-through elements has a lower threshold voltage V. THexhibits. For example, if the pass-through elements are FETs (e.g., MOSFETs), then the FET with the lower V is the one with the lower V. TH(GS) stronger than the other FET. Likewise, if the passband elements are BJTs, then the BJT with the lower V is stronger. TH(BE) stronger than the other BJT. This voltage difference can be determined, for example, using a comparator circuit to determine the absolute voltage difference between the two threshold voltages of the internal and external pass-through element. Fig. 13B illustrates an exemplary method for the determination at 1305 and is described in turn.

[0088] Once the voltage difference is determined, the procedure can further apply the voltage difference (via the voltage source V). CAL , as in Fig. 12A or Fig. (shown in 12B) to a control terminal of the internal pass-through element or the external pass-through element to compensate for this difference. In this way, the voltage source V can CAL They can be used to effectively neutralize any strength or weakness of a given pass-through element, thus enabling load balancing. As described above, the voltage difference can be adjusted by a margin (e.g., 10–100 millivolts) to favor the internal pass-through element being stronger than the external pass-through element. CAL can also be used here to reference the value of the voltage difference itself (as measured during calibration mode), in addition to the voltage source itself that provides this final calibrated voltage value (as used during run mode).

[0089] In some such examples, and with further reference to Fig. 13B includes determining V CAL at 1305 the incremental adjustment 1352 of a resistance value of an adjustable resistor circuit (e.g. 1411 of Fig. 14A-B), while a known current (e.g. I BIAS from Fig. 14A or Fig. 14B) flows through the resistor circuit until a voltage output of the resistor circuit is within a tolerance of the threshold voltage of the external forward element. For example, in the examples of Fig. In section 14A-B, the determination of when the voltage output of the resistor circuit is within a tolerance of the threshold voltage of the external pass-through element is performed by the comparator 1407. In short, and as further described below, the output of the comparator 1407 transitions from a low state to a high state (or vice versa) to signal when the voltage output of the resistor circuit is within a tolerance of the threshold voltage of the external pass-through element. As further described in Fig. As shown in Figure 13B, the method can further involve storing the resistance value of the resistor circuit corresponding to the voltage output of the resistor circuit being within the tolerance of the threshold voltage of the external pass-through element, or a representation of this resistance value. This resistance value is here referred to as R CAL designated. In some such examples, the R CAL - and VCAL - Values, for example, in a control memory or register (e.g., memory 1403 of control 1415 in Fig. 14A-B and Fig. 14D-E) are stored, and the creation of V CAL At 1307, switching a voltage source with the V CAL The value is included in the path between the output of the error amplifier and the external pass-through element (or the internal pass-through element, as may be the case). In such an example, the V includes, for instance, CAL -voltage source a current source I BIAS , which pumps current through a resistor, R CAL for its resistance value (e.g. V) CAL = R CAL -I BIAS , as in Fig. 14A-B and Fig. 14D-E).

[0090] Fig. 14A-B and Fig. Figures 14D-E illustrate exemplary LDO voltage regulators equipped with a calibration circuit (1417n in Fig. 14A and Fig. 14D and Fig. 1417p for Fig. 14B and Fig. 14E) to determine V CAL are configured, in one example. The LDO voltage regulator can be configured in a calibration mode (e.g. Fig. 14A-B) or a normal / run mode (e.g. Fig. 14D-E). In the examples of the Fig. 14A and Fig. 14D is the n-type LDO voltage regulator, and in the examples of the Fig. 14B and Fig. 14E is the p-type LDO voltage regulator. Fig. Figure 14C shows an exemplary calibration method that can be used in both n-type and p-type configurations. It should be noted that features not used for the given operating mode may not be shown in the figure. For example, the one shown in Fig. The exemplary n-type calibration mode shown in Figure 14A does not include all of the exemplary features of the n-type load balancing circuit arrangement 103nc, which is described in Figure 14A. Fig. 14D is represented (e.g., R) INT not in Fig. 14A shown), and the one in Fig. The exemplary n-type sequence mode shown in Figure 14D does not show all of the exemplary features of the n-type calibration circuit arrangement 1417n, which are described in Fig. 14A is shown (e.g., switches S2, S3 and S5 are not in Fig. 14D shown); similarly, the one in Fig. The exemplary p-type calibration mode shown in Figure 14B does not include all of the exemplary features of the p-type load balancing circuit arrangement 103pc shown in Figure 14B. Fig. 14E is shown (e.g., R is INT not in Fig. 14B shown), and the one in Fig. The exemplary p-type operation mode shown in Figure 14E does not show all of the exemplary features of the p-type calibration circuit arrangement 1417p, which are described in Figure 14E. Fig. 14B is shown (e.g., switches S2, S3 and S5 are not in Fig. (shown in Figure 14E). In some examples, the calibration mode may be executed on every startup of the LDO voltage regulator and may also be repeated periodically during longer run-through mode sessions. In other examples, the calibration mode may be executed on every Nth startup (where N is an integer of 2 or more) or less frequently, which may be desirable if a given external pass-through element and load do not change during the period between calibrations. The run-through mode can be enabled (or re-enabled) after the successful completion of the calibration mode. The discussion relevant above applies equally here.

[0091] As further shown in the n-type example of Fig. As shown in Figure 14A, the output of the error amplifier 101 can be switched with both the control connection of the pass-through element 105n (via switch S1 and resistor R). LIM) as well as the control connection of the pass-through element 107n (via a configurable voltage source V) CAL , which can be bypassed by switch S2). As described above, each of the pass-through elements 105n and 107n is connected between the V IN - and V OUT The -terminal is coupled, and the pass-through element 105n can be located internally to the LDO voltage regulator, and the pass-through element 107n can be located externally to the LDO voltage regulator. In this example, the configurable voltage source V includes CAL an adjustable resistor circuit (set to the R CAL -value) and an IBIAS power source.

[0092] As further shown in the n-type example of Fig. As shown in Figure 14A, the calibration circuit 1417n includes an analog multiplexer (MUX) 1405, a comparator 1407, a replica pass-through element 1409n, an adjustable resistor circuit 1411, and an internal load I. LOAD_INT , a power source IBIAS and a controller 1415. Switches S1-S5 can be set for calibration mode or execution mode. The controller 1415 can, for example, have one or more processors 1401, one or more memory units 1403 for storing instructions (e.g., calibration procedure 1400 of Fig. 14C), which can be executed by the one or more processors 1401, and include a number of input / output ports for providing and receiving data and instructions. The controller 1415 may also include other circuitry, such as one or more digital registers, a clock or oscillator circuit, line drivers, amplifiers, logic operators, and a sensing circuit. In this example, the memory 1403 of the controller 1415 stores calibration factors such as R CAL and V CAL .

[0093] As further shown in the n-type example of Fig. As shown in 14A, the replica pass-through element 1409n, the adjustable resistor circuit 1411 and the current source I BIAS serially with each other between the V IN - and V OUT The terminals are coupled and can be switched into or out of the circuit via switch S4. The adjustable resistor circuit 1411 is connected between the current source I BIAS and coupled to the replica pass-through element 1409n and includes a first and second bank of respective switchable resistors (R) UP <n:0>and R DOWN <m:0>), wherein each bank allows an incremental increase in the resistance it provides, based on the resistance control signal(s) provided by the controller 1415. The adjustable resistor circuit 1411 has a first output that supplies the first resistance bank (R UP <n:0>) corresponds to and is coupled to a first input (0) of the multiplexer 1405, and a second output which corresponds to the second resistor bank (R DOWN <m:0>) corresponds to and is coupled to a second input (1) of the multiplexer 1405. The node between the two resistor banks (designated as V) INT in Fig. 14A) is coupled to the control port of the replica pass-through element 1409n, which is a scaled-down replica of the pass-through element 105n and whose source is connected to the V OUT -connection is coupled and its drain is coupled to the second output of the adjustable resistor circuit 1411.

[0094] As further shown in the n-type example of Fig. 14A refers to the voltage V INT at the node between the two resistor banks of the adjustable resistor circuit 1411 to the threshold voltage V TH , for which the replica pass-through element 1409n is switched on to carry the known current supplied by the current source I BIAS is provided. Since the replica pass-through element 1409n is a downscaled replica of the internal pass-through element 105n, V can INT can be used to determine the threshold voltage V TH for the internal passage element 105n (V TH_105n ) to determine. For example, in such an example, the W / L ratio of the internal passband 105n is X times greater than the W / L ratio of the replica passband 1409n, where X is an integer of 2 or more, where W and L are the width and length, respectively, of the current-carrying region of the channel area, and where both 105n and 1409n are NMOS FETs. In such an exemplary case, the threshold voltage V is TH_105n equal V INT .

[0095] As further shown in the n-type example of Fig. As shown in 14A, the first resistor bank (R) enables UP <n:0>) up to N incremental upward adjustments of V INT (e.g. V INT + V UP <n:0>, where V UP <n:0>the voltage drop across R UP <n:0>is), if the internal pass-through element 105n is stronger than the external pass-through element 107n, and the second resistance bank (R DOWN <m:0>) allows up to M incremental downward adjustments of V INT (e.g. V INT - V DOWN <m:0>, where V DOWN <m:0>the voltage drop across R DOWN <m:0>(is), if the external passband 107n is stronger than the internal passband 105n. The output of the analog multiplexer 1405 is coupled to the inverting input of the comparator 1407 and receives the voltage presented at either the first or second MUX input, depending on the control signal EXT_STARK applied to the SEL input. In this example, if the external passband 107n is weaker than the internal passband 105n, then the control signal EXT_STARK is set low, which in turn causes the V CAL -Voltage at the first MUX input (e.g. V CAL = V INT + V UP <n:0>) is provided to the inverting input of comparator 1407. On the other hand, if the external passband 107n is stronger than the internal passband 105n, then the control signal EXT_STARK is set high, which in turn causes the V CAL -Voltage at the second MUX input (e.g. V CAL = V INT - V DOWN <m:0>) is provided to the inverting input of comparator 1407. The non-inverting input of comparator 1407 is coupled to the control terminal of the external pass-through element 107n, which V EXT provides what in this configuration is the threshold voltage of the external pass-through element 107n (V TH_107n ). If V EXT greater than or equal to V CAL If this is the case, then KALIB_THROUGHEFÜTT is set to high (meaning that the internal passband 105n is stronger than the external passband 107n); on the other hand, if V CAL greater than V EXT If this is the case, then KALIB_DURHGEFÜRTT is set to Low (which means that the external pass-through element 107n is stronger than the internal pass-through element 105n).

[0096] In short, the 1417n calibration circuit is operational, and as further explained below with reference to Fig. 14C described, designed to measure the difference between V TH of the passage element 105n and V TH to determine the through-element 107n by setting switches S1-S5 for calibration mode, thereby applying a known load (I LOAD_INT ) on V OUT -connection is forced, and the adjustable resistor circuit 1411 is incrementally adjusted until the voltage V CAL At the inverting input of comparator 1407, the comparator output signal KALIB_DURCHGEFÜHRT switches from one state to another (high to low or low to high). As soon as KALIB_DURCHGEFÜHRT switches, the V CAL -Value at the inverting input of comparator 1407 into the memory 1403 of controller 1415 together with the corresponding R CAL -Value of the adjustable resistor circuit 1411, which determines the V CAL The resulting value will be stored. In some examples, the 1415 controller may be designed to V CAL to the control port of the pass-through element 107n (or 105n, as may be the case), for example by applying the stored or otherwise determined R CAL -value in the variable resistor circuit of the voltage source V CAL is applied so that if I BIAS through the variable resistor circuit, the voltage source the V CAL -voltage is generated. The calibration mode can then end, allowing the normal operating mode to begin or proceed otherwise, with the V CAL -A voltage source is switched in to enable load balancing.

[0097] As further explained in the p-type example of Fig. As shown in Figure 14B, the output of the error amplifier 101 can be switched with both the control terminal of the pass-through element 105p (via switch S1 and resistor R). LIM ) as well as the control connection of the pass-through element 107p (via a configurable voltage source V) CAL , which can be bypassed by switch S2). As described above, each of the pass-through elements 105p and 107p is connected between the V IN - and V OUT The -terminal is coupled, and the pass-through element 105p can be located internally to the LDO voltage regulator, and the pass-through element 107p can be located externally to the LDO voltage regulator. In this example, the configurable voltage source V includes CAL an adjustable resistor circuit (set to the R CAL -value) and an IBIAS power source.

[0098] As further explained in the p-type example of Fig. As shown in Figure 14B, the calibration circuit 1417p includes an analog multiplexer (MUX) 1405, a comparator 1407, a replica pass-through element 1409p, an adjustable resistor circuit 1411, and an internal load I. LOAD_INT , a power source I BIAS and a 1415 controller. Switches S1-S5 can be set to calibration mode or run mode. The above description of the 1415 controller applies equally here.

[0099] As further explained in the p-type example of Fig. As shown in 14B, the replica pass-through element 1409p, the adjustable resistor circuit 1411 and the current source I BIAS serially with each other between the V IN The positive and negative terminals are coupled and can be switched in or out of the circuit via switch S4. The adjustable resistor circuit 1411 is connected between the current source I BIAS and coupled to the replica pass-through element 1409p and includes a first and second bank of respective switchable resistors (R) DOWN <m:0>and R UP <n:0>), wherein each bank allows an incremental increase in the resistance it provides, based on the resistance control signal(s) provided by the controller 1415. The adjustable resistor circuit 1411 has a first output that supplies the first resistance bank (R DOWN <m:0>) corresponds and is coupled to a second input (1) of the multiplexer 1405, and a second output which corresponds to the second resistor bank (R UP <n:0>) corresponds to and is coupled to a first input (0) of the multiplexer 1405. The node between the two resistor banks (designated as V) INT in Fig. 14B) is coupled to the control port of the replica pass-through element 1409p, which is a downscaled replica of the pass-through element 105p and whose source is connected to the V IN -connection is coupled and its drain is coupled to the second output of the adjustable resistor circuit 1411.

[0100] As further explained in the p-type example of Fig. As shown in 14B, the voltage V refers to INT at the node between the two resistor banks of the adjustable resistor circuit 1411 to the threshold voltage V TH , for which the replica pass-through element 1409p is switched on to carry the known current supplied by the current source I BIAS is provided. Since the replica pass-through element 1409p is a downscaled replica of the internal pass-through element 105p, V can INT can be used to determine the threshold voltage V TH for the internal passage element 105p (V TH_105p ) to determine. For example, in such an example, the W / L ratio of the internal passband 105p is X times greater than the W / L ratio of the replica passband 1409p, where X is an integer of 2 or more, where W and L are the width and length, respectively, of the current-carrying region of the channel area, and where both 105p and 1409p are PMOS FETs. In such an exemplary case, the threshold voltage V is TH_105p equal V INT .

[0101] As further explained in the p-type example of Fig. As shown in 14B, the first resistance bank (R) enables DOWN <m:0>) up to M incremental upward adjustments of V INT (e.g. V INT + V DOWN <m:0>, where V DOWN <m:0>the voltage drop across R DOWN <m:0>is), if the internal pass-through element 105p is stronger than the external pass-through element 107p, and the second resistance bank (R UP <n:0>) allows up to N incremental downward adjustments of V INT (e.g. V INT - V UP <n:0>, where V UP <n:0>the voltage drop across R UP <n:0>(is), if the external passband 107p is stronger than the internal passband 105p. The output of the analog multiplexer 1405 is coupled to the non-inverting input of the comparator 1407 and receives the voltage presented at either the first or second MUX input, depending on the control signal EXT_STARK applied to the SEL input. In this example, if the internal passband 105p is stronger than the external passband 107p, then the control signal EXT_STARK is set low, which in turn causes the V CAL -Voltage at the first MUX input (e.g. V CAL = V INT - V UP <n:0>) is provided to the non-inverting input of comparator 1407. On the other hand, if the external passband 107p is stronger than the internal passband 105p, then the control signal EXT_STARK is set high, which in turn causes the V CAL -Voltage at the second MUX input (e.g. V CAL = V INT + V DOWN <m:0>) is provided to the non-inverting input of comparator 1407. The inverting input of comparator 1407 is coupled to the control terminal of the external pass-through element 107p, which V EXT provides what in this configuration is the threshold voltage of the external pass-through element 107p (V TH_107p ). If V EXT less than or equal to V CAL If this is the case, then KALIB_THROUGHEFÜTT is set to high (meaning that the internal passband 105p is stronger than the external passband 107p); on the other hand, if V CAL smaller than V EXT If this is the case, then KALIB_DURHGEFÜRTT is set to Low (which means that the external pass-through element 107p is stronger than the internal pass-through element 105p).

[0102] In short, the 1417p calibration circuit is operational, and as further explained below with reference to Fig. 14D described, designed to measure the difference between V TH of the passage element 105p and V TH to determine the through-element 107p by setting switches S1-S5 for calibration mode, thereby establishing a known load (I LOAD_INT ) on V OUT -connection is forced, and the adjustable resistor circuit 1411 is incrementally adjusted until the voltage V CAL At the non-inverting input of comparator 1407, the comparator output signal KALIB_DURCHGEFÜHRT switches from one state to another (high to low or low to high). As soon as KALIB_DURCHGEFÜHRT switches, the V CAL -Value at the non-inverting input of comparator 1407 into the memory 1403 of controller 1415 together with the corresponding R CAL -Value of the adjustable resistor circuit 1411, which determines the V CAL The resulting value will be stored. In some examples, the 1415 controller may be designed to V CAL to the control port of the pass-through element 107p (or 105p, as may be the case), for example by applying the stored or otherwise determined R CAL -value in the variable resistor circuit of the voltage source V CAL is applied so that if I BIAS through the variable resistor circuit, the voltage source the V CAL -voltage is generated. The calibration mode can then end, allowing the normal operating mode to begin or proceed otherwise, with the V CAL -A voltage source is switched in to enable load balancing.

[0103] Fig. Figure 14C illustrates a calibration procedure 1400, which is carried out by a controller (e.g., processor(s) 1401 of the controller 1415 of the examples that are in Fig. Method 1400 can be used with either n-type or p-type pass-through elements and is further described with reference to Fig. described in 14A-B, but can also be implemented by other voltage regulator configurations that provide comparable functionality.

[0104] Procedure 1400 begins at 1402, which might correspond, for example, to the start of the LDO voltage regulator, a scheduled calibration according to a configured protocol, or a requested calibration. At 1404, variables are initialized, which in this example includes: setting POK to 0 (to indicate that calibration mode is active); initializing counter j and CODE to 0 (to allow incrementing the resistance value and tracking the number of iterations); and setting EXT_STARK to 0, meaning that the default for this example is that the internal pass-through element (105n or 105p) is stronger than the external pass-through element (107n or 107p). Setting POK to 0 can also cause controller 1415 to set one or more switches to place the voltage regulator into calibration mode. For example, in the example of Fig. 14A the switch S2 is closed by the control unit 1415 to the V CAL -to bypass the voltage source (which is not used during calibration). It should be noted that POK and CODE are not intended to convey any substantive meaning and are simply given names for variables.

[0105] In version 1406, procedure 1400 involves switching off or otherwise disabling the internal pass-through element. In the example of Fig. For example, in 14A this can be achieved by the controller 1415, which causes switch S1 to open and switch S3 to close, as in the n-type example of Fig. 14A allows the control terminal of the 105n pass-through element to be connected to ground (which completely switches off the n-type pass-through element), and which in the p-type example of Fig. 14B allows the control port of the through-flow element 105p to be connected to V IN is pulled (which completely switches off the p-type pass-through element). In another example, any such circuit can be performed at 1404, instead of in a separate switch call.

[0106] In the case of 1408, procedure 1400 involves switching on or otherwise activating the internal load I. LOAD_INT In the examples of Fig. For example, in 14A-B this can be achieved by the controller 1415, which closes the switches S4 and S5, allowing a known current I BIAS through the resistor circuit 1411 and the replica pass-through element 1409n or 1409p. In another example, any such circuit can be implemented at 1404, instead of in a separate switch call. In still other embodiments, the current source I BIAS and / or the internal load I LOAD_INT can be activated (and deactivated) directly by the control unit 1415, instead of switching it on.

[0107] In the case of 1410, procedure 1400 involves initializing the resistance of the resistor banks in resistor circuit 1411. In this example, the resistance of each bank (R) is UP <n:0>and R DOWN <m:0>) initially set to zero ohms by one or more resistance control signals generated by the controller 1415 (e.g., n=0; m=0, so that each resistor in each bank is bypassed by a switch controlled by a corresponding resistance control signal from the controller 1415). Therefore, the initial voltage drop across R UP <n:0>(designated as V) UP in Fig. 14A-B) zero volts, and the initial voltage drop across R DOWN <m:0>(designated as V) DOWN in Fig. 14A-B) is also zero volts. Accordingly, both voltages provided at the first and second outputs of the resistor circuit 1411 and applied to the MUX inputs are V INT The voltage V INT is therefore the initial value of V CAL , which connect to the inverting input of comparator 1407 (for n-type in Fig. 14A) or the non-inverting input of comparator 1407 (for p-type in Fig. 14B) is applied, and represents the threshold voltage of the internal pass-through element. The voltage V EXT is connected to the non-inverting input of comparator 1407 (for n-type in Fig. 14A) or the inverting input of comparator 1407 (for p-type in Fig. 14B) is applied and represents the threshold voltage of the external pass-through element. Thus, the comparator can be set to 1407 V. INT and V EXT compare and indicate which is larger (based on the state of KALIB_DURHGEFÜRÄT), thus indicating which of the internal and external pass-through elements is stronger.

[0108] For this purpose, procedure 1400 continues at 1412 by determining whether KALIB_DURHGEFÜHRT is high (or low). This can be done, for example, using controller 1415, which receives and queries the KALIB_DURHGEFÜHRT output of comparator 1407. More precisely, if KALIB_DURHGEFÜHRT is low (logical 0), then procedure 1400 continues at 1414 by setting EXT_STARK to high (logical 1). For the n-type configuration of Fig. 14A causes the Mux 1405 to connect to the second output of the resistor circuit 1411 (V INT - V DOWN ) to the inverting input of comparator 1407; and for the p-type configuration of Fig. 14B causes the Mux 1405 to access the first output of the resistor circuit 1411 (V INT + V DOWN ) to the inverting input of comparator 1407. The differences in the coupling, which in Fig. 14A and Fig. Figure 14B shows the polarity inversion between n-type and p-type configurations with respect to the outputs of the resistor circuit 1411 and the inputs of the multiplexer 1405 and the comparator 1407.

[0109] Procedure 1400 continues at 1416 by determining whether the counter j has already reached its maximum threshold M (which corresponds to the maximum resistance of R). DOWN -resistor bank of resistor circuit 1411). If the threshold M is reached, then an error flag is set at 1424 (e.g., out of range = 1), and the calibration procedure 1400 stops at 1436. If, on the other hand, the threshold M is not reached, then the counter j is incremented at 1418 by the controller 1415, which in turn causes the next incremental resistance value of R to be DOWN -Resistance bank of the resistor circuit 1411 is switched in. For the n-type configuration of Fig. 14A causes the value at the inverting input of comparator 1407 to decrease incrementally (V CAL = V INT - V DOWN <m:0>); and for the p-type configuration of Fig. 14B causes the value at the non-inverting input of comparator 1407 to increase incrementally (V CAL = V INT + V DOWN <m:0>).

[0110] Procedure 1400 then continues at 1420 to determine whether KALIB_DURHGEFÜHRT has transitioned from low to high. This can be performed again using controller 1415, which receives and queries the KALIB_DURHGEFÜHRT output of comparator 1407. If KALIB_DURHGEFÜHRT has transitioned from low to high, procedure 1400 continues at 1416 to determine whether counter j has already reached its maximum threshold M. If so, an error flag is set at 1424 (e.g., out of range = 1), and procedure 1400 stops at 1436. If, on the other hand, the threshold M has not been reached, counter j is incremented again at 1418, which in turn causes the next incremental resistance value of R to be DOWN -resistance bank is switched in. For the n-type configuration of Fig. 14A causes the value at the inverting input of comparator 1407 to decrease incrementally (V CAL = V INT - V DOWN <m:0>); and for the p-type configuration of Fig. 14B causes the value at the non-inverting input of comparator 1407 to increase incrementally (V CAL = V INT + V DOWN <m:0>).

[0111] Procedure 1400 then continues at 1420 by determining again whether KALIB_DURHGEFÜHRT has transitioned from low to high. If not, the increment process from 1416, 1418, and 1420 is repeated. Conversely, if at 1420 it is determined that KALIB_DURHGEFÜHRT has transitioned from low to high, then the procedure continues at 1422, where the counter value j is stored as CODE (which can be used to R CAL the V CAL -voltage source to adjust), V CAL equal I BIAS *R DOWN <j>is set, POK is set to 1 (to exit calibration mode) and I LOAD_INT is set to 0, and procedure 1400 ends. In this way, the transition of the comparator 1407's output from a low state to a high state can be used to signal when the V CAL -Voltage output of the resistor circuit 1411 and the multiplexer 1405 within an acceptable tolerance of the threshold voltage V EXT of the external pass-through element. The tolerance can vary from one example to the next and depends on factors such as the resolution of comparator 1407. For example, in some examples, the output of comparator 1407 can be used to signal when V CAL within 3% of V EXT lies, or when V CAL in the area of ​​V EXT up to 0.95∗V EXT is located, or when V CAL in the area of ​​V EXT up to 0.98∗V EXT is located. The procedure can transition from 1422 to 1436 and stop. With the V CAL -Voltage source present within the load balancing circuit arrangement (as in Fig. (as shown in 14D-E), the execution mode can begin.

[0112] Again with reference to Fig. 14C then remains at 1412 if KALIB_DURCHGEFÜHRT is high (logical 1) and EXT_STARK is set to low (logical 0). For the n-type configuration of Fig. 14A causes the Mux 1405 to access the first output of the resistor circuit 1411 (V INT + V UP ) to the inverting input of comparator 1407; and for the p-type configuration of Fig. 14B causes the Mux 1405 to connect to the second output of the resistor circuit 1411 (V INT - V UP ) to the non-inverting input of comparator 1407. The procedure continues at 1426 by determining whether the counter j has already reached its maximum threshold N (which corresponds to the maximum resistance of R). UP -resistor bank of resistor circuit 1411). If the threshold N is reached, then an error flag is set at 1434 (e.g., out of range = 1), and the procedure 1400 stops at 1436. If, on the other hand, the threshold N is not reached, then the counter j is incremented at 1428, which in turn causes the next incremental resistance value of R to be UP -Resistance bank of the resistor circuit 1411 is switched in. For the n-type configuration of Fig. 14A causes the value at the inverting input of comparator 1407 to increase incrementally (V CAL = V INT + V UP <n:0>); and for the p-type configuration of Fig. 14B causes the value at the non-inverting input of comparator 1407 to decrease incrementally (V CAL = V INT - V UP <n:0>).

[0113] Procedure 1400 then continues at 1430 to determine whether KALIB_DURHGEFÜHRT has transitioned from high to low. This can be performed again using controller 1415, which receives and queries the KALIB_DURHGEFÜHRT output of comparator 1407. If KALIB_DURHGEFÜHRT has transitioned from high to low, procedure 1400 continues at 1426 to determine whether counter j has already reached its maximum threshold N. If so, an error flag is set at 1434 (e.g., out of range = 1), and procedure 1400 stops at 1436. If, on the other hand, the threshold N has not been reached, counter j is incremented again at 1428, which in turn causes the next incremental resistance value of R to be UP -resistance bank is switched in. For the n-type configuration of Fig. 14A causes the value at the inverting input of comparator 1407 to increase incrementally (V CAL = V INT + V UP <n:0>); and for the p-type configuration of Fig. 14B causes the value at the non-inverting input of comparator 1407 to decrease incrementally (V CAL = V INT - V UP <n:0>).

[0114] Procedure 1400 then continues at 1430 by re-determining whether KALIB_DURHGEFÜHRT has transitioned from high to low. If not, the increment process from 1426, 1428, and 1430 is repeated. Conversely, if at 1430 it is determined that KALIB_DURHGEFÜHRT has transitioned from high to low, then procedure 1400 continues at 1432, where the counter value j is stored as CODE (which can be used to R CAL the V CAL -voltage source to adjust), V CAL equal - I BIAS *R UP <j>is set, POK is set to 1 (to exit calibration mode) and I LOAD_INT is set to 0, and procedure 1400 ends. In this way, the transition of the comparator 1407's output from a high state to a low state can be used to signal when the V CAL -Voltage output of the resistor circuit 1411 and the multiplexer 1405 within an acceptable tolerance of the threshold voltage V EXT of the external pass-through element. As described above, the tolerance can vary from one example to the next and depends on factors such as the resolution of comparator 1407. For example, in some examples, the output of comparator 1407 can be used to signal when V CAL within 3% of V EXT lies, or when V CAL in the area of ​​V EXT up to 1.05∗V EXT is located, or when V CAL in the area of ​​V EXT up to 1.02∗V EXT The procedure can move from 1432 to 1436 and stop. With the V CAL -With the voltage source connected within the load balancing circuit arrangement, the operating mode can begin, as shown in Fig. 14D-E shown.

[0115] Fig. Figures 14D-E each show an exemplary LDO voltage regulator in run-down mode with installed V CAL -Voltage source, according to examples. The 1415 controller can control the voltage source V CAL configure to configure the V CAL -to provide voltage, using the final R CAL -value (R CAL_setting ) and V CAL Calibration factors. The 1415 controller can also open switches S2-S5 and close switch S1 to allow normal operation to begin. As further shown, a powered system (represented as I) LOAD ) with the V OUT -connection connected, and the internal load I LOAD_INT is no longer connected to the circuit or otherwise deactivated.

[0116] The exemplary n-type configuration shown in Fig. The one shown in 14D is similar to the one in Fig. 12A example shown, except that R INT implemented with a p-type FET MP1, and the calibration circuit arrangement of Fig. 14A is shown (but currently switched off by switches S2-S5 or otherwise disabled). Additionally, FET MP1 is controlled by a comparator 1419, where in this example its non-inverting input is connected to the node between the output of amplifier 101 and resistor R. LIM is coupled, its inverting input has a threshold voltage V LIM_INT receives and its output is coupled to the control terminal of the FET MP1 (to V PINT to provide). V LIM_INT It can be set, for example, as described above. The description relevant above applies equally here. As further shown, the V CAL -Voltage source now switched in (for the running mode) and coupled between the output of the error amplifier 101 and the control terminal of the external pass-through element 107n and includes a current source I BIAS and a variable resistor circuit that is based on the R CAL The value is set, which is determined during calibration mode. It should be noted that the power source I BIAS the same power source I BIAS This may be used during calibration when R CAL is determined, or can be another power source that provides the same I BIAS -value. In operation, obtaining the I generates BIAS -current through the resistor R CAL the V CAL -voltage. In the case where the external pass-through element 107n is stronger than the internal pass-through element 105n, the positive terminal of the V can be CAL -The voltage source must be connected to the output of amplifier 101, and the negative terminal of the V CAL The voltage source can be connected to the control terminal of the external pass-through element 107n. In this way, the strength of the external pass-through element 107n can be neutralized or otherwise reduced to allow load balancing. In the case where the external pass-through element 107n is weaker than the internal pass-through element 105n, the negative terminal of the V can be used. CAL -The voltage source must be connected to the output of amplifier 101, and the positive terminal of the V CAL The voltage source can be connected to the control terminal of the external pass-through element 107n. In this way, the weakness of the external pass-through element 107n can be neutralized or otherwise reduced to enable load balancing.

[0117] The exemplary p-type configuration shown in Fig. The one shown in 14E is similar to the one in Fig. Example 12B shown, except that R INT implemented with an n-type FET MN1, and the calibration circuit arrangement of Fig. 14B is shown (but currently switched off by switches S2-S5 or otherwise disabled). Additionally, FET MN1 is controlled by a comparator 1420, where in this example its inverting input is connected to the node between the output of amplifier 101 and resistor R. LIM is coupled, its non-inverting input has a threshold voltage V LIM_INT receives and its output is coupled to the control terminal of the FET MN1 (to V NINT to provide). V LM_INT It can be set, for example, as described above. The description relevant above applies equally here. As further shown, the V CAL -Voltage source now switched in (for the run-out mode) and coupled between the output of the error amplifier 101 and the control terminal of the external pass-through element 107p and includes a current source I BIAS and a variable resistor circuit that is based on the R CAL The value is set, which is determined during calibration mode. It should be noted that the power source I BIAS the same power source I BIAS This may be used during calibration when R CAL is determined, or can be another power source that provides the same I BIAS -value. In operation, obtaining the I generates BIAS -current through the resistor R CAL the V CAL -voltage. In the case where the external pass-through element 107p is stronger than the internal pass-through element 105p, the negative terminal of the V can be CAL -The voltage source must be connected to the output of amplifier 101, and the positive terminal of the V CAL The voltage source can be connected to the control terminal of the external pass-through element 107p. In this way, the strength of the external pass-through element 107p can be neutralized or otherwise reduced to allow load balancing. In the event that the external pass-through element 107p is weaker than the internal pass-through element 105p, the positive terminal of the V can be CAL -The voltage source must be connected to the output of amplifier 101, and the negative terminal of the V CAL The voltage source can be connected to the control terminal of the external pass-through element 107p. In this way, the weakness of the external pass-through element 107p can be neutralized or otherwise reduced to enable load balancing.

[0118] Fig. Figure 15 is a schematic diagram of the calibration circuit arrangement designed to determine the value of the calibrated voltage source in another example. This exemplary circuit can be used instead of calibration circuits 1417n and 1417p to determine V CAL to determine, in cases where the external pass-through element 107 (either n-type or p-type) is assumed to be stronger than the internal pass-through element (V TH_107 ≤ V TH_105 A switching scheme can be used to activate the calibration circuit arrangement for calibration mode and to deactivate the calibration circuit arrangement for run mode, for example, by including switches at suitable locations to switch the calibration circuit in (for calibration mode) or out (for run mode). The discussion relevant above applies equally here.

[0119] As shown, the calibration circuit of Fig. 15 a matched pair of NMOS-FETs 1501 and 1503, a current source I BIAS , a downscaled replica pass-through element 1505 (where the pass-through element is 105 N times larger, and the above previous relevant description regarding sizing based on W / L ratios applies equally here), a comparator 1507, and an adjustable resistor circuit 1509. Each of the FETs 1501 and 1503 is connected between the V IN - and ground connection coupled, with their respective drains connected to the V IN The terminals are coupled, and their respective sources are coupled to the ground terminal. The gate of FET 1501 receives V EXT , which in this configuration is also the threshold voltage of the external pass-through element 107n (V TH_107 The gate of FET 1503 is coupled to the drain of FET 1503. As further shown, each of FETs 1501, 1503, and 1505 carries an I BIAS -current, and the adjustable resistor circuit 1509 is coupled between the drain of FET 1503 and the ground terminal. The replica FET is connected between the V IN - and V OUT The -terminal is coupled, and its gate is coupled to the drain of the FET 1503. The circuit can be implemented in a similar way to the calibration circuits 1417n and 1417p, respectively. Fig. 14A-B can be operated. For example, the calibration circuit can be activated when the voltage control starts and initialized so that the R CAL The value of resistor circuit 1509 is zero ohms. In such a configuration, the initial KALIB_PULLED signal generated at the output of comparator 1507 is low. The resistor value R CAL The resistance of the resistor circuit 1509 can then be incrementally adjusted upwards (e.g., under instruction from the controller 1415 or another processor), and when KALIB_DURHGEFÜT transitions from low to high, then the R CAL -value at this time for the variable resistance of the voltage source V CAL can be used. More specifically, KALIB_DURCHGEFÜRT goes high when: V EXT - V TH_1501 + I BIAS (R CAL ) + V TH_1503 > V OUT + V TH_1503 This can be simplified to: V EXT = V OUT + V GS_107 , where KALIB_DURHGEFÜFAHRT goes high when V GS_107 + I BIAS (R CAL ) > V TH_105 .

[0120] Fig. Figure 16 is a schematic diagram of an LDO voltage regulator configured for load balancing using a calibrated voltage source, in another example. This example is similar to the one referenced in Fig. The example described in 14D, except that a load sensing and tracking circuit arrangement in Fig. Figure 16 is shown as an example. Furthermore, the external pass-through element is not yet connected, but would be connected between the V IN - and V OUT -connection coupled, as shown in other figures, and its control connection being connected to the VDRV EXT -connection is coupled, as in Fig. Figure 16 shows that the FET MP1 is also controlled by a comparator 1601, whose inverting input in this example is connected to the node between the resistor R. LIM and the voltage source V CAL is coupled, whose non-inverting input is coupled to the gate and drain of MN1, so that it sets the threshold voltage V LIM_INT receives, and whose output is coupled to the control terminal of FET MP1 (to V PINT to provide). As further shown, V LIM_INT by controlling the maximum current I LIM_INT The replica FET MN1 is set, and the replica FET MN2 is used for load sensing, as described above. In this example, the replica FET MN1 is N times smaller than the internal pass-through element 105n, and the replica FET MN2 is K times smaller than the internal pass-through element 105n (e.g., based on W / L ratios, as described above). In operation, VDRV INT with I LOAD to, until I LIM_INT This is achieved, which in turn causes the FET MN2 I LOAD pursued until I LIM_INT This is achieved, which means that the resistances provided by MP6 and MN3 are also I LOAD follow until I LIM_INT This achieves a load-tracking zero using MP3 for pole-zero compensation and enables internal compensation for the LDO voltage regulator. In more detail, and as above with reference to Fig. 6 further described if I LOAD increases, takes V ZERO_LOAD at the drains of FETs MP6 and MN2, which in turn reduces the resistance of FET MP3 (or otherwise pushes MP3 towards its low impedance or on state) and C PZ This allows compensation for higher load currents. In contrast, if I LOAD decreases, V ZERO_LOAD to, which in turn increases the resistance of MP3 (or otherwise pushes MP3 towards its high-impedance or on-state), ultimately opening the compensation path so that C PZ not with C EXT competes and causes instability at lower load currents. In this example of Fig. 16 can R ZMAX The error amplifier 101 can be used to provide additional bias for the compensation path. The description above applies equally here.

[0121] As shown in this example, load balancing is achieved using an impedance divider (R). LIM and MP1), whose output is coupled to the control terminal of the internal pass-through element 105n, and a voltage source V CAL , which is coupled between the output of the error amplifier 101 and the control terminal of the internal pass-through element 105n. Such a configuration allows an increase in the voltage at the control terminal of the internal pass-through element 105n, instead of a decrease in the voltage at the control terminal of the external pass-through element 107n. A variation of this circuit is the same circuit, only without the voltage source V. CAL , which is coupled between RLIM and the control port of the pass-through element 105n, and instead with a restriction that the internal pass-through element 105n is stronger than the external pass-through element 107n, as further shown below with reference to the examples of Fig. 17A-C and 18A-C explained. Load balancing with restricted external passage element

[0122] Fig. Figure 17A is a schematic diagram of an LDO voltage regulator configured for load balancing using an external n-type pass-through element constrained with respect to an internal n-type pass-through element, in an example. This example is similar to the example of Fig. 12A, except that there is no voltage source V CAL at each of the control terminals for the internal and external pass-through elements 105n and 107n. Instead, the output of the impedance divider (R) LIM and R INT ) is coupled to the control terminal of the internal pass-through element 105n, and the control terminal of the pass-through element 107n is directly coupled to the output of the error amplifier 101. As further shown in the dashed highlighted circle in Fig. As shown in Figure 17A, the NMOS FETs 105n and 107n can be implemented with other transistor technologies, such as NPN BJTs, or a combination of different transistor technologies (e.g., BJT and FET), as described above. Furthermore, in this example, the external passband 107n is restricted to be weaker than the internal passband 105n. Therefore, if the passbands 105n and 107n are NMOS FETs, then V TH(GS)_107n so restricted that they are larger than V TH(GS)_105n is; or if the pass-through elements are 105n and 107n NPN-BJTs, then V TH(BE)_107n so restricted that they are larger than V TH(BE)_105n is; or if the passband element 105n is an NMOS-FET and the passband element 107n is an NPN-BJT, then V TH(BE)_107n so restricted that they are larger than V TH(GS)_105n More generally, the turn-on voltage of the forward element 107n is so limited that it is greater than the turn-on voltage of the forward element 105n.

[0123] Considering that the threshold voltage of the pass-through element is 107n (V TH_107n ) greater than the threshold voltage of the pass-through element 105n (V TH_105n An example of operation is as follows. As the load current increases, the gate-to-source overdrive (V) increases. GS ) from amplifier 101. The I LIM_INT For the pass-through element 105n, the overdrive is limited (e.g., |V). GS |) of the pass-through element 105n using the variable impedance voltage divider (R LIM and R INT ) implemented at the common gate driver output. Example equations include: IINT∝VDRVINT; VDRVINT=VDRVEXT∗RINT / (RINT+RLIM), or VDRVINT=1 / [1+RLIM / RINT]∗VDRVEXT; VDRVEXT∝sqrt(ILOAD); VDRVINT∝sqrt(ILOAD)∗RINT; and If RINT∝1 / sqrt(ILOAD) after ILOAD>ILIM_INT, then VDRVINT independent of ILOAD to ILOAD>ILIM_INT; where ∝ refers to proportionality, and sqrt refers to square root, and each of the reference parameters is as defined above.

[0124] Fig. Figure 17B is a schematic diagram of an LDO voltage regulator configured for load balancing using an external n-type pass-through element, constrained with respect to an internal n-type pass-through element, in another example. This example is similar to the example of Fig. 17A, with the exception that R INT is implemented with the PMOS-FET MP1. As further explained in Fig. As shown in Figure 17B, the FET MP1 is controlled by the comparator 1701, whose inverting input in this example is connected to the node between the resistor R LIM and is coupled to the control terminal of the pass-through element 105n, whose non-inverting input is coupled to the gate and drain of the FET MN1, so that it sets the threshold voltage V LIM_INT receives, and whose output is coupled to the control terminal of FET MP1 (to V PINT to provide). The FET MN1 is between the V OUT -connection and the V CP -connection (or the V) IN (Connection in other examples that do not require a higher charging pump voltage) is coupled, and its gate is coupled to its drain and its source is coupled to the V OUT -connection coupled. The FET MN1 is a scaled-down replica of the internal pass-through element 105n, where the internal pass-through element 105n is N times larger, where N is an integer of 2 or more, and the above previous relevant description regarding dimensioning based on W / L ratios applies equally here. As further shown, V LIM_INT by controlling the maximum current I LIM_INT set in the replica FET MN1. As further shown in the dashed highlighted circle of Fig. As shown in Figure 17B, the NMOS FETs 105n, 107n, and MN1 can be implemented with other transistor technologies, such as NPN BJTs, or a combination of different transistor technologies (e.g., BJT and FET), as described above. Furthermore, in this example, the external passband 107n is restricted to be weaker than the internal passband 105n. Therefore, if the passbands 105n and 107n are NMOS FETs, then V TH(GS)_107n so restricted that they are larger than V TH(GS)_105n is; or if the pass-through elements are 105n and 107n NPN-BJTs, then V TH(BE)_107n so restricted that they are larger than V TH(BE)_105n is; or if the passband element 105n is an NMOS-FET and the passband element 107n is an NPN-BJT, then V TH(BE)_107n so restricted that they are larger than V TH(GS)_105n More generally, the turn-on voltage of the forward element 107n is so limited that it is greater than the turn-on voltage of the forward element 105n.

[0125] Considering that the threshold voltage of the pass-through element is 107n (V TH_107n ) greater than the threshold voltage of the pass-through element 105n (V TH_105n An example of a company that is VDRV is as follows. EXT smaller than V LIM_INT If this is the case, then FET MP1 is switched off (e.g., if R is switched off). INT OPEN), the current through MP1 (R INT ) is zero, and VDRV INT is the same as VDRV EXT (Output of amplifier 101). For I LOAD < I LIM_INT , while I LOAD as increases, VDRV takes INT to what load tracking between VDRV INT and V OUT enabled. While VDRV INT greater than V LIM_INT The output of comparator 1701 (V) PINT ) goes low, and the FET MP1 starts to draw current, causing a drop across R LIM This causes what VDRV INT on V LIM_INT This leads back to a higher I. LOAD This is satisfied by the passage element 107n. Example equations include: VDRVEXT=sqrt[(ILOAD−ILIM_INT) / βEXT]+VOUT+VTH_107n; IRLIM=(VDRVEXT−VLIM_INT) / RLIM; IRLIM∝sqrt[ILOAD / βEXT] / RLIM;(saturation) RINT≥VDRVINT / IRLIM≥VLIM_INT / IRLIM; and RINT∝1 / sqrt[ILOAD]; where I RLIM the current through R LIM is, β EXT The technology parameter of the passage element 107n is , where ∝ refers to proportionality and sqrt refers to square root.

[0126] Fig. Figure 17C is a schematic diagram of an LDO voltage regulator configured for load balancing using an external n-type pass-through element, constrained with respect to an internal n-type pass-through element, in another example. This example is based on the example of Fig. 17B similar, except that the FET MP1 is directly connected through the V LIM_INT -voltage is controlled. As further explained in Fig. Shown in 17C is a bias circuit that controls the FET MP BIAS and the power source I BIAS includes, provided to help with V PINT To adjust. More specifically, the PMOS-FET MP BIAS It is a replica of the PMOS-FET MP1 and is in series with the current source I. BIAS between the V OUT - and ground connection coupled, and its source connection is connected to the V OUT The -terminal is coupled, and its gate and drain terminals are coupled to the source terminal of MN1. Furthermore, the current bias I BIAS between the gate and drain of the FET MP BIAS and coupled to the ground connection. In this example, the V PINT The signal controlling the variable impedance of MP1 is generated by compensating (subtracting) a diode drop that is added by the FET MP1. More precisely, the FET MP1 is turned on when VDRV INT greater than (V UM_INT + VSG_MP1 - VSG_MP BIAS ) where VSG_MP1 is the source-to-gate voltage of MP1 and VSG_MP BIAS the source-to-gate voltage of MP BIAS is. In this way, the replica FET MP represents BIAS A PMOS down (VSG) is ready to compensate for the PMOS up provided by MP1. As further shown in the dashed highlighted circle of Fig. As shown in Figure 17C, the NMOS-FETs 105n, 107n and MN1 can be implemented with other transistor technologies, such as NPN-BJTs, or a combination of different transistor technologies (e.g., BJT and FET), as described above.

[0127] Fig. Figure 18A is a schematic diagram of an LDO voltage regulator configured for load balancing using an external p-type pass-through element constrained with respect to an internal p-type pass-through element, in an example. This example is similar to the example of Fig. 12B, except that there is no voltage source V CAL Each of the control terminals for the internal and external pass-through elements 105p and 107p is present. As shown, the output of the impedance divider (R) LIM and R INT ) is coupled to the control terminal of the internal passband 105p, and the control terminal of the passband 107p is directly coupled to the output of the error amplifier 101. Furthermore, in this example, the external passband 107p is limited to be weaker than the internal passband 105p. Therefore, if the passbands 105p and 107p are PMOS FETs, then V TH(GS)_107p so restricted that they are larger than V TH(GS)_105p is; or if the passband elements are 105p and 107p PNP-BJTs, then V TH(BE)_107p so restricted that they are larger than V TH(BE)_105p is; or if the passband element 105p is a PMOS-FET and the passband element 107p is a PNP-BJT, then V TH(BE)_107p so restricted that they are larger than V TH(GS)_105p More generally, the turn-on voltage of the forward element 107p is limited to be greater than the turn-on voltage of the forward element 105p. As further shown in the dashed highlighted circle of Fig. As shown in Figure 18A, the PMOS-FETs 105p and 107p can be implemented with other transistor technologies, such as PNP-BJTs, or a combination of different transistor technologies (e.g., BJT and FET), as described above.

[0128] Considering that the threshold voltage of the pass-through element is 107p (V TH_107p ) greater than the threshold voltage of the pass-through element 105p (V TH_105p An example of operation is as follows. As the load current increases, the gate-to-source overdrive (V) increases. GS ) from amplifier 101. The I LIM_INT For the pass-through element 105p, the overdrive is limited (e.g., |V). GS |) of the pass-through element 105p using the variable impedance voltage divider (R LIM and R INT ) implemented at the common gate driver output. Example equations include equations 6 to 10 above.

[0129] Fig. Figure 18B is a schematic diagram of an LDO voltage regulator configured for load balancing using an external p-type pass-through element, constrained with respect to an internal p-type pass-through element, in another example. This example is similar to the example of Fig. 18A, with the exception that R INT is implemented with the NMOS-FET MN1. As further explained in Fig. As shown in Figure 18B, the FET MN1 is controlled by the comparator 1801, whose inverting input in this example is connected to the node between the resistor R LIM and is coupled to the control terminal of the pass-through element 105p, whose non-inverting input is coupled to the gate and drain of MP1, so that it sets the threshold voltage V LIM_INT receives, and whose output is coupled to the control terminal of FET MN1 (to V NINT to provide). As further shown, V LIM_INT by controlling the maximum current I LIM_INT The replica FET MP1 is set as described above. Furthermore, in this example, the external passband 107p is restricted to be weaker than the internal passband 105n. Therefore, if the passbands 105p and 107p are PMOS FETs, then V TH(GS)_107p so restricted that they are larger than V TH(GS)_105p is; or if the passband elements are 105p and 107p PNP-BJTs, then V TH(BE)_107p so restricted that they are larger than V TH(BE)_105p is; or if the passband element 105p is a PMOS-FET and the passband element 107p is a PNP-BJT, then V TH(BE)_107p so restricted that they are larger than V TH(GS)_105p More generally, the turn-on voltage of the forward element 107p is limited to be greater than the turn-on voltage of the forward element 105p. As further shown in the dashed highlighted circle of Fig. As shown in Figure 18B, the PMOS-FETs 105p, 107p and MP1 can be implemented with other transistor technologies, such as PNP-BJTs, or a combination of different transistor technologies (e.g., BJT and FET), as described above.

[0130] Considering that the threshold voltage of the pass-through element is 107p (V TH_107p ) greater than the threshold voltage of the pass-through element 105p (V TH_105p An example of a company that is VDRV is as follows. EXT smaller than V LIM_INT If R is switched off, then FET MN1 is switched off (e.g., if R is switched off). INT OPEN), the current through MN1 (R INT ) is zero, and VDRV INT is the same as VDRV EXT (Output of amplifier 101). For I LOAD < I LIM_INT , while I LOAD as increases, VDRV takes INT to what load tracking between VDRV INT and V OUT enabled. While VDRV INT greater than V LIM_INT The output of the comparator 1801 (V) NINT ) goes low, and the FET MN1 starts to draw current, resulting in a drop across R LIM This causes what VDRV INT on V LIM_INT This leads back to a higher I. LOAD This is satisfied by the passage element 107p. Example equations include equations 11 to 15 above.

[0131] Fig. Figure 18C is a schematic diagram of an LDO voltage regulator configured for load balancing using an external p-type pass-through element, constrained with respect to an internal p-type pass-through element, in another example. This example is based on the example of Fig. 18B is similar, except that the FET MN1 is directly connected through the V LIM_INT -voltage is controlled. As further explained in Fig. Shown in 18C is a bias circuit that controls the FET MN BIAS and the power source I BIAS includes, provided to help with V NINT To adjust. More specifically, the NMOS-FET MN BIAS It is a replica of the NMOS-FET MN1 and is in series with the current source I. BIAS between a secondary supply voltage (V SUP The VLIM_INT node (source and drain of MP1) is coupled to its source terminal and the VLIM_INT node (source and drain of MP1), and its gate and drain terminals are coupled to the control terminal of MN1. SUP This can be any suitable power supply, such as a boost converter. Furthermore, the current bias I BIAS between the gate and drain of the FET MN BIAS and the V SUP -connection coupled. In this example, the V NINT The signal controlling the variable impedance of MN1 is generated by compensating (adding) a diode drop that is subtracted by the FET MN1. More precisely, the FET MN1 is turned on when VDRV INT smaller than (V UM_INT -VSG_MN1 + VSG_MN BIAS ) where VSG_MN1 is the source-to-gate voltage of MN1 and VSG_MN BIAS the source-to-gate voltage of MN BIAS is. In this way, the replica FET MN represents BIAS An NMOS up (VSG) is ready to compensate for the NMOS down provided by MN1. As further shown in the dashed highlighted circle of Fig. As shown in Figure 18C, the PNP-BJTs 105p, 107p and MP1 can be implemented with other transistor technologies, such as PMOS-FETs, or a combination of different transistor technologies (e.g. BJT and FET), as described above.

[0132] Fig. Figure 19 is a block diagram of an electronic system that includes an LDO voltage regulator configured for load balancing, in one example. As shown, the system includes a power supply 1901, an LDO voltage regulator 100, an external pass-through element 107, a filter and feedback network 1903, and an application-based system 1905 that includes one or more subcomponents requiring power. Other example systems may be configured differently based on the specific application. More generally, the LDO voltage regulator 100 can be used in the context of any electronic system that requires one or more regulated power supplies.

[0133] The power supply 1901 is designed to provide the input voltage and can be, for example, a battery or battery pack (e.g., a car battery) or an unregulated power supply. The LDO voltage regulator 100 can be any of the LDO voltage regulators described herein (including 100, 100n, 100p, 100nc, and 100pc, or a combination thereof) or any variation thereof. The filter and feedback network 1903 can, for example, be a resistor network including R1 and R2 and an output capacitor C. EXT include, for example, in Fig. 1 shown. The external passage element 107 is located between the V IN - and V OUT -connection coupled, and its control connection is coupled to the output signal connection of the LDO voltage regulator 100, similar to the one in Fig. The exemplary circuit shown in Figure 10. The previous relevant description applies equally here.

[0134] The LDO voltage regulator 100 and the external pass-through element 107 can be either n-type or p-type and can be implemented with any number of transistor technologies, as described in various ways here. The LDO voltage regulator 100 is designed to provide load balancing with a single driver (e.g., error amplifier 101) for an internal element within the regulator 100 and an external pass-through element 107. In some such examples, a first and second voltage divider (as in Fig. (shown in Figures 3 to 10) is used, where each divider has a similar variable impedance arranged in a complementary manner relative to the variable impedance of the other divider. The coupling of the dividers within the voltage regulator circuit and the location of the variable impedance within a given divider depend on the type of voltage regulator. For example, for an n-type LDO voltage regulator (e.g., Fig. 3-6) The first and second voltage dividers are each coupled between the output of the error amplifier and a ground connection, the output of the first voltage divider being coupled to the control terminal of the internal pass-through element, and a variable impedance being present at the lower position of this divider; and the output of the second voltage divider being coupled to the control terminal of the external pass-through element, and a variable impedance being present at the upper position of this divider. For a p-type voltage regulator (e.g., Fig. 7-10) the first and second voltage dividers are each coupled between the output of the error amplifier and the input voltage terminal, wherein the output of the first voltage divider is coupled to the control terminal of the internal pass-through element, and a variable impedance is located at the upper position of this divider, and the output of the second voltage divider is coupled to the control terminal of the external pass-through element, and a variable impedance is located at the lower position of this divider.

[0135] In other examples, the LDO voltage divider 100 can be configured with only one variable voltage divider together with a selectively applied calibrated voltage source to automatically adjust load balancing based on the load current (e.g., as in Fig. 12A-B, Fig. 14D-E and Fig. 16). A calibration circuit arrangement and methods for determining the value of the calibrated voltage source (e.g., as in Fig. (13A-B, 14A-C, and 15 shown), can be located on the chip or otherwise internal to the regulator 100 and can be operated, for example, during the start-up of the voltage regulator (calibration mode). As described above, the calibration circuit arrangement can be designed to detect the difference between the threshold or overdrive voltages of an external and internal pass-through element, and this voltage difference can then be used as the calibrated voltage source. Once determined, the voltage source can then be applied to the control terminal of the internal pass-through element or external pass-through element 107 to compensate for the difference in strength between the two pass-through elements and to enable load balancing during the regular operation (run-off mode) of the voltage regulator 100. The calibrated voltage source can also be used to enable load-dependent pole-zero compensation with an external pass-through element.

[0136] In other examples, the LDO voltage regulator 100 can be configured with only one variable voltage divider (e.g., to automatically adjust load balancing based on the load current), where the external pass-through element 107 can be restricted to be weaker than the internal pass-through element of the regulator 100 to enable load balancing (e.g., as in Fig. 17A-18C shown).

[0137] The LDO voltage regulator 100 can be configured for load-tracking pole-zero compensation using the external pass-through element 107. More specifically, linear voltage regulators employ two-type stability compensation, using two poles and one zero with respect to the unit gain bandwidth to stabilize the control loop. The zero is held outside the unit gain bandwidth to boost the phase with little or no effect on gain roll-off. As the load current increases, the output pole moves out, and the unit gain bandwidth increases. This can result in a constant-frequency zero occurring within the unit gain bandwidth.An LDO voltage regulator with an internal pass-through element can use a load-tracking zero, employing a replica FET (or other replica pass-through element) to mirror / track the load current. This allows the zero to be held at a lower frequency at low loads, moving further out as the load current increases. However, an LDO voltage regulator with an external pass-through element cannot use a load-tracking zero solution because the pass-through element transfer characteristics are unknown (e.g., there is no replica device for a customer-supplied external pass-through element), and therefore the load current cannot be tracked by the voltage regulator.The output pole must therefore be kept outside the unity gain bandwidth (which can increase the quiescent current), or the external compensation component(s) must be used (which can limit the bandwidth). Thus, and according to some examples described here, the voltage regulator 100 is configured for load balancing, as shown in [reference]. Fig. Figures 1 and 2A-D are shown. In some such cases, for example, the internal pass-through element of the controller 100 carries the load current I. LOAD , until I LOAD >I STB , where I STB The minimum load current is at which the output pole moves to more than 10 times the unit gain bandwidth and the internal pole takes over. This enables a load-tracking zero until I LOAD = I STB , even if the external passage element 107 is connected. After I LOAD the I STB -threshold is exceeded, the external pass-through element 107 starts to equalize the load current with the internal pass-through element until the current through the internal pass-through element (I INT ) I LIM_INT achieved, whereby I LIM_INT The maximum load current that the internal pass-through element can reliably carry. After I LOAD I LIM_INT exceeds the current through the external pass-through element (I). EXT ) approximately I LOAD -I LIM_INT .

[0138] As further in Fig. As shown in 19, the application-based system was developed in 1905 between the V OUT - and V RTN - (e.g., ground) connection coupled. The configuration of the application-based system 1905 will vary from one example to the next, but in this example includes one or more processors, one or more sensors, one or more interfaces, memory and storage, and an application circuit arrangement. In some examples, the electronic system is part of an electronic vehicle system, such as a camera system or other detection system (e.g., a blind spot monitoring system). In other examples, the electronic system is part of a control system, such as an electronic radar control unit configured with radar and video interfaces (e.g., for air traffic control). In still other examples, the electronic system is part of a medical system, such as an electrocardiogram system that includes a non-isolated DC-DC power supply (e.g., for air traffic control). Further exemplary embodiments

[0139] The following examples relate to further embodiments, from which numerous permutations and configurations become apparent.

[0140] Example 1 is a circuit comprising: an input voltage terminal; an output voltage terminal; a feedback voltage terminal; an output signal terminal; a pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to the feedback voltage terminal; and a load balancing circuit with an input, a first output and a second output, wherein the input of the load balancing circuit is coupled to the control terminal of the pass-through element and the second output of the load balancing circuit is coupled to the output signal terminal.In some such examples, the pass-through element is an n-type pass-through element.

[0141] Example 2 includes the circuit of Example 1, wherein: the load balancing circuit is designed to generate a first and second drive voltage at the first and second outputs of the load balancing circuit, respectively, based on a drive voltage generated by the error amplifier; wherein both the first and second drive voltages are associated with a rate of change relative to changes in the drive voltage generated by the error amplifier; and the rate of change of the first drive voltage decreases while the rate of change of the second drive voltage increases.

[0142] Example 3 includes the circuit of Example 1 or 2, wherein: the load balancing circuit is designed to generate a first and second drive voltage at the first and second outputs of the load balancing circuit, respectively, based on a drive voltage generated by the error amplifier; wherein a first gain between the amplifier output and the first output of the load balancing circuit decreases relative to increases in the drive voltage generated by the error amplifier; and a second gain between the amplifier output and the second output of the load balancing circuit increases relative to increases in the drive voltage generated by the error amplifier.

[0143] Example 4 includes the circuit of one of Examples 1 to 3, where: the load balancing circuit is designed to provide a first and second control voltage at the first and second terminals, respectively.to generate a second output of the load balancing circuit based on a drive voltage generated by the error amplifier, in response to the first drive voltage at the first output of the load balancing circuit exceeding a first threshold voltage, the load balancing circuit is designed to decrease a rate of change of the first drive voltage relative to changes in the drive voltage generated by the error amplifier; and in response to the first drive voltage at the first output of the load balancing circuit exceeding a second threshold voltage, the load balancing circuit is designed to increase a rate of change of the second drive voltage relative to changes in the drive voltage generated by the error amplifier.

[0144] Example 5 includes the circuit of one of Examples 1 to 4, wherein: the circuit is designed to supply a load current to the output voltage terminal; in response to the load current being less than or equal to a first current threshold, the load balancing circuit is designed to supply substantially all of the load current through the pass-through element; and in response to the load current being greater than a second current threshold, the load balancing circuit is designed to limit the current supplied through the pass-through element, the second current threshold being greater than the first current threshold.

[0145] Example 6 includes the circuit of Example 5, wherein: in response to the load current being greater than the first current threshold, the load balancing circuit is designed to provide a first part of the load current through the pass-through element and to control an external pass-through element to provide a second part of the load current.

[0146] Example 7 includes the circuit of Example 6 and further includes the external pass-through element, wherein the external pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal, such that the second part of the load current is provided through the external pass-through element. In some such cases, the external pass-through element is an n-type pass-through element. For example, in some such examples, the elements of Example 1 are located on an integrated circuit die within an integrated circuit package or are otherwise part of it (e.g., ceramic flat pack with leads, ball grid array, etc.), and the external pass-through element is external to this integrated circuit package. In other examples, the elements of Example 1 are located on a printed circuit board or are otherwise part of it (e.g.,Single-sided, double-sided, multi-layer, flexible, etc.), and the external pass-through element is located external to this printed circuit board. Other examples may be configured differently. Therefore, the level of integration can vary from one example to the next.

[0147] Example 8 includes the circuit of Example 7, wherein: both the passband element and the external passband element are n-channel field-effect transistors or NPN bipolar transistors; or one of the passband element and the external passband element is an n-channel field-effect transistor and the other of the passband element and the external passband element is an NPN bipolar transistor.

[0148] Example 9 includes the circuit of one of Examples 1 to 8, wherein the load balancing circuit comprises: a first impedance divider coupled between the amplifier output and a ground terminal, wherein the first impedance divider includes an output coupled to the first output of the load balancing circuit; and a second impedance divider coupled between the amplifier output and the ground terminal, wherein the second impedance divider includes an output coupled to the output signal terminal.

[0149] Example 10 includes the circuit of Example 9, wherein: the first impedance divider includes a first variable impedance coupled between the output of the first impedance divider and the ground connection; and the second impedance divider includes a second variable impedance coupled between the amplifier output and the output of the second impedance divider.

[0150] Example 11 incorporates the circuit from Example 10, with the first variable impedance including a first field-effect transistor (FET) and the second variable impedance including a second FET. In some such examples, the load balancing circuit includes: a resistor coupled between the amplifier output and a source terminal of the first FET, the resistor and the first FET providing the first impedance divider; and a pull-down circuit coupled between the output signal terminal and the ground terminal, the pull-down circuit and the second FET providing the second impedance divider. In some such examples, the resistor is a first resistor, and the pull-down circuit includes a second resistor and / or a current source.

[0151] Example 12 includes the circuit of Example 11, wherein the resistor is a first resistor, and the load balancing circuit comprises one or more of the following: a third FET coupled between the output voltage terminal and one of the input voltage terminals or a charge pump terminal, wherein the third FET has a gate terminal coupled to a drain terminal and a source terminal coupled to the output voltage terminal; a fourth FET having a gate terminal coupled to a drain terminal and the gate terminal of the first FET, and a source terminal coupled to the gate and drain terminals of the third FET; a first current source coupled between the drain terminal of the fourth FET and the ground terminal;a fifth FET coupled between the ground terminal and one of the input voltage terminal or the charge pump terminal, wherein the fifth FET has a gate terminal coupled to a drain terminal via a second resistor, and a source terminal coupled to one of the input voltage terminal or the charge pump terminal, the drain terminal of the fifth FET being coupled to the gate terminal of the second FET; and / or a second current source coupled between the gate terminal of the fifth FET and the ground terminal. In some such examples: the forward element is of the same type as the third FET, but N times larger, where N is an integer of 2 or more; the first FET and the fourth FET are of the same type; and the second FET and the fifth FET are of the same type.

[0152] Example 13 includes the circuit of Example 12, and further includes: a buffer circuit with a buffer input and a buffer output, wherein the buffer input is coupled to a second output stage of the error amplifier; a sixth FET with a gate terminal coupled to the control terminal of the pass-through element and a source terminal coupled to the output voltage terminal; a seventh FET coupled between the buffer output and the sixth FET, having a gate terminal coupled to a drain terminal and the drain terminal of the sixth FET, and a source terminal coupled to the buffer output; an eighth FET with a gate terminal coupled to the gate and drain terminals of the seventh FET, and a source terminal coupled to the second output stage of the error amplifier;and a capacitor coupled between a drain terminal of the eighth FET and a first output stage of the error amplifier.

[0153] Example 14 includes the circuit of Example 10 or 11, wherein the load balancing circuit comprises: a first comparator circuit designed to control the first variable impedance; and a second comparator circuit designed to control the second variable impedance. In some such examples: the first comparator circuit has a first comparator input coupled to the first output of the load balancing circuit and a first comparator output coupled to the gate terminal of the first FET; and the second comparator circuit has a second comparator input coupled to the first output of the load balancing circuit and a second comparator output coupled to the gate terminal of the second FET.

[0154] Example 15 includes the circuit of one of Examples 1 to 8, wherein the load balancing circuit includes an impedance divider coupled between the amplifier output and a ground terminal, the impedance divider having an output coupled to the first output of the load balancing circuit. In some such examples, the amplifier output is coupled to the output signal terminal without an intervening impedance divider. For example, the amplifier output may be directly coupled to the output signal terminal.

[0155] Example 16 includes the circuit of one of Examples 1 through 15, wherein the passband element is a first passband element (which in some examples is, for instance, an internal passband element), and wherein the circuit includes a second passband element (which in some examples is, for instance, an external passband element) coupled between the input voltage terminal and the output voltage terminal, and has a control terminal coupled to the output signal terminal. In some such examples (e.g., Example 15), the second passband element is weaker than the first passband element. For example, in some such examples, both the first and second passband elements may be, for instance, an n-channel FET, and the threshold voltage of the first passband element is lower than the threshold voltage of the second passband element.In other such examples, both the first and second passband elements are NPN BJTs, and the threshold voltage of the first passband element is lower than the threshold voltage of the second passband element. In still other such examples, one of the first and second passband elements is an NPN BJT, and the other of the first and second passband elements is an n-channel FET, and the threshold voltage of the first passband element is lower than the threshold voltage of the second passband element.

[0156] Example 17 includes the circuit of one of Examples 1 to 16, wherein the pass-through element is restricted to be stronger than any external pass-through element that is to be coupled to the output signal terminal.

[0157] Example 18 includes the circuit of one of Examples 1 to 8 and 15 to 17, and further includes a voltage source coupled between the amplifier output and the control terminal of the pass-through element or between the amplifier output and the output signal terminal.

[0158] Example 19 includes the circuit of Example 18, wherein the voltage source is designed to adjust a control voltage at the control terminal of the pass-through element up or down, or to adjust a control voltage at the output signal terminal up or down, and wherein the voltage source includes a resistor circuit with a calibrated resistance value and a current source with a current value, and wherein the current value was used to determine the calibrated resistance.

[0159] Example 20 includes the circuit of Example 18 or 19, wherein the voltage source is enclosed in the calibration circuit and is coupled between the amplifier output and the first output of the load balancing circuit or between the amplifier output and the second output of the load balancing circuit.

[0160] Example 21 includes the circuit of one of Examples 1 to 20, wherein the error amplifier is designed to generate a drive voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage at the reference voltage terminal.

[0161] Example 22 is a system comprising: the circuit of one of Examples 1 to 21, wherein the pass-through element is a first pass-through element (which may be, for example, an internal pass-through element), a second pass-through element (which may be, for example, an external pass-through element) coupled between the input voltage terminal and the output voltage terminal, and a control terminal coupled to the output signal terminal. In some such examples, the system further comprises a power supply coupled to the input voltage terminal and / or a load coupled to the output voltage terminal.

[0162] Example 23 is a circuit comprising: an input voltage terminal; an output voltage terminal; a feedback voltage terminal; an output signal terminal; a pass-through element coupled between the input voltage terminal and the output voltage terminal, having a control terminal, the pass-through element being an n-type pass-through element; an error amplifier designed to generate an error amplifier output voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage; a first impedance divider comprising a first variable impedance and designed to generate a first drive voltage at the control terminal of the pass-through element based on the error amplifier output voltage;and a second impedance divider, which includes a second variable impedance and is designed to generate a second drive voltage at the output signal terminal based on the error amplifier output voltage.

[0163] Example 24 includes the circuit of Example 23, wherein: the error amplifier has a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input being coupled to a reference voltage terminal and the second amplifier input being coupled to the feedback voltage terminal; the first impedance divider is coupled between the amplifier output and a ground terminal and includes an output coupled to the control terminal of the pass-through element, the first variable impedance being coupled between the output of the first impedance divider and the ground terminal; and the second impedance divider is coupled between the amplifier output and the ground terminal and includes an output coupled to the output signal terminal, the second variable impedance being coupled between the amplifier output and the output of the second impedance divider.

[0164] Example 25 includes the circuit of Example 23 or 24, wherein: both the first and second drive voltages are associated with a rate of change relative to changes in the error amplifier output voltage; and the rate of change of the first drive voltage decreases while the rate of change of the second drive voltage increases.

[0165] Example 26 includes the circuit of one of Examples 23 to 25, wherein: a first gain between the amplifier output and the control terminal of the pass-through element decreases relative to increases in the error amplifier output voltage; and a second gain between the amplifier output and the output signal terminal increases relative to increases in the error amplifier output voltage.

[0166] Example 27 includes the circuit of one of Examples 23 to 26, wherein: the circuit is designed to supply a load current to the output voltage terminal; in response to the load current being less than or equal to a first current threshold, the circuit supplies substantially all of the load current through the pass-through element; in response to the load current being greater than a second current threshold, the circuit limits the current supplied through the pass-through element, the second current threshold being greater than the first current threshold; and in response to the load current being greater than the first current threshold, the first and second impedance dividers cause a first portion of the load current to be supplied through the pass-through element and a second portion of the load current to be supplied through an external n-type pass-through element.

[0167] Example 28 includes the circuit of one of Examples 23 to 27, and further includes the external n-type pass-through element, wherein the external n-type pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal.

[0168] Example 29 includes the circuit of Example 28, wherein: both the passband element and the external passband element are n-channel field-effect transistors or NPN bipolar transistors; or one of the passband element and the external passband element is an n-channel field-effect transistor and the other of the passband element and the external passband element is an NPN bipolar transistor.

[0169] Example 30 is a system comprising: a first n-type pass-through element coupled between an input voltage terminal and an output voltage terminal and having a control terminal; a second n-type pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to a feedback voltage terminal;a first impedance divider coupled between the amplifier output and a ground terminal, comprising an output coupled to the control terminal of the first n-type pass-through element, the first impedance divider further comprising a first variable impedance coupled between the output of the first impedance divider and the ground terminal; and a second impedance divider coupled between the amplifier output and the ground terminal, comprising an output coupled to the control terminal of the second n-type pass-through element, the second impedance divider further comprising a second variable impedance coupled between the amplifier output and the output of the second impedance divider.

[0170] Example 31 includes the system of Example 30, and further includes a power supply coupled to the input voltage connection.

[0171] Example 32 includes the system of Example 30 or 31, and further includes a load coupled to the output voltage terminal.

[0172] Example 33 includes the system of one of Examples 30 to 32, and further includes an electronic system which may, for example, be coupled between the output voltage terminal and the ground terminal.

[0173] Example 34 includes the system of Example 33, where the electronic system is an electronic vehicle system. For example, in such an example, the electronic vehicle system is a camera system.

[0174] Example 35 includes the system of Example 33, where the electronic system is a control system. For example, in such an example, the control system is an electronic radar control unit.

[0175] Example 36 includes the system of Example 33, where the electronic system is a medical system. For example, in such an example, the medical system is an electrocardiogram system.

[0176] Example 37 includes the system of one of Examples 30 to 36, wherein the first n-type pass-through element, the error amplifier, the first impedance divider and the second impedance divider are contained in an integrated circuit chip and the second n-type pass-through element is located external to the integrated circuit chip.

[0177] Example 38 is a circuit comprising: an input voltage terminal; an output voltage terminal; a feedback voltage terminal; an output signal terminal; a pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal; an error amplifier with a first amplifier input, a second amplifier input, and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to the feedback voltage terminal; and a load balancing circuit with an input, a first output, and a second output, wherein the input of the load balancing circuit is coupled to the control terminal of the pass-through element and the second output of the load balancing circuit is coupled to the output signal terminal.In some such examples, the pass-through element is a p-type pass-through element.

[0178] Example 39 includes the circuit of Example 38, wherein: the load balancing circuit is designed to generate a first and second drive voltage at the first and second outputs of the load balancing circuit, respectively, based on a drive voltage generated by the error amplifier; wherein both the first and second drive voltages are associated with a rate of change relative to changes in the drive voltage generated by the error amplifier; and the rate of change of the first drive voltage decreases while the rate of change of the second drive voltage increases.

[0179] Example 40 includes the circuit of Example 38 or 39, wherein: the load balancing circuit is designed to generate a first and second drive voltage at the first and second outputs of the load balancing circuit, respectively, based on a drive voltage generated by the error amplifier; wherein a first gain between the amplifier output and the first output of the load balancing circuit decreases relative to decreases in the drive voltage generated by the error amplifier; and a second gain between the amplifier output and the second output of the load balancing circuit increases relative to decreases in the drive voltage generated by the error amplifier.

[0180] Example 41 includes the circuit of one of Examples 38 to 40, wherein: the load balancing circuit is designed to provide a first and second control voltage at the first and second terminals, respectively.to generate a second output of the load balancing circuit based on a drive voltage generated by the error amplifier, in response to the first drive voltage at the first output of the load balancing circuit falling below a first threshold voltage, the load balancing circuit is designed to decrease the rate of change of the first drive voltage relative to changes in the drive voltage generated by the error amplifier; and in response to the first drive voltage at the first output of the load balancing circuit falling below a second threshold voltage, the load balancing circuit is designed to increase the rate of change of the second drive voltage relative to changes in the drive voltage generated by the error amplifier.

[0181] Example 42 includes the circuit of one of Examples 38 to 41, wherein: the circuit is designed to supply a load current to the output voltage terminal; in response to the load current being less than or equal to a first current threshold, the load balancing circuit is designed to supply substantially all of the load current through the pass-through element; and in response to the load current being greater than a second current threshold, the load balancing circuit is designed to limit the current supplied through the pass-through element, the second current threshold being greater than the first current threshold.

[0182] Example 43 includes the circuit of Example 42, wherein: in response to the fact that the load current is greater than the first current threshold, the load balancing circuit is designed to provide a first part of the load current through the pass-through element and to control an external pass-through element to provide a second part of the load current.

[0183] Example 44 includes the circuit of Example 43 and further includes the external pass-through element, wherein the external pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal, such that the second part of the load current is provided through the external pass-through element. In some such cases, the external pass-through element is a p-type pass-through element. For example, in some such examples, the elements of Example 1 are located on an integrated circuit die within an integrated circuit package or are otherwise part of it (e.g., ceramic flat pack with leads, ball grid array, etc.), and the external pass-through element is external to this integrated circuit package. In other examples, the elements of Example 1 are located on a printed circuit board or are otherwise part of it (e.g.,Single-sided, double-sided, multi-layer, flexible, etc.), and the external pass-through element is located external to this printed circuit board. Other examples may be configured differently. Therefore, the level of integration can vary from one example to the next.

[0184] Example 45 includes the circuit of Example 44, wherein: both the passband element and the external passband element are p-channel field-effect transistors or PNP bipolar transistors; or one of the passband element and the external passband element is a p-channel field-effect transistor and the other of the passband element and the external passband element is a PNP bipolar transistor.

[0185] Example 46 includes the circuit of one of Examples 38 to 45, wherein the load balancing circuit comprises: a first impedance divider coupled between the amplifier output and the input voltage terminal, the first impedance divider including an output coupled to the first output of the load balancing circuit; and a second impedance divider coupled between the amplifier output and the input voltage terminal, the second impedance divider including an output coupled to the output signal terminal.

[0186] Example 47 includes the circuit of Example 46, wherein: the first impedance divider includes a first variable impedance coupled between the output of the first impedance divider and the input voltage terminal; and the second impedance divider includes a second variable impedance coupled between the amplifier output and the output of the second impedance divider.

[0187] Example 48 incorporates the circuit of Example 47, wherein the first variable impedance includes a first field-effect transistor (FET) and the second variable impedance includes a second FET. In some such examples, the load balancing circuit includes: a resistor coupled between the amplifier output and a source terminal of the first FET, the resistor and the first FET providing the first impedance divider; and a pull-up circuit coupled between the output signal terminal and the input voltage terminal, the pull-up circuit and the second FET providing the second impedance divider. In some such examples, the resistor is a first resistor, and the pull-up circuit includes a second resistor and / or a current source.

[0188] Example 49 includes the circuit of Example 48, wherein the resistor is a first resistor, and the load balancing circuit comprises one or more of the following: a current source coupled between the input voltage terminal and the feedback voltage terminal; a second resistor coupled between the current source and the feedback voltage terminal, having a first and second resistor terminal, the first resistor being coupled to the current source; a third FET coupled between the second resistor and the feedback voltage terminal, the third FET having a gate terminal coupled to the first resistor terminal, a drain terminal coupled to the second resistor terminal, and a source terminal coupled to the feedback voltage terminal;and a fourth FET with a gate and drain terminal coupled to the source terminal of the third FET, and a source terminal coupled to the input voltage terminal; wherein the gate terminal of the first FET is coupled to the first resistor terminal and the gate terminal of the second FET is coupled to the second resistor terminal. In some such examples: the forward element is of the same type as the fourth FET, but N times larger, where N is an integer of 2 or more; the first FET and the third FET are of the same type; and the second FET and the third FET are of the same type.

[0189] Example 50 includes the circuit of Example 49, wherein the error amplifier has an output stage, the circuit comprising: a capacitor coupled between the input voltage terminal and the output stage of the error amplifier; and a fifth FET coupled between the input voltage terminal and the capacitor, having a gate terminal coupled to the control terminal of the pass-through element and a source terminal coupled to the input voltage terminal.

[0190] Example 51 includes the circuit of Example 47 or 48, wherein the load balancing circuit comprises: a first comparator circuit designed to control the first variable impedance; and a second comparator circuit designed to control the second variable impedance. In some such examples: the first comparator circuit has a first comparator input coupled to the first output of the load balancing circuit and a first comparator output coupled to the gate terminal of the first FET; and the second comparator circuit has a second comparator input coupled to the first output of the load balancing circuit and a second comparator output coupled to the gate terminal of the second FET.

[0191] Example 52 includes the circuit of one of Examples 38 to 45, wherein the load balancing circuit includes an impedance divider coupled between the amplifier output and the input voltage terminal, the impedance divider having an output coupled to the first output of the load balancing circuit. In some such examples, the amplifier output is coupled to the output signal terminal without an intervening impedance divider. For example, the amplifier output may be directly coupled to the output signal terminal.

[0192] Example 53 includes the circuit of one of Examples 38 to 52, wherein the passband element is a first passband element (which in some examples is, for instance, an internal passband element), and wherein the circuit includes a second passband element (which in some examples is, for instance, an external passband element) coupled between the input voltage terminal and the output voltage terminal, and has a control terminal coupled to the output signal terminal. In some such examples (e.g., Example 52), the second passband element is less sensitive than the first passband element. For example, in some such examples, both the first and second passband elements may be, for instance, a p-channel FET, and the threshold voltage of the first passband element is lower than the threshold voltage of the second passband element.In other such examples, both the first and second passband junctions are PNP-BJTs, and the threshold voltage of the first passband junction is lower than the threshold voltage of the second passband junction. In still other such examples, one of the first and second passband junctions is a PNP-BJT, and the other of the first and second passband junctions is a p-channel FET, and the threshold voltage of the first passband junction is lower than the threshold voltage of the second passband junction.

[0193] Example 54 includes the circuit of one of Examples 38 to 53, wherein the pass-through element is restricted to be stronger than any external pass-through element that is to be coupled to the output signal terminal.

[0194] Example 55 includes the circuit of one of Examples 38 to 45 and 52 to 54, and further includes a voltage source coupled between the amplifier output and the control terminal of the pass-through element or between the amplifier output and the output signal terminal.

[0195] Example 56 includes the circuit of Example 55, wherein the voltage source is designed to adjust a control voltage at the control terminal of the pass-through element up or down, or to adjust a control voltage at the output signal terminal up or down, and wherein the voltage source includes a resistor circuit with a calibrated resistance value and a current source with a current value, and wherein the current value was used to determine the calibrated resistance.

[0196] Example 56 includes the circuit of Example 55 or 56, wherein the voltage source is enclosed in the calibration circuit and is coupled between the amplifier output and the first output of the load balancing circuit or between the amplifier output and the second output of the load balancing circuit.

[0197] Example 57 includes the circuit of one of Examples 38 to 56, wherein the error amplifier is designed to generate a drive voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage at the reference voltage terminal.

[0198] Example 58 is a system comprising: the circuit of one of Examples 38 to 57, wherein the pass-through element is a first pass-through element (which may be, for example, an internal pass-through element), a second pass-through element (which may be, for example, an external pass-through element) is coupled between the input voltage terminal and the output voltage terminal, and a control terminal is coupled to the output signal terminal. In some such examples, the system further comprises a power supply coupled to the input voltage terminal and / or a load coupled to the output voltage terminal.

[0199] Example 59 is a circuit comprising: an input voltage terminal; an output voltage terminal; a feedback voltage terminal; an output signal terminal; a pass-through element coupled between the input voltage terminal and the output voltage terminal, having a control terminal, the pass-through element being a p-type pass-through element; an error amplifier designed to generate an error amplifier output voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage; a first impedance divider comprising a first variable impedance and designed to generate a first drive voltage at the control terminal of the pass-through element based on the error amplifier output voltage;and a second impedance divider, which includes a second variable impedance and is designed to generate a second drive voltage at the output signal terminal based on the error amplifier output voltage.

[0200] Example 60 includes the circuit of Example 59, wherein: the error amplifier has a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input being coupled to a reference voltage terminal and the second amplifier input being coupled to the feedback voltage terminal; the first impedance divider is coupled between the amplifier output and the input voltage terminal and includes an output coupled to the control terminal of the pass-through element, the first variable impedance being coupled between the output of the first impedance divider and the ground terminal; and the second impedance divider is coupled between the amplifier output and the ground terminal and includes an output coupled to the output signal terminal, the second variable impedance being coupled between the amplifier output and the output of the second impedance divider.

[0201] Example 61 includes the circuit of Example 59 or 60, wherein: both the first and second drive voltages are associated with a rate of change relative to changes in the error amplifier output voltage; and the rate of change of the first drive voltage decreases while the rate of change of the second drive voltage increases.

[0202] Example 62 includes the circuit of one of Examples 59 to 61, wherein: a first gain between the amplifier output and the control terminal of the pass-through element decreases relative to decreases in the error amplifier output voltage; and a second gain between the amplifier output and the output signal terminal increases relative to decreases in the error amplifier output voltage.

[0203] Example 63 includes the circuit of one of Examples 59 to 62, wherein: the circuit is designed to supply a load current to the output voltage terminal; in response to the load current being less than or equal to a first current threshold, the circuit supplies substantially all of the load current through the pass-through element; in response to the load current being greater than a second current threshold, the circuit limits the current supplied through the pass-through element, the second current threshold being greater than the first current threshold; and in response to the load current being greater than the first current threshold, the first and second impedance dividers cause a first portion of the load current to be supplied through the pass-through element and a second portion of the load current to be supplied through an external n-type pass-through element.

[0204] Example 64 includes the circuit of one of Examples 59 to 63, and further includes the external n-type pass-through element, wherein the external n-type pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal.

[0205] Example 65 includes the circuit of Example 64, wherein: both the passband element and the external passband element are p-channel field-effect transistors or PNP bipolar transistors; or one of the passband element and the external passband element is a p-channel field-effect transistor and the other of the passband element and the external passband element is a PNP bipolar transistor.

[0206] Example 66 is a system comprising: a first p-type pass-through element coupled between an input voltage terminal and an output voltage terminal and having a control terminal; a second p-type pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to a feedback voltage terminal;a first impedance divider coupled between the amplifier output and the input voltage terminal, comprising an output coupled to the control terminal of the first p-type pass-through element, the first impedance divider further comprising a first variable impedance coupled between the output of the first impedance divider and the input voltage terminal; and a second impedance divider coupled between the amplifier output and the input voltage terminal, comprising an output coupled to the control terminal of the second p-type pass-through element, the second impedance divider further comprising a second variable impedance coupled between the amplifier output and the output of the second impedance divider.

[0207] Example 67 includes the system of Example 66, and further includes a power supply coupled to the input voltage connection.

[0208] Example 68 includes the system of Example 66 or 67, and further includes a load coupled to the output voltage terminal.

[0209] Example 69 includes the system of one of Examples 66 to 38, and further includes an electronic system which may, for example, be coupled between the output voltage terminal and the ground terminal.

[0210] Example 70 includes the system of Example 69, where the electronic system is an electronic vehicle system. For example, in such an example, the electronic vehicle system is a camera system.

[0211] Example 71 includes the system of Example 69, where the electronic system is a control system. For example, in such an example, the control system is an electronic radar control unit.

[0212] Example 72 includes the system of Example 69, where the electronic system is a medical system. For example, in such an example, the medical system is an electrocardiogram system.

[0213] Example 73 includes the system of one of Examples 66 to 72, wherein the first p-type passband, the error amplifier, the first impedance divider and the second impedance divider are contained in an integrated circuit chip and the second p-type passband is located external to the integrated circuit chip.

[0214] Example 74 is a circuit comprising: an input voltage terminal; an output voltage terminal; an output signal terminal; an error amplifier with an amplifier output; a pass-through element coupled between the input voltage terminal and the output voltage terminal, having a control terminal and a threshold voltage; and a calibration circuit designed to determine the difference between the threshold voltage of the pass-through element and a threshold voltage of an external pass-through element.

[0215] Example 75 includes the circuit of Example 74, and further includes an external pass-through element having the threshold voltage of the external pass-through element and coupled between the input voltage terminal and the output voltage terminal, wherein the control terminal of the external pass-through element is coupled to the output signal terminal.

[0216] Example 76 includes the circuit of Example 74 or 75, wherein, in determining the difference between the threshold voltage of the pass-through element and the threshold voltage of the external pass-through element, the calibration circuit is designed to incrementally adjust a resistance value of a resistor circuit while a current flows through the resistor circuit until a voltage output of the resistor circuit is within a tolerance of the threshold voltage of the external pass-through element.

[0217] Example 77 includes the circuit of Example 76, wherein the calibration circuit is further designed to store a final resistance value of the resistor circuit or a representation of the final resistance value, wherein the final resistance value is the resistance value which causes the output voltage of the resistor circuit to be within the tolerance of the threshold voltage of the external pass-through element.

[0218] Example 78 includes the circuit of one of Examples 74 to 77, wherein the calibration circuit includes: an adjustable resistor circuit; and a controller designed to adjust a resistance value of the adjustable resistor circuit until the difference between the relevant threshold voltage of the pass-through element and the threshold voltage of the external pass-through element is within a tolerance, while a load is connected to the output voltage terminal.

[0219] Example 79 includes the circuit of one of Examples 74 to 78, wherein the calibration circuit further includes: a memory designed to store a representation of a final resistance value of the adjustable resistance circuit, wherein the final resistance value is the resistance value which causes the difference between the relevant threshold voltage of the pass-through element and the threshold voltage of the external pass-through element to be within a tolerance.

[0220] Example 79 includes the circuit of one of Examples 74 to 79, wherein the calibration circuit includes: a load coupled between the output voltage terminal and a ground terminal; a current source coupled between the input voltage terminal and the output voltage terminal and having a current value; a variable resistance circuit coupled between the current source and the ground terminal and having a resistance value that can be adjusted; a control circuit designed to incrementally adjust the resistance value of the variable resistance circuit while a current with the current value flows through the variable resistance circuit until a voltage provided by the variable resistance circuit is within a tolerance of the threshold voltage of the external pass-through element;and a comparator circuit designed to determine when the voltage provided by the variable resistor circuit is within the tolerance of the threshold voltage of the external pass-through element.

[0221] Example 80 includes the circuit of Example 79, wherein the variable resistor circuit includes a first voltage output and a second voltage output, the first voltage output being used to provide incrementally increasing voltage values ​​and the second voltage output being used to provide incrementally decreasing voltage values, and the calibration circuit further includes: a multiplexer with a first and second multiplexer input and a multiplexer output, wherein the first multiplexer input is coupled to the first voltage output of the variable resistor circuit, the second multiplexer input is coupled to the second voltage output of the variable resistor circuit, and the multiplexer output is coupled to an input of the comparator circuit, wherein the multiplexer is configured to pass a voltage at its first voltage input to the multiplexer output in response thereto.that the threshold voltage of the pass-through element is less than the threshold voltage of the external pass-through element, and wherein the multiplexer is designed to pass a voltage at its second voltage input to the multiplexer output in response to the fact that the threshold voltage of the pass-through element is greater than the threshold voltage of the external pass-through element.

[0222] Example 81 includes the circuit of Example 80, wherein the input of the comparator circuit is a first input of the comparator circuit, and wherein the comparator circuit has a second input coupled to the output signal terminal.

[0223] Example 82 includes the circuit of one of Examples 74 to 81, wherein the calibration circuit includes: an internal load coupled between the output voltage terminal; a current source coupled between the input voltage terminal and the output voltage terminal to provide current; a field-effect transistor (FET) coupled between the current source and the output voltage terminal, having a source terminal coupled to the output voltage terminal; a first variable resistor circuit coupled between the current source and the FET, wherein a first terminal of the first variable resistor circuit is coupled to the current source and a second terminal of the first variable resistor circuit is coupled to a gate terminal of the FET;a second variable resistor circuit coupled between the first variable resistor circuit and the FET, wherein a first terminal of the second variable resistor circuit is coupled to the second terminal of the first variable resistor circuit and a second terminal of the second variable resistor circuit is coupled to a drain terminal of the FET; a multiplexer with a first and second multiplexer input and a multiplexer output, wherein the first multiplexer input is coupled to the first terminal of the first variable resistor circuit and the second multiplexer input is coupled to the second terminal of the second variable resistor circuit;and a comparator circuit with a first and second comparator input and a comparator output, wherein the first comparator input is coupled to the comparator output, the second comparator input is coupled to the output signal terminal, and the comparator output switches from a first state to a second state in response to the difference between the threshold voltage of the pass-through element and the threshold voltage of the external pass-through element being within a tolerance.

[0224] Example 83 includes the circuit of Example 82, wherein the calibration circuit further includes a controller designed to: incrementally adjust one of the first or second variable resistor circuits while current flows through one of the first and second variable resistor circuits until an output voltage of one of the first and second variable resistor circuits is within a tolerance of the threshold voltage of the external pass-through element; and in response to the comparator output switching from the first state to the second state, store a variable corresponding to a current resistance value of one of the first and second variable resistor circuits.

[0225] Example 84 is a circuit comprising: an input voltage terminal; an output voltage terminal; a feedback voltage terminal; an output signal terminal; a pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to the feedback voltage terminal;and a load balancing circuit with an input, a first output and a second output, wherein the input of the load balancing circuit is coupled to the amplifier output, the first output of the load balancing circuit is coupled to the control terminal of the pass-through element and the second output of the load balancing circuit is coupled to the output signal terminal, wherein the load balancing circuit includes an impedance divider coupled between the amplifier output and a ground terminal or the input voltage terminal, wherein the impedance divider has an output coupled to the first output of the load balancing circuit.

[0226] Example 85 includes the circuit of Example 84, wherein: the circuit is designed to supply a load current to the output voltage terminal; in response to the load current being less than or equal to a first current threshold, the load balancing circuit is designed to supply substantially all of the load current through the pass-through element; in response to the load current being greater than a second current threshold, the load balancing circuit is designed to limit the current supplied through the pass-through element, the second current threshold being greater than the first current threshold; and in response to the load current being greater than the first current threshold, the load balancing circuit is designed to supply a first portion of the load current through the pass-through element and to control an external pass-through element to supply a second portion of the load current.

[0227] Example 86 includes the circuit of Example 85 and further includes the external pass-through element, wherein the external pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal, such that the second part of the load current is provided by the external pass-through element. In some such examples, the external pass-through element may be external to an integrated circuit or a printed circuit board that incorporates the pass-through element (which may be referred to as an internal pass-through element).

[0228] Example 87 includes the circuit of Example 86, wherein both the pass element and the external pass element are n-type transistor devices, or both the pass element and the external pass element are p-type transistor devices.

[0229] Example 88 includes the circuit of Example 86 or 87, wherein: both the passband element and the external passband element are n-channel field-effect transistors or NPN bipolar transistors; or both the passband element and the external passband element are p-channel field-effect transistors or PNP bipolar transistors; or one of the passband element and the external passband element is an n-channel field-effect transistor and the other of the passband element and the external passband element is an NPN bipolar transistor; or one of the passband element and the external passband element is a p-channel field-effect transistor and the other of the passband element and the external passband element is a PNP bipolar transistor.

[0230] Example 89 includes the circuit of one of Examples 84 to 88, wherein the amplifier output is coupled to the output signal terminal without an intermediate impedance divider.

[0231] Example 90 includes the circuit of one of Examples 84 to 89, where the amplifier output is directly coupled to the output signal connection.

[0232] Example 91 includes the circuit of one of Examples 84 to 90, and further includes a voltage source coupled between the amplifier output and the control terminal of the pass-through element, or between the amplifier output and the output signal terminal. In some such examples, the voltage source is designed to adapt a control voltage at the control terminal of the pass-through element, either up or down, or to adapt a control voltage at the output signal terminal, either up or down.

[0233] Example 92 includes the circuit of Example 91, wherein the voltage source includes: a resistor circuit with a configurable resistance; and a current source with a current value.

[0234] Example 93 includes the circuit of one of Examples 84 to 92, and further includes a calibration circuit designed to determine the difference between a threshold voltage of the forward element and a threshold voltage of an external forward element. In some such examples (such as Example 92), the calibration circuit is designed to determine a resistance setting for the resistor circuit using the current value by determining the difference between the threshold voltage of the forward element and the threshold voltage of the external forward element.

[0235] Example 94 includes the circuit of Example 93, wherein the calibration circuit comprises: a variable resistor circuit coupled between the input voltage terminal and the ground terminal, having a resistance value that can be adjusted; a control circuit designed to incrementally adjust the resistance value of the variable resistor circuit while a current of the specified value flows through the variable resistor circuit until a voltage provided by the variable resistor circuit is within a tolerance of the threshold voltage of the external forward element; and a comparator circuit designed to indicate when the voltage provided by the variable resistor circuit is within the tolerance of the threshold voltage of the external forward element.

[0236] Example 95 includes the circuit of one of Examples 84 to 94, wherein the error amplifier is designed to generate a drive voltage based on a feedback voltage at the feedback voltage terminal and a reference voltage at the reference voltage terminal.

[0237] Example 96 is a system that includes the circuit of one of Examples 84 to 95, and further includes: a power supply coupled to the input voltage terminal; and / or a load coupled to the output voltage terminal.

[0238] Example 97 includes a system comprising the circuit of one of Examples 84 to 95 or the system of Example 96, and further includes an electronic system which may, for example, be coupled between the output voltage terminal and the ground terminal.

[0239] Example 98 includes the system of Example 97, where the electronic system is an electronic vehicle system. For example, in such an example, the electronic vehicle system is a camera system.

[0240] Example 99 includes the system of Example 97, where the electronic system is a control system. For example, in such an example, the control system is an electronic radar control unit.

[0241] Example 100 includes the system of Example 97, where the electronic system is a medical system. For example, in such an example, the medical system is an electrocardiogram system.

[0242] Example 101 is a method for calibrating a voltage regulator system, comprising: disabling a first pass-through element coupled between an input voltage terminal of the voltage regulator system and an output voltage terminal of the voltage regulator system; generating a load current at the output voltage terminal, the load current passing through a second pass-through element coupled between the input voltage terminal and the output voltage terminal; determining a voltage difference between a threshold voltage of the first pass-through element and a threshold voltage of the second pass-through element; and applying the voltage difference to a control terminal of the first pass-through element or a control terminal of the second pass-through element.

[0243] Example 102 incorporates the procedure of Example 101, wherein the difference between the threshold voltage of the first forward element and the threshold voltage of the second forward element is determined by: incrementally adjusting a resistance value of a resistor circuit while a current flows through the resistor circuit until a voltage output of the resistor circuit is within a tolerance of the threshold voltage of the second forward element.

[0244] Example 103 includes the procedure of Example 102, and further includes: storing the resistance value of the resistor circuit corresponding to the voltage output of the resistor circuit being within the tolerance of the threshold voltage of the second pass-through element, or a representation of that resistance value.

[0245] Example 104 includes the procedure of one of Examples 101 to 103, wherein determining the voltage difference between the threshold voltage of the first pass-through element and the threshold voltage of the second pass-through element involves: adjusting a resistance value of a variable resistor circuit until the difference between the threshold voltage of the first pass-through element and the threshold voltage of the second pass-through element is within a tolerance while the load current flows through the second pass-through element; and storing a representation of a final resistance value, wherein the final resistance value is the resistance value that causes the difference between the threshold voltage of the first pass-through element and the threshold voltage of the second pass-through element to be within the tolerance.

[0246] Example 105 is a method for supplying a load current to an electronic system, the method comprising: in response to the load current being less than or equal to a first current threshold, supplying the entire load current through a first pass-through element; in response to the load current being greater than the first current threshold, supplying a first part of the load current through the first pass-through element and a remaining part of the load current through a second pass-through element; and in response to the load current being greater than a second current threshold, limiting the first part of the load current supplied through the first pass-through element to a maximum current level associated with the first pass-through element, the second current threshold being greater than the first current threshold.

[0247] Example 106 includes the method of Example 105, wherein the first passband element is contained within an integrated circuit chip and the second passband element is located external to the integrated circuit chip. In some cases, the integrated circuit chip includes a low-dropout (LDO) voltage regulator.

[0248] Example 107 includes the method of Example 105 or 106, wherein both the first and second pass-through element have a control terminal, and wherein: in response to the load current being less than or equal to the first current threshold, the method includes applying a first voltage to the control terminal of the first pass-through element so that the first pass-through element provides all the load current, and applying a second voltage to the control terminal of the second pass-through element so that the second pass-through element does not provide any load current.

[0249] Example 108 includes the method of one of Examples 105 to 107, wherein both the first and the second pass-through element have a control terminal, and wherein: in response to the fact that the load current is greater than the first current threshold, the method includes applying a first voltage to the control terminal of the first pass-through element so that the first pass-through element provides a first part of the load current, and applying a second voltage to the control terminal of the second pass-through element so that the second pass-through element provides a second or remaining part of the load current.

[0250] Example 109 includes the method of one of Examples 105 to 108, wherein both the first passing element and the second passing element are n-type transistor devices.

[0251] Example 110 includes the method of one of Examples 105 to 108, wherein both the first passing element and the second passing element are p-type transistor devices.

[0252] Example 111 is a low-dropout (LDO) voltage regulator that: incorporates the circuitry of one of Examples 1 through 21, 23 through 29, 38 through 57, 59 through 65, and 74 through 95; or is contained within the system of one of Examples 22, 30 through 37, 58, 66 through 73, and 96 through 100; or is designed to perform the procedure of one of Examples 101 through 110. Other examples may use other voltage regulators.

[0253] In this description, the term "couple" can cover connections, communications, or signal paths that enable a functional relationship corresponding to this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0254] A device that is "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at a point in time to perform that function, and / or can be configured (or reconfigured) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the design and / or layout of hardware components and interconnections of the device, or a combination thereof.

[0255] As used here, the terms "terminal," "node," "connection," "pin," and "line" are used interchangeably. Unless otherwise specified, the use of these terms generally means a connection between, or termination of, a device element, circuit element, integrated circuit, appliance, or semiconductor component. Furthermore, a voltage rail, or more simply a "rail," may also be called a voltage terminal and can generally mean a common node or a set of coupled nodes in a circuit with the same potential.

[0256] A circuit or device that, according to the present description, includes certain components, may instead be configured to be coupled with these components to form the described circuit arrangement or device. For example, a structure that, according to the description, includes one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources), may instead comprise only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled, either during or after manufacturing, for example, by an end user and / or a third party, with at least some of the passive elements and / or the sources to form the described structure.

[0257] Although the use of specific transistors is described here, other transistors (or equivalent devices) may be used instead. For example, a p-channel field-effect transistor (PFET) may be used instead of an n-channel field-effect transistor (NFET) with little or no modification to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)). The devices may also be implemented in / on a silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) substrate. Additionally, references to transistor features such as gate, source, or drain are not intended to exclude suitable transistor technologies. For example, features such as source, drain, and gate are typically used to refer to a FET, while emitter, collector, and base are typically used to refer to a BJT.Such features can be used interchangeably here. For example, a reference to the gate of a transistor can refer to either the gate of a FET or the base of a BJT, and vice versa. In some examples, a control terminal can refer to either the gate of a FET or the base of a BJT. Any other suitable transistor technologies can be used. Each of these transistors can be used as a switch, with the gate or base, or some other comparable feature, acting as a switch selection input that can be driven to connect the source and drain (or, if appropriate, the emitter and collector).

[0258] References herein to a field-effect transistor (FET) being "on" (or a switch being closed) mean that the FET's conduction channel is present and drain current can flow through the FET. References herein to a FET being "off" (or a switch being open) mean that the conduction channel is not present and no drain current flows through the FET. However, current can still flow through the transistor's body diode when the FET is off.

[0259] The circuits described here are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component exchange. Unless otherwise specified, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an impedance value represented by the resistor shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.These are capacitors that are connected in series between the same two nodes as the single resistor or capacitor.

[0260] Uses of the term "mass" in the foregoing description include chassis mass, earth mass, floating mass, virtual mass, digital mass, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. Unless otherwise specified, in this description, "about," "approximately," or "essentially" preceding a parameter means a range within + / - 10% of that parameter.

[0261] Within the scope of protection of the claims, modifications of the described examples as well as other examples are possible.< / j> < / j>

Claims

[1] Circuit, comprising: an input voltage connection; an output voltage connection; a feedback voltage connection; an output signal connection; a pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal, wherein the pass-through element is an n-type pass-through element; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage terminal and the second amplifier input is coupled to the feedback voltage terminal; and a load balancing circuit with one input, one first output and one second output, wherein the input of the load balancing circuit is coupled to the amplifier output, the first output of the load balancing circuit is coupled to the control terminal of the pass-through element, and the second output of the load balancing circuit is coupled to the output signal terminal. [2] Circuit according to claim 1, wherein: The load balancing circuit is designed to provide a first and second control voltage at the first and second outputs of the load balancing circuit, respectively, based on a control voltage generated by the error amplifier. to produce; both the first and second drive voltages with a rate of change relative to changes in the drive voltage generated by the error amplifier, is associated; and The rate of change of the first control voltage decreases, while the rate of change of the second control voltage increases. [3] Circuit according to claim 1, wherein: the load balancing circuit is designed to generate a first and second control voltage at the first and second outputs of the load balancing circuit based on a control voltage generated by the error amplifier; a first gain between the amplifier output and the first output of the load balancing circuit decreases relative to increases in the drive voltage generated by the error amplifier; and A second gain between the amplifier output and the second output of the load balancing circuit increases relative to increases in the drive voltage generated by the error amplifier. [4] Circuit according to claim 1, wherein: the load balancing circuit is designed to generate a first and second control voltage at the first and second outputs of the load balancing circuit based on a control voltage generated by the error amplifier; In response to the first drive voltage at the first output of the load balancing circuit exceeding a first threshold voltage, the load balancing circuit is designed to reduce the rate of change of the first drive voltage relative to changes in the drive voltage generated by the error amplifier; and In response to the first drive voltage at the first output of the load balancing circuit exceeding a second threshold voltage, the load balancing circuit is designed to increase a rate of change of the second drive voltage relative to changes in the drive voltage generated by the error amplifier. [5] Circuit according to claim 1, wherein: the circuit is designed to provide a load current to the output voltage terminal; as a reaction to the load current being less than or equal to a first current threshold, The load balancing circuit is designed to supply essentially the entire load current through the pass-through element; and In response to the fact that the load current is greater than a second current threshold, the load balancing circuit is designed to limit the current supplied through the pass-through element, where the second current threshold is greater than the first current threshold. [6] Circuit according to claim 5, wherein: in response to the fact that the load current is greater than the first current threshold, the load balancing circuit is designed to provide a first part of the load current via the pass-through element and to control an external pass-through element to provide a second part of the load current. [7] Circuit according to claim 6, further comprising the external pass-through element, wherein the external pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal connected to the output signal terminal, such that the second part of the load current is provided through the external pass-through element, and wherein the external pass-through element is an n-type pass-through element. [8] Circuit according to claim 7, wherein: both the passband element and the external passband element are n-channel field-effect transistors or NPN bipolar transistors; or one of the passband element and the external passband element is an n-channel field-effect transistor and the other of the passband element and the external passband element is an NPN bipolar transistor. [9] Circuit according to claim 1, wherein the load balancing circuit comprises: a first impedance divider coupled between the amplifier output and a ground connection, wherein the first impedance divider includes an output coupled to the first output of the load balancing circuit; and a second impedance divider coupled between the amplifier output and the ground connection, wherein the second impedance divider includes an output coupled to the output signal connection. [10] Circuit according to claim 9, wherein: the first impedance divider includes a first variable impedance that is coupled between the output of the first impedance divider and the ground connection; and The second impedance divider includes a second variable impedance that is coupled between the amplifier output and the output of the second impedance divider. [11] Circuit according to claim 10, wherein the first variable impedance includes a first field-effect transistor (FET) and the second variable impedance includes a second FET, and wherein the load balancing circuit comprises: a resistor coupled between the amplifier output and a source terminal of the first FET, wherein the resistor and the first FET provide the first impedance divider; and a pull-down circuit coupled between the output signal terminal and the ground terminal, with the pull-down circuit and the second FET providing the second impedance divider. [12] Circuit according to claim 11, wherein the resistor is a first resistor and comprises the load balancing circuit: a third FET coupled between the output voltage terminal and one of the input voltage terminals or a charge pump terminal, wherein the third FET has a gate terminal coupled to a drain terminal, and has a source terminal coupled to the output voltage terminal; a fourth FET with a gate terminal coupled to a drain terminal and the gate terminal of the first FET, and a source terminal coupled to the gate and drain terminals of the third FET; a first current source coupled between the drain terminal of the fourth FET and the ground terminal; a fifth FET coupled between the ground terminal and one of the input voltage terminal or the charge pump terminal, wherein the fifth FET has a gate terminal coupled to a drain terminal via a second resistor and a source terminal coupled to one of the input voltage terminal or the charge pump terminal, wherein the drain terminal of the fifth FET is coupled to the gate terminal of the second FET; and a second current source coupled between the gate terminal of the fifth FET and the ground terminal. [13] Circuit according to claim 12, comprising: a buffer circuit with a buffer input and a buffer output, wherein the buffer input is coupled to a second output stage of the error amplifier; a sixth FET with a gate terminal coupled to the control terminal of the pass element and a source terminal coupled to the output voltage terminal; a seventh FET coupled between the buffer output and the sixth FET, and has a gate terminal coupled to a drain terminal and the drain terminal of the sixth FET, and a source terminal coupled to the buffer output; an eighth FET with a gate terminal coupled to the gate and drain terminals of the seventh FET, and a source terminal coupled to the second output stage of the error amplifier; and a capacitor coupled between a drain terminal of the eighth FET and a first output stage of the error amplifier. [14] Circuit according to claim 10, wherein the load balancing circuit comprises: a first comparator circuit designed to control the first variable impedance; and a second comparator circuit designed to control the second variable impedance. [15] Circuit according to claim 1, wherein the load balancing circuit includes an impedance divider coupled between the amplifier output and a ground connection, wherein the impedance divider has an output coupled to the first output of the load balancing circuit, and wherein the amplifier output is coupled to the output signal connection without an intermediate impedance divider. [16] Circuit, comprising: an input voltage connection; an output voltage connection; a feedback voltage connection; an output signal connection; a pass-through element coupled between the input voltage terminal and the output voltage terminal and having a control terminal, wherein the pass-through element is an n-type pass-through element; an error amplifier designed to provide an error amplifier output voltage based on a feedback voltage at the feedback voltage terminal and to generate a reference voltage; a first impedance divider, which includes a first variable impedance and is designed to generate a first drive voltage at the control terminal of the pass-through element based on the error amplifier output voltage; and a second impedance divider which includes a second variable impedance and is designed to generate a second drive voltage at the output signal terminal based on the error amplifier output voltage. [17] Circuit according to claim 16, wherein: the circuit is designed to provide a load current to the output voltage terminal; as a reaction to the load current being less than or equal to a first current threshold, the circuit essentially provides the entire load current via the pass-through element; In response to the load current being greater than a second current threshold, the circuit limits the current supplied through the pass-through element, where the second current threshold is greater than the first current threshold; and in response to the fact that the load current is greater than the first current threshold, the first and Second impedance dividers cause a first part of the load current to be supplied via the internal pass-through element and a second part of the load current to be supplied via an external n-type pass-through element. [18] Circuit according to claim 17, further comprising the external n-type pass-through element, wherein the external n-type pass-through element is coupled between the input voltage terminal and the output voltage terminal and has a control terminal which is connected to the output signal terminal. [19] System, encompassing: a first n-type pass-through element that connects an input voltage terminal and is coupled to an output voltage connection and has a control connection; a second n-type pass-through element, located between the input voltage terminal and is coupled to the output voltage connection and has a control connection; an error amplifier with a first amplifier input, a second amplifier input and an amplifier output, wherein the first amplifier input is coupled to a reference voltage connection and the second amplifier input is coupled to a feedback voltage connection; a first impedance divider coupled between the amplifier output and a ground terminal, and an output coupled to the control terminal of the first n-type pass-through element, wherein the first impedance divider further includes a first variable impedance coupled between the output of the first impedance divider and the ground terminal; and a second impedance divider coupled between the amplifier output and the ground terminal, and an output coupled to the control terminal of the second n-type pass-through element, wherein the second impedance divider further includes a second variable impedance coupled between the amplifier output and the output of the second impedance divider. [20] System according to claim 19, wherein the first n-type pass-through element, the error amplifier, the first impedance divider and the second impedance divider are contained in an integrated circuit chip and the second n-type pass-through element is located external to the integrated circuit chip.

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