DISPLAY DEVICE

Abstract

The present application provides a display device. The display device comprises a substrate (102) having a pixel area (P); a thin-film transistor on the substrate (102) and in the pixel area (P); a planarization layer (150, 250, 350, 450) covering the thin-film transistor; and a light-emitting diode (D) on the planarization layer (150, 250, 350, 450) and in the pixel area (P). and a pixel definition layer (156, 256, 356, 456) at an edge of the pixel area (P), wherein the pixel definition layer (156, 256, 356, 456) has a light absorption property and the planarization layer (150, 250, 350, 450) has a scattering particle (152, 154; 252, 254; 352, 354; 452a, 452b, 454a, 454b).

Description

TECHNICAL AREA The present disclosure relates in general to a display device, and for example, in particular, without limitation, to a display device capable of preventing a deterioration of the display quality and a leakage current of a thin-film transistor and a particle on an anode. DESCRIPTION OF RELATED TECHNOLOGY Display devices, such as a television (TV), a monitor, a smartphone, a tablet PC or a laptop, show images in a variety of formats and shapes. The display device comprises a display field with a plurality of light-emitting elements or a liquid crystal for displaying images, and transistors for controlling the operation of the light-emitting element or the liquid crystal. The display device shows the desired image through the light-emitting element or the liquid crystal. Light emission display technology, which incorporates a light-emitting diode, is developing rapidly. Light emission display devices can be categorized into organic light emission display devices, which use an organic emitting material, and inorganic light emission display devices, which use an inorganic emitting material. To reduce or minimize external light reflection (e.g., ambient light reflection), the light emission display device incorporates a polarizing plate on the display surface. Recently, various research and development efforts have been undertaken to improve the reliability and quality of display devices. The description provided in the discussion of the related technology section should not be considered prior art simply because it is mentioned or associated with that section. The discussion of the related technology section may contain information describing one or more aspects of the technology under consideration, and the description in that section does not limit the disclosure. BRIEF EXPLANATION OF THE INVENTION The present disclosure relates to a display device which substantially avoids one or more of the problems associated with the limitations and disadvantages of the related conventional technique. One objective of the present disclosure is to provide a display device capable of improving the reliability of a pixel definition layer. One objective of the present disclosure is to provide a display device capable of improving or maintaining an external light reflection property with a reduced amount of black particles in a pixel definition layer. One objective of the present disclosure is to provide a display device capable of preventing leakage current from a thin-film transistor with a reduced amount of black particles in a pixel definition layer. Additional features and advantages of this disclosure are set forth in the following description and will become apparent from the description or through the practical implementation of this disclosure. The objectives and other advantages of this disclosure are realized and achieved through the features described herein and in the accompanying drawings. To achieve these and other advantages according to the purpose of the embodiments of the present disclosure as described herein, one aspect of the present disclosure is a display device comprising a substrate including a pixel region; a thin-film transistor on the substrate and in the pixel region; a planarization layer covering the thin-film transistor; a light-emitting diode on the planarization layer and in the pixel region; and a pixel definition layer at an edge of the pixel region, wherein the pixel definition layer has a light-absorbing property and the planarization layer includes a scattering particle. Preferred embodiments of the display device are described in the dependent claims. It is understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to further explain the present disclosure as claimed. Other systems, methods, features, and advantages will be apparent to the person skilled in the art upon review of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages are included in this description, being within the scope of protection of the present disclosure and protected by the following claims. Nothing in this section should be considered a limitation of these claims. Further aspects and advantages are discussed below in connection with embodiments of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the present disclosure and which are incorporated into and form part of this description, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Fig. 1 is a schematic view showing an organic light emission indicator device of the present disclosure. Fig. 2 is a schematic circuit diagram of an organic light emission indicator device of the present disclosure. Fig. 3 is a schematic cross-sectional view showing an organic light emission indicator device according to a first embodiment of the present disclosure. Fig. 4 is a schematic cross-sectional view showing the extinction of light within a planarization layer.Figure 5 is a schematic cross-sectional view showing an organic light emission indicator device according to a second embodiment of the present disclosure. Figure 6 is a schematic cross-sectional view showing an organic light emission indicator device according to a third embodiment of the present disclosure. Figure 7 is a schematic organic light emission view showing a light emission indicator device according to a fourth embodiment of the present disclosure. Figure 8 is a schematic perspective exploded view of an indicator module according to an embodiment of the present disclosure. Figure 9 is a schematic cross-sectional view of an indicator module according to an embodiment of the present disclosure. Figure 10 is a schematic top view of an indicator module according to an embodiment of the present disclosure. Unless otherwise specified, the same reference symbols used in the drawings and the detailed description are to be understood as referring to the same elements, features, and structures. The relative size and representation of these elements may be exaggerated for the sake of clarity, illustration, and practicality. DETAILED DESCRIPTION Extensive reference will now be made to aspects of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, where a detailed description of well-known functions or configurations relating to this document is found to unnecessarily obscure a core of the inventive concept, the detailed description thereof will be omitted. The sequence of processing steps and / or operations described is an example; however, the sequence of steps and / or operations is not limited to that set forth herein and may be modified as is known in the art, except that steps and / or operations must necessarily occur in a specific order. Identical reference numerals throughout denote identical elements.The names of the respective elements used in the following explanations are chosen solely for the convenience of writing the description and may therefore differ from those used in actual products. The advantages and features of the present disclosure and the methods for achieving them will become apparent with reference to the aspects described in detail below with the accompanying drawings. However, the present disclosure is not limited to the aspects disclosed below, but can be realized in a variety of different ways, and only these aspects make the present disclosure complete. The present disclosure is provided to fully inform the person skilled in the art in the field of the present disclosure about the scope of the disclosure. The shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings to explain aspects of the present disclosure are illustrative, and the present disclosure is not limited to the objects depicted. The same reference signs refer to the same elements throughout the description. Additionally, in describing the present disclosure, if it is found that a detailed description of related known technology would unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof may be omitted. When "showing," "having," "including," and the like are used in this description, other parts may be added unless "only" is used. When a component is expressed in the singular, cases including the plural are included unless a specific statement is being described. The phrase “at least one of a, b and c”, which appears throughout the description, may include “a alone”, “b alone”, “c alone”, “a and b”, “a and c”, “b and c”, or “all of a, b and c”. The advantages and features of the present application and the methods for achieving them will become apparent by reference to the embodiments described in detail below with the accompanying drawings. When designing an element, the element is designed to include an error or tolerance range, even though there is no explicit description of such an error or tolerance range. When describing a positional relationship, for example, when a positional relationship between two parts is described as 'on', 'above', 'below' and 'next', one or more other parts may be positioned between the two parts unless a restrictive term such as 'only' or 'directly' is used. When describing a temporal relationship, for example, when the temporal sequence is described as "after", "subsequent", "next" and "before", a case that is not continuous may be included unless a restrictive term such as "only", "immediately" or "directly" is used. The area, length or thickness of each component described in the description is shown for convenience of explanation, and the present application is not necessarily limited to the area and thickness of the component shown. It is understood that, although the terms "first...", "second...", etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without departing from the scope of the present revelation. Features of various aspects of the present disclosure may be partially or completely coupled or combined and may interact and be operated in various ways, as a person skilled in the art can reasonably understand. The aspects of the present disclosure may be implemented independently of one another or together in a mutually dependent relationship. Throughout the drawings and detailed description, unless otherwise specified, the same reference numerals used in the drawings are to be understood as referring to the same elements, features, and structures. The relative size and representation of these elements may be exaggerated for the sake of clarity, illustration, and practicality. The sequence of processing steps and / or operations described is an example; however, the sequence of steps and / or operations is not limited to that shown herein and may be modified as is known in the art, except that steps and / or operations must necessarily occur in a specific order. The same reference numerals consistently denote the same elements.The names of the respective elements used in the following explanations are chosen solely for the convenience of writing the description and may therefore differ from those used in actual products. Any implementation described herein as an “example” is not necessarily to be interpreted as preferable or advantageous over other implementations. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they would normally be understood by a person skilled in the art in the field to which the examples of implementation belong. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant technology, and not in an idealized or overly formal sense, unless expressly defined as such herein.For example, the term "part" or "unit" may be applied to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform a described function as it should be understood by an average person skilled in the field. Without a specific description, a transistor forming the pixel circuit of the present disclosure may include at least one of an oxide thin-film transistor (oxide TFT), an amorphous silicon TFT (a-Si TFT) and a low-temperature polysilicon (LTPS) TFT. The following embodiments are described with reference to organic light emission indicator devices. However, the embodiment of the present disclosure is not limited to organic light emission indicator devices. For example, an indicator device according to one embodiment of the present disclosure may be an organic light emission indicator device using an organic light-emitting material, an inorganic light emission indicator device using an inorganic light-emitting material such as a quantum dot, or a micro-LED indicator device. In particular, the light-emitting diode indicator device of the present disclosure may be an organic light emission indicator device, an inorganic light emission indicator device, or a micro-LED indicator device. Now, detailed reference will be made to some of the examples and preferred embodiments shown in the accompanying drawings. Fig. 1 is a schematic view showing an organic light emission indicator device of the present disclosure. As shown in Fig. 1, an organic light emission display device according to an embodiment of the present disclosure comprises a timing control unit 120 (e.g. a circuit), a data driver unit 122 (e.g. a circuit), a first and second gate driver unit 124 and 126 (e.g. circuits) and a display panel 128. The timing unit 120 generates an image data RGB signal, a data control signal, and a gate control signal using an image signal and a variety of timing signals, including a data release signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, transmitted from an external system such as a graphics card or a television system. The timing unit 120 transmits the image data and the data control signal to the data driver unit 122 and transmits the gate control signal to the first and second gate driver units 124 and 126. The data driver unit 122 generates a data signal (a data voltage) Vda (from Fig. 2) using the image data and the data control signal transmitted by the timing control unit 120, and transmits the data signal Vda to a data line DL of the display panel 128. The first and second gate driver units 124 and 126 generate a gate signal (a gate voltage) Vsc and Vse (from Fig. 2) using the gate control signal transmitted by the timing control unit 120, and apply the gate signal Vsc and Vse to a gate line GL of the display panel 128. The first and second gate driver units 124 and 126 can be of a gate-in-panel (GIP) type, which is to be formed in a non-display area NDA of a substrate of the display panel 128 with the gate line GL, the data line DL and a pixel area P. Although the first and second gate driver units 124 and 126 are arranged in both side sections of the display panel 128 in the embodiment of Fig. 1, a gate driver unit may be arranged in one side section of the display panel 128 in another embodiment. The display panel 128 has a display area DA in a central section and a non-display area NDA surrounding the display area DA. The display panel 128 displays an image using the gate signals Vsc and Vse and the data signal Vda. To display an image, the display panel 128 has a plurality of pixel areas P, a plurality of gate lines GL, and a plurality of data lines DL in the display area DA. The gate line GL and the data line DL cross each other to define the first, second, third, and fourth pixel areas P1, P2, P3, and P4. For example, the first, second, third, and fourth pixel areas P1, P2, P3, P4, and SP4 can correspond to red, green, blue, and white colors, respectively. Each of the first, second, third and fourth pixel areas P1, P2, P3 and P4 can have a variety of transistors, such as a switching transistor Tsw (from Fig. 2 ), a driver transistor Tdr (from Fig. 2 ) and a sensing transistor Tse (from Fig. 2 ), a storage capacitor Cst (from Fig. 2 ) and a light-emitting diode D (from Fig. 2 ). Fig. 2 is a schematic circuit diagram of an organic light emission indicator device of the present disclosure. Referring to Fig. 2 with Fig. 1, each of the first, second, third and fourth pixel areas P1, P2, P3 and P4 of the light emission indicator device according to an embodiment of the present disclosure comprises a switching transistor Tsw, a driver transistor Tdr, a detection transistor Tse, a storage capacitor Cst and a light-emitting diode D. Although each of the first, second, third and fourth pixel areas P1, P2, P3 and P4 has a 3T1C structure with three transistors and a storage capacitor in the embodiment of Fig. 2, each of the first, second, third and fourth pixel areas P1, P2, P3 and P4 can have a 6T1C structure with six transistors and a storage capacitor, a 7T1C structure with seven transistors and a storage capacitor and an 8T1C structure with eight transistors and a storage capacitor in another embodiment. Although the switching transistor Tsw, the driver transistor Tdr and the sensing transistor Tse may have a negative type in the embodiment of Fig. 2, at least one of the switching transistor Tsw, the driver transistor Tdr and the sensing transistor Tse may have a positive type in another embodiment. The switching transistor Tsw is switched according to a sampling signal Vsc in order to transmit a data signal Vda to a first node N1. A gate electrode of the switching transistor Tsw is connected to the gate line GL to receive the sampling signal Vsc, a drain electrode of the switching transistor Tsw is connected to the data line DL to receive the data signal Vda, and a source electrode of the switching transistor Tsw is connected to the first node N1. The driver transistor Tdr is switched according to a voltage from the first node N1 to transmit a high-level signal (high-level voltage) Vdd to a second node N2. A gate electrode of the driver transistor Tdr is connected to the first node N1, a drain electrode of the driver transistor Tdr is connected to a high-level power line to receive the high-level signal Vdd, and a source electrode of the driver transistor Tdr is connected to the second node N2. The sensing transistor Tse is switched according to a sensing signal (sensing voltage) Vse in order to transmit a reference signal (reference voltage) Vre to the second node N2 or to transmit a voltage from the second node N3 to a reference line. A gate electrode of the sensing transistor Tse is connected to the gate line GL to receive the sensing signal Vse, a drain electrode of the sensing transistor Tse is connected to the reference line to receive the reference signal Vre or to transmit a voltage from the second node N2 to the reference line, and a source electrode of the sensing transistor Tse is connected to the second node N2. The storage capacitor Cst holds the data signal Vda, which is provided to the first node N1, for one frame and stores a threshold voltage Vth of the driver transistor Tdr. A first capacitor electrode of the storage capacitor Cst is connected to the first node N1, and a second capacitor electrode of the storage capacitor Cst is connected to the second node N2. The light-emitting diode D emits light with a luminance proportional to a current of the driver transistor Tdr. An anode of the light-emitting diode D is connected to the second node N2, and a cathode of the light-emitting diode D is connected to a low-level power line to receive a low-level signal (low-level voltage) Vss. The source electrode of the switching transistor Tsw, the gate electrode of the driver transistor Tdr and the first capacitor electrode of the storage capacitor Cst form the first node N1, and the source electrode of the driver transistor Tdr, the source electrode of the sensing transistor Tse, the second capacitor electrode of the storage capacitor Cst and the anode of the light-emitting diode D form the second node N2. The light-emitting diode D can display an image with a luminance corresponding to the image data RGB according to a control of pixel circuits of the first, second, third and fourth pixel area P1, P2, P3 and P4. Fig. 3 is a schematic cross-sectional view showing an organic light emission indicator device according to a first embodiment of the present disclosure. As shown in Fig. 3, the organic light emission display device 100 has a substrate 102, a thin-film transistor (TFT) on the substrate 102, a planarization layer 150 covering the TFT, an organic light-emitting diode (OLED) D on the planarization layer 150, and a pixel definition layer (e.g., a wall) 156 on the planarization layer 150 and at an edge of a pixel area P. A multitude of pixel areas P are defined on substrate 102. Substrate 102 can be a glass substrate or a plastic substrate. For example, substrate 102 can be a polyimide (PL) substrate, a polyethersulfone (PES) substrate, a polyethylene phthalate (PEN) substrate, a polyethylene terephthalate (PET) substrate, or a polycarbonate (PC) substrate. In one embodiment of the present disclosure, the substrate 102 can have a three-layer structure comprising a first polyimide (Pl) layer, a second Pl layer and an inorganic intermediate layer between the first and second Pl layers. A first light-shielding structure 104 is arranged on the substrate 102. The light passing through the substrate 102 can be blocked by the first light-shielding structure 104. For example, the first light-shielding structure 104 can be made of a metallic material, e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, and can have a single-layer or multi-layer structure. A first buffer layer 106, covering the first light-shielding structure 104, is arranged over the substrate 102. Moisture and / or oxygen can be blocked by the first buffer layer 106. For example, the first buffer layer 106 can be formed from an inorganic insulating material, such as silicon dioxide or silicon nitride, and can have a single-layer or multi-layer structure. If the first light-shielding structure 104 is omitted, the first buffer layer 106 can be formed directly on the substrate 102 and contact it. A first semiconductor layer 110, corresponding to the first light-shielding structure 104, is arranged on the first buffer layer 106. The first semiconductor layer 110 can be made of a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. If the first light-shielding structure 104 and the first buffer layer 106 are omitted, the first semiconductor layer 110 can be arranged directly on the substrate 102. In an exemplary embodiment of the present disclosure, the first semiconductor layer 110 can be formed from a polysemiconductor material, e.g., polycrystalline silicon. The first semiconductor layer 110 can have a first channel region 110a, a first source region 110b on one side of the first channel region 110a, and a first drain region 110c on the other side of the first channel region 110a. Impurities can be doped into the first source and drain regions 110b and 110c. A first gate insulating layer 112, covering the first semiconductor layer 110, is arranged above the first buffer layer 106. The first gate insulating layer 112 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A first gate electrode 114, corresponding to the first channel region 110a of the first semiconductor layer 110, is arranged on the first gate insulating layer 112. Additionally, a first capacitor electrode 116, located at a distance from the first gate electrode 114, is arranged on the first gate insulating layer 112. The first gate electrode 114 and the first capacitor electrode 116 can be arranged on the same or substantially the same layer and can be made of the same or substantially the same material. For example, both the first gate electrode 114 and the first capacitor electrode 116 can be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, and can have a single-layer or multi-layer structure. A first intermediate insulating layer 118, covering the first gate electrode 114 and the first capacitor electrode 116, is arranged on the first gate insulating layer 112. The first intermediate insulating layer 118 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A second capacitor electrode 130, corresponding to the first capacitor electrode 116, and a second light shielding structure 132, which is spaced apart from the second capacitor electrode 130, are arranged on the first intermediate insulating layer 118. The second capacitor electrode 130 and the second light-shielding structure 132 can be arranged on the same or substantially the same layer and can be formed from the same or substantially the same material. For example, both the second capacitor electrode 130 and the second light-shielding structure 132 can be formed from a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, and can have a single-layer or a multi-layer structure. A second intermediate insulating layer 134, covering the first second capacitor electrode 130 and the second light-shielding structure 132, is arranged on top of the first intermediate insulating layer 118. Moisture and / or oxygen from the outside can be blocked by the second intermediate insulating layer 134. For example, the second intermediate insulating layer 134 can be made of an inorganic insulating material, e.g., silicon oxide or silicon nitride, or an organic insulating material, e.g., photoacrylic or benzocyclobutene (BCB), and can have a single-layer or a multi-layer structure. A second semiconductor layer 136, corresponding to the second light-shielding structure 132, is arranged on the second intermediate insulating layer 134. The second semiconductor layer 136 can comprise a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. In an exemplary embodiment of the present disclosure, the second semiconductor layer 136 can be formed from an oxide semiconductor material, e.g. indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO) or indium aluminum zinc oxide (IAZO). The second semiconductor layer 136 can have a second channel region 136a, a second source region 136b on one side of the second channel region 136a, and a second drain region 136c on the other side of the second channel region 136a. Impurities can be doped into the second source and drain regions 136b and 136c. A second gate insulating layer 138, covering the second semiconductor layer 136, is arranged above the second interlayer insulating layer 134. The second gate insulating layer 138 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A second gate electrode 140, corresponding to the second channel region 136a of the second semiconductor layer 136, is arranged on the second gate insulating layer 138. For example, the second gate electrode 140 can be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, and can have a single-layer or multi-layer structure. A third intermediate insulating layer 142, covering the second gate electrode 140, is arranged on the second gate insulating layer 138. The third intermediate insulating layer 142 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A first source electrode 144a, a first drain electrode 144b, a second source electrode 146a and a second drain electrode 146b are arranged on the third intermediate insulating layer 142. The first source electrode 144a and the first drain electrode 144b are each connected to the first source region 110b and the first drain region 110c via contact holes through the third interlayer insulating layer 142, the second gate insulating layer 138, the second interlayer insulating layer 134, the first interlayer insulating layer 118, and the first gate insulating layer 112. The first source electrode 144a is connected to the first capacitor electrode 116 via a contact hole through the third interlayer insulating layer 142, the second gate insulating layer 138, the second interlayer insulating layer 134, and the first interlayer insulating layer 118. The second source electrode 146a and the second drain electrode 146b are each connected to the second source region 136b and the second drain region 136c via contact holes through the third interlayer insulating layer 142 and the second gate insulating layer 138. The second source electrode 146a is connected to the second capacitor electrode 130 via a contact hole through the third interlayer insulating layer 142, the second gate insulating layer 138, and the second interlayer insulating layer 134. The first source and drain electrode 144a and 144b and the second source and drain electrode 146a and 146b can be arranged on the same or substantially the same layer and be formed from the same or substantially the same material. For example, both the first source and drain electrode 144a and 144b and the second source and drain electrode 146a and 146b can be formed from a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, and can have a single-layer or a multi-layer structure. The first semiconductor layer 110, the first gate electrode 114, the first source electrode 144a, and the first drain electrode 144b form a first TFT T1, and the second semiconductor layer 136, the second gate electrode 140, the second source electrode 146a, and the second drain electrode 146b form a second TFT T2. For example, the first TFT T1 can be a switching TFT, and the second TFT T2 can be a driver TFT. Additionally, the first and second capacitor electrodes 116 and 130 form a storage capacitor. The organic light emission display device of the present disclosure comprises the first and second TFTs T1 and T2. Both the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 can comprise a polysemiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 can comprise the oxide semiconductor material. In an exemplary embodiment of the present disclosure, the first semiconductor layer 110 of the first TFT T1 can be formed from the polysemiconductor material, e.g., polycrystalline silicon, and the second semiconductor layer 136 of the second TFT T2 can be formed from the oxide semiconductor material. In Fig. 3, the first gate electrode 114, the first source electrode 144a, and the first drain electrode 146a are arranged above the first semiconductor layer 110, and the second gate electrode 140, the second source electrode 146a, and the second drain electrode 146b are arranged above the second semiconductor layer 136. Both the first and second TFTs T1 and T2 have a coplanar structure. Alternatively, in both the first and second TFTs T1 and T2, a gate electrode can be arranged below a semiconductor layer, and a source electrode and a drain electrode can be arranged above the semiconductor layer. Each of the TFTs T1 and T2 can have an inverted staggered structure. A planarization layer 150, covering the first source electrode and the first drain electrode 144a and 144b and the second source electrode and the second drain electrode 146a and 146b, is arranged on the third intermediate insulating layer 142. The planarization layer 150 can be formed from an organic insulating material, e.g., photoacrylic or BCB. The planarization layer 150 can have a first planarization layer 150a on the first source electrode and the first drain electrode 144a and 144b and the second source electrode and the second drain electrode 146a and 146b, a second planarization layer 150b on the first planarization layer 150a and a third planarization layer 150c on the second planarization layer 150b. A connecting electrode 148, corresponding to the second source electrode 146a, is arranged on the first planarization layer 150a. The connecting electrode 148 can be connected to the second source electrode 146a via a contact hole in the first planarization layer 150a. For example, the connecting electrode 148 can be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, and can have a single-layer or multi-layer structure. The second planarization layer 150b is arranged on top of the first planarization layer 150a to cover the connecting electrode 148, and the third planarization layer 150c is arranged on top of the second planarization layer 150b. The flatness of an anode 160a of the OLED D can be degraded by a step difference resulting from an electrode or a signal line beneath the anode 160a, potentially leading to a problem such as a reduction in the lifetime of the OLED D. However, in the organic light emission display device 100 of the present disclosure, the step difference can be compensated for by the third planarization layer 160c, thus preventing the above problem. In Fig. 3, the planarization layer 150 comprises the first to third planarization layers 150a, 150b, and 150c to form a three-layer structure. In one embodiment of the present disclosure, the connecting electrode 148 and the first planarization layer 150a can be omitted, so that the planarization layer 150 can have a two-layer structure. In another embodiment of the present disclosure, an additional planarization layer can be arranged, so that the planarization layer 150 can have four or more layers. The planarization layer 150 contains a scattering particle. For example, in the planarization layer 150, the scattering particle can be dispersed in an organic insulating material. In one embodiment of the present disclosure, at least one of the first to third planarization layers 150a, 150b and 150c can comprise the scattering particle. For example, the second planarization layer 150b can comprise a first scattering particle 152 and the third planarization layer 150c can comprise a second scattering particle 154. Each of the first and second scattering particles 152 and 154 can be formed from an inorganic material, e.g. silicon dioxide (SiO2), or an organic material, e.g. polyoxyethylene, polyoxyethylene glycol, polyoxypropylene alkyl ether, polyoxypropylene monoalkyl ether, polyoxypropylene alkyl, polyoxyethylene talgamine, polyoxyethylene oleylamine, polyoxyethylene sterylamine, polyoxyethylene laurylamine, polyoxyethylene sorbitan ester, polyoxyethylene octyl ether, polyoxyethylene glycerol ether, polyacrylic acid, polysulfonic acid, polyacrylamine, triethyleneamine, their copolymer or their blocked copolymer. Each of the first and second scattering particles 152 and 154 can have a diameter (e.g., a size) in the range of 1 nm to 80 nm or in the range of 100 nm to 1000 nm. For example, each of the first and second scattering particles 152 and 154 can have a diameter in the range of 10 nm to 80 nm or in the range of 300 nm to 700 nm. If each of the first and second scattering particles 152 and 154 has a diameter in the range of 1 nm to 80 nm, Rayleigh scattering can occur for each of the first and second scattering particles 152 and 154. Alternatively, if each of the first and second scattering particles 152 and 154 has a diameter in the range of 100 nm to 1000 nm, Mie scattering can occur for each of the first and second scattering particles 152 and 154. In Fig. 3, the planarization layer 150 comprises the first to third planarization layers 150a, 150b, and 150c, and the second and third planarization layers 150b and 150c each comprise the first and second scattering particles 152 and 154, respectively. In one embodiment of the present disclosure, the first planarization layer 150a also comprises a scattering particle. The scattering particle in the first planarization layer 150a can have the same diameter as the first and second scattering particles 152 and 154. A first electrode 160a is arranged on the second planarization layer 150b. The first electrode 160a corresponds to the connecting electrode 148 and is connected to the connecting electrode 148 by a contact hole in the second and third planarization layers 150b and 150c. For example, the first electrode 160a is formed separately in each pixel area P. The first electrode 160a can be an anode and can have a transparent conductive oxide (TCO) layer, which is formed from a conductive material, e.g., a transparent conductive oxide material, with a relatively high work function, and a reflective layer. For example, the transparent conductive oxide material can comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin-zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer can comprise at least one of silver (Ag), an alloy of Ag and palladium (Pd), Cu, In and Nd, and aluminum palladium-copper alloy (APC). For example, the first electrode 160a can have a double-layer structure of Ag / ITO or APC / ITO, or a triple-layer structure of ITO / Ag / ITO or ITO / APC / ITO. A pixel definition layer 156 is formed on the third planarization layer 150c at an edge of the pixel area. The pixel definition layer 156 covers an edge of the first electrode 160a and has an opening to expose the center of the first electrode 160a. The opening of the pixel definition layer 156 corresponds to the OLED D. The pixel definition layer 156 can have a light-absorbing property. The pixel definition layer 156 can be a black pixel definition layer or a gray pixel definition layer. The pixel definition layer 156 can contain a black particle, e.g., a light-absorbing particle, arranged in an organic material, e.g., a binder. For example, the organic material can be at least one of photoacrylic, benzocyclobutene, and polyimide, and the black particle can be at least one of carbon black, carbon nanotubes (CNTs), and graphene. The pixel definition layer 156 can have a first optical density (OD) of 1.0 or less. For example, the first OD can be in a range of 0.5 to 1.0. In the organic light emission display device, after the first electrode 160a is formed, the pixel definition layer 156, which covers an edge of the first electrode 160a, is formed by coating the organic material containing the black particle and performing a masking process. If the pixel definition layer has a relatively high OD (organic density), the amount of black particle in the organic material increases, while the amount of organic material decreases. As a result, the curing process on the organic material is incomplete, and a particle may remain on the first electrode 160a. In this case, a problem may occur with the driver voltage and the lifetime of the OLED D. In the organic light emission display device 100 of the present disclosure, the above problem can be prevented by reducing an amount in the pixel definition layer 156, so that the pixel definition layer 156 has a relatively low OD. If the pixel definition layer 156 has a relatively low optical density (OD), external light (e.g., ambient light) can pass through the pixel definition layer 156 and be reflected by an electrode and / or a signal line beneath the pixel definition layer 156, thus potentially increasing external light reflection. Additionally, the external light passing through the pixel definition layer 156 can strike the first semiconductor layer 110 of the first TFT T1 and / or the second semiconductor layer 136 of the second TFT T2, potentially causing leakage current. For example, if the external light strikes the first semiconductor layer 110 of the first TFT T1, which is made of a high-mobility oxide semiconductor material, the performance of the first TFT T1 can be significantly degraded by the leakage current. However, in the organic light emission display device 100 of the present disclosure, the second and third planarization layers 150b and 150c under the pixel definition layer 156 each have the first and second scattering particles 152 and 154, respectively, whereby the above problems of external light reflection and / or leakage current from the first and second TFT T1 and T2 can be prevented or minimized. Referring to Fig. 4, which is a schematic cross-sectional view showing the extinction of light within a planarization layer, a portion of the external light passes through the pixel definition layer 156, which has a relatively low OD, and falls onto the planarization layer 150. In the organic light emission display device 100 of the present disclosure, since the second and third planarization layers 150b and 150c each contain the first and second scattering particles 152 and 154, respectively, the external light passing through the pixel definition layer 156 is scattered by the first and second scattering particles 152 and 154 in the second and third planarization layers 150b and 150c and is extinguished by destructive interference. Accordingly, the degradation of the display quality due to external light reflection and / or the leakage current of the TFTs T1 and T2 can be prevented or minimized. Referring again to Fig. 3, a first spacer 158a with a reverse-tapered shape and a second spacer 158b with a tapered shape are arranged on the pixel definition layer 156. For example, both the first spacer 158a and the second spacer 158b can be formed from an organic insulating material, e.g., photoacrylic or benzocyclobutene (BCB), and can have a single-layer or multi-layer structure. At least one of the first spacer 158a and the second spacer 158b can be omitted. An organic light-emitting layer 160b, covering the first electrode 160a, the pixel definition layer 156, and the first and second spacers 158a and 158b, is arranged. The organic light-emitting layer 160b contacts the first electrode 160a in the opening of the pixel definition layer 156. Specifically, the organic light-emitting layer 160b can be formed to contact a top surface of the first electrode 160a, a side surface and a top surface of the pixel definition layer 156, a top surface of the first spacer 158a, and a side surface and a top surface of the second spacer 158b. For example, the organic light emission layer 160b can have an organic emission material layer (EML) comprising a host and a dopant. Additionally, the organic light emission layer 160b can further comprise at least one hole injection layer (HIL), one hole transport layer (HTL), one electron blocking layer (EBL), one hole blocking layer (HBL), one electron transport layer (ETL), and one electron injection layer (EIL) to form a multilayer structure. A second electrode 160c is formed above the substrate 102, where the organic light-emitting layer 160b is formed. The second electrode 160c covers an entire area of ​​the display area. The second electrode 160c can be formed from at least one of ITO, IZO, Al, Ag, Cu, Pb, Magnesium (Mg), Mo, Ti, and their alloys, and can have a single-layer or multi-layer structure. The second electrode 160c can have a thin profile (low thickness) to provide a light-transmitting (or semi-transmitting) property. The first electrode 160a, the organic light-emitting layer 160b, and the second electrode 160c form an organic light-emitting diode (OLED) D. The OLED D can emit red, green, and blue light in the red, green, and blue pixel regions, respectively. Alternatively, the OLED D can emit white light in the red, green, blue, and white pixel regions. In the organic light emission display device 100, light from the light emission layer 160b passes through the second electrode 160c and a color filter layer 182 to display an image. The organic light emission display device 100 of the present disclosure is, in fact, a top-emission display device. An encapsulation layer (or encapsulation film) 162 is formed on the second electrode 160c to prevent moisture from entering the organic light-emitting diode D. The encapsulation layer 162 can cover the entire substrate 102. The encapsulation layer 162 comprises a first inorganic insulating layer 162a, an organic insulating layer 162b, and a second inorganic insulating layer 162c, which are stacked sequentially. Each of the first and second inorganic insulating layers 162a and 162c can be formed from an inorganic insulating material, e.g. silicon oxide or silicon nitride. The organic insulating layer 162b can be formed from an organic insulating material, e.g. acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin. A second buffer layer 164 is arranged on the encapsulation layer 162 and over the entire surface of the substrate 102. Moisture and / or oxygen can be blocked by the second buffer layer 164. For example, the second buffer layer 164 can be formed from an inorganic insulating material, e.g., silicon dioxide or silicon nitride, and can have a single-layer or a multi-layer structure. A multitude of bridge structures 166 are arranged on the second buffer layer 164. For example, each of the multitude of bridge structures 166 can be formed from ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti and their alloys and can have a single-layer or a multi-layer structure. A fourth intermediate insulating layer 168 is arranged on the bridge structure 166 and over an entire area of ​​the substrate 102. The fourth intermediate insulating layer 168 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, or an organic insulating material, e.g., photoacrylic or BCB, and can have a single-layer or a multi-layer structure. A sensor structure 170 is arranged on the fourth intermediate insulating layer 168. The sensor structure 170 can have a plurality of first sensor structures 170a spaced apart from one another and a plurality of second sensor structures 170b arranged between adjacent first sensor structures 170a. The first sensor structure 170a is connected to the bridge structure 166 by a contact hole in the fourth intermediate insulating layer 168. For example, both the first and second sensor structures 170a and 170b can be formed from one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti and their alloys and can have a single-layer or multi-layer structure. A first protective layer 172 is arranged over the entire surface of the substrate 102 to cover the first and second sensor structures 170a and 170b. The first protective layer 172 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, or an organic insulating material, e.g., photoacrylic or benzocyclobutene, and can have a single-layer or a multi-layer structure. A third buffer layer 174 is arranged on top of the first protective layer 172 and covers an entire area of ​​the substrate 102. The third buffer layer 174 can be made of an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A black matrix 180 is arranged on the third buffer layer 174. The black matrix 180 is positioned at an edge of the pixel area P and has an opening corresponding to the organic light-emitting diode D. The opening of the black matrix 180 corresponds to the opening of the pixel definition layer 156. The black matrix 180 has a second OD that is larger than the first OD of the pixel definition layer 156. The second OD of the black matrix 180 can be in a range of 0.8 or higher. For example, the second OD can be in a range of 0.8 to 1.8. The black matrix 180 can contain a black particle, e.g. soot, CNT or graphene. In one embodiment of the present disclosure, both the pixel definition layer 156 and the black matrix 180 can be formed by stacking at least two layers of a red color filter layer, a green color filter layer and a blue color filter layer. The size (e.g., a flat surface) of the opening in the black matrix 180 can be larger than the size of the opening in the pixel definition layer 156. If the opening of the black matrix 180 can be equal to or smaller than the opening of the pixel definition layer 156, the viewing angle of the organic light emission display device 100 can be reduced. The black matrix 180 has an aperture larger than the aperture of the pixel definition layer 156, and the pixel definition layer 156 has a relatively low OD. Consequently, external light can pass through the aperture of the black matrix 180 and an edge of the pixel definition layer 156, potentially leading to problems of external light reflection and / or leakage current from the TFT. However, as described above, in the organic light emission display device 100 of the present disclosure, since the planarization layer 150, e.g. the second and third planarization layers 150b and 150c, under the pixel definition layer 156 has the first and second scattering particles 152 and 154, the problem of external light reflection and leakage current in the TFT T1 and T2, caused by the black matrix 180, which has an aperture larger than an aperture of the pixel definition layer 156, and the pixel definition layer 156, which has a relatively low OD, can be prevented or minimized. A color filter layer 182, corresponding to the black matrix 180, is arranged on the third buffer layer 174. The color filter layer 182 can have a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area. Since the organic light emission display device 100 has the color filter layer 182, external light reflection can be reduced or minimized. Specifically, since the organic light emission display device 100 has the color filter layer 182 without a polarizing plate, external light reflection can be reduced by minimizing the decrease in luminance. A second protective layer 184 is arranged on the black matrix 180 and the color filter layer 182 and over an entire area of ​​the substrate 102. The second protective layer 184 can be formed from an inorganic insulating material, e.g. silicon oxide or silicon nitride, or an organic insulating material, e.g. photoacrylic or benzocyclobutene, and can have a single-layer or a multi-layer structure. In the organic light emission display device 100 of the present disclosure, the pixel definition layer 156 has a relatively low OD, e.g. a relatively small amount of the black particle, so that a problem arising from a particle in a manufacturing process can be prevented. Since the planarization layer 150, e.g. the second and third planarization layers 150b and 150c, under the pixel definition layer 156 has the first and second scattering particles 152 and 154, the problem of external light reflection and leakage current in the TFT T1 and T2 can also be reduced, prevented or minimized. Since the organic light emission indicator device 100 has the color filter layer 182 without a polarizing plate, external light reflection can also be reduced by minimizing the decrease in luminance. Fig. 5 is a schematic cross-sectional view showing an organic light emission indicator device according to a second embodiment of the present disclosure. As shown in Fig. 5, the organic light emission display device 200 has a substrate 202, a TFT on the substrate 202, a planarization layer 250 covering the TFT, an OLED D on the planarization layer 250 and a pixel definition layer 256 on the planarization layer 250 and at an edge of a pixel area P. A plurality of pixel regions P is defined on the substrate 202. The substrate 202 can be a glass substrate or a plastic substrate. In one embodiment of the present disclosure, the substrate 202 can have a three-layer structure comprising a first polyimide (Pl) layer, a second Pl layer, and an inorganic intermediate layer between the first and second Pl layers. A first light-shielding structure 204 is arranged on the substrate 202, and a first buffer layer 206, which covers the first light-shielding structure 204, is arranged above the substrate 202. A first semiconductor layer 210, corresponding to the first light-shielding structure 204, is arranged on the first buffer layer 206. The first semiconductor layer 210 can be made of a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. If the first light-shielding structure 204 and the first buffer layer 206 are omitted, the first semiconductor layer 210 can be arranged directly on the substrate 202. In an exemplary embodiment of the present disclosure, the first semiconductor layer 210 can be formed from a polysemiconductor material, e.g., polycrystalline silicon. The first semiconductor layer 210 can have a first channel region 210a, a first source region 210b on one side of the first channel region 210a, and a first drain region 210c on the other side of the first channel region 210a. Impurities can be doped into the first source and drain regions 210b and 210c, respectively. A first gate isolation layer 212, covering the first semiconductor layer 210, is arranged above the first buffer layer 206. A first gate electrode 214, corresponding to the first channel region 210a of the first semiconductor layer 210, is arranged on the first gate insulating layer 212. Additionally, a first capacitor electrode 216, located at a distance from the first gate electrode 214, is arranged on the first gate insulating layer 212. A first intermediate insulating layer 218, covering the first gate electrode 214 and the first capacitor electrode 216, is arranged on the first gate insulating layer 212. A second capacitor electrode 230, corresponding to the first capacitor electrode 216, and a second light shielding structure 232, which is spaced apart from the second capacitor electrode 230, are arranged on the first intermediate insulating layer 218. A second intermediate insulating layer 234, covering the second capacitor electrode 230 and the second light shielding structure 232, is arranged on the first intermediate insulating layer 218. A second semiconductor layer 236, corresponding to the second light-shielding structure 232, is arranged on the second intermediate insulating layer 234. The second semiconductor layer 236 can comprise a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. In an exemplary embodiment of the present disclosure, the second semiconductor layer 236 can be formed from an oxide semiconductor material, e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO). The second semiconductor layer 236 can have a second channel region 236a, a second source region 236b on one side of the second channel region 236a, and a second drain region 236c on the other side of the second channel region 236a. Impurities can be doped into the second source and drain regions 236b and 236c, respectively. A second gate isolation layer 238, covering the second semiconductor layer 236, is arranged above the second interlayer isolation layer 234. A second gate electrode 240, corresponding to the second channel region 236a of the second semiconductor layer 236, is arranged on the second gate insulating layer 238. A third intermediate insulating layer 242, covering the second gate electrode 240, is arranged on the second gate insulating layer 238. A first source electrode 244a, a first drain electrode 244b, a second source electrode 246a and a second drain electrode 246b are arranged on the third intermediate insulating layer 242. The first source electrode 244a and the first drain electrode 244b are each connected to the first source region 210b and the first drain region 210c via contact holes through the third interlayer insulating layer 242, the second gate insulating layer 238, the second interlayer insulating layer 234, the first interlayer insulating layer 218, and the first gate insulating layer 212. The first source electrode 244a is connected to the first capacitor electrode 216 via a contact hole through the third interlayer insulating layer 242, the second gate insulating layer 238, the second interlayer insulating layer 234, and the first interlayer insulating layer 218. The second source electrode 246a and the second drain electrode 246b are each connected to the second source region 236b and the second drain region 236c via contact holes through the third interlayer insulating layer 242 and the second gate insulating layer 238. The second source electrode 246a is connected to the second capacitor electrode 230 via a contact hole through the third interlayer insulating layer 242, the second gate insulating layer 238, and the second interlayer insulating layer 234. The first semiconductor layer 210, the first gate electrode 214, the first source electrode 244a and the first drain electrode 244b form a first TFT T1, and the second semiconductor layer 236, the second gate electrode 240, the second source electrode 246a and the second drain electrode 246b form a second TFT T2. For example, the first TFT T1 can be a switching TFT and the second TFT T2 can be a driver TFT. The organic light emission display device of the present disclosure comprises the first and second TFTs T1 and T2. Both the first semiconductor layer 210 of the first TFT T1 and the second semiconductor layer 236 of the second TFT T2 can comprise a polysemiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 210 of the first TFT T1 and the second semiconductor layer 236 of the second TFT T2 can comprise the oxide semiconductor material. In an exemplary embodiment of the present disclosure, the first semiconductor layer 210 of the first TFT T1 can be formed from the polysemiconductor material, e.g., polycrystalline silicon, and the second semiconductor layer 236 of the second TFT T2 can be formed from the oxide semiconductor material. A planarization layer 250, covering the first source electrode and the first drain electrode 244a and 244b and the second source electrode and the second drain electrode 246a and 246b, is arranged on the third intermediate insulating layer 242. The planarization layer 250 can be formed from an organic insulating material, e.g., photoacrylic or BCB. The planarization layer 250 can have a first planarization layer 250a on the first source electrode and the first drain electrode 244a and 244b and the second source electrode and the second drain electrode 246a and 246b, a second planarization layer 250b on the first planarization layer 250a and a third planarization layer 250c on the second planarization layer 250b. A connecting electrode 248, corresponding to the second source electrode 246a, is arranged on the first planarization layer 250a. The connecting electrode 248 can be connected to the second source electrode 246a through a contact hole in the first planarization layer 250a. The second planarization layer 250b is arranged on top of the first planarization layer 250a to cover the connecting electrode 248, and the third planarization layer 250c is arranged on top of the second planarization layer 250b. The flatness of an anode 260a of the OLED D can be degraded by a step difference resulting from an electrode or a signal line beneath the anode 260a, potentially leading to a problem such as a reduction in the lifetime of the OLED D. However, in the organic light emission display device 200 of the present disclosure, the step difference can be compensated for by the third planarization layer 250c, thus preventing the above problem. In Fig. 5, the planarization layer 250 comprises the first to third planarization layers 250a, 250b, and 250c to form a three-layer structure. In one embodiment of the present disclosure, the connecting electrode 248 and the first planarization layer 250a can be omitted, so that the planarization layer 250 can have a two-layer structure. In another embodiment of the present disclosure, an additional planarization layer can be arranged, so that the planarization layer 250 can have four or more layers. The planarization layer 250 contains a scattering particle. For example, in the planarization layer 250, the scattering particle can be dispersed in an organic insulating material. In one embodiment of the present disclosure, at least one of the first to third planarization layers 250a, 250b and 250c can comprise the scattering particle. For example, the second planarization layer 250b can comprise a first scattering particle 252 and the third planarization layer 250c can comprise a second scattering particle 254. Each of the first and second scattering particles 252 and 254 can be formed from an inorganic material, e.g. silicon dioxide (SiO2), or an organic material, e.g. polyoxyethylene, polyoxyethylene glycol, polyoxypropylene alkyl ether, polyoxypropylene monoalkyl ether, polyoxypropylene alkyl, polyoxyethylene talgamine, polyoxyethylene oleylamine, polyoxyethylene sterylamine, polyoxyethylene laurylamine, polyoxyethylene sorbitan ester, polyoxyethylene octyl ether, polyoxyethylene glycerol ether, polyacrylic acid, polysulfonic acid, polyacrylamine, triethyleneamine, their copolymer or their blocked copolymer. The first scattering particle 252 has a first diameter (e.g., a size), and the second scattering particle 254 has a second diameter that is larger than the first. The first scattering particle 252 can have a diameter in the range of 1 nm to 80 nm, and the second scattering particle 254 can have a diameter in the range of 100 nm to 1000 nm. For example, the first scattering particle 252 can have a diameter in the range of 10 nm to 80 nm, and the second scattering particle 254 can have a diameter in the range of 300 nm to 700 nm. Rayleigh scattering can occur due to the first scattering particle 252, and Mie scattering can occur due to the second scattering particle 254. In Fig. 5, the first planarization layer 250a is formed by an organic insulating material without a scattering particle. Alternatively, the first planarization layer 250a can include a third scattering particle. The third scattering particle can have a diameter equal to or substantially equal to that of the second scattering particle 254. For example, the third scattering particle can have a diameter in the range of 100 nm to 1000 nm, e.g., 300 nm to 700 nm. As a result, Mie scattering by the third scattering particle can occur. A first electrode 260a is arranged on the second planarization layer 250b. The first electrode 260a corresponds to the connecting electrode 248 and is connected to the connecting electrode 248 by a contact hole in the second and third planarization layers 250b and 250c. For example, the first electrode 260a is formed separately in each pixel area P. The first electrode 260a can be an anode and can have a transparent conductive oxide (TCO) layer formed from a conductive material, e.g., a transparent conductive oxide material with a relatively high work function, and a reflective layer. For example, the transparent conductive oxide material can comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin-zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer can comprise at least one of silver (Ag), an alloy of Ag and palladium (Pd), Cu, In and Nd, and an aluminum-palladium-copper alloy (APC). For example, the first electrode 260a can have a double-layer structure of Ag / ITO or APC / ITO, or a triple-layer structure of ITO / Ag / ITO or ITO / APC / ITO. A pixel definition layer 256 is formed on the third planarization layer 250c at an edge of the pixel area. The pixel definition layer 256 covers an edge of the first electrode 260a and has an opening to expose the center of the first electrode 260a. The pixel definition layer 256 can have a light-absorbing property. The pixel definition layer 256 can be a black pixel definition layer or a gray pixel definition layer. The pixel definition layer 256 can contain a black particle, e.g., a light-absorbing particle, arranged in an organic material, e.g., a binder. For example, the organic material can be at least one of photoacrylic, benzocyclobutene, and polyimide, and the black particle can be at least one of carbon black, carbon nanotubes (CNTs), and graphene. The pixel definition layer 256 can have a first optical density (OD) of 1.0 or less. For example, the first OD can be in a range of 0.5 to 1.0. In the organic light emission display device, after the first electrode 260a is formed, the pixel definition layer 256, which covers an edge of the first electrode 260a, is formed by coating it with the organic material containing the black particle and performing a masking process. If the pixel definition layer has a relatively high OD (organic density), the amount of black particle in the organic material increases, while the amount of organic material decreases. As a result, the curing process on the organic material is incomplete, so that a particle may remain on the first electrode 260a. In this case, a problem may occur with the driver voltage and the lifetime of the OLED D. In the organic light emission display device 200 of the present disclosure, the above problem can be prevented by reducing an amount in the pixel definition layer 256, so that the pixel definition layer 256 has a relatively low OD. If the pixel definition layer 256 has a relatively low optical density (OD), external light (e.g., ambient light) can pass through the pixel definition layer 256 and be reflected by an electrode and / or a signal line beneath the pixel definition layer 256, thus potentially increasing external light reflection. Additionally, the external light passing through the pixel definition layer 256 can strike the first semiconductor layer 210 of the first TFT T1 and / or the second semiconductor layer 236 of the second TFT T2, potentially causing leakage current. For example, if the external light strikes the first semiconductor layer 210 of the first TFT T1, which is made of a high-mobility oxide semiconductor material, the performance of the first TFT T1 can be significantly degraded by the leakage current. However, in the organic light emission display device 200 of the present disclosure, the second and third planarization layers 250b and 250c under the pixel definition layer 256 each have the first and second scattering particles 252 and 254, respectively, whereby the above problems of external light reflection and / or leakage current from the first and second TFT T1 and T2 can be reduced, prevented or minimized. Additionally, Mie scattering can occur due to the second scattering particle 254, and Rayleigh scattering can occur due to the first scattering particle 252. As a result, the amount of light passing through the pixel definition layer 256 and directed onto the first and second TFTs T1 and T2 can be reduced or minimized, thus reducing, minimizing, or preventing the leakage current in the first and second TFTs T1 and T2 caused by external light. A first spacer 258a with a reverse tapered shape and a second spacer 258b with a tapered shape are arranged on the pixel definition layer 256. An organic light-emitting layer 260b, covering the first electrode 260a, the pixel definition layer 256, and the first and second spacers 258a and 258b, is arranged. The organic light-emitting layer 260b contacts the first electrode 260a in the opening of the pixel definition layer 256. Specifically, the organic light-emitting layer 260b can be formed to contact a top surface of the first electrode 260a, a side surface and a top surface of the pixel definition layer 256, a top surface of the first spacer 258a, and a side surface and a top surface of the second spacer 258b. For example, the organic light emission layer 260b can have an organic emission material layer (EML) comprising a host and a dopant. Additionally, the organic light emission layer 260b can further comprise at least one HIL, one HTL, one EBL, one HBL, one ETL, and one EIL to have a multilayer structure. A second electrode 260c is formed above the substrate 202, where the organic light-emitting layer 260b is formed. The second electrode 260c covers an entire area of ​​the display area. The second electrode 260c can be formed from at least one of ITO, IZO, Al, Ag, Cu, Pb, Magnesium (Mg), Mo, Ti, and their alloys, and can have a single-layer or multi-layer structure. The second electrode 260c can have a thin profile (low thickness) to provide a light-transmitting property (or a semi-transmitting property). The first electrode 260a, the organic light-emitting layer 260b, and the second electrode 260c form an organic light-emitting diode (OLED) D. The OLED D can emit red, green, and blue light in the red, green, and blue pixel regions, respectively. Alternatively, the OLED D can emit white light in the red, green, blue, and white pixel regions. In the organic light emission display device 200, light from the light emission layer 260b passes through the second electrode 260c and a color filter layer 282 to display an image. The organic light emission display device 200 of the present disclosure is, in fact, a top-emission display device. An encapsulation layer (or encapsulation film) 262 is formed on the second electrode 260c to prevent moisture from entering the organic light-emitting diode D. The encapsulation layer 262 can cover the entire substrate 202. The encapsulation layer 262 comprises a first inorganic insulating layer 262a, an organic insulating layer 262b, and a second inorganic insulating layer 262c, which are stacked sequentially. A second buffer layer 264 is arranged on top of the encapsulation layer 262 and over the entire surface of the substrate 202. Moisture and / or oxygen can be blocked by the second buffer layer 264. A multitude of bridge structures 266 are arranged on the second buffer layer 264, and a fourth intermediate layer insulation layer 268 is arranged on the bridge structure 266 and over an entire area of ​​the substrate 202. A sensor structure 270 is arranged on the fourth intermediate insulating layer 268. The sensor structure 270 can have a plurality of first sensor structures 270a spaced apart from one another and a plurality of second sensor structures 270b arranged between adjacent first sensor structures 270a. The first sensor structure 270a is connected to the bridge structure 266 by a contact hole in the fourth intermediate insulating layer 268. A first protective layer 272 is arranged over an entire area of ​​the substrate 202 to cover the first and second sensor structures 270a and 270b, and a third buffer layer 274 is arranged on the first protective layer 272 and over an entire area of ​​the substrate 202. A black matrix 280 is arranged on the third buffer layer 274. The black matrix 280 is positioned at an edge of the pixel area P and has an opening corresponding to the organic light-emitting diode D. The opening of the black matrix 280 corresponds to the opening of the pixel definition layer 256. The black matrix 280 has a second OD that is larger than the first OD of the pixel definition layer 256. The second OD of the black matrix 280 can be in a range of 0.8 or higher. For example, the second OD can be in a range of 0.8 to 1.8. The size (e.g., a flat surface) of the opening in the black matrix 280 can be larger than that of the opening in the pixel definition layer 256. If the opening of the black matrix 280 can be equal to or smaller than the opening of the pixel definition layer 256, the viewing angle of the organic light emission display device 200 can be reduced. The black matrix 280 has an aperture larger than the aperture of the pixel definition layer 256, and the pixel definition layer 256 has a relatively low OD. Consequently, external light can pass through the aperture of the black matrix 280 and an edge of the pixel definition layer 256, potentially leading to problems of external light reflection and / or leakage current from the TFT. However, as described above, in the organic light emission display device 200 of the present disclosure, since the planarization layer 250 under the pixel definition layer 256 has the first and second scattering particles 252 and 254, the problem of external light reflection and leakage current in the TFT T1 and T2, caused by the black matrix 280, which has an aperture larger than an aperture of the pixel definition layer 256, and the pixel definition layer 256, which has a relatively low OD, can be reduced, prevented or minimized. Additionally, the second planarization layer 250b has the first scattering particle 252 with the first diameter, and the third planarization layer 250c, which is positioned between the second planarization layer 250b and the pixel definition layer 256, has the second scattering particle 254 with the second diameter, which is larger than the first diameter. Accordingly, the external light reaching the TFTs T1 and T2 can be further reduced, thus further preventing leakage current in the TFTs T1 and T2. A color filter layer 282, corresponding to the black matrix 280, is arranged on the third buffer layer 274. The color filter layer 282 can have a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area. Since the organic light emission display device 200 has the color filter layer 282, external light reflection can be reduced or minimized. Specifically, since the organic light emission display device 200 has the color filter layer 282 without a polarizing plate, external light reflection can be reduced by minimizing the decrease in luminance. A second protective layer 284 is arranged on the black matrix 280 and the color filter layer 282 and over an entire area of ​​the substrate 202. In the organic light emission display device 200 of the present disclosure, the pixel definition layer 256 has a relatively low OD, e.g. a relatively small amount of the black particle, so that a problem arising from a particle in a manufacturing process can be prevented. Since the planarization layer 250, e.g. the second and third planarization layers 250b and 250c, under the pixel definition layer 256 has the first and second scattering particles 252 and 254, the problem of external light reflection and leakage current in the TFT T1 and T2 can also be reduced, prevented or minimized. Since the organic light emission indicator device 200 has the color filter layer 282 without a polarizing plate, external light reflection can also be reduced by minimizing the decrease in luminance. Furthermore, the second planarization layer 250b contains the first scattering particle 252 with the first diameter, and the third planarization layer 250c, which is positioned between the second planarization layer 250b and the pixel definition layer 256, contains the second scattering particle 254 with the second diameter, which is larger than the first diameter. Accordingly, the external light reaching the TFTs T1 and T2 can be further reduced, thus further preventing leakage current in the TFTs T1 and T2. Fig. 6 is a schematic cross-sectional view showing an organic light emission indicator device according to a third embodiment of the present disclosure. As shown in Fig. 6, the organic light emission display device 300 has a substrate 302, a TFT on the substrate 302, a planarization layer 350 covering the TFT, an OLED D on the planarization layer 350 and a pixel definition layer 356 on the planarization layer 350 and at an edge of a pixel area P. A plurality of pixel regions P is defined on the substrate 302. The substrate 302 can be a glass substrate or a plastic substrate. In one embodiment of the present disclosure, the substrate 302 can have a three-layer structure comprising a first polyimide (Pl) layer, a second Pl layer, and an inorganic intermediate layer between the first and second PI layers. A first light-shielding structure 304 is arranged on the substrate 302, and a first buffer layer 306, which covers the first light-shielding structure 304, is arranged above the substrate 302. A first semiconductor layer 310, corresponding to the first light-shielding structure 304, is arranged on the first buffer layer 306. The first semiconductor layer 310 can be made of a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. If the first light-shielding structure 304 and the first buffer layer 306 are omitted, the first semiconductor layer 310 can be arranged directly on the substrate 302. In an exemplary embodiment of the present disclosure, the first semiconductor layer 310 can be formed from a polysemiconductor material, e.g., polycrystalline silicon. The first semiconductor layer 310 can have a first channel region 310a, a first source region 310b on one side of the first channel region 310a, and a first drain region 310c on the other side of the first channel region 310a. Impurities can be doped into the first source and drain regions 310b and 310c, respectively. A first gate isolation layer 312, covering the first semiconductor layer 310, is arranged above the first buffer layer 306. A first gate electrode 314, corresponding to the first channel region 310a of the first semiconductor layer 310, is arranged on the first gate insulating layer 312. Additionally, a first capacitor electrode 316, located at a distance from the first gate electrode 314, is arranged on the first gate insulating layer 312. A first intermediate insulating layer 318, covering the first gate electrode 314 and the first capacitor electrode 316, is arranged on the first gate insulating layer 312. A second capacitor electrode 330, corresponding to the first capacitor electrode 316, and a second light shielding structure 332, which is spaced apart from the second capacitor electrode 330, are arranged on the first intermediate insulating layer 318. A second intermediate insulating layer 334, covering the second capacitor electrode 330 and the second light shielding structure 332, is arranged on the first intermediate insulating layer 318. A second semiconductor layer 336, corresponding to the second light-shielding structure 332, is arranged on the second intermediate insulating layer 334. The second semiconductor layer 336 can comprise a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. In an exemplary embodiment of the present disclosure, the second semiconductor layer 336 can be formed from an oxide semiconductor material, e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO). The second semiconductor layer 336 can have a second channel region 336a, a second source region 336b on one side of the second channel region 336a, and a second drain region 336c on the other side of the second channel region 336a. Impurities can be doped into the second source and drain regions 336b and 336c, respectively. A second gate insulation layer 338, covering the second semiconductor layer 336, is arranged above the second interlayer insulation layer 334. A second gate electrode 340, corresponding to the second channel region 336a of the second semiconductor layer 336, is arranged on the second gate insulating layer 338. A third intermediate insulating layer 342, covering the second gate electrode 340, is arranged on the second gate insulating layer 338. A first source electrode 344a, a first drain electrode 344b, a second source electrode 346a and a second drain electrode 346b are arranged on the third interlayer insulating layer 342. The first source electrode 344a and the first drain electrode 344b are each connected to the first source region 310b and the first drain region 310c via contact holes through the third interlayer insulating layer 342, the second gate insulating layer 338, the second interlayer insulating layer 334, the first interlayer insulating layer 318, and the first gate insulating layer 312. The first source electrode 344a is connected to the first capacitor electrode 316 via a contact hole through the third interlayer insulating layer 342, the second gate insulating layer 338, the second interlayer insulating layer 334, and the first interlayer insulating layer 318. The second source electrode 346a and the second drain electrode 346b are each connected to the second source region 336b and the second drain region 336c via contact holes through the third interlayer insulating layer 342 and the second gate insulating layer 338. The second source electrode 346a is connected to the second capacitor electrode 330 via a contact hole through the third interlayer insulating layer 342, the second gate insulating layer 338, and the second interlayer insulating layer 334. The first semiconductor layer 310, the first gate electrode 314, the first source electrode 344a and the first drain electrode 344b form a first TFT T1, and the second semiconductor layer 336, the second gate electrode 340, the second source electrode 346a and the second drain electrode 346b form a second TFT T2. For example, the first TFT T1 can be a switching TFT and the second TFT T2 can be a driver TFT. The organic light emission display device of the present disclosure comprises the first and second TFTs T1 and T2. Both the first semiconductor layer 310 of the first TFT T1 and the second semiconductor layer 336 of the second TFT T2 can comprise a polysemiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 310 of the first TFT T1 and the second semiconductor layer 336 of the second TFT T2 can comprise the oxide semiconductor material. In an exemplary embodiment of the present disclosure, the first semiconductor layer 310 of the first TFT T1 can be formed from the polysemiconductor material, e.g., polycrystalline silicon, and the second semiconductor layer 336 of the second TFT T2 can be formed from the oxide semiconductor material. A planarization layer 350, covering the first source electrode and the first drain electrode 344a and 344b and the second source electrode and the second drain electrode 346a and 346b, is arranged on the third intermediate insulating layer 342. The planarization layer 350 can be formed from an organic insulating material, e.g., photoacrylic or BCB. The planarization layer 350 can have a first planarization layer 350a on the first source electrode and the first drain electrode 344a and 344b and the second source electrode and the second drain electrode 346a and 346b, a second planarization layer 350b on the first planarization layer 350a and a third planarization layer 350c on the second planarization layer 350b. A connecting electrode 348, corresponding to the second source electrode 346a, is arranged on the first planarization layer 350a. The connecting electrode 348 can be connected to the second source electrode 346a through a contact hole in the first planarization layer 350a. The second planarization layer 350b is arranged on top of the first planarization layer 350a to cover the connecting electrode 348, and the third planarization layer 350c is arranged on top of the second planarization layer 350b. The flatness of an anode 360a of the OLED D can be degraded by a step difference resulting from an electrode or a signal line beneath the anode 360a, potentially leading to a problem such as a reduction in the lifetime of the OLED D. However, in the organic light emission display device 300 of the present disclosure, the step difference can be compensated for by the third planarization layer 350c, thus preventing the above problem. In Fig. 6, the planarization layer 350 comprises the first to third planarization layers 350a, 350b, and 350c to form a three-layer structure. In one embodiment of the present disclosure, the connecting electrode 348 and the first planarization layer 350a can be omitted, so that the planarization layer 350 can have a two-layer structure. In another embodiment of the present disclosure, an additional planarization layer can be arranged, so that the planarization layer 350 can have four or more layers. The planarization layer 350 contains a scattering particle. For example, in the planarization layer 350, the scattering particle can be dispersed in an organic insulating material. In one embodiment of the present disclosure, at least one of the first to third planarization layers 350a, 350b and 350c can comprise the scattering particle. For example, the second planarization layer 350b can comprise a first scattering particle 352 and the third planarization layer 350c can comprise a second scattering particle 354. Each of the first and second scattering particles 352 and 354 can be formed from an inorganic material, e.g. silicon dioxide (SiO2), or an organic material, e.g. polyoxyethylene, polyoxyethylene glycol, polyoxypropylene alkyl ether, polyoxypropylene monoalkyl ether, polyoxypropylene alkyl, polyoxyethylene talgamine, polyoxyethylene oleylamine, polyoxyethylene sterylamine, polyoxyethylene laurylamine, polyoxyethylene sorbitan ester, polyoxyethylene octyl ether, polyoxyethylene glycerol ether, polyacrylic acid, polysulfonic acid, polyacrylamine, triethyleneamine, their copolymer or their blocked copolymer. The first scattering particle 352 has a first diameter (e.g., a size), and the second scattering particle 354 has a second diameter that is smaller than the first. The first scattering particle 352 can have a diameter in the range of 100 nm to 1000 nm, and the second scattering particle 354 can have a diameter in the range of 1 nm to 80 nm. For example, the first scattering particle 352 can have a diameter in the range of 300 nm to 700 nm, and the second scattering particle 354 can have a diameter in the range of 10 nm to 80 nm. Mie scattering can occur due to the first scattering particle 352, and Rayleigh scattering can occur due to the second scattering particle 354. In Fig. 6, the first planarization layer 350a is formed by an organic insulating material without a scattering particle. Alternatively, the first planarization layer 350a can include a third scattering particle. The third scattering particle can have a diameter equal to or substantially equal to that of the second scattering particle 354. For example, the third scattering particle can have a diameter in the range of 1 nm to 80 nm, e.g., 10 nm to 70 nm. As a result, Rayleigh scattering by the third scattering particle can occur. A first electrode 360a is arranged on the second planarization layer 350b. The first electrode 360a corresponds to the connecting electrode 348 and is connected to the connecting electrode 348 by a contact hole in the second and third planarization layers 350b and 350c. For example, the first electrode 360a is formed separately in each pixel area P. The first electrode 360a can be an anode and can have a transparent conductive oxide (TCO) layer, which is formed from a conductive material, e.g., a transparent conductive oxide material, with a relatively high work function, and a reflective layer. For example, the transparent conductive oxide material can comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer can comprise at least one of silver (Ag), an alloy of Ag and palladium (Pd), Cu, In and Nd, and aluminum palladium copper alloy (APC). For example, the first electrode 360a can have a double-layer structure of Ag / ITO or APC / ITO, or a triple-layer structure of ITO / Ag / ITO or ITO / APC / ITO. A pixel definition layer 356 is formed on the third planarization layer 350c at an edge of the pixel area. The pixel definition layer 356 covers an edge of the first electrode 360a and has an opening to expose the center of the first electrode 360a. The pixel definition layer 356 can have a light-absorbing property. The pixel definition layer 356 can be a black pixel definition layer or a gray pixel definition layer. The pixel definition layer 356 can contain a black particle, e.g., a light-absorbing particle, arranged in an organic material, e.g., a binder. For example, the organic material can be at least one of photoacrylic, benzocyclobutene, and polyimide, and the black particle can be at least one of carbon black, carbon nanotubes (CNTs), and graphene. The pixel definition layer 356 can have a first optical density (OD) of 1.0 or less. For example, the first OD can be in a range of 0.5 to 1.0. In the organic light emission display device, after the first electrode 360a is formed, the pixel definition layer 356, which covers an edge of the first electrode 360a, is formed by coating the organic material containing the black particle and performing a masking process. If the pixel definition layer has a relatively high OD (organic density), the amount of black particle in the organic material is increased, while the amount of organic material itself is decreased. As a result, the curing process on the organic material is incomplete, and a particle may remain on the first electrode 360a. In this case, a problem may occur with the driver voltage and the lifetime of the OLED D. In the organic light emission display device 300 of the present disclosure, the above problem can be prevented by reducing an amount in the pixel definition layer 356, so that the pixel definition layer 356 has a relatively low OD. If the pixel definition layer 356 has a relatively low optical density (OD), external light (e.g., ambient light) can pass through the pixel definition layer 356 and be reflected by an electrode and / or a signal line beneath the pixel definition layer 356, thus potentially increasing external light reflection. Additionally, the external light passing through the pixel definition layer 356 can strike the first semiconductor layer 310 of the first TFT T1 and / or the second semiconductor layer 336 of the second TFT T2, potentially causing leakage current. For example, if the external light strikes the first semiconductor layer 310 of the first TFT T1, which is made of a high-mobility oxide semiconductor material, the performance of the first TFT T1 can be significantly degraded by the leakage current. However, in the organic light emission display device 300 of the present disclosure, the second and third planarization layers 350b and 350c under the pixel definition layer 356 each have the first and second scattering particles 352 and 354, respectively, whereby the above problems of external light reflection and / or leakage current from the first and second TFT T1 and T2 can be reduced, prevented or minimized. Additionally, Rayleigh scattering can occur due to the second scattering particle 354, and Mie scattering can occur due to the first scattering particle 352. As a result, the amount of light passing through the pixel definition layer 356 and directed onto the first and second TFTs T1 and T2 can be reduced or minimized, thus reducing, minimizing, or preventing the leakage current in the first and second TFTs T1 and T2 caused by external light. A first spacer 358a with a reverse tapered shape and a second spacer 358b with a tapered shape are arranged on the pixel definition layer 356. An organic light-emitting layer 360b, covering the first electrode 360a, the pixel definition layer 356, and the first and second spacers 358a and 358b, is arranged. The organic light-emitting layer 360b contacts the first electrode 360a in the opening of the pixel definition layer 356. Specifically, the organic light-emitting layer 360b can be formed to contact a top surface of the first electrode 360a, a side surface and a top surface of the pixel definition layer 356, a top surface of the first spacer 358a, and a side surface and a top surface of the second spacer 358b. For example, the organic light emission layer 360b can have an organic emission material layer (EML) comprising a host and a dopant. Additionally, the organic light emission layer 360b can further comprise at least one HIL, one HTL, one EBL, one HBL, one ETL, and one EIL to have a multilayer structure. A second electrode 360c is formed above the substrate 302, where the organic light-emitting layer 360b is formed. The second electrode 360c covers an entire area of ​​the display region. The second electrode 360c can be formed from at least one of ITO, IZO, Al, Ag, Cu, Pb, Magnesium (Mg), Mo, Ti, and their alloys, and can have a single-layer or multi-layer structure. The second electrode 360c can have a thin profile (low thickness) to provide a light-transmitting (or semi-transmitting) property. The first electrode 360a, the organic light-emitting layer 360b, and the second electrode 360c form an organic light-emitting diode (OLED) D. The OLED D can emit red, green, and blue light in the red, green, and blue pixel areas, respectively. Alternatively, the OLED D can emit white light in the red, green, blue, and white pixel areas. In the organic light emission display device 300, light from the light emission layer 360b passes through the second electrode 360c and a color filter layer 382 to display an image. The organic light emission display device 300 of the present disclosure is, in fact, a top-emission display device. An encapsulation layer (or encapsulation film) 362 is formed on the second electrode 360c to prevent moisture from entering the organic light-emitting diode D. The encapsulation layer 362 can cover the entire substrate 302. The encapsulation layer 362 comprises a first inorganic insulating layer 362a, an organic insulating layer 362b, and a second inorganic insulating layer 362c, which are stacked sequentially. A second buffer layer 364 is arranged on top of the encapsulation layer 362 and over the entire surface of the substrate 302. Moisture and / or oxygen can be blocked by the second buffer layer 364. A multitude of bridge structures 366 are arranged on the second buffer layer 364, and a fourth intermediate layer insulation layer 368 is arranged on the bridge structure 366 and over an entire area of ​​the substrate 302. A sensor structure 370 is arranged on the fourth intermediate insulating layer 368. The sensor structure 370 can have a plurality of first sensor structures 370a spaced apart from one another, and a plurality of second sensor structures 370b arranged between adjacent first sensor structures 370a. The first sensor structure 370a is connected to the bridge structure 366 by a contact hole in the fourth intermediate insulating layer 368. A first protective layer 372 is arranged over an entire area of ​​the substrate 302 to cover the first and second sensor structures 370a and 370b, and a third buffer layer 374 is arranged on the first protective layer 372 and over an entire area of ​​the substrate 302. A black matrix 380 is arranged on the third buffer layer 374. The black matrix 380 is positioned at an edge of the pixel area P and has an opening corresponding to the organic light-emitting diode D. The opening of the black matrix 380 corresponds to the opening of the pixel definition layer 356. The black matrix 380 has a second OD that is larger than the first OD of the pixel definition layer 356. The second OD of the black matrix 380 can be in a range of 0.8 or higher. For example, the second OD can be in a range of 0.8 to 1.8. The size (e.g., a flat surface) of the opening in the black matrix 380 can be larger than that of the opening in the pixel definition layer 356. If the opening of the black matrix 380 can be equal to or smaller than the opening of the pixel definition layer 356, the viewing angle of the organic light emission display device 300 can be reduced. The black matrix 380 has an aperture larger than that of the pixel definition layer 356, and the pixel definition layer 356 has a relatively low OD. Consequently, external light can pass through the aperture of the black matrix 380 and an edge of the pixel definition layer 356, potentially leading to problems of external light reflection and / or leakage current from the TFT. However, as described above, in the organic light emission display device 300 of the present disclosure, since the planarization layer 350 under the pixel definition layer 356 has the first and second scattering particles 352 and 354, the problem of external light reflection and leakage current in the TFT T1 and T2, caused by the black matrix 380, which has an aperture larger than an aperture of the pixel definition layer 356, and the pixel definition layer 356, which has a relatively low OD, can be reduced, prevented or minimized. Additionally, the second planarization layer 350b contains the first scattering particle 352 with the first diameter, and the third planarization layer 350c, which is positioned between the second planarization layer 350b and the pixel definition layer 356, contains the second scattering particle 354 with the second diameter, which is smaller than the first diameter. Accordingly, the external light reaching the TFTs T1 and T2 can be further reduced, thus further preventing leakage current in the TFTs T1 and T2. A color filter layer 382, ​​corresponding to the black matrix 380, is arranged on the third buffer layer 374. The color filter layer 382 can have a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area. Since the organic light emission display device 300 has the color filter layer 382, ​​external light reflection can be reduced or minimized. Specifically, since the organic light emission display device 300 has the color filter layer 382 without a polarizing plate, external light reflection can be reduced by minimizing the decrease in luminance. A second protective layer 384 is arranged on the black matrix 380 and the color filter layer 382 and over an entire area of ​​the substrate 302. In the organic light emission display device 300 of the present disclosure, the pixel definition layer 356 has a relatively low OD, e.g. a relatively small amount of the black particle, so that a problem arising from a particle in a manufacturing process can be prevented. Since the planarization layer 350, e.g. the second and third planarization layers 350b and 350c, under the pixel definition layer 356 has the first and second scattering particles 352 and 354, the problem of external light reflection and leakage current in the TFT T1 and T2 can also be reduced, prevented or minimized. Since the organic light emission indicator device 300 has the color filter layer 382 without a polarizing plate, external light reflection can also be reduced by minimizing the decrease in luminance. Furthermore, the second planarization layer 350b contains the first scattering particle 352 with the first diameter, and the third planarization layer 350c, which is positioned between the second planarization layer 350b and the pixel definition layer 356, contains the second scattering particle 354 with the second diameter, which is smaller than the first diameter. Accordingly, the external light reaching the TFTs T1 and T2 can be further reduced, thus further preventing leakage current in the TFTs T1 and T2. Fig. 7 is a schematic organic light emission view showing a light emission indicator device according to a fourth embodiment of the present disclosure. As shown in Fig. 7, the organic light emission display device 400 has a substrate 402, a TFT on the substrate 402, a planarization layer 450 covering the TFT, an OLED D on the planarization layer 450 and a pixel definition layer 456 on the planarization layer 450 and at an edge of a pixel area P. A plurality of pixel regions P is defined on the substrate 402. The substrate 402 can be a glass substrate or a plastic substrate. In one embodiment of the present disclosure, the substrate 302 can have a three-layer structure comprising a first polyimide (Pl) layer, a second PI layer, and an inorganic intermediate layer between the first and second Pl layers. A first light-shielding structure 404 is arranged on the substrate 402, and a first buffer layer 406, which covers the first light-shielding structure 404, is arranged above the substrate 402. A first semiconductor layer 410, corresponding to the first light-shielding structure 404, is arranged on the first buffer layer 406. The first semiconductor layer 410 can be made of a polysemous semiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. If the first light-shielding structure 404 and the first buffer layer 406 are omitted, the first semiconductor layer 410 can be arranged directly on the substrate 402. In an exemplary embodiment of the present disclosure, the first semiconductor layer 410 can be formed from a polysemiconductor material, e.g., polycrystalline silicon. The first semiconductor layer 410 can have a first channel region 410a, a first source region 410b on one side of the first channel region 410a, and a first drain region 410c on the other side of the first channel region 410a. Impurities can be doped into the first source and drain regions 410b and 410c, respectively. A first gate isolation layer 412, covering the first semiconductor layer 410, is arranged above the first buffer layer 406. A first gate electrode 414, corresponding to the first channel region 410a of the first semiconductor layer 410, is arranged on the first gate insulating layer 412. Additionally, a first capacitor electrode 416, located at a distance from the first gate electrode 414, is arranged on the first gate insulating layer 412. A first intermediate insulating layer 418, covering the first gate electrode 414 and the first capacitor electrode 416, is arranged on the first gate insulating layer 412. A second capacitor electrode 430, corresponding to the first capacitor electrode 416, and a second light shielding structure 432, which is spaced apart from the second capacitor electrode 430, are arranged on the first intermediate insulating layer 418. A second intermediate insulating layer 434, covering the first second capacitor electrode 430 and the second light shielding structure 432, is arranged on the first intermediate insulating layer 418. A second semiconductor layer 436, corresponding to the second light-shielding structure 432, is arranged on the second intermediate insulating layer 434. The second semiconductor layer 436 can comprise a polysemiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. In an exemplary embodiment of the present disclosure, the second semiconductor layer 436 can be formed from an oxide semiconductor material, e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO). The second semiconductor layer 436 can have a second channel region 436a, a second source region 436b on one side of the second channel region 436a, and a second drain region 436c on the other side of the second channel region 436a. Impurities can be doped into the second source and drain regions 436b and 436c, respectively. A second gate isolation layer 438, covering the second semiconductor layer 436, is arranged above the second interlayer isolation layer 434. A second gate electrode 440, corresponding to the second channel region 436a of the second semiconductor layer 436, is arranged on the second gate insulating layer 438. A third intermediate insulating layer 442, covering the second gate electrode 440, is arranged on the second gate insulating layer 438. A first source electrode 444a, a first drain electrode 444b, a second source electrode 446a and a second drain electrode 446b are arranged on the third interlayer insulating layer 442. The first source electrode 444a and the first drain electrode 444b are each connected to the first source region 410b and the first drain region 410c via contact holes through the third interlayer insulating layer 442, the second gate insulating layer 438, the second interlayer insulating layer 434, the first interlayer insulating layer 418, and the first gate insulating layer 412. The first source electrode 444a is connected to the first capacitor electrode 416 via a contact hole through the third interlayer insulating layer 442, the second gate insulating layer 438, the second interlayer insulating layer 434, and the first interlayer insulating layer 418. The second source electrode 446a and the second drain electrode 446b are each connected to the second source region 436b and the second drain region 436c via contact holes through the third interlayer insulating layer 442 and the second gate insulating layer 438. The second source electrode 446a is connected to the second capacitor electrode 430 via a contact hole through the third interlayer insulating layer 442, the second gate insulating layer 438, and the second interlayer insulating layer 434. The first semiconductor layer 410, the first gate electrode 414, the first source electrode 444a and the first drain electrode 444b form a first TFT T1, and the second semiconductor layer 436, the second gate electrode 440, the second source electrode 446a and the second drain electrode 446b form a second TFT T2. For example, the first TFT T1 can be a switching TFT and the second TFT T2 can be a driver TFT. The organic light emission display device of the present disclosure comprises the first and second TFTs T1 and T2. Both the first semiconductor layer 410 of the first TFT T1 and the second semiconductor layer 436 of the second TFT T2 can comprise a polysemiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 410 of the first TFT T1 and the second semiconductor layer 436 of the second TFT T2 can comprise the oxide semiconductor material. In an exemplary embodiment of the present disclosure, the first semiconductor layer 410 of the first TFT T1 can be formed from the polysemiconductor material, e.g., polycrystalline silicon, and the second semiconductor layer 436 of the second TFT T2 can be formed from the oxide semiconductor material. A planarization layer 450, covering the first source electrode and the first drain electrode 444a and 444b and the second source electrode and the second drain electrode 446a and 446b, is arranged on the third intermediate insulating layer 442. The planarization layer 450 can be formed from an organic insulating material, e.g., photoacrylic or BCB. The planarization layer 450 can have a first planarization layer 450a on the first source electrode and the first drain electrode 444a and 444b and the second source electrode and the second drain electrode 446a and 446b, a second planarization layer 450b on the first planarization layer 450a and a third planarization layer 450c on the second planarization layer 450b. A connecting electrode 448, corresponding to the second source electrode 446a, is arranged on the first planarization layer 450a. The connecting electrode 448 can be connected to the second source electrode 446a through a contact hole in the first planarization layer 450a. The second planarization layer 450b is arranged on top of the first planarization layer 450a to cover the connecting electrode 448, and the third planarization layer 450c is arranged on top of the second planarization layer 450b. The flatness of an anode 460a of the OLED D can be degraded by a step difference resulting from an electrode or a signal line beneath the anode 460a, potentially leading to a problem such as a reduction in the lifetime of the OLED D. However, in the organic light emission display device 400 of the present disclosure, the step difference can be compensated for by the third planarization layer 450c, thus preventing the above problem. In Fig. 7, the planarization layer 450 comprises the first to third planarization layers 450a, 450b, and 450c to form a three-layer structure. In one embodiment of the present disclosure, the connecting electrode 448 and the first planarization layer 450a can be omitted, so that the planarization layer 450 can have a two-layer structure. In another embodiment of the present disclosure, an additional planarization layer can be arranged, so that the planarization layer 450 can have four or more layers. The planarization layer 450 contains a scattering particle. For example, in the planarization layer 450, the scattering particle can be dispersed in an organic insulating material. In one embodiment of the present disclosure, at least one of the first to third planarization layers 450a, 450b and 450c can comprise the scattering particle. For example, the second planarization layer 450b can comprise a first scattering particle 452a and a second scattering particle 452b, and the third planarization layer 450c can comprise a third scattering particle 454a and a fourth scattering particle 454b. Each of the first to fourth scattering particles 452a, 452b, 454a and 454b can be formed from an inorganic material, e.g. silicon dioxide (SiO2), or an organic material, e.g. polyoxyethylene, polyoxyethylene glycol, polyoxypropylene alkyl ether, polyoxypropylene monoalkyl ether, polyoxypropylene alkyl, polyoxyethylene talgamine, polyoxyethylene oleylamine, polyoxyethylene sterylamine, polyoxyethylene laurylamine, polyoxyethylene sorbitan ester, polyoxyethylene octyl ether, polyoxyethylene glycerol ether, polyacrylic acid, polysulfonic acid, polyacrylamine, triethyleneamine, their copolymer or their blocked copolymer. The first scattering particle 452a has a first diameter (e.g., a size), and the second scattering particle 452b has a second diameter that is smaller than the first diameter. The third scattering particle 454a has a third diameter, and the fourth scattering particle 454b has a fourth diameter that is smaller than the third diameter. Each of the first and third scattering particles, 452a and 454a, can have a diameter in the range of 100 nm to 1000 nm, and each of the second and fourth scattering particles, 452b and 454b, can have a diameter in the range of 1 nm to 80 nm. For example, each of the first and third scattering particles, 452a and 454a, can have a diameter in the range of 300 nm to 700 nm, and each of the second and fourth scattering particles, 452b and 454b, can have a diameter in the range of 10 nm to 70 nm. The diameter of the first scattering particle, 452a, and the diameter of the third scattering particle, 454a, can be the same or different, and the diameter of the second scattering particle, 452b, and the diameter of the fourth scattering particle, 454b, can be the same or different. Mie scattering can occur through each of the first and third scattering particles 452a and 454a, and Rayleigh scattering can occur through each of the second and fourth scattering particles 452b and 454b. In the second planarization layer 450b, the quantity of the first scattering particle 452a and the quantity of the second scattering particle 452b can be equal or different. For example, in the second planarization layer 450b, the quantity of the first scattering particle 452a can be less than the quantity of the second scattering particle 452b. In one embodiment of the present disclosure, the ratio of the quantity of the first scattering particle 452a to the quantity of the second scattering particle 452b can be 1:2. In the third planarization layer 450c, the quantity of the third scattering particle 454a and the quantity of the fourth scattering particle 454b can be equal or different. For example, in the third planarization layer 450c, the quantity of the third scattering particle 454a can be less than the quantity of the fourth scattering particle 454b. In one embodiment of the present disclosure, the ratio of the quantity of the third scattering particle 454a to the quantity of the fourth scattering particle 454b can be 1:2. In Fig. 7, the first planarization layer 450a is formed by an organic insulating material without a scattering particle. Alternatively, the first planarization layer 450a can include a fifth and a sixth scattering particle, and the diameter of the fifth scattering particle can be larger than that of the sixth scattering particle. The fifth scattering particle can have a diameter equal to or substantially equal to that of at least one of the first and third scattering particles, and the sixth scattering particle can have a diameter equal to or substantially equal to that of at least one of the second and fourth scattering particles. For example, the fifth scattering particle can have a diameter in the range of 100 nm to 1000 nm, e.g., 300 nm to 700 nm, and the sixth scattering particle can have a diameter in the range of 1 nm to 80 nm, e.g., 10 nm to 70 nm.Accordingly, Mie scattering can occur due to the fifth scattering particle, and Rayleigh scattering can occur due to the sixth scattering particle. In Fig. 7, the second planarization layer 450b comprises the first and second scattering particles 452a and 452b of different sizes, and the third planarization layer 450c comprises the third and fourth scattering particles 454a and 454b of different sizes. In one embodiment of the present disclosure, the second planarization layer 450b comprises the first and second scattering particles 452a and 452b of different sizes, and the third planarization layer 450c comprises a scattering particle of the same or substantially the same size. In another embodiment of the present disclosure, the third planarization layer 450c comprises the third and fourth scattering particles 454a and 454b of different sizes, and the second planarization layer 450b comprises a scattering particle of the same or substantially the same size. A first electrode 460a is arranged on the second planarization layer 450b. The first electrode 460a corresponds to the connecting electrode 448 and is connected to the connecting electrode 448 by a contact hole in the second and third planarization layers 450b and 450c. For example, the first electrode 460a is formed separately in each pixel area P. The first electrode 460a can be an anode and can have a transparent conductive oxide (TCO) layer formed from a conductive material, e.g., a transparent conductive oxide material with a relatively high work function, and a reflective layer. For example, the transparent conductive oxide material can comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin-zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer can comprise at least one of silver (Ag), an alloy of Ag and palladium (Pd), Cu, In and Nd, and an aluminum-palladium-copper alloy (APC). For example, the first electrode 460a can have a double-layer structure of Ag / ITO or APC / ITO, or a triple-layer structure of ITO / Ag / ITO or ITO / APC / ITO. A pixel definition layer 456 is formed on the third planarization layer 450c at an edge of the pixel area. The pixel definition layer 456 covers an edge of the first electrode 460a and has an opening to expose the center of the first electrode 460a. The pixel definition layer 456 can have a light-absorbing property. The pixel definition layer 456 can be a black pixel definition layer or a gray pixel definition layer. The pixel definition layer 456 can contain a black particle, e.g., a light-absorbing particle, arranged in an organic material, e.g., a binder. For example, the organic material can be at least one of photoacrylic, benzocyclobutene, and polyimide, and the black particle can be at least one of carbon black, carbon nanotubes (CNTs), and graphene. The pixel definition layer 456 can have a first optical density (OD) of 1.0 or less. For example, the first OD can be in a range of 0.5 to 1.0. In the organic light emission display device, after the first electrode 460a is formed, the pixel definition layer 456, which covers an edge of the first electrode 460a, is formed by coating it with the organic material containing the black particle and performing a masking process. If the pixel definition layer has a relatively high OD (organic density), the amount of black particle in the organic material increases, while the amount of organic material decreases. As a result, the curing process on the organic material is incomplete, and a particle may remain on the first electrode 460a. In this case, a problem may occur with the driver voltage and the lifetime of the OLED D. In the organic light emission display device 400 of the present disclosure, the above problem can be prevented by reducing an amount in the pixel definition layer 456, so that the pixel definition layer 456 has a relatively low OD. If the pixel definition layer 456 has a relatively low optical density (OD), external light (e.g., ambient light) can pass through the pixel definition layer 456 and be reflected by an electrode and / or a signal line beneath the pixel definition layer 456, thus potentially increasing external light reflection. Additionally, the external light passing through the pixel definition layer 456 can strike the first semiconductor layer 410 of the first TFT T1 and / or the second semiconductor layer 436 of the second TFT T2, potentially causing leakage current. For example, if the external light strikes the first semiconductor layer 410 of the first TFT T1, which is made of a high-mobility oxide semiconductor material, the performance of the first TFT T1 can be significantly degraded by the leakage current. However, in the organic light emission display device 400 of the present disclosure, the second planarization layer 450b has the first and second scattering particles 452a and 452b, and the third planarization layer 450c has the third and fourth scattering particles 454a and 454b. Accordingly, the above problems of external light reflection and / or leakage current from the first and second TFTs T1 and T2 can be reduced, prevented, or minimized. Additionally, Mie scattering and Rayleigh scattering can occur due to the first scattering particle 452a and the second scattering particle 452b in the second planarization layer 450b, and Mie scattering and Rayleigh scattering can occur due to the third scattering particle 454a and the fourth scattering particle 454b in the third planarization layer 450c. As a result, the amount of light passing through the pixel definition layer 456 and directed towards the first and second TFTs T1 and T2 can be reduced or minimized, thus reducing, minimizing, or preventing the leakage current in the first and second TFTs T1 and T2 caused by external light. A first spacer 458a with a reverse tapered shape and a second spacer 458b with a tapered shape are arranged on the pixel definition layer 456. An organic light-emitting layer 460b, covering the first electrode 460a, the pixel definition layer 456, and the first and second spacers 458a and 458b, is arranged. The organic light-emitting layer 460b contacts the first electrode 460a in the opening of the pixel definition layer 456. Specifically, the organic light-emitting layer 460b can be formed to contact a top surface of the first electrode 460a, a side surface and a top surface of the pixel definition layer 456, a top surface of the first spacer 458a, and a side surface and a top surface of the second spacer 458b. For example, the organic light emission layer 460b can have an organic emission material layer (EML) comprising a host and a dopant. Additionally, the organic light emission layer 460b can further comprise at least one HIL, one HTL, one EBL, one HBL, one ETL, and one EIL to have a multilayer structure. A second electrode 460c is formed above the substrate 402, where the organic light-emitting layer 460b is formed. The second electrode 460c covers an entire area of ​​the display region. The second electrode 460c can be formed from at least one of ITO, IZO, Al, Ag, Cu, Pb, Magnesium (Mg), Mo, Ti, and their alloys, and can have a single-layer or multi-layer structure. The second electrode 460c can have a thin profile (low thickness) to provide light transmission (or semi-transmission) properties. The first electrode 460a, the organic light-emitting layer 460b, and the second electrode 460c form an organic light-emitting diode (OLED) D. The OLED D can emit red, green, and blue light in the red, green, and blue pixel areas, respectively. Alternatively, the OLED D can emit white light in the red, green, blue, and white pixel areas. In the organic light emission display device 400, light from the light emission layer 460b passes through the second electrode 460c and a color filter layer 482 to display an image. The organic light emission display device 400 of the present disclosure is, in fact, a top-emission display device. An encapsulation layer (or encapsulation film) 462 is formed on the second electrode 460c to prevent moisture from entering the organic light-emitting diode D. The encapsulation layer 462 can cover the entire substrate 402. The encapsulation layer 462 comprises a first inorganic insulating layer 462a, an organic insulating layer 462b, and a second inorganic insulating layer 462c, which are stacked sequentially. A second buffer layer 464 is arranged on top of the encapsulation layer 462 and over the entire surface of the substrate 402. Moisture and / or oxygen can be blocked by the second buffer layer 464. A multitude of bridge structures 466 are arranged on the second buffer layer 464, and a fourth intermediate layer insulation layer 468 is arranged on the bridge structure 466 and over an entire area of ​​the substrate 402. A sensor structure 470 is arranged on the fourth intermediate insulating layer 468. The sensor structure 470 can have a plurality of first sensor structures 470a spaced apart from one another and a plurality of second sensor structures 470b arranged between adjacent first sensor structures 470a. The first sensor structure 470a is connected to the bridge structure 466 by a contact hole in the fourth intermediate insulating layer 468. A first protective layer 472 is arranged over an entire area of ​​the substrate 402 to cover the first and second sensor structures 470a and 470b, and a third buffer layer 474 is arranged on the first protective layer 472 and over an entire area of ​​the substrate 402. A black matrix 480 is arranged on the third buffer layer 474. The black matrix 480 is positioned at an edge of the pixel area P and has an opening corresponding to the organic light-emitting diode D. The opening of the black matrix 480 corresponds to the opening of the pixel definition layer 456. The black matrix 480 has a second OD that is larger than the first OD of the pixel definition layer 456. The second OD of the black matrix 480 can be in a range of 0.8 or higher. For example, the second OD can be in a range of 0.8 to 1.8. The size (e.g., a flat surface) of the opening in the black matrix 480 can be larger than that of the opening in the pixel definition layer 456. If the opening of the black matrix 480 can be equal to or smaller than the opening of the pixel definition layer 456, the viewing angle of the organic light emission display device 400 can be reduced. The black matrix 480 has an aperture larger than that of the pixel definition layer 456, and the pixel definition layer 456 has a relatively low OD. Consequently, external light can pass through the aperture of the black matrix 480 and an edge of the pixel definition layer 456, potentially leading to problems of external light reflection and / or leakage current from the TFT. However, as described above, in the organic light emission display device 400 of the present disclosure, since the planarization layer 450 under the pixel definition layer 456 has the first to fourth scattering particles 452a, 452b, 454a and 454b, the problem of external light reflection and leakage current in the TFT T1 and T2, caused by the black matrix 480, which has an aperture larger than an aperture of the pixel definition layer 456, and the pixel definition layer 456, which has a relatively low OD, can be reduced, prevented or minimized. Additionally, Mie scattering and Rayleigh scattering can occur due to the first scattering particle 452a and the second scattering particle 452b in the second planarization layer 450b, and Mie scattering and Rayleigh scattering can occur due to the third scattering particle 454a and the fourth scattering particle 454b in the third planarization layer 450c. Accordingly, the amount of light reaching the TFTs T1 and T2 and the amount of light reaching the pixel definition layer 456 can be reduced or minimized, thus further reducing or preventing the degradation of display quality due to external light reflection and leakage current in the TFTs T1 and T2. A color filter layer 482, corresponding to the black matrix 480, is arranged on the third buffer layer 474. The color filter layer 482 can have a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area. Since the organic light emission display device 400 has the color filter layer 482, external light reflection can be reduced or minimized. Specifically, since the organic light emission display device 400 has the color filter layer 482 without a polarizing plate, external light reflection can be reduced by minimizing the decrease in luminance. A second protective layer 484 is arranged on the black matrix 480 and the color filter layer 482 and over an entire area of ​​the substrate 402. In the organic light emission display device 400 of the present disclosure, the pixel definition layer 456 has a relatively low OD, e.g. a relatively small amount of the black particle, so that a problem arising from a particle in a manufacturing process can be prevented. Furthermore, since the planarization layer 450 under the pixel definition layer 456 has the first to fourth scattering particles 452a, 452b, 454a and 454b, the problem of external light reflection and leakage current in the TFT T1 and T2 can be reduced, prevented or minimized. Since the organic light emission indicator device 400 has the color filter layer 482 without a polarizing plate, external light reflection can also be reduced by minimizing the decrease in luminance. Furthermore, Mie scattering and Rayleigh scattering can occur due to the first scattering particle 452a and the second scattering particle 452b in the second planarization layer 450b, and Mie scattering and Rayleigh scattering can occur due to the third scattering particle 454a and the fourth scattering particle 454b in the third planarization layer 450c. Accordingly, the amount of light reaching the TFT T1 and T2 and the amount of light reaching the pixel definition layer 456 can be reduced or minimized, thus further reducing or preventing the degradation of display quality due to external light reflection and leakage current in the TFT T1 and T2. Fig. 8 is a schematic perspective exploded view of a display module according to an embodiment of the present disclosure, Fig. 9 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure, and Fig. 10 is a schematic top view of a display module according to an embodiment of the present disclosure. Fig. 9 is a cross-sectional view along line EE' in Fig. 8. Referring to Figs. 8, 9 to 10, the display module 500 of the present disclosure can be a foldable display device module and can have a folding axis A1-A1' of the display module 500 along a second direction DR2. A first direction DR1 can be perpendicular to the second direction DR2, and a third direction DR3 can be perpendicular to the first and second directions DR1 and DR2. An upper frame TF is arranged on the uppermost section of the display module 500. With respect to the folding axis A1, the upper frame TF comprises the first upper frame TF1, which is arranged on one side, and the second upper frame TF2, which is arranged on the other side. The upper frame TF can be arranged to cover an edge of a display device 510. The upper frame TF can protect the display device 510 from an external impact. The upper frame TF can form a bezel of the display device 510. A cover layer CG can be arranged below the upper frame TF. The cover layer CG can be arranged above the display device 510. The cover layer CG can be arranged above the display device 510 to protect elements located under the cover layer CG from the outside. An assembly is arranged beneath the top layer CG. The assembly comprises the display device 510 and a plate PLT. The display device 510 can have essentially the same structure as one of the display devices 100, 200, 300, and 400. The PLT plate can be arranged below the display device 510 and can have various plates for supporting the display device 510. For example, the plate can have a back plate for supporting the display device 510, an upper plate arranged below the back plate and made of stainless steel (SUS), a lower plate arranged below the upper plate and having a pattern formed on a folding section, a heat dissipation film for heat dissipation, and a middle plate for covering an uneven surface due to various elements of the hinge assembly. The lower plate can be made of SUS material. A slot pattern PTN can be formed in the plate PLT. The slot pattern PTN can be formed at a position corresponding to the folding area FA of the display device 510. The slot pattern PTN can be a slot-shaped etched section formed in the plate PLT. For example, the plate PLT can be made of a metal, e.g., a SUS material. In this case, damage to the plate PLT can occur during the folding and / or unfolding process. However, in the present application, the plate PLT has the slot pattern PTN, so the aforementioned damage to the plate PLT can be prevented. A center plate (MST) is located beneath the assembly. The center plate (MST) supports elements arranged above it. Additionally, the hinge assembly (520) and the cover frame (CF) are located beneath the center plate (MST), and their upper surfaces may be uneven. The center plate (MST) can flatten an uneven lower surface. The center plate (MST) can be made of a material such as plastic, polyimide, or metal to increase the rigidity of the display module (500). For example, the center plate (MST) can be made of aluminum or SUS, but is not limited to these materials. The intermediate plate MST can have a first intermediate plate section MSTH1, which is arranged in a first unfolding area NFA1, and a second intermediate plate section MSTH2, which is arranged in a second unfolding area NFA2. The hinge assembly 520 is located below the assembly. The hinge assembly 520 is located below the folding area FA. The hinge assembly 520 can have a shape that extends along the folding axis A1-A1'. The hinge assembly 520 can perform a folding movement in which one side and the other side rotate around the folding axis A1-A1'. The cover frame CF is arranged beneath the hinge assembly 520. A receiving groove, in which a section of the hinge assembly 520 can be arranged, can be formed in an upper surface of the cover frame CF. The cover frame CF comprises the first cover frame CF1, which is arranged on one side of the folding axis A1-A1', and the second cover frame CF2, which is arranged on the other side of the folding axis A1-A1'. The cover frame CF can form a housing for defining the side and rear surfaces of the display module 500. The cover frame CF can protect the display module 500 from external impact. The cover frame CF can be coupled to the hinge assembly 520. Folding and unfolding of the display module 500 can be achieved by rotating the cover frames CF1 and CF2. Coupling elements BM1, BM2, and BM3 for coupling the adjacent elements MST, PLT, PNL, and CG can also be arranged between the adjacent elements. In each of the deployment areas NFA1 and NFA2, the first coupling element BM1 can couple the intermediate plate sections MSTH1 and MSTH2 with the plate PLT, and the second coupling element BM2 can couple the plates PLT and PTN with the display device 510. The third coupling element BM3 can couple the display device 510 with the top layer CG. The PLT plate, the MST intermediate plate, and the coupled MST intermediate plate can be mounted on the CF1 and CF2 cover frames. The display device 510 can perform folding and unfolding operations by means of the hinge assembly 520, which is arranged on the CF1 and CF2 cover frames. The PLT plate and the MST center plate, which are coupled together, can be arranged on the CF1 and CF2 cover frames. The 500 display module can be folded and unfolded by the 520 hinge assembly, which is located in the CF1 and CF2 cover frames. The display device 510 can have a display area DA and a non-display area NDA outside the display area DA. The non-display area NDA can surround the display area DA. A plurality of pixel areas P1, P2, and P3 are arranged within the display area DA. The display device 510 can have a folding area FA and a first unfolding area NFA1 on one side of the folding area FA and a second unfolding area NFA2 on the other side of the folding area FA.

Claims

A display device (100, 200, 300, 400) comprising: a substrate (102) with a pixel area (P); a thin-film transistor (T1, T2) on the substrate (102) and in the pixel area (P); a planarization layer (150, 250, 350, 450) covering the thin-film transistor (T1, T2); a light-emitting diode (D) on the planarization layer (150, 250, 350, 450) and in the pixel area (P); and a pixel definition layer (156, 256, 356, 456) at an edge of the pixel area (P), wherein the pixel definition layer (156, 256, 356, 456) has a light absorption property and the planarization layer (150, 250, 350, 450) has a scattering particle (152, 154; 252, 254; 352, 354; 452a, 452b, 454a, 454b). The display device (100, 200, 300) according to claim 1, wherein the planarization layer (150, 250, 350) comprises a first planarization layer (150b, 250b, 350b) and a second planarization layer (150c, 250c, 350c) on the first planarization layer (150b, 250b, 350b), and wherein the first planarization layer (150b, 250b, 350b) comprises a first scattering particle (152, 252, 352) and the second planarization layer (150c, 250c, 350c) comprises a second scattering particle (154, 254, 354). The display device (100) according to claim 2, wherein the first and the second scattering particles (152, 154) are of the same size. The display device (200, 300) according to claim 2, wherein the first and the second scattering particles (252, 254; 352, 354) have different sizes. The display device (200, 300) according to claim 2 or 4, wherein one of the first and second scattering particles (252, 254; 352, 354) has a diameter in a range of 1 nm to 80 nm and the other of the first and second scattering particles (252, 254; 352, 354) has a diameter in a range of 100 nm to 1000 nm. The display device (200) according to claim 2 or 4, wherein the planarization layer (250) further comprises a third planarization layer (250a) below the first planarization layer (250b), wherein the third planarization layer (250a) comprises a third scattering particle and wherein a size of each of the second and the third scattering particle (250c) is larger than a size of the first scattering particle (250b). The display device (300) according to claim 2 or 4, wherein the planarization layer (350) further comprises a third planarization layer (350a) below the first planarization layer (350b), wherein the third planarization layer (350a) comprises a third scattering particle and wherein a size of each of the second and the third scattering particle (350c) is smaller than a size of the first scattering particle (350b). The display device (400) according to claim 1, wherein the planarization layer (450) comprises a first planarization layer (450b) and a second planarization layer (450c) on the first planarization layer (450b), wherein the first planarization layer (450b) comprises a first scattering particle (452a) and a second scattering particle (452b), and the second planarization layer (450c) comprises a third scattering particle (454a) and a fourth scattering particle (454b), wherein the size of the first scattering particle (452a) is larger than the size of the second scattering particle (452b), and the size of the third scattering particle (454a) is larger than the size of the fourth scattering particle (454b). The display device (400) according to claim 8, wherein each of the first and third scattering particles (452a, 454a) has a diameter in the range of 100 nm to 1000 nm and each of the second and fourth scattering particles (452b, 454b) has a diameter in the range of 1 nm to 80 nm. The display device (200, 300, 400) according to claim 1, wherein the scattering particle (252, 254; 352, 354; 452a, 452b, 454a, 454b) comprises a first scattering particle (254, 352, 452a, 454a) with a diameter in a range of 100 nm to 1000 nm and a second scattering particle (252, 354, 452b, 454b) with a diameter in a range of 1 nm to 80 nm. The display device (200, 300, 400) according to claim 10, wherein Rayleigh scattering occurs through the first scattering particle (254, 352, 452a, 454a) and Mie scattering occurs through the second scattering particle (252, 354, 452b, 454b). The display device (100, 200, 300, 400) according to any one of claims 1 to 11, wherein the thin-film transistor (T1, T2) has a semiconductor layer (110, 136; 210, 236; 310, 336; 410, 436) comprising an oxide semiconductor material. The display device (100, 200, 300, 400) according to any one of claims 1 to 11, wherein the thin-film transistor (T1, T2) comprises a first thin-film transistor (T1) having a first semiconductor layer (110, 210, 310, 410) and a second thin-film transistor (T2) having a second semiconductor layer (136, 236, 336, 436), and wherein at least one of the first and second semiconductor layers (110, 136; 210, 236; 310, 336; 410, 436) comprises an oxide semiconductor material. The display device according to any one of claims 1 to 11, wherein the thin-film transistor (T1, T2) comprises a first thin-film transistor (T1) having a first semiconductor layer (110, 210, 310, 410) and a second thin-film transistor (T2) having a second semiconductor layer (136, 236, 336, 436), and wherein one of the first and second semiconductor layers (110, 136; 210, 236; 310, 336; 410, 436) comprises an oxide semiconductor material and the other of the first and second semiconductor layers (110, 136; 210, 236; 310, 336; 410, 436) comprises polycrystalline silicon. The display device (100, 200, 300, 400) according to claim 14, wherein the second semiconductor layer (136, 236, 336, 436) comprises the oxide semiconductor material and the second thin-film transistor (T2) is a driver thin-film transistor connected to the light-emitting diode (D). The display device (100, 200, 300, 400) according to any one of claims 1 to 15, wherein the pixel definition layer (156, 256, 356, 456) is a black pixel definition layer or a grey pixel definition layer. The display device (100, 200, 300, 400) according to any one of claims 1 to 16, further comprising: an encapsulation layer (162, 262, 362, 462) covering the light-emitting diode (D) and the pixel definition layer (156, 256, 356, 456); a color filter layer (182, 282, 382, ​​482) arranged on the encapsulation layer (162, 262, 362, 462) and corresponding to the light-emitting diode (D); and a black matrix (180, 280, 380, 480) arranged on the encapsulation layer (162, 262, 362, 462) and corresponding to the pixel definition layer (156, 256, 356, 456). The display device (100, 200, 300, 400) according to claim 17, wherein the black matrix (180, 280, 380, 480) has a first optical density and the pixel definition layer (156, 256, 356, 456) has a second optical density, and wherein the second optical density is less than the first optical density. The display device (100, 200, 300, 400) according to claim 18, wherein the first optical density is in a range of 0.5 to 1.0 and the second optical density is in a range of 0.8 to 1.

8. The display device (100, 200, 300, 400) according to one of claims 17 to 19, wherein the pixel definition layer (156, 256, 356, 456) has a first opening corresponding to the light-emitting diode (D), and the black matrix (180, 280, 380, 480) has a second opening corresponding to the light-emitting diode (D), and wherein the size of the second opening is larger than the size of the first opening.

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