DISPLAY DEVICE

Abstract

A display device (1) according to an embodiment of the present disclosure comprises a substrate (101) on which a first sub-pixel (SP1), a second sub-pixel (SP2) and a third sub-pixel (SP3) are arranged, a first circuit line (CL1) arranged on the substrate (101), a thin-film transistor (120, 130) arranged between the substrate (101) and the first circuit line (CL1), a first protective layer (111) arranged on the first circuit line (CL1) and the thin-film transistor (120, 130), a second circuit line (CL2) arranged on the first protective layer (111), a second protective layer (112) arranged on the second circuit line (CL2), and a first anode electrode (ANO1) of the first sub-pixel (SP1) arranged on the second protective layer (112), wherein the first protective layer (111) in an area,in which the first protective layer (111) overlaps the first anode electrode (ANO1) and has different thicknesses.

Description

Background of the invention; Field of the invention

[0001] The present description refers to a display device. Description of the related technique

[0002] With the development of the information society, the demands on display devices for showing images are increasing, and numerous types of display devices are used, such as liquid crystal display devices (LCD devices) and display devices with organic light-emitting diodes (OLED displays).

[0003] Among display devices, the OLED display, being the self-illuminating type, has the advantage of a wider viewing angle and a higher contrast ratio. It can also be lighter and thinner, and consumes less energy than LCDs because it does not require a separate backlight. Furthermore, the OLED display can operate at low voltage, has a fast response time, and is particularly inexpensive to manufacture. Summary of the invention

[0004] The present description concerns the provision of a display device which makes it possible to improve the flatness of an anode electrode.

[0005] The present description also relates to the provision of a display device in which it is possible to realize the shape of a convex anode electrode uniformly.

[0006] The present description also aims to provide a display device in which it is possible to improve the color viewing angle properties.

[0007] The objectives of this description are not limited to those described above, and further technical objectives can be derived from the following embodiments. Numerous embodiments of this description provide display devices according to the independent claims. Further embodiments are described in the dependent claims.

[0008] According to one embodiment of the present description, a display device is provided which has a substrate on which a first sub-pixel, a second sub-pixel and a third sub-pixel are arranged, a first circuit line which is arranged on the substrate, a thin-film transistor which is arranged between the substrate and the first circuit line, a first protective layer which is arranged on the first circuit line and the thin-film transistor, a second circuit line which is arranged on the first protective layer, a second protective layer which is arranged on a second circuit line, and a first anode electrode of the first sub-pixel which is arranged on the second protective layer, wherein the first protective layer has different thicknesses in a region in which the first protective layer overlaps the first anode electrode.

[0009] According to a further embodiment of the present description, a display device is provided which has a substrate on which a first sub-pixel, a second sub-pixel and a third sub-pixel are arranged, a first circuit line which is arranged on the substrate, a thin-film transistor which is arranged between the substrate and the first circuit line, a first protective layer which is arranged on the first circuit line and the thin-film transistor, a second protective layer which is arranged on the first protective layer, a second protective layer which is arranged on a second circuit line, a first anode electrode of the first sub-pixel which is arranged on the second protective layer, and a second anode electrode of the second sub-pixel which is arranged on the second protective layer.wherein in an area where the first protective layer overlaps the second anode electrode, the first protective layer has a groove recessed in one thickness direction and the second circuit line is arranged in the groove.

[0010] Details of other embodiments are included in the detailed description and the accompanying drawings.

[0011] According to the embodiments described in the present description, it is possible to improve the flatness of the anode electrode.

[0012] According to the embodiments described in the present text, it is possible to realize the shape of the convex anode electrode uniformly.

[0013] According to the embodiments described above, it is possible to improve the color viewing angle properties.

[0014] According to the embodiments described above, it is possible to improve the color viewing angle characteristics, thereby enabling low-power operation of the display device and reducing energy consumption.

[0015] However, the effects obtainable with the present description are not limited to those described above, and further effects not mentioned will be clearly understandable to those skilled in the art to which the present description refers, based on the following description. Brief description of the drawings Fig. Figure 1 is a schematic representation which depicts a configuration of a display device according to embodiments of the present disclosure. Fig. Figure 2 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure. Fig. Figure 3 shows a flat surface structure of a display panel according to one embodiment. Fig. 4 is a cross-sectional view along line AA' in Fig. 3. Fig. Figure 5 is a cross-sectional view along line BB' in Fig. 3. Fig. Figure 6 is a specific cross-sectional view of a light-emitting part of Fig. 4. Fig. Figure 7 is a specific cross-sectional view of a light-emitting part according to a modified example. Fig. Figure 8 is a cross-sectional view of a contact part according to Fig. 4. Fig. Figure 9 is a cross-sectional view of a sub-pixel according to another embodiment. Fig. Figure 10 is a cross-sectional view of a sub-pixel according to another embodiment. Detailed description of the invention

[0016] The following are descriptions of embodiments with reference to the accompanying drawings. When a first component (or area, layer, section, etc.) is described as being "on," "connected to," or "coupled with" a second component, this means that the first component may be directly connected / coupled to the second component, or that a third component may be positioned between them.

[0017] The same reference numerals denote identical components. Furthermore, the thicknesses, proportions, and dimensions of components are exaggerated in the drawings for the effective description of the technical content. The term "and / or" encompasses all combinations of one or more elements that can be defined by the listed configurations.

[0018] Terms such as "first" and "second" can be used to describe numerous components, but the components are not limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, the second component may also be referred to as the first component, without altering the scope of embodiment. The singular includes the plural unless the context clearly indicates otherwise.

[0019] Terms such as "below," "on a lower side," "above," and "on an upper side" are used to describe the relationship between the components depicted in the drawings. These terms are relative concepts and are described in relation to the directions indicated in the drawings.

[0020] It is understood that terms such as "exhibits" or "has" serve to indicate the presence of features, numbers, steps, processes, components, parts or a combination thereof described in the description, and do not preclude the presence or possibility of adding one or more further features, numbers, steps, processes, components, parts or combinations thereof.

[0021] Fig. Figure 1 is a schematic view representing a configuration of a display device according to embodiments of the present disclosure.

[0022] With reference to Fig. 1. A display device 1 according to embodiments of the present disclosure may comprise a display panel 100 for displaying a video, an image, etc., a gate control circuit 200, a data control circuit 300, a control device 400, etc. for controlling the display panel 100.

[0023] A plurality of sub-pixels SP can be arranged on the display panel 100. The sub-pixels SP can be arranged repeatedly in a first direction DR1 and a second direction DR2.

[0024] In embodiments, the first direction DR1 and the second direction DR2 can refer to different and intersecting directions. For example, the first direction DR1 and the second direction DR2 can refer to directions that intersect vertically in a top view. Fig. 1. The first direction DR1 can refer to a left-right direction in a top view, and the second direction DR2 can refer to a vertical direction in a top view. However, the directions described in the embodiments are to be understood as relative directions, and the embodiments are not limited to the directions described.

[0025] On the display panel 100, a plurality of gate lines GL and a plurality of data lines DL are arranged, and the sub-pixel is arranged in an area which is defined by the intersection of the gate line GL and the data lines DL.

[0026] The gate drive circuit 200 is controlled by the control unit 400 and sequentially outputs sampling signals to the majority of gate lines GL, which are arranged on the display panel 100, in order to control the drive timing of the majority of sub-pixels SP.

[0027] In some cases, the gate drive circuit 200 can output a sampling signal for controlling the drive timing of the sub-pixel SP and a light emission control signal for controlling the light emission timing of the sub-pixel SP. In this case, the circuits for outputting the sampling signal and for outputting the light emission control signal can be implemented as separate circuits or as a single circuit.

[0028] The gate control circuit 200 can include one or more integrated gate driver circuits GDIC and can be arranged on one side or on both sides of the display panel 100, depending on the control method.

[0029] Each integrated gate driver circuit (GDIC) can be connected to a bonding pad of the display panel 100 by an automatic tape bonding (TAB) process, a chip-on-glass (COG) process, or a chip-on-polyimide (COP) process, or it can be implemented as a gate-in-panel (GIP) type and mounted directly on the display panel 100, and in some cases, integrally on the display panel 100. Additionally, each integrated gate driver circuit (GDIC) can be implemented by a chip-on-film (COF) process, mounted on a film bonded to the display panel 100.

[0030] The data control circuit 300 receives image data from the control unit 400 and converts the image data into an analog data voltage. Furthermore, the data control circuit 300 outputs the data voltage to each data line DL according to the timing with which the sampling signal is applied via the gate line GL, so that each sub-pixel SP has a brightness according to the image data.

[0031] The data control circuit 300 can have one or more integrated source driver circuits SDIC.

[0032] Each integrated source driver circuit (SDIC) can include a shift register, a latch circuit, a digital-to-analog converter (DAC), a buffer memory, etc.

[0033] Each SDIC integrated source driver circuit can be connected to a connection pad of the display panel 100 by a TAB method, a COG method, or a COP method, or it can be located directly on the display panel 100, and in some cases, be integrally located on the display panel 100. Additionally, each SDIC integrated source driver circuit can be implemented by a COF method, in which case each SDIC integrated source driver circuit can be mounted on the film connected to the display panel 100 and electrically connected to the display panel 100 via traces on the film.

[0034] The control unit 400 supplies numerous control signals to the gate control circuit 200 and the data control circuit 300 and controls the operation of the gate control circuit 200 and the data control circuit 300.

[0035] The control unit 400 can be mounted on a printed circuit board, a flexible circuit board, etc., and can be electrically connected to the gate control circuit 200 and the data control circuit 300 via the printed circuit board, the flexible circuit board, etc.

[0036] The control unit 400 controls the gate drive circuit 200 to output the sampling signal according to the timing implemented in each frame, converts the image data received from outside according to a data signal format used in the data drive circuit 300 and outputs the converted image data to the data drive circuit 300.

[0037] The control unit 400 receives numerous timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data release signal (DE), a clock signal (CLK), etc., along with the image data from an external source (e.g., a host system).

[0038] The control unit 400 can generate numerous control signals using numerous externally received timing signals and output the generated control signals to the gate control circuit 200 and the data control circuit 300.

[0039] For example, to control the gate control circuit 200, the control unit 400 outputs numerous gate control signals GCS, which include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc.

[0040] The gate start pulse (GSP) controls the start-up time of one or more integrated gate driver circuits (GDICs), which together form the gate drive circuit 200. The gate shift clock (GSC) is a clock signal that is input to the one or more integrated gate driver circuits (GDICs) and controls the switching timing of the sampled signal. The gate output enable signal (GOE) provides the timing information to the one or more integrated gate driver circuits (GDICs).

[0041] To control the data control circuit 300, the control unit 400 also outputs numerous data control signals DCS, which include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), etc.

[0042] Here, the source start pulse (SSP) controls the data sampling timing of one or more integrated source driver circuits (SDICs), which together form the data control circuit 300. The source sampling clock (SSC) is a clock signal used to control the data sampling timing in each integrated source driver circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data control circuit 300.

[0043] The display device 1 may further include an integrated power management circuit (not shown) to supply numerous voltages or currents to the display panel 100, the gate drive circuit 200, the data drive circuit 300, etc., or to control numerous voltages or currents being supplied.

[0044] Each sub-pixel SP is defined by the intersection of the gate line GL and the data line DL, and a liquid crystal or light-emitting element EL can be arranged according to the type of display device 1.

[0045] Fig. Figure 2 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure.

[0046] With reference to the Fig. 1 and Fig. 2. According to the embodiment of the present disclosure, the display device 1 can have a plurality of sub-pixels SP. Each of the sub-pixels SP can have a plurality of thin-film transistors. The plurality of thin-film transistors can have a driver transistor and a switching transistor.

[0047] The embodiments described herein are not limited to the following, but the switching transistors are provided as a plurality of switching transistors, and at least one of the plurality of switching transistors can be configured as an oxide semiconductor transistor. Furthermore, the driver transistor can be configured as a low-temperature polycrystalline silicon transistor (LTPS transistor). However, the embodiments described herein are not limited to this, and a multiple-type thin-film transistor can be configured in numerous ways. Moreover, a pixel circuit in the display device 1 may not include the multiple-type thin-film transistor, but rather a single-type thin-film transistor.

[0048] The in Fig. 2 The pixel circuit shown is a pixel circuit arranged in an nth row, consisting of a plurality of pixel circuits arranged in matrix form on the display panel 100.

[0049] The pixel circuit according to the embodiment consists of eight transistors and a capacitor. A first transistor T1, a second transistor T2, and a fifth transistor T5 can be designed as oxide semiconductor transistors, which use an oxide semiconductor material as an active layer.

[0050] Most switching transistors can have a first to seventh transistor, T1 to T7. The first to seventh transistors, T1 to T7, can receive sampling signals and a light emission control signal from the gate lines of the same row.

[0051] For example, in the Fig. In the pixel circuit shown in Figure 2, which is arranged in the nth row, the first to seventh transistors T1 to T7 receive sampling signals SC1[n], SC2[n], SC3[n] and SC4[n] and a light emission control signal EM[n] from the gate lines of the nth row.

[0052] The control transistor DT supplies a control current to the light-emitting element EL. The control transistor DT has a first electrode connected to a first node N1, a gate electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0053] The first transistor T1 has a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to a first sampling signal SC1[n]. The first transistor T1 is switched on when the first sampling signal SC1[n] is high and electrically connects the second node N2 to the third node N3.

[0054] A second transistor T2 has a first electrode connected to the first node N1, a second electrode connected to a data voltage VDATA, and a gate electrode connected to a second sampling signal SC2[n]. The second transistor T2 is switched on when the second sampling signal SC2[n] is high and supplies the data voltage VDATA to the first node N1.

[0055] This means that the second sampling signal SC2[n], which differs from the first sampling signal SC1[n], which is applied to the gate electrode of the first transistor T1, can be applied to the gate electrode of the second transistor T2.

[0056] A third transistor T3 has a first electrode connected to a high-potential supply voltage VDD, a second electrode connected to the first node N1, and a gate electrode connected to the light emission control signal EM[n]. The third transistor T3 is switched on when the light emission control signal EM[n] is low and supplies the high-potential supply voltage VDD to the first node N1.

[0057] A fourth transistor T4 has a first electrode connected to the third node N3, a second electrode connected to a fourth node N4, and a gate electrode connected to the light emission control signal EM[n]. The fourth transistor T4 is switched on when the light emission control signal EM[n] is low, electrically connecting the third node N3 to the fourth node N4.

[0058] A fifth transistor, T5, has a first electrode connected to the first node N2, a second electrode connected to an initialization voltage VINI, and a gate electrode connected to a third sampling signal SC3[n]. The fifth transistor, T5, is switched on when the third sampling signal SC3[n] is high and supplies the initialization voltage VINI to the second node N2.

[0059] This means that a third sampling signal SC3[n], which differs from the first sampling signal SC1[n] applied to the gate electrode of the first transistor T1, can be applied to the gate electrode of the fifth transistor T5.

[0060] A sixth transistor T6 has a first electrode connected to an anode reset voltage VAR, a second electrode connected to the fourth node N4, and a gate electrode connected to a fourth sampling signal SC4[n]. The sixth transistor T6 is switched on when the fourth sampling signal SC4[n] is low and supplies the anode reset voltage VAR to the fourth node N4.

[0061] The seventh transistor T7 has a first electrode connected to a bias voltage VOBS, a second electrode connected to the first node N1, and a gate electrode connected to the fourth sampling signal SC4[n]. A seventh transistor T7 is switched on when the fourth sampling signal SC4[n] is low and supplies the bias voltage VOBS to the first node N1.

[0062] The light-emitting element EL has one anode electrode connected to the fourth node N4 and another anode electrode connected to a low-potential supply voltage VSS. The light-emitting element EL receives a drive current from the drive transistor DT and emits light.

[0063] A storage capacitor CST is connected between a high-potential supply voltage source (VDD) and the second node N2. The storage capacitor CST maintains the data voltage signal VDATA in a pixel.

[0064] Fig. Figure 3 shows a flat surface of a display panel according to one embodiment. Fig. Figure 4 is a cross-sectional view along line AA' in Fig. 3. Fig. Figure 5 is a cross-sectional view along line BB' in Fig. 3.

[0065] With reference to the Fig. 3, Fig. 4 to Fig. The display panel 100 can have a plurality of sub-pixels SP (SP1, SP2, and SP3). The plurality of sub-pixels SP can consist of a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0066] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can form a pixel PX, and the display panel 100 can have a plurality of pixels PX. The plurality of pixels PX can be arranged repeatedly in the first direction DR1 and the second direction DR2.

[0067] The first sub-pixel SP1 and the third sub-pixel SP3 can be arranged alternately in the second direction DR2. The second sub-pixel SP2 can be arranged in a direction between the first direction DR1 and the second direction DR2 of the first sub-pixel SP1 and the third sub-pixel SP3. The second sub-pixel SP2 can be arranged repeatedly in the second direction DR2.

[0068] The majority of sub-pixels can have a red sub-pixel (red SP) (or the first sub-pixel SP1) which emits red light, a blue sub-pixel (blue SP) (or the second sub-pixel SP2) which emits blue light, and a green sub-pixel (green SP) (or the third sub-pixel SP3) which emits green light.

[0069] In Fig. 3. The flat surface shapes of the plurality of sub-pixels SP1, SP2 and SP3 are shown as circles, but the embodiments of the present description are not limited thereto, and the flat surface shapes of the plurality of sub-pixels SP1, SP2 and SP3 can be manifold, for example as a polygon, for example as a quadrilateral, etc., or an oval, etc.

[0070] Each of the sub-pixels SP1, SP2, and SP3 can contain a light-emitting area EA. The light-emitting area EA can contain multiple light-emitting areas EA1, EA2, and EA3. The light-emitting areas EA1, EA2, and EA3 can each be located within the sub-pixels SP1, SP2, and SP3, respectively. This means that the first sub-pixel SP1 can contain a first light-emitting area EA1, the second sub-pixel SP2 can contain a second light-emitting area EA2, and the third sub-pixel SP3 can contain a third light-emitting area EA3.

[0071] A pixel of the display panel 100 can have a plurality of sub-pixels SP1, SP2, and SP3. The first sub-pixel SP1 can be red, the second sub-pixel SP2 can be blue, and the third sub-pixel SP3 can be green; however, the embodiments described herein are not limited to these. In some embodiments, the pixel can further have a fourth sub-pixel, and the fourth sub-pixel can be white; however, the embodiments described herein are not limited to these.

[0072] The display panel 100 can have a first circuit line CL1, extending in the first direction DR1, and a second circuit line CL2, extending in the second direction DR2. The pixel PX and the sub-pixels SP1, SP2, and SP3 can be arranged in an area where the first circuit line CL1 and the second circuit line CL2 intersect.

[0073] The first circuit line CL1 can be arranged under and covered by a first protective layer 111. The first circuit line CL1 can also be arranged between the first protective layer 111 and a sixth insulating layer 109.

[0074] The first circuit line CL1 can include an 11th circuit line CL11, a 12th circuit line CL12, a 13th circuit line CL13, a 14th circuit line CL14, a 15th circuit line CL15, a 16th circuit line CL16, a 17th circuit line CL17, an 18th circuit line CL18, and a 19th circuit line CL19. Circuit lines CL11 to CL19 can be arranged alternately and repeatedly in the second direction DR2.

[0075] The first circuit line CL1 can be a first sampling line, which carries the first sampling signal SC1[n] from Fig. 2 transmits, a second sampling line which transmits the second sampling signal SC2[n], a third sampling line which transmits the third sampling signal SC3[n], a fourth sampling line which transmits the fourth sampling signal SC4[n], an anode reset line which transmits the anode reset voltage VAR, a bias line which transmits the bias voltage VOBS, an initialization line which transmits the initialization voltage VINI, a light emission control line which transmits the light emission control signal EM[n], etc.

[0076] This means that each of the 11th to 19th circuit lines CL11 to CL19 can be configured as one of the first sampling lines, which transmits the first sampling signal SC1[n], the second sampling line, which transmits the second sampling signal SC2[n], the third sampling line, which transmits the third sampling signal SC3[n], the fourth sampling line, which transmits the fourth sampling signal SC4[n], the anode reset line, which transmits the anode reset voltage VAR, the bias line, which transmits the bias voltage VOBS, the initialization line, which transmits the initialization voltage VINI, and the light emission control line, which transmits the light emission control signal EM[n].

[0077] The second circuit line CL2 can be located on a different layer than the first circuit line CL1. The second circuit line CL2 can be located between the first protective layer 111 and a second protective layer 112 and be covered by the second protective layer 112.

[0078] The second circuit line CL2 can include a 21st circuit line CL21, a 22nd circuit line CL22, a 23rd circuit line CL23, a 24th circuit line CL24, a 25th circuit line CL25, a 26th circuit line CL26, and a 27th circuit line CL27. Circuit lines CL21 to CL27 can be arranged alternately and repeatedly in the first direction DR1.

[0079] The second circuit line CL2 can be the data line, which transmits the data voltage VDATA, a high-potential current line, which transmits the high-potential supply voltage VDD, the anode reset line, which transmits the anode reset voltage VAR, a low-potential current line, which transmits the low-potential supply voltage VSS, etc. Fig. 2.

[0080] This means that each of the circuit lines CL22 to CL27, from the 21st to the 27th, is considered one of the data lines, which transmits the data voltage VDATA, the high-potential current line, which transmits the high-potential supply voltage VDD, the anode reset line, which transmits the anode reset voltage VAR, and the low-potential current line, which transmits the low-potential supply voltage VSS, in Fig. 2 can be trained.

[0081] The following is a cross-sectional structure of the first sub-pixel SP1. Fig. 4 described.

[0082] The display panel 100 can comprise the substrate 101, the first thin-film transistor 120, the second thin-film transistor 130, the storage capacitor 140, a light-emitting part 150, an encapsulation part 170, a contact part 180, a filter insulating layer 114, a black matrix BM, color filters 191, 192 and 193, and a planarization layer OC. The light-emitting part 150 can be configured as a light-emitting element EL. Fig. 2 correspond.

[0083] The display panel 100 can have at least one panel insulating layer and at least one contact insulating layer between the substrate 101 and the light-emitting part 150. The at least one panel insulating layer can comprise at least one buffer layer 102, a first insulating layer 103, a second insulating layer 104, a 3-1 insulating layer 105-1, a 3-2 insulating layer 105-2, a fourth insulating layer 106, a fifth insulating layer 108, a sixth insulating layer 109, a first protective layer 111, and a second protective layer 112; and the at least one contact insulating layer can comprise at least one contact buffer layer 181, a first contact insulating layer 183, and a second contact insulating layer 184.

[0084] The substrate 101 can comprise one or more plastic materials. For example, the substrate 101 can be a multi-layered substrate comprising a plurality of plastic materials, such as polyimide, etc. For example, the substrate 101 can have a first substrate section 101a and a second substrate section 101b, each comprising a plastic material, and a third substrate section 101c, comprising an inorganic insulating material between the first substrate section 101a and the second substrate section 101b; however, the embodiments described herein are not limited to these.

[0085] A buffer layer 102 can be arranged on the substrate 101. The buffer layer 102 can minimize or delay the diffusion of moisture or oxygen penetrating the substrate 101. The buffer layer 102 can be formed by at least one alternating layer of silicon nitride (SiN₂). x ) and silicon dioxide (SiO₂) x ) may be designed, but the embodiments described herein are not limited to this.

[0086] A first light-blocking layer 126 can be arranged on the buffer layer 102. The first light-blocking layer 126 can prevent light from penetrating a first semiconductor layer 123 of the first thin-film transistor 120. For example, the first semiconductor layer 123 can be arranged to overlap the first light-blocking layer 126. The first light-blocking layer 126 can be formed from a single layer or from multiple layers formed from molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments described herein are not limited to these.

[0087] The first insulating layer 103 can be arranged on the buffer layer 102 and the first light-blocking layer 126. The first insulating layer 103 can prevent a short circuit between a component of the first thin-film transistor 120 and the first light-blocking layer 126. The first insulating layer 103 can be made of the same material as the buffer layer 102, but the embodiments described here are not limited to this. For example, the first insulating layer 103 can be made of an inorganic insulating material, such as silicon nitride (SiN₂). x ) or silicon dioxide (SiO₂) x ), but the embodiments described herein are not limited to this.

[0088] The first thin-film transistor 120 can be arranged on the first insulating layer 103. The first thin-film transistor 120 can have a first source electrode 121, a first gate electrode 122, the first semiconductor layer 123, and a first drain electrode 124.

[0089] The first semiconductor layer 123 can be arranged on the first insulating layer 103. The first semiconductor layer 123 can comprise a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), and a silicon-based semiconductor material, such as amorphous silicon, polycrystalline silicon, etc., but the embodiments described herein are not limited to these. The first semiconductor layer 123 can have a channel region, a source region, and a drain region.

[0090] Since the polycrystalline semiconductor layer exhibits higher mobility than the amorphous semiconductor layer and the oxide semiconductor layer, its energy consumption can be lower and its reliability excellent. Accordingly, a driver transistor can be made from the polycrystalline semiconductor layer.

[0091] The second insulating layer 104 can be arranged on the first semiconductor layer 123. The second insulating layer 104 can be made of the same material as the first insulating layer 103 and can prevent a short circuit between the first semiconductor layer 123 and another component of the first thin-film transistor 120.

[0092] The first gate electrode 122 can be arranged on the second insulating layer 104. The first gate electrode 122 can be arranged on the second insulating layer 104 to overlap the channel region of the first semiconductor layer 123. The first gate electrode 122 can be formed from a single layer or from multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof, but the embodiments described herein are not limited to these. The first gate electrode 122 can be arranged together with a gate conductor.

[0093] The third insulating layers 105-1 and 105-2 can be arranged on the first gate electrode 122. The third insulating layers 105-1 and 105-2 can be formed by at least one alternating layer of silicon nitride (SiN₂). x ) and silicon dioxide (SiO₂) x) may be designed, the embodiments of which are not limited thereto. For example, the 3-1 insulating layer may be 105-1 silicon oxide (SiO₂). x ) and can exhibit the 3-2 insulating layer 105-2 silicon nitride (SiN x ) exhibit, but the embodiments described herein are not limited to them.

[0094] The first source electrode 121 and the first drain electrode 124 can be arranged on the third insulating layers 105-1 and 105-2.

[0095] The first source electrode 121 and the first drain electrode 124 can be electrically connected to the first semiconductor layer 123 via contact holes. The first source electrode 121 and the first drain electrode 124 can be made of a metallic material. For example, the first source electrode 121 and the first drain electrode 124 can be formed from a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments described herein are not limited to these.

[0096] The first source electrode 121 and the first drain electrode 124 can be arranged together with a data line. For example, the data line can be made of the same material as the first source electrode 121 and the first drain electrode 124 and be formed on the same layer as the first source electrode 121 and the first drain electrode 124, but the embodiments described here are not limited to this.

[0097] The storage capacitor 140 can be arranged at a distance from the first thin-film transistor 120. The storage capacitor 140 can have a first storage electrode 141 and a second storage electrode 142.

[0098] The first storage electrode 141 can be made of the same material as the first gate electrode 122 and arranged on the same layer as the first gate electrode 122, but the embodiments described herein are not limited to this.

[0099] The second storage electrode 142 can be arranged on the first storage electrode 141. The second storage electrode 142 can be arranged on the third insulating layers 105-1 and 105-2, and the third insulating layers 105-1 and 105-2 between the first storage electrode 141 and the second storage electrode 142 can be used as a dielectric to create capacitance. The second storage electrode 142 can be made of the same material as the first storage electrode 141, but the embodiments described here are not limited to this.

[0100] The second thin-film transistor 130 can be arranged such that it is spaced apart from the first thin-film transistor 120 and the storage capacitor 140. The second thin-film transistor 130 can have a second source electrode 131, a second gate electrode 132, a second semiconductor layer 133, and a second drain electrode 134.

[0101] A second light-blocking layer 136 can be arranged on the same layer as the second storage electrode 142.

[0102] The second light-blocking layer 136, similar to the first light-blocking layer 126, can prevent light from reaching the second semiconductor layer 133, thereby extending the lifetime of the second thin-film transistor 130. For example, the second semiconductor layer 133 can be arranged to overlap the second light-blocking layer 136.

[0103] The fourth insulating layer 106 can be arranged on the second light-blocking layer 136. The fourth insulating layer 106 can be made of the same material as the first insulating layer 103, the second insulating layer 104, or the third insulating layers 105-1 and 105-2, but the embodiments described herein are not limited to this.

[0104] The second semiconductor layer 133 can be arranged on the fourth insulating layer 106. The second semiconductor layer 133 can have a source region, a drain region, and a channel region between the source region and the drain region.

[0105] The second semiconductor layer 133 can comprise a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), and a silicon-based semiconductor material, such as amorphous silicon, polycrystalline silicon, etc., but the embodiments described herein are not limited thereto.

[0106] The fifth insulating layer 108 can be arranged on the second semiconductor layer 133. The fifth insulating layer 108 can be made of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2, or the fourth insulating layer 106, but the embodiments described herein are not limited to these.

[0107] The second gate electrode 132 can be arranged on the fifth insulating layer 108. The second gate electrode 132 can be made of the same material as the first gate electrode 122. For example, the second gate electrode 132 can be made of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof, the embodiments described herein being no longer limited to these.

[0108] The sixth insulating layer 109 can be arranged on the second gate electrode 132. The sixth insulating layer 109 can be made of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2, the fourth insulating layer 106, or the fifth insulating layer 108, but the embodiments described herein are not limited to this.

[0109] The first source electrode 121, the first drain electrode 124, the second source electrode 131, the second drain electrode 134 and the first circuit line CL1 can be arranged on the sixth insulating layer 109.

[0110] The second source electrode 131, the second drain electrode 134, and the first circuit line CL1 can be made of the same material as the first source electrode 121 and the first drain electrode 124 and arranged on the same layer as the first source electrode 121 and the first drain electrode 124, but the embodiments described herein are not limited to this. For example, the second source electrode 131, the second drain electrode 134, and the first circuit line CL1 can be a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments described herein are not limited to this. For example, the second source electrode 131 can be electrically connected to the second storage electrode 142.The second source electrode 131 can pass through the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 106 and can be electrically connected to the second storage electrode 142.

[0111] The first thin-film transistor 120 can be a drive transistor, and the second thin-film transistor 130 can be a switching transistor, but the embodiments of the present description are not limited thereto.

[0112] The first protective layer 111 can be arranged on the first source electrode 121, the first drain electrode 124, the second source electrode 131, the second drain electrode 134 and the first circuit line CL1.

[0113] The first protective layer 111 can planarize the upper sections of the first thin-film transistor 120 and the second thin-film transistor 130, thus protecting them. The first protective layer 111 can be made of an organic material. For example, the first protective layer 111 can be made of an organic material comprising an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but the embodiments described herein are not limited to these.

[0114] The first protective layer 111 can have a first overlap region OA1, in which the first protective layer 111 overlaps the first circuit line CL1 in one thickness direction (a third direction DR3), and a first non-overlap region NOA1, in which the first protective layer 111 does not overlap the first circuit line CL1. The thickness TH1 of the first protective layer 111 in the first overlap region OA1 can be less than the thickness TH2 of the first protective layer 111 in the first non-overlap region NOA1.

[0115] In an area where the first protective layer 111 overlaps a first anode electrode ANO1, the thickness TH1 of the first protective layer 111 in the first overlap area OA1 can be smaller than the thickness TH2 of the first protective layer 111 in the first non-overlap area NOA1.

[0116] Accordingly, the upper surface of the first protective layer 111 can be flat. Here, the upper surface of the first protective layer 111 can refer to a surface facing the second protective layer 112. Accordingly, the second protective layer 112 arranged on the first protective layer 111 can also generally be flat. Furthermore, the first anode electrode ANO1 arranged on the second protective layer 112 can also be flat, thereby improving the flatness of the first anode electrode ANO1 and suppressing or preventing defects in the display panel 100.

[0117] This means that the shape of the first anode electrode ANO1 can be more uniformly shaped to a desired form. Furthermore, it is also possible to increase the degree of freedom with regard to the design of the layout of the display panel 100.

[0118] By using a slit mask, a halftone mask, etc., a portion of the upper surface of the first protective layer 111, which is located in the first overlap area OA1, can be etched to form the flat upper surface of the first protective layer 111.

[0119] The second circuit line CL2 can be arranged on the first protective layer 111. The second circuit line can be a single layer or multiple layers, which may be formed, for example, from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, although the embodiments described herein are not limited to these.

[0120] The second protective layer 112 can be arranged on the second circuit line CL2. The second protective layer 112 can be made of the same material as the first protective layer 111, but the embodiments described here are not limited to this.

[0121] In some embodiments, a third protective layer may additionally be arranged on an upper surface of the second protective layer 112, but the embodiments of the present description are not limited to this.

[0122] Although not shown, an additional connecting electrode can be arranged between the first protective layer 111 and the second protective layer 112.

[0123] The connecting electrode can electrically connect the first thin-film transistor 120 to the light-emitting part 150. The connecting electrode can be made of the same material as the first source electrode 121 and the first drain electrode 124, but the embodiments described here are not limited to this.

[0124] The connecting electrode can be formed from a single layer or multiple layers made of molybdenum (Mo), aluminium (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but the embodiments described herein are not limited to such materials.

[0125] The light-emitting part 150 can be arranged on the second protective layer 112. The light-emitting part 150 can have a first electrode 151, an organic layer 152, and a second electrode 153. The embodiments described herein are not limited to these, but the first electrode 151 can serve as the anode and the second electrode 153 can serve as the cathode.

[0126] The first electrode 151 can be arranged on the second protective layer 112. The first electrode 151 can be electrically connected to the connecting electrode via a through-hole formed in the second protective layer 112 and electrically connected to the first thin-film transistor 120.

[0127] The first electrode 151 can be a reflective electrode that reflects light, but the embodiments described herein are not limited to this. The first electrode 151 can be a metallic material with a high reflectivity, such as a stacked structure (Ti / Al / Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO / Al / ITO) of aluminum (Al) and indium tin oxide (ITO), or an APC alloy, and can be formed from a single layer or multiple layers, but the embodiments described herein are not limited to this.

[0128] The first electrode 151 can have the first anode electrode ANO1, which is located in the first sub-pixel SP1, a second anode electrode ANO2, which is located in the second sub-pixel SP2, and a third anode electrode ANO3, which is located in the third sub-pixel SP3.

[0129] The organic layer 152 can be arranged on the first electrode 151. The organic layer 152 can have one or more light-emitting structures (or light-emitting elements or components) which are stacked on the first electrode 151 in the sequence or in reverse order of a hole transfer layer and an electron transfer layer.

[0130] For example, the hole transfer layer can comprise a hole transport layer, a hole injection layer, an electron blocking layer, a p-type charge generation layer, etc., but the embodiments described herein are not limited to these. Similarly, the electron transfer layer can comprise an electron transport layer, an electron injection layer, a hole blocking layer, an n-type charge generation layer, etc., but the embodiments described herein are not limited to these.

[0131] The organic layer 152 can be an organic light emission layer, an inorganic light emission layer, a quantum dot light emission layer, a micro light-emitting diode, a micro mini light-emitting diode, etc., but the scope of the present description is not limited to this.

[0132] For example, according to one embodiment of the present description, the organic layer 152 of the display panel 100 can have an organic light-emitting layer. The organic layer 152 can have a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The organic layer 152 can be a white light-emitting layer, but the embodiments of the present description are not limited to this. A specific structure of the organic layer 152 according to one embodiment is described below.

[0133] Fig. Figure 6 is a specific cross-sectional view of a light-emitting part of Fig. 4.

[0134] With reference to Fig. 6 the light-emitting part 150 can be arranged above the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3.

[0135] The thickness of the light-emitting part 150 in each sub-pixel SP1, SP2 or SP3 can be different, but the embodiments of the present description are not limited in this respect, and the thickness of the light-emitting part 150 in each sub-pixel SP1, SP2 or SP3 can be the same.

[0136] The organic layer 152 can have a first organic layer 152a, located in the first sub-pixel SP1, a second organic layer 152b, located in the second sub-pixel SP2, and a third organic layer 152c, located in the third sub-pixel SP3. The light-emitting layers EML1, EML2, and EML3 of the organic layers 152a, 152b, and 152c can be physically separated from each other, but the lower and upper layers of the light-emitting layers EML1, EML2, and EML3 can be integrally formed over the sub-pixels SP1, SP2, and SP3. The thickness of each light-emitting layer EML1, EML2, or EML3 can be different.For example, the thickness of a first light-emitting layer EML1 can be the largest, the thickness of a second light-emitting layer EML2 the second largest, and the thickness of the third light-emitting layer EML3 the smallest, but the embodiments of the present description are not limited thereto.

[0137] A hole injection layer (HIL) can be arranged on the first electrode 151. The hole injection layer (HIL) can be arranged between the first electrode 151 and the light emission layers EML1, EML2, and EML3. The hole injection layer (HIL) can be formed integrally over the sub-pixels SP1, SP2, and SP3. For example, the hole injection layer (HIL) can be formed from a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(Biphenyl-4-yl)-9,9-Dimethyl-N-(4-(9-Phenyl-9H-Carbazol-3-yl)Phenyl)-9H-Fluoren-2-Amine, etc., but the embodiments described herein are not limited to these.

[0138] A hole transport layer (HTL) can be arranged on the hole injection layer (HIL). The hole transport layer (HTL) can be arranged between the hole injection layer (HIL) and the light emission layers (EML1), (EML2), and (EML3). The hole transport layer (HTL) can be integral to the sub-pixels (SP1), (SP2), and (SP3).The hole transport layer (HTL) can consist of one or more materials selected from the group consisting of arylamine-based materials, such as NPB (N,N-naphthyl-N,N'-phenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), PPD, TTBND, FFD, p-dmDPS and TAPC; aromatic starburst amine-based materials, such as TCTA, PTDATA, TDAPB, TDBA, 4-a and TCTA; and spiro- and conductor-type materials, such as Spiro-TPD, Spiro-mTTB and Spiro-2, NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), s-TAD and MTDATA (4,4',4"-Tris(N-3-Methylphenyl-N-Phenylamino)-Triphenylamine), but the embodiments described herein are not limited to this.

[0139] The light emission layers EML1, EML2, and EML3 can be arranged on the hole transport layer HTL. The first light emission layer EML1 can be located in the first sub-pixel SP1, the second light emission layer EML2 can be located in the second sub-pixel SP2, and the third light emission layer EML3 can be located in the third sub-pixel SP3.

[0140] The thickness of each light-emitting layer EML1, EML2, or EML3 can vary. For example, the first light-emitting layer EML1 can have a thickness of 600 to 800 angstroms (10 -10 The second light-emitting layer EML2 can be formed with a thickness of 300 to 500 angstroms (10 -10 meter) and the third light-emitting layer EML3 can be formed with a thickness of 100 to 300 angstroms (10 -10 may be designed in meters), but the embodiments described herein are not limited to this.

[0141] Each of the first light emission layer EML1, the second light emission layer EML2 and the light emission layer EML3 can have a material which can emit light in the visible light range by receiving and combining holes and electrons.

[0142] A hole-blocking layer (HBL) can be placed on any light-emitting layer (EML1), EML2, or EML3. The hole-blocking layer (HBL) can be integrally arranged across the sub-pixels (SP1), SP2, and SP3.

[0143] An electron transport layer (ETL) can be arranged on the electron blocking layer (HBL). The electron transport layer (ETL) can be integrally arranged across the sub-pixels SP1, SP2, and SP3. The electron transport layer (ETL) can be formed from an anthracene derivative and lithium quinolate (Liq), or from one or more selected compounds from oxadiazole, triazole, phenanthroline, benzoxazole, benzthiazole, or benzimidazole (e.g., 2-[4-(9,10-Di-2-naphthalenyl-2-anthracenyl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described herein are not limited to these.

[0144] The second electrode 153 can be arranged on the electron transport layer ETL.

[0145] Fig. Figure 7 is a specific cross-sectional view of a light-emitting part according to a modified example.

[0146] With reference to the Fig. 6 and Fig. 7 an organic layer 152_1 can have a first organic layer 152a_1 which is located in the first sub-pixel SP1, a second organic layer 152b_1 which is located in the second sub-pixel SP2, and a third organic layer 152c_1 which is located in the third sub-pixel SP3.

[0147] The light-emitting layers of each organic layer 152a_1, 152b_1, or 152c_1 may be physically separated from one another, but the lower and upper layers of the light-emitting layers may be integrally formed over the sub-pixels SP1, SP2, and SP3. The thickness of each light-emitting layer may vary. For example, the thickness of the first light-emitting layer of the first sub-pixel may be the greatest, the thickness of the second light-emitting layer of the second sub-pixel may be the second greatest, and the thickness of the third light-emitting layer of the third sub-pixel may be the smallest, but the embodiments described herein are not limited to these variations. Furthermore, the light-emitting layers of each organic layer 152a_1, 152b_1, or 152c_1 may be configured as two or more light-emitting layers.

[0148] A hole injection layer (HIL) can be arranged on the first electrode 151. The hole injection layer (HIL) can be arranged between the first electrode 151 and the light emission layers EML1a, EML2a, and EML3a. The hole injection layer (HIL) can be formed integrally over the sub-pixels SP1, SP2, and SP3. For example, the hole injection layer (HIL) can be formed from a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(Biphenyl-4-yl)-9,9-Dimethyl-N-(4-(9-Phenyl-9H-Carbazol-3-yl)Phenyl)-9H-Fluoren-2-Amine, etc., but the embodiments described herein are not limited to these.

[0149] A first hole transport layer HTL1 can be arranged on the hole injection layer HIL. The first hole transport layer HTL1 can be arranged between the hole injection layer HIL and the light emission layers EML1a, EML2a, and EML3a. The first hole transport layer HTL1 can be integrally formed across the sub-pixels SP1, SP2, and SP3.The first hole transport layer HTL1 can consist of one or more materials selected from the group consisting of arylamine-based materials, such as NPB (N,N-naphthyl-N,N'-phenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), PPD, TTBND, FFD, p-dmDPS and TAPC; aromatic starburst amine-based materials, such as TCTA, PTDATA, TDAPB, TDBA, 4-a and TCTA; and spiro- and conductor-type materials, such as Spiro-TPD, Spiro-mTTB and Spiro-2, NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), s-TAD and MTDATA (4,4',4"-Tris(N-3-Methylphenyl-N-Phenylamino)-Triphenylamine), but the embodiments described herein are not limited to this.

[0150] The light-emitting layers EML1a, EML2a, and EML3a can be arranged on the first hole transport layer HTL1. A 1-1 light-emitting layer EML1a can be arranged in the first sub-pixel SP1, a 2-1 light-emitting layer EML2a can be arranged in the second sub-pixel SP2, and a 3-1 light-emitting layer EML3a can be arranged in the third sub-pixel SP3. Each of the light-emitting layers EML1a, EML2a, and EML3a can be connected to each of the light-emitting layers EML1, EML2, and EML3, respectively. Fig. 7 be identical.

[0151] The thickness of each light-emitting layer EML1a, EML2a, or EML3a can vary. For example, the 1-1 light-emitting layer EML1a can have a thickness of 600 to 800 angstroms (10 -10 The 2-1 light emission layer EML2a can be formed with a thickness of 300 to 500 angstroms (10 -10meters) and can be formed by the 3-1 light emission layer EML3a with a thickness of 100 to 300 angstroms (10 -10 may be designed in meters), but the embodiments described herein are not limited to this.

[0152] A first hole-blocking layer HBL1 can be arranged on any light-emitting layer EML1a, EML2a, or EML3a. The first hole-blocking layer HBL1 can be integrally formed across the sub-pixels SP1, SP2, and SP3.

[0153] A first electron transport layer ETL1 can be arranged on the first hole-blocking layer HBL1. The first electron transport layer ETL1 can be integrally formed over the sub-pixels SP1, SP2, and SP3. The first electron transport layer ETL1 can be formed from an anthracene derivative and lithium quinolate (Liq), or from one or more selected from oxadiazole, triazole, phenanthroline, benzoxazole, benzthiazole, or benzimidazole (e.g., 2-[4-(9,10-Di-2-naphthalenyl-2-anthracenyl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described herein are not limited to these.

[0154] A common charge layer CGL can be arranged on the first electron transport layer ETL1. The common charge layer CGL can be arranged between the first electron transport layer ETL1 and a second hole transport layer HTL2. The common charge layer CGL can comprise a conductive material, but the embodiments of the present disclosure are not limited thereto.

[0155] The second hole transport layer HTL2 can be arranged on the common charge layer CGL. The second hole transport layer HTL2 can be arranged between the hole blocking layer HBL and the light emission layers EML1b, EML2b, and EML3b. The second hole transport layer HTL2 can be integral to the sub-pixels SP1, SP2, and SP3. The material of the second hole transport layer HTL2 can be the same as the material of the first hole transport layer HTL1, but the embodiments described here are not limited to this.

[0156] The light-emitting layers EML1b, EML2b, and EML3b can be arranged on the second hole transport layer HTL2. A 1-2 light-emitting layer EML1b can be located in the first sub-pixel SP1, a 2-2 light-emitting layer EML2b can be located in the second sub-pixel SP2, and a 3-2 light-emitting layer EML3b can be located in the third sub-pixel SP3. Each of the light-emitting layers EML1b, EML2b, and EML3b can be identical to each of the respective light-emitting layers EML1a, EML2a, and EML3a.

[0157] The thickness of each light-emitting layer EML1b, EML2b, or EML3b can vary. For example, the EML1b light-emitting layer can have a thickness of 600 to 800 angstroms (10 -10 The 2-2 light emission layer EML2b can be formed with a thickness of 300 to 500 angstroms (10 -10meters) and can be formed by the 3-2 light emission layer EML3b with a thickness of 100 to 300 angstroms (10 -10 may be designed in meters), but the embodiments described herein are not limited to this.

[0158] A second hole-blocking layer HBL2 can be arranged on each light-emitting layer EML1b, EML2b, or EML3b. The second hole-blocking layer HBL2 can be integral to the sub-pixels SP1, SP2, and SP3.

[0159] A second electron transport layer ETL2 can be arranged on the second hole-blocking layer HBL2. The second electron transport layer ETL2 can be integrally formed over the sub-pixels SP1, SP2, and SP3. The second electron transport layer ETL2 can be formed from an anthracene derivative and lithium quinolate (Liq), or from one or more selected from oxadiazole, triazole, phenanthroline, benzoxazole, benzthiazole, or benzimidazole (e.g., 2-[4-(9,10-Di-2-naphthalenyl-2-anthracenyl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described herein are not limited to these.

[0160] The second electrode 153 can be arranged on the second electron transport layer ETL2.

[0161] Referring to Fig. 4. The second electrode 153 can be arranged on the organic layer 152. The second electrode 153 can be a transparent electrode that transmits light, but the embodiments described herein are not limited to this. For example, the second electrode 153 can comprise a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal that transmits visible light, but the embodiments described herein are not limited to this.

[0162] A wall 154 can be arranged such that it exposes the first electrode 151. The wall 154 can be arranged such that it defines the light-emitting area EA (EA1, EA2 and EA3 of the sub-pixels SP1, SP2 and SP3) and covers an edge section (or a perimeter) of the first electrode 151.

[0163] The non-light-emitting area (NEA) can be arranged around the light-emitting area (EA). The Wall 154 can be located within the non-light-emitting area (NEA).

[0164] The light-emitting area EA can comprise the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, each located within sub-pixels SP1, SP2, and SP3, respectively. The non-light-emitting area NEA can surround each light-emitting area EA1, EA2, or EA3. The non-light-emitting area NEA can correspond to the boundaries of adjacent sub-pixels SP1, SP2, and SP3.

[0165] Wall 154 can be formed from an organic material, such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, a photosensitive polymer, etc. However, the embodiments described herein are not limited to these, and Wall 154 can also be carbon black based. For example, Wall 154 can be formed from a material containing black pigment or from an organic material, such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, a photosensitive polymer, etc., but the embodiments described herein are not limited to these. If Wall 154 is formed from a material containing black pigment or black dye, Wall 154 can be an opaque wall.If the Wall 154 is made of a material containing black pigment or black dye, it is possible to block external light or reflected external light, thereby further increasing the luminance of the display device.

[0166] A RAS barrier can also be located on Wall 154. As in Fig. As shown in Figure 6, the barrier RAS can be arranged at all boundaries (the non-display areas NEA) between the sub-pixels SP1, SP2, and SP3, but the embodiments described herein are not limited to this. The barrier RAS can be arranged directly on an upper surface of the wall 154, but the embodiments described herein are not limited to this. The barrier RAS can serve to separate the organic layer 152 from the boundaries of adjacent sub-pixels SP1, SP2, and SP3. In some embodiments, the barrier can be omitted, and a recessed area in the thickness direction can be arranged in the wall 154.

[0167] A spacer 155 can further be arranged on the wall 154. The spacer 155 can be made of the same material as the wall 154, but the embodiments described herein are not limited to this. For example, the spacer 155 can be a transparent wall, but this is not limited, and the spacer 155 can be made of the same material as the wall 154. For example, the spacer 155 can be arranged at at least one of the boundaries of the first to third sub-pixels SP1, SP2, and SP3, but the embodiments described herein are not limited to this. The wall 154 and the spacer 155 can be made of the same material and simultaneously be formed by a halftone mask, but the embodiments described herein are not limited to this.

[0168] The organic layer 152 can be arranged on the first electrode 151, the wall 154, and the spacer 155. The second electrode 153 can be arranged on the organic layer 152.

[0169] The encapsulation part 170 can be arranged on the second electrode 153. The encapsulation section 170 can have one or more insulating layers. For example, the encapsulation section 170 can have a first encapsulation layer 171, a second encapsulation layer 172 arranged on top of the first encapsulation layer 171, and a third encapsulation layer 173 arranged on top of the second encapsulation layer 172. The encapsulation part 170 can have one or more inorganic insulating material layers and one or more organic material layers. For example, the first encapsulation layer 171 and the third encapsulation layer 173 can have an inorganic insulating material, and the second encapsulation layer 172 can have an organic material, but the embodiments described herein are not limited to these.

[0170] The contact part 180 can be arranged on the encapsulation part 170. The contact part 180 can comprise the contact buffer layer 181, a first contact conductive layer, the first contact insulating layer 183, the second contact insulating layer 184, and a second contact conductive layer. In some embodiments, one or more organic contact layers can additionally be arranged on the second contact conductive layer, but the embodiments described herein are not limited to this.

[0171] Fig. Figure 8 is a cross-sectional view of a contact part according to Fig. 4.

[0172] With reference to the Fig. 4 and Fig. 8. The contact buffer layer 181 can be arranged on the encapsulation part 170. For example, a contact buffer layer 181 can be arranged on the third encapsulation layer 173. The contact buffer layer 181 can be made of the same material as the buffer layer 102, but the embodiments described herein are not limited to this.

[0173] The first contact conductive layer can be arranged on the contact buffer layer 181. The first contact conductive layer can have a bridge electrode 182. The bridge electrode 182 and a sensor electrode 185, which is described below, can be arranged at any of the boundaries between adjacent sub-pixels SP1, SP2, and SP3. For example, the bridge electrode 182 and the sensor electrode 185 can be arranged in the non-light-emitting regions NEA. The bridge electrode 182 and the sensor electrode 185 can overlap the black matrix BM, which is described below, in the thickness direction. The black matrix BM can cover the bridge electrode 182 and the sensor electrode 185. Accordingly, the bridge electrode 182 and the sensor electrode 185 can be prevented from being visible from the outside.

[0174] The first contact insulating layer 183 and the second contact insulating layer 184, which is arranged on the first contact insulating layer 183, can be arranged on the first contact conductive layer. The first contact insulating layer 183 and the second contact insulating layer 184, which is arranged on the first contact insulating layer 183, can prevent a short circuit between the first contact conductive layer and the second contact conductive layer. The first contact insulating layer 183 can be made of silicon dioxide (SiO₂). x ), silicon nitride (SiN xThe second contact insulating layer 184 may comprise one or more layers, but the embodiments described herein are not limited to this. The second contact insulating layer 184 may comprise an organic insulating material, but the embodiments described herein are not limited to this, and the second contact insulating layer 184 may comprise the same material as the first contact insulating layer 183.

[0175] The second contact conductive layer can be arranged on the second contact insulating layer 184. The second contact conductive layer can have a first sensor electrode 185a and a second sensor electrode 185b. The sensor electrode 185 can be located opposite the first sensor electrode 185a, which is oriented in the first direction DR1 (see Fig. 1) extends, and the second sensor electrode 185b, which extends in the second direction DR2 (see Fig. 1), which differs from the first direction DR1, extend.

[0176] The bridge electrode 182 can be electrically connected to the first sensor electrode 185a via a contact hole formed in the first contact insulating layer 183 and the second contact insulating layer 184. For example, the first sensor electrode 185a and the bridge electrode 182 can be connected in the first direction DR1 (see Fig. 1) extend.

[0177] The sensor electrode 185 and the bridge electrode 182 can be made of a metallic material. For example, the sensor electrode 185 and the bridge electrode 182 can be made of titanium (Ti), nickel (Ni), aluminum (Al), or an alloy thereof, and can be formed from a triple layer, for example titanium (Ti) / aluminium (Al) / titanium (Ti), but the embodiments described herein are not limited to these.

[0178] In the present embodiment, an example has been described in which the contact part 180 is arranged directly on the encapsulation part 170, but the embodiments described here are not limited to this. For example, the contact part 180 can be arranged as a separate component, distinct from the display panel 100, or a substrate and / or an insulating layer can be arranged between the contact part 180 and the encapsulation part 170.

[0179] Referring to Fig. 4. The filter insulating layer 114 can be arranged on the sensor electrode 185. The filter insulating layer 114 can be made of an inorganic insulating material, such as silicon nitride (SiN₂). x ) or silicon dioxide (SiO₂) x ), but the embodiments described herein are not limited to this.

[0180] The black matrix BM can be arranged on the filter insulating layer 114. The black matrix BM can be made of a black material. For example, the black matrix BM can be an opaque or a light-absorbing material. For example, the black matrix BM can be made of a material containing a black pigment, a black dye, etc. The black matrix BM can cover the bridge electrode 182 and the sensor electrode 185. Accordingly, the bridge electrode 182 and the sensor electrode 185 can be prevented from being visible from the outside. For example, the width of the black matrix BM can be smaller than the width of the wall 154.

[0181] For example, the distances between one end of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA can be larger than the distances between one end of the wall 154 and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA. The end of the wall 154 can be aligned with the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA, but the embodiments described herein are not limited to this.Since, in the case of the display panel 100 according to one embodiment of the wall 154, it can comprise a carbon black-based material, and since the distances between the end of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA can be greater than the distances between the end of the wall 154 and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA, the light emitted by the light-emitting areas EA1, EA2, and EA3 can be emitted upwards with wider viewing angles, which are as large as the distances between the end of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA. Accordingly, it is possible to minimize a reduction in luminance depending on the viewing angle.However, if the distances between the end of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA are longer than the distances between the end of the wall 154 and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA, and if the wall 154 is made of a transparent material only, then externally incident light can be reflected by the wall 154, resulting in visible ring-shaped spots. In the case of the display panel 100 according to one embodiment, however, the externally incident light can be absorbed or blocked by the wall 154, which has a carbon black-based material, thus preventing the appearance of the ring-shaped spots.

[0182] Color filters 191, 192, and 193 can be arranged on the black matrix BM. Each color filter can be positioned on the first, second, and third sub-pixels SP1, SP2, and SP3, respectively, and block specific colors from the light emitted by the light-emitting areas EA1, EA2, and EA3 of sub-pixels SP1, SP2, and SP3. A first color filter 191 can be provided to block light of colors other than red (R). In this case, the first color filter 191 can be a red filter. A second color filter 192 can be provided to block light of colors other than green (G). In this case, a second color filter 192 can be a green filter. A third color filter 193, provided in the third sub-pixel SP3, may be intended to block light of colors other than blue (B) light. In this case, the third color filter 193 may be a blue color filter.However, the embodiments described herein are not limited to this.

[0183] For example, each color filter 191, 192, or 193 can come into direct contact with the side faces and top faces of the black matrix BM. For example, each color filter 191, 192, or 193 can be arranged at a distance from the boundaries of adjacent sub-pixels SP1, SP2, and SP3, but the embodiments described herein are not limited to this, and the color filters 191, 192, and 193 can overlap each other in the thickness direction.

[0184] The planarization layer OC can be arranged on the color filters 191, 192, and 193. The planarization layer OC can serve to planarize a step formed by the color filters 191, 192, and 193. For example, the planarization layer OC can comprise an organic insulating material.

[0185] As described above, an example was given in which the black matrix BM and the color filters 191, 192, and 193 are arranged directly on the contact part 180, but the embodiments described in the present text are not limited to this. For example, separate substrates and insulating layers can additionally be arranged between the black matrix BM and the color filters 191, 192, and 193 and the contact part 180, or an optical layer, etc., can additionally be arranged between them.

[0186] The following is a cross-sectional structure of the second sub-pixel SP2 of Fig. 5 described. For content that falls under the first sub-pixel SP1 of Fig. Since the four components are essentially the same, the same reference symbols are used, and the overlapping content can be omitted or briefly described.

[0187] The first protective layer 111, which is located in the second sub-pixel SP2 of Fig. 5 is arranged, a different structure than the first protective layer 111, which is in the first sub-pixel SP1 of Fig. 4 is arranged, exhibit.

[0188] In Fig. 5. The first protective layer 111 can have a second overlap region OA2, in which the first protective layer 111 overlaps the second circuit line CL2 in the thickness direction (the third direction DR3), and a second non-overlap region NOA2, in which the first protective layer 111 does not overlap the second circuit line CL2. The thickness TH3 of the first protective layer 111 in the second overlap region OA2 can be less than the thickness TH4 of the first protective layer 111 in the second non-overlap region NOA2.

[0189] In an area where the first protective layer 111 overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3), the thickness TH3 of the first protective layer 111 in the second overlap area OA2 can be smaller than the thickness TH4 of the second protective layer 111 in the second non-overlap area NOA2.

[0190] The first protective layer 111 can define a plurality of trenches TR. The trench TR can be formed by recessing (deepening) the upper surface of the first protective layer 111 in the thickness direction (the third direction DR3). The plurality of trenches TR can be arranged in the second overlap area OA2. The plurality of trenches TR can be arranged in the second overlap area OA2 and can overlap the second anode electrode ANO2 in the thickness direction (the third direction DR3), but is not restricted to doing so.

[0191] Using a slot mask, a halftone mask, etc., part of the upper surface of the first protective layer 111, which is located in the second overlap area OA2, can be etched to form the trench TR.

[0192] The second circuit line CL2 can be arranged in the trench TR. The second circuit line CL2 arranged in the trench TR can be the second circuit line CL2 that overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3).

[0193] For example, at least parts of the 23rd to 27th circuit lines CL23 to CL27 can be made from Fig. 5. The second anode electrode ANO2 overlaps in the thickness direction (the third direction DR3). Circuit lines 23 to 27, CL23 to CL27, may be located in the trench TR. Sections of circuit lines 23 to 27, CL23 to CL27, which overlap the second anode electrode ANO2 in the thickness direction (the third direction DR3), may be located in the trench TR, but are not restricted to it.

[0194] The TR trenches can be excavated to the same depth, but are not limited to this. The TR trenches can be excavated to different depths.

[0195] The height h of the upper surface of the second circuit line CL2, which is arranged in the trench TR, can be the same. To ensure that the height h of the upper surface of the second circuit line CL2 is at the same level, the depth of the trench TR can be adjusted in various ways. The upper surface of the second circuit line CL2 can refer to the surface facing the second protective layer 112.

[0196] The upper surface of the second circuit line CL2 can project from the upper surface of the first protective layer 111 towards the second protective layer 112. However, the embodiments described herein are not limited to this, and in the area where the second circuit line CL2 overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3), the height h of the upper surface of the second circuit line CL2 can be equal to the height of the upper surface of the first protective layer 111.

[0197] Since the first protective layer 111 defines the trench TR and the second circuit line CL2, at least part of which overlaps the second anode electrode ANO2 in the trench TR, the height h of the upper surface of the second circuit line CL2 can be reduced. That is, the height h of the upper surface of the second circuit line CL2 can be adjusted by the trench TR.

[0198] Accordingly, the upper surface of the first protective layer 111 can be flat. The upper surface of the first protective layer 111 can refer to the surface facing the second protective layer 112. The second protective layer 112, which is arranged on top of the first protective layer 111, can also be designed to be generally flat. Furthermore, the second anode electrode ANO2, arranged on the second protective layer 112, can also be designed to be flat, thereby improving the flatness of the second anode electrode ANO2 and suppressing or preventing defects in the display panel 100.

[0199] The first overlap area OA1 and the second overlap area OA2 of Fig. The four layers can overlap in some areas in the thickness direction (the third direction DR3). In this case, the thickness of the first protective layer 111 in an area where the first overlap area OA1 and the second overlap area OA2 overlap can be smaller than the thickness TH1 of the first protective layer 111 of the first overlap area OA1 and the thickness TH3 of the first protective layer 111 of the second overlap area OA2, but is not limited to this.

[0200] As described above, the cross-sectional structure of the first sub-pixel SP1 and the cross-sectional structure of the second sub-pixel SP2 have been described. Content that substantially matches the cross-sectional structure of the first sub-pixel SP1, or content that substantially matches the cross-sectional structure of the second sub-pixel SP2, can be applied to the third sub-pixel SP3.

[0201] Further embodiments of the present description are described below. For content which, among the components included in other embodiments, is essentially the same as that described with reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. 8. If the information described above matches, the same reference symbols are used, and overlapping content can be omitted or briefly described.

[0202] Fig. Figure 9 is a cross-sectional view of a sub-pixel according to another embodiment.

[0203] With reference to Fig. 9 a display panel 100_2 of the display device according to the present embodiment has the first electrode 151 (see Fig. 3) and the first anode electrode ANO1 can have a convex shape in a direction in which light is emitted.

[0204] In particular, the first anode electrode ANO1 of the first sub-pixel SP1 can have a convex shape in the direction in which light is emitted. The first anode electrode ANO1 is not limited to this, but it can also have a convex shape in the first light-emitting region EA1.

[0205] The second protective layer 112 can have a convex shape which projects towards the encapsulation part 170 in a region where the second protective layer 112 overlaps the first anode electrode ANO1 in the thickness direction (the third direction DR3). The second protective layer 112 can also have a convex shape which projects towards the encapsulation part 170 in a region where the second protective layer 112 overlaps the first light-emitting area EA1 in the thickness direction (the third direction DR3).

[0206] Since the first anode electrode ANO1, which is arranged on the second protective layer 112, can be arranged according to the curvature of the upper surface of the second protective layer 112, the first anode electrode ANO1 can have a convex shape.

[0207] The convex shape of the second protective layer 112 can be formed using a slit mask, a halftone mask, etc., but the method for forming the convex shape of the second protective layer 112 is not limited to this and can be varied.

[0208] Accordingly, the shape of the first anode electrode ANO1 can be more uniformly shaped to achieve a desired form. Furthermore, it is also possible to increase the degree of freedom with regard to the design of the layout of the display panel 100.

[0209] Since the first anode electrode ANO1 has a convex shape in the direction in which light is emitted, it is possible to improve the color viewing angle characteristics and to enable low-power operation of the display device, thereby reducing energy consumption.

[0210] As described above, the first sub-pixel SP1 was described as an example, but the description can be applied in the same way to the second sub-pixel SP2 and the third sub-pixel SP3.

[0211] Fig. Figure 10 is a cross-sectional view of a sub-pixel according to another embodiment.

[0212] With reference to Fig. In a display panel 100_3 of the display device according to the present embodiment, the grooves TR can have different depths D1, D2, D3, D4 and D5. The depths D1, D2, D3, D4 and D5 of the grooves TR can refer to the degree (depth) of the indentation from the upper surface to the lower surface of the first protective layer 111.

[0213] For example, in the second sub-pixel SP2, in an area that overlaps with the second anode electrode ANO2, the trenches TR can have a first to fifth trench TR1 to TR5. The 23rd to 27th circuit lines CL23 to CL27 can each be located in the first to fifth trenches TR1 to TR5.

[0214] In the area where the trench TR overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3), the recessed depths of at least some of the trenches TR may differ.

[0215] For example, in the area where the trench TR overlaps the second anode electrode ANO2, the recessed depth of the trench TR can increase when moving from a central section of the second anode electrode ANO2 towards one side and / or the other side of the second anode electrode ANO2 in the first direction DR1.

[0216] In Fig. 10. The depth D3 of a third trench TR3 may be smaller than the depth D2 of a second trench TR2 and the depth D4 of a fourth trench TR4, the depth D2 of the second trench TR2 may be smaller than the depth D1 of a first trench TR1, and the depth D4 of the fourth trench TR4 may be smaller than the depth D5 of a fifth trench TR5.

[0217] In the area where the second circuit line CL2 overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3), the height of the upper surface of the second circuit line CL2 (see Fig. 3) be different.

[0218] For example, in the area where the second circuit line CL2 overlaps the second anode electrode ANO2, the height of the upper surface of the second circuit line CL2 (see Fig. 3) increase when moving from the circumference (edge) of the second anode electrode ANO2 towards the central section of the second anode electrode ANO2 in the first direction DR1.

[0219] In Fig. 10. The height h3 of the 25th circuit line CL25 can be higher than the height h2 of the 24th circuit line CL24 and the height h4 of the 26th circuit line CL26; the height h2 of the 24th circuit line CL24 can be higher than the height h1 of the 23rd circuit line CL23; and the height h4 of the 26th circuit line CL26 can be higher than the height h5 of the 27th circuit line CL27.

[0220] The heights h1, h2, h3, h4 and h5 of the circuit lines CL23 to CL27 can refer to the heights of the upper surfaces of the circuit lines CL23 to CL27 from the substrate 101.

[0221] Accordingly, the upper surface of the second protective layer 112 can be designed to correspond to the heights h1, h2, h3, h4, and h5 of the circuit lines CL23 to CL27. This means that the second protective layer 112 can have a convex shape which, in the area where the second protective layer 112 overlaps the second anode electrode ANO2 in the thickness direction (the third direction DR3), projects towards the encapsulation part 170. This means that the second protective layer 112 can have a convex shape which, in the area where the second protective layer 112 overlaps the second circuit line CL2 (see Fig.3) and overlaps the second light-emitting area EA2 in the thickness direction (of the third direction DR3), protrudes.

[0222] Since the second anode electrode ANO2, which is arranged on the second protective layer 112, can be arranged in such a way that it corresponds to the curvature of the upper surface of the second protective layer 112, the second anode electrode ANO2 can have a convex shape.

[0223] Accordingly, the shape of the second anode electrode ANO2 can be more uniformly shaped to achieve a desired form. Furthermore, it is also possible to increase the degree of freedom with regard to the design of the layout of the display panel 100.

[0224] Since the second anode electrode ANO2 has a convex shape in the direction in which light is emitted, it is possible to improve the color viewing angle characteristics and to enable low-power operation of the display device, thereby reducing energy consumption.

[0225] As described above, the second sub-pixel SP2 was described as an example, but the description can be applied in the same way to the first sub-pixel SP1 and the third sub-pixel SP3.

[0226] A display device according to numerous embodiments of the present description can be described as follows.

[0227] A display device according to embodiments of the present disclosure comprises a substrate on which a first sub-pixel, a second sub-pixel and a third sub-pixel are arranged, a first circuit line which is arranged on the substrate, a thin-film transistor which is arranged between the substrate and the first circuit line, a first protective layer which is arranged on the first circuit line and the thin-film transistor, a second circuit line which is arranged on the first protective layer, a second protective layer which is arranged on the second circuit line, and a first anode electrode of the first sub-pixel which is arranged on the second protective layer, wherein the first protective layer has different thicknesses in a region where the first protective layer overlaps the first anode electrode.

[0228] According to numerous embodiments of the present description, the display device further comprises a second anode electrode of the second sub-pixel, which is arranged on the second protective layer, wherein in an area where the first protective layer overlaps the second anode electrode, the first protective layer may have a groove recessed in one thickness direction and the second circuit line may be arranged in the groove.

[0229] According to numerous embodiments of the present description, the height of an upper surface of the second circuit line can be the same as the height of an upper surface of the first protective layer.

[0230] According to numerous embodiments of the present description, the first circuit line can comprise at least one of a sampling line transmitting a sampling signal, an initialization line transmitting an initialization voltage, and a light emission control line transmitting a light emission control signal, wherein the second circuit line can comprise at least one of a data line transmitting a data voltage, a high-potential current line transmitting a high-potential supply voltage, an anode reset line transmitting an anode reset voltage, and a low-potential current line transmitting a low-potential supply voltage.

[0231] According to numerous embodiments of the present description, the second circuit line and the trench are each provided as a plurality of second circuit lines and trenches, and all heights of the upper surfaces of the plurality of second circuit lines can be the same in the area where the second circuit line overlaps the second anode electrode.

[0232] According to numerous embodiments of the present description, the first circuit line can extend in a first direction, and the second circuit line can extend in a second direction which intersects the first direction.

[0233] According to numerous embodiments of the present description, the second circuit line and the trench can each be provided as a plurality of second circuit lines and trenches, and in the area where the second circuit line overlaps the second anode electrode, the heights of the upper surfaces of the plurality of second circuit lines can decrease when moving from a central section of the second anode electrode in the direction to one side and the other side (e.g. in the direction to a circumference of the second anode electrode) in the first direction.

[0234] According to numerous embodiments of the present description, the second anode electrode can be formed in a convex shape in one thickness direction.

[0235] According to numerous embodiments of the present description, in the area where the first protective layer overlaps the first anode electrode, the thickness of a first overlapping area, where the first protective layer overlaps the first circuit line, can be smaller than the thickness of a first non-overlapping area, where the first protective layer does not overlap the first circuit line.

[0236] According to numerous embodiments of the present description, the first circuit line can be provided as a plurality of first circuit lines, and in the area where the first circuit line overlaps the first anode electrode, all heights of the upper surfaces of the plurality of first circuit lines can be the same.

[0237] According to numerous embodiments of the present description, the display device may further comprise a second anode electrode of a second sub-pixel, which is arranged on the second protective layer, wherein in an area where the first protective layer overlaps the second anode electrode, the thickness of a second overlap area, where the first protective layer overlaps the second circuit line, may be smaller than the thickness of a second non-overlap area, where the first protective layer does not overlap the second circuit line.

[0238] According to numerous embodiments of the present description, in the area where the first protective layer overlaps the first anode electrode, an upper surface of the first protective layer may be flat, and in the area where the first protective layer overlaps the second anode electrode, the first protective layer may have a groove recessed from its upper surface.

[0239] The first sub-pixel can emit red light, and the second sub-pixel can emit blue light.

[0240] According to numerous embodiments of the present description, the second protective layer can have a convex shape in the direction of the first anode electrode in an area where the second protective layer overlaps the first anode electrode, and the first anode electrode can have a convex shape corresponding to the convex shape of the second protective layer.

[0241] According to embodiments of the present description, a display device is provided comprising a substrate on which a first sub-pixel, a second sub-pixel, and a third sub-pixel are arranged, a first circuit line arranged on the substrate, a thin-film transistor arranged between the substrate and the first circuit line, a first protective layer arranged on the first circuit line and the thin-film transistor, a second protective layer arranged on the first protective layer, a second protective layer arranged on the second circuit line, a first anode electrode of the first sub-pixel arranged on the second protective layer, and a second anode electrode of the second sub-pixel arranged on the second protective layer, wherein in a region,in which the first protective layer overlaps the second anode electrode, the first protective layer has a groove recessed in one thickness direction, and the second circuit line is arranged in the groove.

[0242] According to numerous embodiments of the present description, in the area where the first protective layer overlaps the second anode electrode, the thickness of a second overlap area, where the first protective layer overlaps the second circuit line, can be smaller than the thickness of a second non-overlap area, where the first protective layer does not overlap the second circuit line.

[0243] According to numerous embodiments of the present description, the height of an upper surface of the second circuit line can be the same as the height of an upper surface of the first protective layer.

[0244] The second circuit line and the trench can each be provided as a plurality of second circuit lines and trenches, and all heights of the upper surfaces of the plurality of second circuit lines can be the same in the area where the second circuit line overlaps the second anode electrode.

[0245] According to numerous embodiments of the present description, the first circuit line can extend in a first direction and the second circuit line can extend in a second direction that intersects the first direction.

[0246] According to numerous embodiments of the present description, the second circuit line and the trench can each be provided as a plurality of second circuit lines and trenches, and in the area where the second circuit line overlaps the first anode electrode, the heights of the upper surfaces of the plurality of second circuit lines can decrease when moving from a central section of the second anode electrode in the direction to one side and the other side (e.g. in the direction to a circumference of the second anode electrode) in the first direction. Reference symbol description 1 Display device 100 display panels 101 Substrat 120 First thin-film transistor 130 Second thin-film transistor 140 storage capacitor 111 First protective layer 112 Second protective layer CL1 First circuit line CL2 Second circuit line TR Trench 150 Light-emitting part 151 First electrode ANO anode electrode 152 Organic layer 153 Second electrode 170 Encapsulation part 180 Contact part

Claims

A display device (1) comprising: a substrate (101) on which a first sub-pixel (SP1), a second sub-pixel (SP2) and a third sub-pixel (SP3) are arranged, a first circuit line (CL1) which is arranged on the substrate (101), a thin-film transistor (120, 130) which is arranged between the substrate (101) and the first circuit line (CL1), a first protective layer (111) which is arranged on the first circuit line (CL1) and the thin-film transistor (120, 130), a second circuit line (CL2) which is arranged on the first protective layer (111), a second protective layer (112) which is arranged on the second circuit line (CL2), and a first anode electrode (ANO1) of the first sub-pixel (SP1) which is arranged on the second protective layer (112), wherein the first protective layer (111) in an area where the first protective layer (111) overlaps the first anode electrode (ANO1),has different thicknesses. The display device (1) according to claim 1, further comprising a second anode electrode (ANO2) of the second sub-pixel (SP2) which is arranged on the second protective layer (112), wherein in an area where the first protective layer (111) overlaps the second anode electrode (ANO2), the first protective layer (111) has a groove (TR) recessed in a thickness direction and the second circuit line (CL23, CL24, ..., CL27) is arranged in the groove (TR). The display device (1) according to claim 2, wherein a height (h) of an upper surface of the second circuit line (CL23, CL24, ..., CL27) is equal to a height of an upper surface of the first protective layer (111). The display device (1) according to claim 3, wherein the first circuit line (CL1) comprises at least one of a sampling line transmitting a sampling signal (SC1[n], ..., SC4[n]), an initialization line transmitting an initialization voltage (VINI), and a light emission control line transmitting a light emission control signal (EM[n]), and the second circuit line (CL2) comprises at least one of a data line (DL) transmitting a data voltage (VDATA), a high-potential current line transmitting a high-potential supply voltage (VDD), an anode reset line transmitting an anode reset voltage (VAR), and a low-potential current line transmitting a low-potential supply voltage (VSS). The display device (1) according to one of claims 2 to 4, wherein the second circuit line (CL2) and the trench (TR) are each provided as a plurality of second circuit lines (CL23, CL24, ..., CL27) and trenches (TR), and in the area where the second circuit line (CL2) overlaps the second anode electrode (ANO2), all heights of upper surfaces of the plurality of second circuit lines (CL23, CL23, ..., CL27) are equal. The display device (1) according to one of claims 2 to 4, wherein the first circuit line (CL1) extends in a first direction (DR1) and the second circuit line (CL2) extends in a second direction (DR2), which intersects the first direction (DR1). The display device (1) according to claim 6, wherein the second circuit line (CL2) and the trench (TR) are each provided as a plurality of second circuit lines (CL23, CL24, ..., CL27) and trenches (TR), and in the area where the second circuit line (CL2) overlaps the second anode electrode (ANO2), heights (h1, ..., h5) of upper surfaces of the plurality of second circuit lines (CL23, CL24, ..., CL27) decrease when moving from a central section of the second anode electrode (ANO2) towards a circumference of the second anode electrode (ANO2) in the first direction (DR1). The display device (1) according to claim 7, wherein the second anode electrode (ANO1) is formed in a convex shape in the thickness direction (DR3). The display device (1) according to one of claims 1 to 8, wherein in the area in which the first protective layer (111) overlaps the first anode electrode (ANO1), a thickness (TH1) of a first overlap area (OA1) in which the first protective layer (111) overlaps the first circuit line (CL14, CL15, ..., CL18) is smaller than a thickness (TH2) of a first non-overlap area (NOA1) in which the first protective layer (111) does not overlap the first circuit line (CL14, CL15, ..., CL18). The display device (1) according to one of claims 1 to 9, wherein the first circuit line (CL1) is provided as a plurality of first circuit lines (CL14, CL15, ..., CL18), and in the area where the first circuit line (CL2) overlaps the first anode electrode (ANO1), all heights of upper surfaces of the plurality of first circuit lines (CL14, CL15, ..., CL18) are equal. The display device (1) according to claim 1, further comprising a second anode electrode (ANO2) of the second sub-pixel (SP2) which is arranged on the second protective layer (112), wherein in a region in which the first protective layer (111) overlaps the second anode electrode (ANO2), a thickness (TH3) of a second overlap region (OA2) in which the first protective layer (111) overlaps the second circuit line (CL23, ..., CL27) is smaller than a thickness (TH4) of a second non-overlap region (NOA2) in which the first protective layer (111) does not overlap the second circuit line (CL23, ..., CL27). The display device (1) according to claim 11, wherein an upper surface of the first protective layer (111) is flat in the area where the first protective layer (111) overlaps the first anode electrode (ANO1), and in the area where the first protective layer (111) overlaps the second anode electrode (ANO2), the first protective layer (111) has a recess (TR) from its upper surface. The display device (1) according to claim 12, wherein the first sub-pixel (SP1) emits red light and the second sub-pixel (SP2) emits blue light. The display device (1) according to one of claims 1 to 13, wherein in a region where the second protective layer (112) overlaps the first anode electrode (ANO1), the second protective layer (112) has a convex shape in the direction of the first anode electrode (ANO1), and the first anode electrode (ANO1) has a convex shape corresponding to the convex shape of the second protective layer (112). A display device (1) comprising: a substrate (101) on which a first sub-pixel (SP1), a second sub-pixel (SP2) and a third sub-pixel (SP3) are arranged; a first circuit line (CL1) arranged on the substrate (101); a thin-film transistor (120, 130) arranged between the substrate (101) and the first circuit line (CL1); a first protective layer (111) arranged on the first circuit line (CL1) and the thin-film transistor (120, 130); a second circuit line (CL2) arranged on the first protective layer (111); a second protective layer (112) arranged on the second circuit line (CL2); and a first anode electrode (ANO1) of the first sub-pixel. (SP1), which is located on the second protective layer (112),and a second anode electrode (ANO2) of the second sub-pixel (SP2), which is arranged on the second protective layer (112), wherein in an area where the first protective layer (111) overlaps the second anode electrode (ANO2), the first protective layer (111) has a groove (TR) recessed in one thickness direction and the second circuit line (CL23, CL24, ..., CL27) is arranged in the groove (TR). The display device (1) according to claim 15, wherein in the area where the first protective layer (111) overlaps the second anode electrode (ANO2), a thickness (TH3) of a second overlap area (OA2) where the first protective layer (111) overlaps the second circuit line (CL23, CL24, ..., CL27) is smaller than a thickness (TH4) of a second non-overlap area (NOA2) where the first protective layer (111) does not overlap the second circuit line (CL23, CL24, ..., CL27). The display device (1) according to claim 15 or 16, wherein a height (h) of an upper surface of the second circuit line (CL2) is equal to a height of an upper surface of the first protective layer (111). The display device (1) according to one of claims 15 to 17, wherein the second circuit line (CL2) and the trench (TR) are each provided as a plurality of second circuit lines (CL23, CL24, ..., CL27) and trenches (TR), and in the area where the second circuit line (CL2) overlaps the second anode electrode (ANO2), all heights of upper surfaces of the plurality of second circuit lines (CL23, CL24, ..., CL27) are the same. The display device (1) according to one of claims 15 to 17, wherein the first circuit line (CL1) extends in a first direction (DR1) and the second circuit line (CL2) extends in a second direction (DR2), which intersects the first direction (DR1). The display device (1) according to claim 19, wherein the second circuit line (CL2) and the trench (TR) are each provided as a plurality of second circuit lines (CL23, CL24, ..., CL27) and trenches (TR), and in the area where the second circuit line (CL2) overlaps the first anode electrode (ANO1), heights (h1, h2, ..., h5) of upper surfaces of the plurality of second circuit lines (CL23, CL24, ..., CL27) decrease when moving from a central section of the second anode electrode (ANO2) towards a circumference of the second anode electrode (ANO2) in the first direction (DR1).

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