Light-emitting display device and pixel circuit

Abstract

A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines, a data drive circuit designed to supply data signals to the data lines, and a gate drive circuit designed to supply sampling signals to the gate lines, wherein each of the multiple subpixels comprises a light-emitting device, a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, and a second switching transistor designed tobetween a second node of the drive transistor, which is connected to the light-emitting device, and the data line, may include a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node.

Description

This application claims the benefit and priority of Korean patent application No. 10-2024-0197613, which was filed in the Republic of Korea on December 26, 2024. Technical field The present disclosure relates to a light-emitting display device and a pixel circuit. Description of the state of the art With the development of the information society, the demand for display devices for showing images in various forms is increasing, and light-emitting display devices such as liquid crystal displays (LCD), organic light-emitting displays (OLED), micro-light-emitting diode displays (micro-LED displays) and quantum dot displays (QD) are being used. A light-emitting display device arranges multiple pixels, each containing a light-emitting device, in a matrix and controls the luminance of the pixels according to a gradation of the image data. Each pixel includes a drive transistor for controlling a drive current flowing through the light-emitting device according to a gate-source voltage (Vgs) and one or more switching transistors for programming the gate-source voltage of the drive transistor. The gradation (or luminance) is controlled based on an emission quantity of the light-emitting device that is proportional to the drive current. However, due to various causes, including process variations, deviations in the drive characteristics between pixels can occur. Furthermore, the degradation among the pixels progresses at different rates depending on the drive time of the light-emitting display device, which can further amplify these differences in drive characteristics. Therefore, the amount of drive current flowing through the light-emitting device varies depending on the deviation in the drive characteristics between the pixels, resulting in uneven image quality. SUMMARY A light-emitting display device may include a compensation circuit to compensate for variations in the drive characteristics of a driver transistor. The compensation circuit may be implemented within a pixel and is designed to probe or detect the gate-source voltage of the driver transistor and compensate for the driver transistor's drive characteristics based on the detected value. However, the compensation circuit requires a separate reference voltage line (or detection voltage line) to initialize or detect the gate-source voltage of the driver transistor, resulting in a reduction of the display panel's on / off percentage. It is an object of the present disclosure to provide a light-emitting display device that can simplify a pixel circuit and voltage lines and improve the aperture fraction of a light-emitting section or the transparency of a transmission area by initializing a drive transistor using a data signal via a data line without requiring a reference voltage line. Another objective of the present disclosure is to provide a light-emitting display device that can simplify pixel circuitry and voltage lines while reducing data rate loss and compensating for fluctuations in the control characteristics of a drive transistor. One or more of these problems are solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.According to one aspect, a light-emitting display device comprises a display panel comprising several subpixels connected by data lines, gate lines, and gate drive voltage lines; a data drive circuit designed to supply data signals to the data lines; and a gate drive circuit designed to supply sampling signals to the gate lines, each of the several subpixels comprising a light-emitting device; a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device; a first switching transistor designed to connect between a first node of the drive transistor and the data line; and a second switching transistor designed to connect between a second node of the drive transistor.to connect the light-emitting device and the data line, a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node. The voltage of the second node can correspond to the capacitance of the second capacitor. The voltage at the second node can be proportional to the capacitance of the second capacitor. The second node can be electrically floating when the second switching transistor is off, and can reflect an electrical property of the driving transistor based on the second capacitor. The electrical properties of the driver transistor can include a threshold voltage and / or a mobility of the driver transistor. Each of the multiple subpixels can be driven according to a first period, a second period, and a third period. The data drive circuit can be designed to supply a first data signal with an initialization voltage during the first period and a second data signal with a data voltage higher than the initialization voltage during the second and third periods. The first period can be the initialization period, during which the first and second nodes are initialized to the initialization voltage. In the second period, the programming of the data voltage and the sampling of an electrical characteristic of the drive transistor can be performed simultaneously. In the third period, the light-emitting device can be driven to emit light based on the data voltage. The programmed data voltage can be stored in the first capacitor. A sampling voltage, reflecting or representing the electrical properties of the drive transistor, can be stored in the second node based on the second capacitor. The first switching transistor can be controlled by a first sampling signal supplied by the gate drive circuit. The second switching transistor can be controlled by a second sampling signal supplied by the gate drive circuit. The first period can begin at a time specified when the first data signal is delivered, can overlap with the ON states of the first and second sampling signals, and can end at a time specified when the second sampling signal is switched to an OFF state. The first and second sampling signals can be switched to an ON state before the first period. The second period can begin at a time specified when the second data signal is delivered, overlap with an ON state of the first sample signal, and end at a time specified when the first sample signal is switched to an OFF state. The second sampling signal can be switched to an OFF state before the second period. The third period can begin at a specified time at which the first sampling signal is switched to an OFF state, during the third period the second data signal can be maintained, and the third period can end at a specified time at which the first and second sampling signals are switched to an ON state. The gate lines can extend in a first direction. The data lines and the gate drive voltage lines can extend in a second direction that intersects the first direction. The multiple subpixels can be arranged in either the first or the second direction. The drive voltage lines can be located within the multiple subpixels. The multiple subpixels can include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. The control voltage line can be located between a second data line of the second subpixel and a third data line of the third subpixel. The second capacitor can be a double-capacitance structure or a triple-capacitance structure that overlaps at least one section of the drive voltage line. The light-emitting device may comprise a pixel electrode, an emissive layer, and a common electrode. The light-emitting device may further comprise a common voltage line connected to the common electrode. The common voltage line may extend in the second direction and / or be arranged to overlap at least one section of the data lines. The scoreboard can comprise a substrate. The scoreboard can comprise a first metal layer on the substrate. The scoreboard can comprise a first insulating layer on the first metal layer. The scoreboard can comprise a semiconductor layer on the first insulating layer. The scoreboard can comprise a second insulating layer on the semiconductor layer. The scoreboard can comprise a second metal layer on the second insulating layer. The scoreboard can comprise a third insulating layer on the second metal layer. The scoreboard can comprise a third metal layer on top of or within the third insulating layer. At least one of the data lines and the drive voltage lines can be formed from the first metal layer. The drive transistor can be formed from the semiconductor layer and the second metal layer. The first capacitor can be formed from the first metal layer, the semiconductor layer contained in the drive transistor, and the second metal layer contained in the drive transistor. The second capacitor can be formed from the first metal layer contained in the drive voltage line, the semiconductor layer overlapping the drive voltage line, and the second metal layer overlapping the drive voltage line. The second capacitor can be electrically connected to the second node of the driver transistor via a connecting wire. The connecting wire can be made of the same material as the semiconductor layer. The light-emitting display device may further comprise a common voltage line. The common voltage line may be formed from the third metal layer and / or overlap at least one section of the data lines. The second capacitor may be formed from the first metal layer contained in the drive voltage line. The semiconductor layer may overlap the drive voltage line. The second metal layer may overlap the drive voltage line. The third metal layer may overlap the drive voltage line. The third insulating layer can comprise an intermediate insulating layer and / or a passivation layer. The third metal layer can be positioned between the intermediate insulating layer and the passivation layer. A light-emitting display device according to a further aspect comprises a display panel comprising several subpixels connected by data lines, gate lines, and gate drive voltage lines; wherein the several subpixels comprise at least one first subpixel arranged along a first direction and several second subpixels arranged along a second direction intersecting the first direction, each of the several subpixels comprising a light-emitting device and a subpixel circuit designed to drive the light-emitting device, the subpixel circuit of the at least one first subpixel arranged along the first direction comprising: a drive transistor designed to connect between the drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device,a first switching transistor designed to connect between a first node of the drive transistor and the data line, a second switching transistor designed to connect between a second node of the drive transistor connected to the light-emitting device and the data line, a first capacitor connected between the first node and the second node, and wherein the subpixel circuit of each of the several second subpixels arranged along the second direction comprises the drive transistor, the first switching transistor, the second switching transistor, the first capacitor, and a second capacitor connected between a third node of the drive transistor connected to the drive voltage line and the second node. The capacitance of the first capacitor in the subpixel circuit of the at least one first subpixel can be greater than the capacitance of the first capacitor in the subpixel circuit of each of the several second subpixels. A pixel circuit, according to another aspect, is designed to control a light-emitting device and may include a drive transistor designed to connect between a drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and a data line, a second switching transistor designed to connect between a second node of the drive transistor connected to the light-emitting device and the data line, a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor connected to the drive voltage line and the second node. The light-emitting display device according to the present disclosure can simplify a pixel circuit and voltage lines and improve an aperture fraction of a light-emitting section or a transparency of a transmission area by initializing a drive transistor using a data signal via a data line without requiring a reference voltage line. Furthermore, the light-emitting display device according to the present disclosure can simplify a pixel circuit and voltage lines while simultaneously reducing the loss of the data transmission rate and compensating for fluctuations in the control characteristics of a control transistor. The light-emitting display device according to the present disclosure can improve the aperture ratio of a light-emitting section or the transparency of a transmission area by simplifying a pixel circuit and voltage lines, reducing data rate loss, and compensating for variations in the drive characteristics of a driver transistor. Accordingly, it is possible to reduce the cost of the light-emitting display device, improve its reliability and display quality, and reduce manufacturing energy consumption, thereby enabling the implementation of environmental, social, and governance (ESG) principles. The effects of this disclosure are not limited to the foregoing, but other effects not described here will be clearly understandable to experts from the following descriptions. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, included for better understanding of the disclosure, are integrated into and form part of this disclosure. They illustrate aspects and embodiments of the disclosure and, together with the description, serve to explain the principles and examples of the disclosure. Fig. 1 shows a schematic configuration of a display device according to an embodiment of the present disclosure. Fig. 2 shows a circuit configuration of a subpixel according to an embodiment of the present disclosure. Fig. 3 shows a control timing specification of a subpixel according to an embodiment of the present disclosure. Fig. 4 shows an operating state of a pixel circuit in a first period of the subpixel shown in Fig. 3 according to an embodiment of the present disclosure. Fig. 5 shows voltage changes of nodes in the pixel circuit shown in Fig. 4 according to an embodiment of the present disclosure.Figure 6 shows an operating state of a pixel circuit in a second period of the subpixel shown in Figure 3 according to an embodiment of the present disclosure. Figure 7 shows voltage changes of nodes in the pixel circuit shown in Figure 6 according to an embodiment of the present disclosure. Figure 8 shows an operating state of a pixel circuit in a third period of the subpixel shown in Figure 3 according to an embodiment of the present disclosure. Figure 9 shows voltage changes of nodes in the pixel circuit shown in Figure 8 according to an embodiment of the present disclosure. Figure 10 shows voltage changes of nodes in the pixel circuit according to a further embodiment of the present disclosure. Figure 11 shows voltage changes of nodes in the pixel circuit according to a further embodiment of the present disclosure.Figure 12 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Figure 13 is a sectional view along line II' shown in Figure 12 according to a further embodiment of the present disclosure. Figure 14 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Figure 15 is a sectional view along line II-II' shown in Figure 14 according to a further embodiment of the present disclosure. Figure 16 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Figure 17 is a sectional view along line III-III' shown in Figure 16 according to a further embodiment of the present disclosure. Unless otherwise specified, the same drawing reference symbols in the drawings and the detailed description consistently refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, areas, and elements, as well as their representation, may be exaggerated for clarity, illustration, and / or practicality. DETAILED DESCRIPTION The advantages and features of the present disclosure, as well as its implementation methods, are explained with reference to the embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are examples provided to ensure that this disclosure is complete and thorough in order to assist those skilled in the art in understanding the inventive concepts without limiting the scope of protection of the present disclosure. The forms (e.g., sizes, lengths, widths, heights, thicknesses, locations, radii, diameters, and areas), dimensions, ratios, angles, numbers, and the like disclosed herein, including those illustrated in the drawings, are merely examples, and therefore the present disclosure is not limited to the details shown. Any implementation described herein as an "example" is not necessarily to be understood as preferred or advantageous over other implementations. However, it should be noted that the relative dimensions of the components shown in the drawings are part of the present disclosure. When the terms “comprise”, “have”, “contain”, “consist of”, “formed of”, or the like are used in reference to one or more elements, one or more other elements may be added unless a term such as “only” or the like is used. The terms used in this disclosure serve only to describe embodiments and are not intended to limit the scope of this disclosure. Singular terms may also include the plural unless the context clearly indicates otherwise. When interpreting an element, the element is designed to encompass an error range, even if this is not explicitly described. For example, if the positional sequence is described as "on", "above", "below", "below" and "next to", the case without contact in between may be included unless terms such as "immediate" or "direct" are used. When it is mentioned that a first element is positioned "on" a second element, this does not mean that the first element is essentially positioned above the second element in the figure. The upper and lower parts of an object in question can vary depending on the object's orientation. Consequently, the case in which a first element is positioned "on" a second element, in the figure or in an actual configuration, includes both the case in which the first element is positioned "below" the second element and the case in which the first element is positioned "above" the second element. For example, when describing a temporal relationship, if the temporal sequence is described as "after", "subsequently", "next", and "before", a case that is not continuous may be included unless "immediately" or "directly" is used. It is understood that the terms "first," "second," etc., used here to describe different elements, are not intended to restrict these elements. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and likewise a second element could be called a first element. In describing elements of this revelation, the terms “first”, “second”, “A”, “B”, “(a)”, “(b)”, or similar terms may be used. These terms serve to distinguish one or more corresponding elements from the other elements and are not used to define the nature, basis, order, or number of the elements. When an element is described as being "connected", "coupled", "attached", "moved" or the like to another element, the element may not only be directly connected, coupled, attached, or the like to another element, but may also be indirectly connected, coupled, attached, or the like to another element, with one or more intermediate elements arranged or interposed between the elements, unless otherwise specified. For example, the expression "A is connected to B" encompasses both a direct connection—where there are no intervening components or elements—and an indirect connection, where one or more intervening components or elements exist between A and B. In other words, "A is connected to B" includes both direct physical or electrical coupling and indirect coupling via one or more intervening components. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The term "coupled" and other terms listed above are to be interpreted in the same way. When an element is described as "contacting", "overlapping", or the like, it can mean not only that the element directly contacts, overlaps, or the like, but also that it indirectly contacts, overlaps, or the like, with one or more intermediate elements placed or interposed between the elements, unless otherwise specified. The term "at least one" should be understood to encompass all combinations of one or more of the listed elements. For example, "at least one of a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each individual element of the first, second, and third elements. Features of different embodiments of the present disclosure can be partially or completely coupled or combined, technically connected, and interact, linked, or jointly controlled in various ways. The embodiments of the present disclosure can be implemented or executed independently of one another or in a mutual dependency or relationship with each other. In one or more aspects, the components of each device according to different embodiments of the present disclosure are operationally coupled and configured. The following description details various embodiments of the present disclosure with reference to the accompanying drawings. With regard to the reference numerals for elements in each of the drawings, the same elements may be shown in other drawings, and identical reference numerals may refer to identical elements unless otherwise indicated. Identical or similar elements may be designated by the same reference numerals even if they are shown in different drawings. Furthermore, for the sake of simplicity, the scales, dimensions, sizes, and thicknesses of the individual elements shown in the accompanying drawings may differ from the actual scales, dimensions, sizes, and thicknesses, so that the embodiments of the present disclosure are not limited to the scales, dimensions, sizes, and thicknesses shown in the drawings. Fig. 1 shows a schematic configuration of a display device according to an embodiment of the present disclosure. With reference to Fig. 1, a light-emitting display device 100 according to an embodiment of the present disclosure can comprise a display panel 110 on which several subpixels SP are arranged in matrix form and several gate lines GL and data lines DL are connected, a gate drive circuit 120 designed to drive the several gate lines GL, a data drive circuit 130 designed to drive the several data lines DL, a timing controller 140 designed to control the gate drive circuit 120 and the data drive circuit 130, and a power management IC (PMIC) 150. The display panel 110 can display an image based on a sampling signal transmitted from the gate control circuit 120 via the multiple gate lines GL and a data signal transmitted from the data control circuit 130 via the multiple data lines DL. The display panel 110 can comprise several pixels arranged in a matrix, and each pixel can contain subpixels SP of different colors. For example, the multiple subpixels SP can include multiple red subpixels, multiple green subpixels, multiple blue subpixels, and multiple white subpixels. Each subpixel SP can be defined by multiple data lines DL and multiple gate lines GL. Each pixel can contain four subpixels (SP) in red, green, blue, and white. If the display board's resolution is 2160 × 3840, it can contain a total of 15,360 data lines (DL), since 3,840 data lines (DL) are provided for each of the four subpixels (SP) and 2,160 gate lines (GL). Each subpixel (SP) can be located at an intersection of the gate lines (GL) and the data lines (DL). The gate control circuit 120 is controlled by the timing controller 140 and can control a timing specification of the several subpixels SP by sequentially outputting sampling signals to the several gate lines GL, which are arranged in the display panel 110. Depending on the control method of the display panel 110, the gate control circuit 120 can be arranged on one side or on both sides of the display panel 110. For example, the gate control circuit 120 can be implemented in a frame area of ​​the display panel 110 using a GIP (gate-driver-in-panel) method or a TAB (tape-automated bonding) method, but the embodiments of the present disclosure are not limited thereto. The data control circuit 130 can receive image data DATA from the timing controller 140 and convert the received image data DATA into an analog data signal (or a data voltage). The data control circuit 130 outputs data signals synchronously with a timing signal, to which sampling signals are applied via gate lines GL, to the respective data lines DL, so that each subpixel SP connected to the data lines DL can display a light emission signal with a brightness corresponding to the data signals. According to one embodiment of the present disclosure, the data control circuit 130 can comprise a first data signal with an initialization voltage and a second data signal with a data voltage.For example, the data control circuit 130 can supply a first data signal with an initialization voltage to the data lines DL during an initialization period of each pixel and supply a second data signal with a data voltage to the data lines DL during a data programming period of each pixel. The data control circuit 130 can comprise one or more integrated source control circuits SDICs. The integrated source control circuit SDIC can be connected to bonding points of the display panel 110 by a TAB (tape-automated bonding) or COF (chip-on-film) method, or it can be arranged directly on the display panel 110, but the embodiments of the present disclosure are not limited thereto. The timing controller 140 can supply various control signals to the gate drive circuit 120 and the data drive circuit 130 and control the operation of the gate drive circuit 120 and the data drive circuit 130. For example, the timing controller 140 can control the gate drive circuit 120 to output sampling signals according to the timing implemented in each frame and to supply digital image data (DATA) received from an external source to the data drive circuit 130. The timing controller 140 can receive various timing signals, including image data DATA, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data release signal DE, and a master clock MCLK, from an external host system 200. The host system 200 can be, for example, a television system TV, a side-by-side display, a navigation system, a personal computer PC, a home theater system, a mobile device, and / or a portable device, but the embodiments of the present disclosure are not limited to these. The timing controller 140 can generate control signals using various timing signals received from the host system 200 and supply the control signals to the gate control circuit 120 and the data control circuit 130. The timing controller 140 can output various gate control signals to control the gate drive circuit 120. These include a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE. For example, the gate start pulse GSP can control the timing at which the gate drive circuit 120 begins operation. The gate clock GCLK is a clock signal that is input to the gate drive circuit 120 and can control the offset timing of the sampled signals. The gate output enable signal GOE can control the output timing of the gate drive circuit 120. The timing controller 140 can output various data control signals to control the data control circuit 130, including a source start pulse (SSP), a source sample clock (SCLK), and a source output enable signal (SOE). For example, the source start pulse (SSP) can control the timing at which the data control circuit 130 begins data sampling. The source sample clock (SCLK) can be a clock signal that controls the timing for data sampling in the data control circuit 130. The source output enable signal (SOE) can control the output timing of the data control circuit 130. The light-emitting display device 100 according to an embodiment of the present disclosure may include a power management circuit 150 designed to supply different voltages or currents to the display panel 110, the gate drive circuit 120 and the data drive circuit 130, or to control the supply of different voltages or currents to them. The power management circuit 150 can generate the power required to drive the display panel 110, the gate drive circuit 120 and the data drive circuit 130 by adjusting a DC input voltage Vin supplied from the host system 200. Fig. 2 shows a circuit configuration of a subpixel according to an embodiment of the present disclosure. With reference to Fig. 2, the light-emitting display device according to an embodiment of the present disclosure comprises several subpixels SP forming a unit pixel, and each of the several subpixels SP can include a pixel circuit comprising a drive transistor DT, a first switching transistor ST1, a second switching transistor ST2, a first capacitor Cst and a second capacitor Cds, as well as a light-emitting device ED. At least one of the transistors DT, ST1, and ST2 included in the pixel circuit can be a three-electrode device comprising a gate, a source, and a drain. The source and drain electrodes are not fixed and can change depending on the voltage applied to the gate electrode and the current direction. Accordingly, one of the source and drain electrodes can be designated as the first electrode and the other as the second electrode. At least one of the transistors DT, ST1, and ST2 can be implemented as an oxide thin-film transistor with an oxide semiconductor, as a low-temperature polysilicon LTPS TFT with low-temperature polysilicon, or the like. Furthermore, at least one transistor DT, ST1, and ST2 can be a P-type or an N-type transistor, or a combination of P-type and N-type transistors, but the embodiments of the present disclosure are not limited thereto. The at least one transistor DT, ST1, and ST2 can be switched to the ON or OFF state by a sampling signal (or gate signal) applied to the gate electrode. The sampling signal can oscillate between a gate-in voltage and a gate-out voltage. The gate-in voltage is set higher than a threshold voltage of the at least one transistor DT, ST1, and ST2, and the gate-out voltage is set lower than the threshold voltage of the at least one transistor DT, ST1, and ST2. The at least one transistor DT, ST1, and ST2 can be turned on in response to the gate-in voltage or turned off in response to the gate-out voltage. For example, in the case of an N-type transistor, the gate-in voltage can be a gate-high voltage VGH, and the gate-out voltage can be a gate-low voltage VGL. In the case of a P-type transistor, the gate-on voltage can be the gate-low voltage VGL and the gate-off voltage can be the gate-high voltage VGH. The light-emitting device ED can comprise a pixel electrode (a first electrode or an anode electrode) connected to the pixel circuit, a common electrode (a second electrode or a cathode electrode) connected to a common voltage line CVL, and an emissive layer between the pixel electrode and the common electrode. The pixel electrode can be an independent electrode for each individual light-emitting device, and the common electrode can be a common electrode for all light-emitting devices. The light-emitting device ED can produce light with a predetermined luminance corresponding to a quantity of current supplied by the pixel circuit. The driver transistor DT can be connected between a drive voltage line DVL (a first power voltage line) and the light-emitting device ED. The driver transistor DT is a control element that regulates a current flowing through the light-emitting device ED according to a gate-source voltage Vgs and can have a first node N1 (or gate node) to which a data signal Vdata is applied, a second node N2 (or source node) connected to a pixel electrode of the light-emitting device ED, and a third node N3 (or drain node) connected to the drive voltage line DVL and supplied with a drive power voltage EVDD (or first power voltage). The first switching transistor ST1 can be connected between the first node N1 of the driver transistor DT and a data line DL. The first switching transistor ST1 can connect the data line DL to the first node N1. For example, the first switching transistor ST1 can be switched on by a first sampling signal Scan1 and deliver the data signal Vdata applied via the data line DL to the first node N1, which is a gate electrode of the driver transistor DT. The second switching transistor ST2 can be connected between the second node N2 of the driver transistor DT and the data line DL. The second switching transistor ST2 can connect the data line DL to the second node N2. For example, the second switching transistor ST2 can be switched on by a second scanning signal Scan2 and supply the data signal Vdata applied via the data line DL to the second node N2, which is a source electrode of the driver transistor DT. The first capacitor Cst can be connected between the first node N1 and the second node N2 of the driver transistor DT. The first capacitor Cst can be a storage capacitor that maintains a voltage of the data signal Vdata, which is supplied to the driver transistor DT during a single frame. The first capacitor Cst can maintain a constant voltage difference between the first node N1 and the second node N2 of the driver transistor DT. For example, the first capacitor Cst can store the voltage of the data signal Vdata, which is supplied via the first switching transistor ST1, and turn on the driver transistor DT using the stored voltage. The second capacitor Cds can be connected between the third node N3 and the second node N2 of the driver transistor DT. The second capacitor Cds can serve to compensate for a voltage across the second node N2 of the driver transistor DT. The second capacitor Cds can be designed to limit a voltage rise across the second node N2 during a data voltage programming operation, ensuring that the gate-source voltage Vgs of the driver transistor DT is at a suitable level. The voltage across the second node N2 can correspond to the capacitance of the second capacitor Cds. For example, the voltage across the second node N2 can be determined proportionally to the capacitance of the second capacitor Cds. Furthermore, the second node N2 can be electrically floating when the second switching transistor ST2 is off, thus reflecting an electrical characteristic of the driver transistor DT based on the second capacitor Cds.For example, the electrical property of the drive transistor DT may include a threshold voltage or a mobility of the drive transistor DT. The light-emitting display device according to one embodiment of the present disclosure can omit a reference voltage line from the second node N2 of the driver transistor DT and can be configured to initialize the first node N1 and the second node N2 of the driver transistor DT using the data signal Vdata via the data line DL. Accordingly, during the programming of the data voltage, when the first switching transistor ST1 is on and the second switching transistor ST2 is off, the light-emitting display device can cause the second node N2 to be electrically suspended, and the voltage of the second node N2 can rise due to the data voltage at the first node N1, thereby decreasing the gate-source voltage Vgs of the driver transistor DT.For example, reducing the gate-source voltage Vgs of the driver transistor DT can decrease the data transmission rate, which can lead to problems such as a shortened emission time and a reduction in the luminance of the light-emitting device. The data transmission rate can also refer to a ratio of the gate-source voltage Vgs, which is based on the difference between a data voltage and an initialization voltage. The second capacitor Cds according to one embodiment of the present disclosure can limit a voltage rise at the second node N2 during the programming of the data voltage and thereby maintain the gate-source voltage Vgs of the drive transistor DT at a suitable level. As a result, the electrical characteristics of the drive transistor DT can be reflected at the second node N2, and the sampling of the threshold voltage of the drive transistor DT and the programming of the data voltage can be performed simultaneously. Fig. 3 illustrates a control time specification of a subpixel according to an embodiment of the present disclosure. Referring to Fig. 3, several subpixels SP can be controlled according to an embodiment of the present disclosure according to a first period P1, a second period P2 and a third period P3. Each subpixel SP can receive a drive voltage EVDD, a common power voltage EVSS, a data signal Vdata which has an initialization voltage and a data voltage, a first sampling signal Scan1 and a second sampling signal Scan2. The first sampling signal, Scan1, can be a signal for controlling the first switching transistor, ST1, and the second sampling signal, Scan2, can be a signal for controlling the second switching transistor, ST2. The first and second sampling signals, Scan1 and Scan2, can be supplied by the gate drive circuit 120. For example, the first and second sampling signals, Scan1 and Scan2, can have a gate-on voltage or a gate-off voltage at predetermined time intervals. For example, the gate-on voltage can be a gate high voltage of 24 V, which turns on a transistor, and the gate-off voltage can be a gate low voltage of -6 V, which turns off a transistor, but the embodiments of the present disclosure are not limited thereto. The data signal Vdata can comprise a first data signal with an initialization voltage (or a reference voltage) and a second data signal with a data voltage. For example, the initialization voltage of the first data signal can be a voltage to initialize the first node N1 and the second node N2 of the driver transistor DT and can be 0 V, but the embodiments of the present disclosure are not limited thereto. Furthermore, the data voltage of the second data signal can be a voltage applied to the first node N1 of the driver transistor DT to cause the light-emitting device ED to emit light with a predetermined luminance and can be higher than the initialization voltage. The drive voltage EVDD can be a high potential voltage and be 24 V, and the common power voltage EVSS can be a low potential voltage, lower than the drive voltage EVDD, and be 0 V, but embodiments of the present disclosure are not limited thereto. The first period P1 can be an initialization period for initializing the first node N1 and the second node N2 of the drive transistor DT. During the first period P1, the first sample signal Scan1 and the second sample signal Scan2 can have the gate drive voltage, and the data signal Vdata can be the first data signal with the initialization voltage. For example, the first period P1 can begin at the time the first data signal (or the initialization voltage) is applied, overlap with an on-state of the first and second sample signals Scan1 and Scan2, and end at the time the second sample signal Scan2 is switched off. For example, the first and second sample signals Scan1 and Scan2 can be switched on before the first period P1, but embodiments of the present disclosure are not limited to this. The second period P2 can be a data programming period for programming the data voltage into the pixel circuit. Furthermore, data programming and the sampling of an electrical property of the drive transistor DT can be performed simultaneously during the second period P2. In the second period P2, the first sampling signal Scan1 can maintain the gate turn-on voltage, the second sampling signal Scan2 can have the gate turn-off voltage, and the data signal Vdata can be the second data signal along with the data voltage. For example, the second period P2 can begin at the time the second data signal (or data voltage) is applied, overlap with the on state of the first sampling signal Scan1, and end at the time the first sampling signal Scan1 switches to an off state.For example, the second scanning signal Scan2 can be switched to the off state before the second period P2, but embodiments of the present disclosure are not limited to this. The third period P3 can be a light emission period for driving the light-emitting device ED so that it emits light. During the third period P3, the first and second sampling signals Scan1 and Scan2 can maintain the gate-off voltage, and the data signal Vdata can be the second data signal along with the data voltage. For example, the third period P3 can begin when the first sampling signal Scan1 is switched to an off state, continue while the second data signal (or data voltage) is maintained, and end when the first and second sampling signals Scan1 and Scan2 are switched to an on state. Fig. 4 shows an operating state of a pixel circuit in a first period of the subpixel shown in Fig. 3 according to an embodiment of the present disclosure. Fig. 5 shows voltage changes of nodes in the pixel circuit shown in Fig. 4 according to an embodiment of the present disclosure. Referring to Figures 4 and 5, in the first period P1 of subpixel SP, the first switching transistor ST1 can be switched on by the first sampling signal Scan1, which is applied with a gate-on voltage, and the second switching transistor ST2 can be switched on by the second sampling signal Scan2, which is applied with a gate-on voltage. Additionally, the data line DL can receive a first data signal with an initialization voltage IV. During the first period P1, since the first and second switching transistors ST1 and ST2 are switched on, the initialization voltage IV (or the first data signal) can be supplied to the first node N1 and the second node N2 of the drive transistor DT. Accordingly, the voltage D1 of the first node N1 and the voltage D2 of the second node N2 can be initialized to the initialization voltage IV. Fig. 6 shows an operating state of a pixel circuit in a second period of the subpixel shown in Fig. 3 according to an embodiment of the present disclosure. Fig. 7 shows voltage changes of nodes in the pixel circuit shown in Fig. 6 according to an embodiment of the present disclosure. Referring to Figures 6 and 7, in the second period P2 of subpixel SP2, the first switching transistor ST1 can be held in an on state by the first sampling signal Scan1, which maintains the gate-on voltage, and the second switching transistor ST2 can be switched off by the second sampling signal Scan2, which switches to the gate-off voltage. Additionally, the data line DL can receive a second data signal with a data voltage DV. During the second period P2, since the first switching transistor ST1 remains on, the data voltage DV (or the second data signal) can be applied to the first node N1 of the driver transistor DT. Furthermore, the second node N2 of the driver transistor DT can be made electrically floating, since the second switching transistor ST2 is off. In the second period P2, the second node N2 of the driver transistor DT can be electrically floating and reflect an electrical property of the driver transistor DT based on the second capacitor Cds. For example, the electrical property of the driver transistor DT can include a threshold voltage or a mobility of the driver transistor DT. During the second period P2, the data voltage DV (or the second data signal) for data programming can be applied to the first node N1 of the driver transistor DT, and the voltage D1 of the first node N1 can rise to the data voltage DV. The programmed data voltage DV can be stored in the first capacitor Cst. The second node N2 of the driver transistor DT can be made electrically floating. Since the gate-source voltage Vgs of the driver transistor DT is greater than the threshold voltage Vth of the driver transistor DT, current can flow between the third node N3 and the second node N2 of the driver transistor DT, and the voltage D2 of the second node N2 can rise to the threshold voltage Vth of the driver transistor DT. Accordingly, a sampling voltage (Vth sampling), which reflects the threshold voltage Vth of the driver transistor DT, can be stored in the second node N2.For example, the sampling voltage (Vth sampling), which reflects the electrical property of the drive transistor DT, can be stored on the basis of the second capacitor Cds in the second node N2. The second capacitor Cds according to one embodiment of the present disclosure can be configured to limit the voltage rise of the second node N2 during the second period P2, thereby maintaining the gate-source voltage Vgs of the drive transistor DT at a suitable level. As a result, an electrical characteristic of the drive transistor DT can be reflected in the second node N2, and the sampling of the threshold voltage of the drive transistor DT and the data programming can be performed simultaneously. Fig. 8 shows an operating state of a pixel circuit in a third period of the subpixel shown in Fig. 3 according to an embodiment of the present disclosure. Fig. 9 shows voltage changes of nodes in the pixel circuit shown in Fig. 8 according to an embodiment of the present disclosure. Referring to Fig. 8 and Fig. 9, in the third period P3 of subpixel SP the first and second switching transistors ST1 and ST2 can maintain an off state and the data line DL can receive a second data signal with a data voltage DV. During the third period P3, the control transistor DT can be switched on according to the data voltage DV programmed into the first capacitor Cst and generate a control current from the control power voltage EVDD supplied via the control power line DVL and deliver the control current to the light-emitting device ED. During the third period P3, the gate-source voltage Vgs of the drive transistor DT can be kept constant by the first capacitor Cst. Fig. 10 shows voltage changes of nodes in the pixel circuit according to a further embodiment of the present disclosure. Fig. 11 shows voltage changes of nodes in the pixel circuit according to a further embodiment of the present disclosure. Referring to Fig. 10 and Fig. 11, according to a further embodiment of the present disclosure, the second capacitor Cds can compensate a voltage of a second node N2 of the drive transistor DT according to a capacitance of the second capacitor Cds. If the capacitance of the second capacitor Cds is designed to be small, a voltage D2 of the second node N2 can be stored as a sampling voltage (Vth sampling) that adequately reflects a threshold voltage Vth of the drive transistor DT, as shown in Fig. 10. For example, the capacitance of the second capacitor Cds can be less than or equal to 1 pF, but the embodiments of the present disclosure are not limited to this. Accordingly, the gate-source voltage Vgs of the drive transistor DT can be reduced by increasing the voltage D2 of the second node N2.Therefore, if the capacitance of the second capacitor Cds is small, the sampling characteristic of the drive transistor DT can be improved, but the luminance of the light-emitting device ED can be slightly reduced due to a decrease in the gate-source voltage Vgs, leading to a reduction in the data transmission rate. If the capacitance of the second capacitor Cds is designed to have a large value, the voltage D2 of the second node N2 may approach an initialization voltage IV, and a threshold voltage Vth of the drive transistor DT may not be sampled, as shown in Fig. 11. For example, the capacitance of the second capacitor Cds may be greater than or equal to 1 pF, but the embodiments of the present disclosure are not limited to this. Accordingly, the gate-source voltage Vgs of the drive transistor DT may be increased due to a reduction in the voltage D2 of the second node N2.Therefore, if the capacitance of the second capacitor Cds is large, a sampling characteristic of the drive transistor DT may not be reflected, but the luminance of the light-emitting device ED can be improved due to an increase in the gate-source voltage Vgs, leading to an increase in the data transmission rate. Fig. 12 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Fig. 13 is a sectional view along line II' shown in Fig. 12 according to a further embodiment of the present disclosure. Referring to Figures 12 and 13, the display panel 110, according to a further embodiment of the present disclosure, can be configured as a downward-emitting display panel and implemented in a structure that, by excluding a reference voltage line, ensures design flexibility for a voltage line and improves the aperture of a light-emitting section. Although Figures 12 and 13 describe the display panel 110 as a downward-emitting display panel, the embodiments of the present disclosure are not limited thereto and can also be implemented as an upward-emitting display panel. Referring to Fig. 12, the display panel 110, according to a further embodiment of the present disclosure, can comprise several subpixels SP1, SP2, SP3, and SP4, which express different colors and form a unit pixel. The several subpixels SP1, SP2, SP3, and SP4 can be arranged in a strip-like fashion along a first direction (or an X-axis direction) or a second direction (or a Y-axis direction). For example, the several subpixels SP1, SP2, SP3, and SP4 can be arranged along the first direction (or the X-axis direction), but embodiments of the present disclosure are not limited thereto, and an arrangement order or design configuration can be modified in various ways. Each of the multiple subpixels SP1, SP2, SP3, and SP4 can comprise a light-emitting device ED with a pixel electrode AE, an emissive layer, and a common electrode, as well as a pixel circuit with at least one transistor DT, ST1, and ST2, a first capacitor Cst, and a second capacitor Cds. The multiple subpixels SP1, SP2, SP3, and SP4 can also comprise at least one gate line GL1 and GL2, multiple data lines DL1, DL2, DL3, and DL4, and a gate drive voltage line DVL.For example, in the display panel 110, a section in which the light-emitting device ED is located can be an emission area (or an aperture area), a section in which the pixel circuitry is located can be a circuit area (or a first non-emission area), and a section in which the multiple data lines DL1, DL2, DL3 and DL4 as well as the drive voltage line DVL are located can be a line area (or a second non-emission area). According to a further embodiment of the present disclosure, the display panel 110 can be implemented as a downward-emitting type, and the emission area (or aperture area) in which the light-emitting device ED is arranged and the circuit area (or first non-emission area) in which the pixel circuit is arranged may not overlap or may partially overlap. For example, the multiple subpixels SP1, SP2, SP3, and SP4 may be arranged in the first direction (or the X-axis direction), the emission area may be arranged on a top side in the second direction (or the Y-axis direction), and the circuit area may be arranged on a bottom side in the second direction, but embodiments of the present disclosure are not limited thereto. According to a further embodiment of the present disclosure, the at least one transistor DT, ST1 and ST2 and the first capacitor Cst of the pixel circuit can be arranged in the circuit region (or the first non-emission region), the at least one gate line GL1 and GL2 can be arranged in the circuit region (or the first non-emission region), and the second capacitor Cds of the pixel circuit can be arranged in the line region (or the second non-emission region). For example, the second capacitor Cds in the line region (or the second non-emission region) can be arranged such that it overlaps with the drive voltage line DVL. The at least one gate line GL1 and GL2 can be arranged to overlap the circuit area. For example, the at least one gate line GL1 and GL2 can extend in the first direction (or X-axis direction) such that it crosses the circuit area. The at least one gate line GL1 and GL2 can comprise a first gate line GL1 and a second gate line GL2. The first gate line GL1 can supply a first sample signal Scan1 to the first switching transistor ST1 of each subpixel SP1, SP2, SP3, and SP4, and the second gate line GL2 can supply a second sample signal Scan2 to the second switching transistor ST2 of each subpixel SP1, SP2, SP3, and SP4. The multiple data lines DL1, DL2, DL3, and DL4 can be arranged between the multiple subpixels SP1, SP2, SP3, and SP4. For example, the first and second data lines DL1 and DL2 can extend in the second direction (or Y-axis direction) between the first subpixel SP1 and the second subpixel SP2. The first data line DL1 can be located on the right side of the first subpixel SP1 to deliver a data signal to the first subpixel SP1, and the second data line DL2 can be located on the left side of the second subpixel SP2 to deliver a data signal to the second subpixel SP2. Additionally, a third and a fourth data line DL3 and DL4 can extend in the second direction (or Y-axis direction) between the third subpixel SP3 and the fourth subpixel SP4.The third data line DL3 can be located on the right side of the third subpixel SP3 to provide a data signal to the third subpixel SP3, and the fourth data line DL4 can be located on the left side of the fourth subpixel SP4 to provide a data signal to the fourth subpixel SP4. The drive voltage line DVL can be located within the multiple subpixels SP1, SP2, SP3, and SP4. For example, the drive voltage line DVL can extend in the second direction (or Y-axis direction) between the second subpixel SP2 and the third subpixel SP3. The drive voltage line DVL can supply a drive voltage EVDD to each of the subpixels SP1, SP2, SP3, and SP4 via a drive voltage bridge line DVBL extending in the first direction (or X-axis direction). The pixel circuit of each subpixel SP1, SP2, SP3 and SP4 can include a drive transistor DT, a first switching transistor ST1, a second switching transistor ST2, a first capacitor Cst and a second capacitor Cds. The driver transistor DT can be located on one side of the circuit area. A gate electrode of the driver transistor DT can be connected to one end of the first capacitor Cst and a source electrode of the first switching transistor ST1. A drain electrode of the driver transistor DT can be connected to the gate drive voltage line DVBL, which extends from the drive voltage line DVL, and a source electrode of the driver transistor DT can be connected to the pixel electrode AE ​​of the light-emitting device ED. The first and second switching transistors, ST1 and ST2, can be arranged on the same side of the circuit. A gate electrode of the first switching transistor, ST1, can be formed as a section of the first gate line, GL1; a drain electrode of the first switching transistor, ST1, can be connected to a data line, DL; and a source electrode of the first switching transistor, ST1, can be connected to one end of the first capacitor, Cst, and the gate electrode of the driver transistor, DT. A gate electrode of the second switching transistor, ST2, can be formed as a section of the second gate line, GL2; a drain electrode of the second switching transistor, ST2, can be connected to a data bridge line, DBL, extending from the data line, DL; and a source electrode of the second switching transistor, ST2, can be connected to the source electrode of the driver transistor, DT. The first capacitor Cst can be located in a central section of the circuit. One end of the first capacitor Cst can be connected between the gate electrode of the drive transistor DT and the source electrode of the first switching transistor ST1, and the other end of the first capacitor Cst can be connected between the source electrode of the drive transistor DT and the pixel electrode AE ​​of the light-emitting device ED. Alternatively, the other end of the first capacitor Cst can be connected to the source electrode of the second switching transistor ST2. For example, the first capacitor Cst can be configured in a dual-capacitor structure, comprising a first electrode made of the same material as a light-blocking layer, a second electrode made of a conductive active layer, and a third electrode made of the same material as the gate electrode. The second capacitor Cds can be arranged to overlap at least one section of the drive voltage line DVL. One end of the second capacitor Cds can be connected to the drive voltage line DVL, and the other end of the second capacitor Cds can be connected, via a connecting line CL running through the emission region, between the source electrode of the drive transistor DT and the pixel electrode AE ​​of the light-emitting device ED. Alternatively, the other end of the second capacitor Cds can be connected to the source electrode of the second switching transistor ST2. For example, the connecting line CL of the second capacitor Cds can be formed from a conductive active layer.The second capacitor Cds can be configured in a dual-capacitance structure comprising a first electrode formed from a section of the drive voltage line DVL, a second electrode formed from a conductive active layer, and a third electrode formed from the same material as the gate electrode. For example, the drive voltage line DVL can be formed from the same material and in the same layer as the light-blocking layer. Referring to Fig. 13, the display panel 110, according to a further embodiment of the present disclosure, can comprise a first metal layer M1 arranged on a substrate 101, a first insulating layer BF (or buffer layer) arranged on the first metal layer M1, an active layer ACT (or semiconductor layer) arranged on the first insulating layer BF, a second insulating layer GI (or gate insulating layer) arranged on the active layer ACT, and a second metal layer M2 arranged on the second insulating layer GI. Furthermore, at least one third insulating layer ILD and PAS (intermediate insulating layer or passivation layer) can be arranged on the second metal layer M2, a planarization layer PLN can be arranged on the at least one third insulating layer ILD and PAS, and the pixel electrode AE ​​can be arranged on the planarization layer PLN.Furthermore, a bank layer BA can be arranged on the planarization layer PLN and the pixel electrode AE. The first metal layer M1 can be arranged on the substrate 101 and serve as a light-blocking layer that blocks external light incident on the active layer ACT of the at least one transistor DT, ST1 and ST2. For example, the light-blocking layer can be formed as a single layer or as a multiple layer of any material including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto. The first metal layer M1 can be configured as at least one signal line or at least one power line. For example, at least one of the data line DL and the drive voltage line DVL can be formed from the first metal layer M1. Furthermore, at least one of the first electrode Cst1 of the first capacitor Cst and the first electrode Cds1 of the second capacitor Cds can be formed from the first metal layer M1. The first insulating layer BF (or buffer layer) can be arranged on the substrate 101 such that it covers the first metal layer M1. The first insulating layer BF is designed to prevent the diffusion of impurity ions and the ingress of moisture or ambient air, and to insulate the first metal layer ML1 and the active layer ACT. The first insulating layer BF can consist of a single layer or multiple layers containing an inorganic insulating material, but the embodiments described in this disclosure are not limited to this. The active layer ACT (or semiconductor layer) can be arranged on the first insulating layer BF. The active layer ACT can be formed from an oxide semiconductor material or a silicon-based semiconductor material, but the embodiments of the present disclosure are not limited thereto. The active layer ACT can form a semiconductor channel of the at least one transistor DT, ST1, and ST2. Furthermore, the active layer ACT can be conductive and configured as a conductive electrode or line. For example, at least one of the second electrodes Cst2 of the first capacitor Cst and one of the second electrodes Cds2 of the second capacitor Cds can be formed from the conductive active layer ACT. The conductive active layer ACT forming the second capacitor Cds can be arranged to overlap the drive voltage line DVL.Furthermore, the connecting line CL of the second capacitor Cds can be formed from the conductive active layer ACT. The second insulating layer GI (or gate insulating layer) can be arranged on the first insulating layer BF such that it covers at least a portion or all of the active layer ACT. For example, the second insulating layer GI can be arranged between the active layer ACT and the second metal layer M2. The second insulating layer GI can be structured together with the second metal layer M2 in a process for structuring the second metal layer M2. The second insulating layer GI is designed to prevent the diffusion of impurity ions and to insulate the active layer ACT and the second metal layer M2. The second insulating layer GI can consist of a single layer or multiple layers containing an inorganic insulating material, but the embodiments of the present disclosure are not limited thereto. The second metal layer M2 can be arranged on the second insulating layer GI. The second metal layer M2 can be arranged on the second insulating layer GI and structured together with the second insulating layer GI. The second metal layer M2 can form a gate electrode GE or a source / drain electrode SD1 and SD2 of the at least one transistor DT, ST1, and ST2. Furthermore, the second metal layer M2 can form at least one signal line or at least one power line. For example, at least one of the gate line GL, the gate drive voltage line DVL, and the gate drive voltage bridge line DVBL can be formed from the second metal layer M2. Additionally, at least one of the third electrode Cst3 of the first capacitor Cst and the third electrode Cds3 of the second capacitor Cds can be formed from the second metal layer M2.For example, the third electrode Cds3 of the second capacitor Cds can be arranged so that it overlaps the control voltage line DVL. The at least one third insulating layer ILD and PAS (intermediate insulating layer or passivation layer) can be arranged on the second metal layer M2. For example, the at least one third insulating layer ILD and PAS can comprise an intermediate insulating layer ILD and a passivation layer PAS. The at least one third insulating layer ILD and PAS can be arranged to cover a gate electrode GE and a first and second source / drain electrode SD1 and SD2 of the at least one transistor DT, ST1, and ST2. The at least one third insulating layer ILD and PAS is designed to protect the at least one transistor DT, ST1, and ST2 and can be formed from a single layer or multiple layers containing an inorganic insulating material, but the embodiments of the present disclosure are not limited thereto.For example, one of the intermediate insulating layer (ILD) and passivation layer (PAS) can be omitted. The display panel 110 according to a further embodiment of the present disclosure can omit a reference voltage line and arrange the drive voltage line DVL within the several subpixels SP1, SP2, SP3 and SP4, thereby ensuring a design flexibility of the pixel circuitry and the voltage lines and improving an aperture fraction of a light-emitting section. Fig. 14 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Fig. 15 is a cross-sectional view along line II-II' shown in Fig. 14 according to a further embodiment of the present disclosure. Figs. 14 and 15 show embodiments of the present disclosure in which a configuration of the display panel 110 in the light-emitting display device described with reference to Figs. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 to 13 is modified. In the following description with reference to Figs. 14 and 15, the same reference numerals are used for the same components, with the exception of the modified configurations, and redundant descriptions thereof are omitted or given briefly. Referring to Figures 14 and 15, the display panel 110, according to a further embodiment of the present disclosure, can be a transparent display panel configured as an upward-emitting or dual-emission type. The display panel 110 can be designed such that, by eliminating a reference voltage line, it improves the design flexibility for voltage lines and enhances the open area of ​​a light-emitting section as well as the transparency of the transmission area. Although Figures 14 and 15 depict the display panel 110 as a transparent display panel with an upward-emitting transmission area, the embodiments of the present disclosure are not limited thereto and can be implemented as a downward-emitting type or as a light-emitting display panel without a transmission area. Referring to Fig. 14, in a further embodiment of the present disclosure, several subpixels SP1, SP2, SP3, and SP4 can be arranged adjacent to one another in a first direction (or X-axis direction) and a second direction (or Y-axis direction) in the display panel 110. The several subpixels SP1, SP2, SP3, and SP4 can be arranged in a matrix in a quad format along the first and second directions. For example, a first subpixel SP1 and a second subpixel SP2 can be arranged on the left side of a drive voltage line DVL, and a third subpixel SP3 and a fourth subpixel SP4 can be arranged on the right side of the drive voltage line DVL. According to a further embodiment of the present disclosure, the display panel 110 can be implemented as a transparent, upward-emitting display panel and comprise a non-transmittal area NTA, in which the multiple subpixels SP1, SP2, SP3, and SP4 are arranged, and a transmission area TA. For example, the multiple subpixels SP1, SP2, SP3, and SP4 can be arranged adjacent to each other in the first and second directions. Furthermore, the transmission area TA can be arranged adjacent to the multiple subpixels SP1, SP2, SP3, and SP4 in the first direction. The transmission area TA can be an area that transmits most of the incident light, and the non-transmittal area NTA can be an area that does not transmit most of the incident light.For example, the transmission area TA can be an area with a transmittance greater than a%, and the non-transmission area NTA can be an area with a transmittance less than b%. In this case, a can be a value greater than b. According to a further embodiment of the present disclosure, the light-emitting display device can, by virtue of the transmission area TA, see an object or background located on a rear surface (or back face) of the display panel 110. The non-transmission area (NTA) can include a first non-transmission area (NTA1), a second non-transmission area (NTA2), and the multiple subpixels SP1, SP2, SP3, and SP4. The first non-transmission area NTA1 can extend in the second direction (or Y-axis direction) within the display panel 110 and each of the subpixels SP1, SP2, SP3 and SP4 can be located within the first non-transmission area NTA1. The first non-transmission region NTA1 can be multiple. These multiple first non-transmission regions NTA1 can extend in the second direction and be spaced apart in the first direction (or X-axis direction). Two adjacent first non-transmission regions NTA1 can be spaced apart, with the transmission region TA located between them. For example, the transmission region TA can be located between two adjacent first non-transmission regions NTA1. At least one signal line and at least one voltage line extending in the second direction can be located within the first non-transmission region NTA1. For example, the at least one signal line can include multiple data lines DL1, DL2, DL3, and DL4, and the at least one voltage line can include a drive voltage line DVL and a common voltage line CVL. The multiple data lines DL1, DL2, DL3, and DL4 can be arranged adjacent to the multiple subpixels SP1, SP2, SP3, and SP4. For example, the first and second data lines DL1 and DL2 can be located to the left of the first and second subpixels SP1 and SP2. The first data line DL1 can be located far to the left in the first direction, and the second data line DL2 can be located between the first data line DL1 and the first and second subpixels SP1 and SP2. Furthermore, the third and fourth data lines DL3 and DL4 can be located to the right of the third and fourth subpixels SP3 and SP4. The fourth data line DL4 can be located far to the right in the first direction, and the third data line DL3 can be located between the third and fourth subpixels SP3 and SP4 and the fourth data line DL4. The drive voltage line DVL (or first power supply voltage line) can be located within the multiple subpixels SP1, SP2, SP3, and SP4. For example, the drive voltage line DVL can be located between the first and second subpixels SP1 and SP2, and the third and fourth subpixels SP3 and SP4. The drive voltage line DVL can supply a drive voltage EVDD to each of the subpixels SP1, SP2, SP3, and SP4 via a drive voltage bridge line DVBL extending in the first direction. The common voltage line CVL (or second power supply line) can supply a second power voltage EVSS to the cathode electrodes of subpixels SP1, SP2, SP3, and SP4. For example, the second power voltage EVSS can be a common power supply shared by the multiple subpixels SP1, SP2, SP3, and SP4. The common voltage line CVL can be located either to the left or right of the subpixels SP1, SP2, SP3, and SP4. For example, the common voltage line CVL can be located to the right of the multiple subpixels SP1, SP2, SP3, and SP4 and overlap at least one segment of the multiple data lines DL1, DL2, DL3, and DL4. For example, the common voltage line CVL can overlap the third and fourth data lines DL3 and DL4. The second non-transmission area NTA2 can extend in the first direction within the display panel 110 and be arranged such that it overlaps at least one section of each of the subpixels SP1, SP2, SP3, and SP4. For example, the second non-transmission area NTA2 can extend in the first direction between two adjacent first non-transmission areas NTA1. Multiple second non-transmission areas NTA2 can be provided, extending in the first direction and spaced apart in the second direction. Two adjacent second non-transmission areas NTA2 can be spaced apart, with the transmission area TA positioned between them. At least one gate line extending in the first direction can be located within the second non-transmission area NTA2 and overlap it. The multiple subpixels SP1, SP2, SP3, and SP4 can be arranged at the intersections of the first and second non-transmission regions NTA1 and NTA2 and emit light to display an image. Each of the subpixels SP1, SP2, SP3, and SP4 can comprise an emission region containing a light-emitting device ED and a circuit region CA1, CA2, CA3, and CA4 that overlaps at least one transistor DT, ST1, and ST2, and a first capacitor Cst. According to a further embodiment of the present disclosure, each subpixel SP1, SP2, SP3, and SP4 can comprise a light emission region subdivided into several regions. For example, a pixel electrode AE ​​(first electrode or anode electrode) of each of the subpixels SP1, SP2, SP3, and SP4 can comprise a first pixel electrode AE1 and a second pixel electrode AE2, which are separated from each other. The first and second pixel electrodes AE1 and AE2 can be spaced apart from each other in the first direction (or X-axis direction) or in the second direction (or Y-axis direction). For example, the first and second pixel electrodes AE1 and AE2 can be adjacent to each other in the second direction. Accordingly, each of the subpixels SP1, SP2, SP3, and SP4 can comprise two subdivided emission regions. The circuit sections CA1, CA2, CA3, and CA4 of each of the subpixels SP1, SP2, SP3, and SP4 can comprise a drive transistor DT, a first switching transistor ST1, a second switching transistor ST2, and the first capacitor Cst of a pixel circuit. A second capacitor Cds of the pixel circuit can be arranged to overlap the drive voltage line DVL. The second capacitor Cds can be arranged to overlap at least one section of the gate voltage line DVL. One end of the second capacitor Cds can be connected to the gate voltage line DVL, and the other end of the second capacitor Cds can be connected to the circuit sections CA1, CA2, CA3, and CA4 via a connecting line CL. For example, the connecting line CL of the second capacitor Cds can be formed from a conductive active layer. The second capacitor Cds can be configured in a dual-capacitor structure comprising a first electrode formed from a section of the gate gate voltage line DVL, a second electrode formed from the conductive active layer, and a third electrode formed from the same material as the gate electrode.For example, the control voltage line DVL can be made of the same material in the same layer as a light-blocking layer. The second capacitor Cds can be configured as multiple second capacitors Cds arranged on the drive voltage line DVL. These multiple second capacitors Cds can be connected to the pixel circuits CA1, CA2, CA3, and CA4 of the multiple subpixels SP1, SP2, SP3, and SP4. For example, the second capacitor Cds corresponding to the first subpixel SP1 can be located on a top side of the drive voltage line DVL adjacent to the first subpixel SP1 in the second direction (or Y-axis direction) and connected to the pixel circuit CA1 of the first subpixel SP1 via the connecting line CL, which extends to the left in the first direction (or X-axis direction).Furthermore, the second capacitor Cds, corresponding to the second subpixel SP2, can be located on the middle lower side of the drive voltage line DVL, adjacent to the second subpixel SP2 in the second direction, and connected to the pixel circuit CA2 of the second subpixel SP2 via the connecting line CL, which extends to the left in the first direction. Similarly, the second capacitor Cds, corresponding to the third subpixel SP3, can be located on the middle upper side of the drive voltage line DVL, adjacent to the third subpixel SP3 in the second direction, and connected to the pixel circuit CA3 of the third subpixel SP3 via the connecting line CL, which extends to the right in the first direction.Furthermore, the second capacitor Cds, corresponding to the fourth subpixel SP4, can be arranged on a lower side of the drive voltage line DVL adjacent to the fourth subpixel SP4 in the second direction and connected to the pixel circuit CA4 of the fourth subpixel SP4 via the connecting line CL, which extends to the right in the first direction, but the embodiments of the present disclosure are not limited thereto. For example, the second capacitors Cds, corresponding to the respective subpixels SP1, SP2, SP3 and SP4, can be configured separately from one another or connected together on the drive voltage line DVL, but the embodiments of the present disclosure are not limited thereto. The first and second pixel electrodes AE1 and AE2 of each of the subpixels SP1, SP2, SP3, and SP4, which are divided, can be electrically connected to the circuit areas CA1, CA2, CA3, and CA4 via a connection pattern CP. Furthermore, the first and second pixel electrodes AE1 and AE2 can be electrically connected to each other via the connection pattern CP. The connection pattern CP can be used to repair an obscuration in either the first or second pixel electrode AE1 or AE2. For example, the connection pattern CP can be T-shaped. One end of the connection pattern CP can branch to both sides to connect electrically to each of the first and second pixel electrodes AE1 and AE2, and the other end of the connection pattern CP can connect electrically to the circuit areas CA1, CA2, CA3, and CA4 of each of the subpixels SP1, SP2, SP3, and SP4.The connection pattern CP can block the electrical connection between a pixel electrode containing foreign material and the circuit areas CA1, CA2, CA3 and CA4 if the foreign material is present on either the first pixel electrode AE1 or the second pixel electrode AE2, thus only causing the pixel electrode with the foreign material to darken, while the other pixel electrode is repaired to function normally. Referring to Fig. 15, the display panel 110, according to a further embodiment of the present disclosure, can further comprise a third metal layer M3. For example, at least one third insulating layer ILD and PAS can comprise an intermediate insulating layer ILD and a passivation layer PAS, and the third metal layer M3 can be arranged between the intermediate insulating layer ILD and the passivation layer PAS. The third metal layer M3 can be configured as at least one signal line or at least one power line. For example, the common voltage line CVL and / or the connection pattern CP can be configured in the third metal layer M3. For example, the third metal layer M3 can serve as a section of the second capacitor Cds, thereby forming a triple capacitance structure for the second capacitor Cds. The display panel 110 according to a further embodiment of the present disclosure can ensure the design freedom for the pixel circuitry and the voltage lines by excluding the reference voltage line, arranging the control voltage line DVL within the several subpixels SP1, SP2, SP3 and SP4 and overlapping the common voltage line CVL with at least one section of the data lines DL1, DL2, DL3 and DL4, and improve both the aperture fraction of the light-emitting section and the transparency of the transmission area TA. Fig. 16 shows a design of several subpixels in a display panel according to a further embodiment of the present disclosure. Fig. 17 is a cross-sectional view along line III-III' shown in Fig. 16 according to a further embodiment of the present disclosure. Figs. 16 and 17 show embodiments of the present disclosure in which the configuration of the display panel 110 is modified in the light-emitting display device described with reference to Figs. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 to 15. In the following description with reference to Fig. 16 and Fig. 17, the same reference symbols are used for the same components, with the exception of the modified configurations, and redundant descriptions of them are omitted or given briefly. Referring to Figures 16 and 17, the display panel 110, according to a further embodiment of the present disclosure, can be a transparent display panel configured as an upward-emitting or dual-emission type and implemented in a structure that, by eliminating a reference voltage line, ensures design flexibility for voltage lines and improves the aperture of the light-emitting section as well as the transparency of the transmission area. Although Figures 16 and 17 describe the display panel 110 as a transparent display panel with an upward-emitting transmission area, the embodiments of the present disclosure are not limited thereto and can be implemented as a downward-emitting type or as a light-emitting display panel without the transmission area. Referring to Fig. 16, in a further embodiment of the present disclosure, several subpixels SP1, SP2, SP3, and SP4 of the display panel 110 can be arranged in different directions, forming a cross shape or a pinwheel shape. For example, at least some of the subpixels SP1, SP2, SP3, and SP4 can be arranged in a first direction, and at least some other subpixels can be arranged in a second direction. For example, the first to third subpixels SP1, SP2, and SP3 among the several subpixels SP1, SP2, SP3, and SP4 can be arranged in the second direction, and a fourth subpixel SP4 among the several subpixels SP1, SP2, SP3, and SP4 can be arranged in the first direction. Multiple data lines DL1, DL2, DL3, and DL4 can be arranged adjacent to multiple subpixels SP1, SP2, SP3, and SP4. For example, the multiple data lines DL1, DL2, DL3, and DL4 can be arranged to the left of subpixels SP1, SP2, SP3, and SP4. For example, a first data line DL1 can be arranged far to the left in the first direction, and a fourth data line DL4 can be arranged adjacent to the first through third subpixels SP1, SP2, and SP3. A second data line DL2 can be arranged adjacent to the first data line DL1, and a third data line DL3 can be arranged adjacent to the fourth data line DL4. A drive voltage line DVL (or first power supply voltage line) can be placed between the multiple data lines DL1, DL2, DL3, and DL4. For example, the drive voltage line DVL can be placed between the first and second data lines DL1 and DL2, and the third and fourth data lines DL3 and DL4. The drive voltage line DVL can supply a drive voltage EVDD to each of the subpixels SP1, SP2, SP3, and SP4 via a drive voltage bridge line DVBL extending in the first direction. A common voltage line (CVL) can be located to the left or right of the multiple subpixels SP1, SP2, SP3, and SP4. For example, the common voltage line CVL can be located to the left of the multiple subpixels SP1, SP2, SP3, and SP4. The common voltage line CVL can overlap at least one segment of the multiple data lines DL1, DL2, DL3, and DL4. For example, the common voltage line CVL can overlap the first and second data lines DL1 and DL2. Circuit sections CA1, CA2, CA3 and CA4 of each of the subpixels SP1, SP2, SP3 and SP4 can include a drive transistor DT, a first switching transistor ST1, a second switching transistor ST2 and a first capacitor Cst of a pixel circuit, and a second capacitor Cds of the pixel signal circuit can be arranged to overlap the drive voltage line DVL. The second capacitor Cds can be arranged to overlap at least one section of the gate voltage line DVL. One end of the second capacitor Cds can be connected to the gate voltage line DVL, and the other end can be connected via a connecting line CL to circuit sections CA1, CA2, CA3, and CA4. For example, the connecting line CL of the second capacitor Cds can be formed from a conductive active layer. The second capacitor Cds can be formed in a dual-capacitance structure comprising a first electrode formed from a section of the gate gate voltage line DVL, a second electrode formed from the conductive active layer, and a third electrode formed from the same material as a gate electrode.For example, the control voltage line DVL can be made of the same material and in the same layer as a light-blocking layer. According to a further embodiment of the present disclosure, the second capacitor Cds can be configured in a triple-capacitance structure. For example, a fourth electrode, made of the same material as the common voltage line CVL, can be arranged to overlap the drive voltage line DVL to form the triple-capacitance structure. According to a further embodiment of the present disclosure, the second capacitor Cds can be arranged in the first to third subpixels SP1, SP2, and SP3, among the multiple subpixels SP1, SP2, SP3, and SP4, and can be omitted in the fourth subpixel SP4. Since, for example, the fourth subpixel SP4 is arranged in the first direction and its circuit area CA4 is extended in the first direction, the first capacitor Cst of the fourth subpixel SP4 can have a larger capacitance than those of the other subpixels SP1, SP2, and SP3, so that the second capacitor Cds, which provides additional capacitance, can be omitted. The second capacitor Cds can be configured as multiple second capacitors Cds arranged on the drive voltage line DVL. These multiple second capacitors Cds can be connected to the pixel circuits CA1, CA2, and CA3 of subpixels SP1, SP2, and SP3, respectively, within the subpixels SP1, SP2, SP3, and SP4. For example, the second capacitor Cds corresponding to the first subpixel SP1 can be located on a top side of the drive voltage line DVL, adjacent to the first subpixel SP1 in the second direction, and connected to the pixel circuit CA1 of the first subpixel SP1 via a connecting line CL extending to the right in the first direction.Furthermore, the second capacitor Cds, corresponding to the second subpixel SP2, can be arranged on a central section of the drive voltage line DVL adjacent to the second subpixel SP2 in the second direction and connected to the pixel circuit CA2 via a connecting line CL extending to the right in the first direction. Additionally, the second capacitor Cds, corresponding to the third subpixel SP3, can be arranged on a lower side of the drive voltage line DVL adjacent to the third subpixel SP3 in the second direction and connected to the pixel circuit CA3 via a connecting line CL extending to the right in the first direction, but the embodiments of the present disclosure are not limited thereto.For example, the second capacitors Cds, corresponding to the subpixels SP1, SP2 and SP3, can be configured separately or connected together to the drive voltage line DVL. Referring to Fig. 17, the display panel 110, according to a further embodiment of the present disclosure, can also comprise a third metal layer M3. The third metal layer M3 can be configured as at least one signal line or at least one power line. For example, the common voltage line CVL, the connection pattern CP, and / or the drive voltage bridge line DVBL can be configured in the third metal layer M3. For example, the third metal layer M3 can serve as a section of the second capacitor Cds, thereby forming the second capacitor Cds in a triple-capacitance structure. The second capacitor Cds can comprise a first electrode Cds1 formed from a first metal layer M1, a second electrode Cds2 formed from an active layer ACT, a third electrode Cds3 formed from a second metal layer M2, and a fourth electrode Cds4 formed from the third metal layer M3. The display panel 110 according to a further embodiment of the present disclosure can ensure design flexibility for the pixel circuitry and the voltage lines by excluding the reference voltage line, arranging the control voltage line DVL between the data lines DL1, DL2, DL3 and DL4 and overlapping the common voltage line CVL with at least one section of the data lines DL1, DL2, DL3 and DL4, and improve both the aperture fraction of the light-emitting section and the transparency of the transmission area TA. The following describes a light-emitting display device according to one or more embodiments of the present disclosure. A light-emitting display device according to one or more embodiments of the present disclosure may comprise: a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines; a data drive circuit configured to supply data signals to the data lines; and a gate drive circuit configured to supply sampling signals to the gate lines, each of the multiple subpixels comprising a light-emitting device; a drive transistor configured to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device; a first switching transistor configured to connect between a first node of the drive transistor and the data line; and a second switching transistor configured toto connect between a second node of the drive transistor, which is connected to the light-emitting device, and the data line, comprising a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node. According to one or more embodiments of the present disclosure, a voltage of the second node can correspond to a capacitance of the second capacitor. According to one or more embodiments of the present disclosure, a voltage of the second node can be proportional to a capacitance of the second capacitor. According to one or more embodiments of the present disclosure, the second node can be electrically floating when the second switching transistor is switched off, and can reflect an electrical property of the driving transistor based on the second capacitor. According to one or more embodiments of the present disclosure, the electrical property of the control transistor may comprise one or more of a threshold voltage or a mobility of the control transistor. According to one or more embodiments of the present disclosure, each of the multiple subpixels can be driven according to a first period, a second period and a third period, and the data drive circuit can be designed to supply a first data signal with an initialization voltage during the first period and to supply a second data signal with a data voltage higher than the initialization voltage during the second and third periods. According to one or more embodiments of the present disclosure, the first period can be a period in which the first node and the second node are initialized to the initialization voltage, in the second period the programming of the data voltage and the sampling of an electrical property of the control transistor are carried out simultaneously, and in the third period the light-emitting device is controlled so that it emits light on the basis of the data voltage. According to one or more embodiments of the present disclosure, the programmed data voltage can be stored in the first capacitor and a sampling voltage, which reflects the electrical properties of the drive transistor, can be stored in the second node based on the second capacitor. According to one or more embodiments of the present disclosure, the first switching transistor can be controlled by a first sampling signal supplied from the gate drive circuit, and the second switching transistor can be controlled by a second sampling signal supplied from the gate drive circuit. According to one or more embodiments of the present disclosure, the first period can begin at a time specified when the first data signal is supplied, overlap with ON states of the first and second sampling signals, and end at a time specified when the second sampling signal is switched to an OFF state. According to one or more embodiments of the present disclosure, the first and second sampling signals can be switched to an ON state before the first period. According to one or more embodiments of the present disclosure, the second period can begin at a time specified when the second data signal is supplied, overlap with an ON state of the first sampling signal, and end at a time specified when the first sampling signal is switched to an OFF state. According to one or more embodiments of the present disclosure, the second sampling signal can be switched to an OFF state before the second period. According to one or more embodiments of the present disclosure, the third period can begin at a time at which the first sampling signal is switched to an OFF state, during the third period the second data signal can be maintained, and the third period can end at a time at which the first and second sampling signals are switched to an ON state. According to one or more embodiments of the present disclosure, the gate lines can extend in a first direction, the data lines and the gate drive voltage lines can extend in a second direction that intersects the first direction, the multiple subpixels can be arranged in the first direction or the second direction, and the gate drive voltage lines can be arranged within the multiple subpixels. According to one or more embodiments of the present disclosure, the multiple subpixels can comprise a first subpixel, a second subpixel, a third subpixel and a fourth subpixel, and the control voltage line can be arranged between a second data line of the second subpixel and a third data line of the third subpixel. According to one or more embodiments of the present disclosure, the second capacitor can be a double-capacitance structure or a triple-capacitance structure that overlaps at least one section of the drive voltage line. According to one or more embodiments of the present disclosure, the light-emitting device may comprise a pixel electrode, an emission layer and a common electrode, wherein the light-emitting device may further comprise a common voltage line connected to the common electrode and the common voltage line may extend in the second direction and be arranged to overlap at least one section of the data lines. According to one or more embodiments of the present disclosure, the display panel may comprise a substrate, a first metal layer on the substrate, a first insulating layer on the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, a second metal layer on the second insulating layer, a third insulating layer on the second metal layer, and a third metal layer on or in the third insulating layer. According to one or more embodiments of the present disclosure, at least one of the data lines and the control voltage lines can be formed from the first metal layer, the control transistor can be formed from the semiconductor layer and the second metal layer, the first capacitor can be formed from the first metal layer, the semiconductor layer contained in the control transistor and the second metal layer contained in the control transistor, and the second capacitor can be formed from the first metal layer contained in the control voltage line, the semiconductor layer overlapping the control voltage line, and the second metal layer overlapping the control voltage line. According to one or more embodiments of the present disclosure, the second capacitor can be electrically connected to the second node of the control transistor via a connecting line made of the same material as the semiconductor layer. According to one or more embodiments of the present disclosure, the light-emitting display may further comprise a common voltage line formed from the third metal layer and overlapping at least one section of the data lines, and the second capacitor may be formed from the first metal layer contained in the drive voltage line, the semiconductor layer overlapping the drive voltage line, the second metal layer overlapping the drive voltage line, and the third metal layer overlapping the drive voltage line. According to one or more embodiments of the present disclosure, the third insulating layer may comprise an intermediate insulating layer and a passivation layer, and the third metal layer is arranged between the intermediate insulating layer and the passivation layer. A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel having several subpixels connected by data lines, gate lines, and gate drive voltage lines; wherein the several subpixels comprise at least one first subpixel arranged along a first direction and several second subpixels arranged along a second direction intersecting the first direction, each of the several subpixels comprising a light-emitting device and a subpixel circuit configured to drive the light-emitting device, the subpixel circuit of the at least one first subpixel arranged along the first direction comprising: a drive transistor configured toto connect between the drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, a second switching transistor designed to connect between a second node of the drive transistor connected to the light-emitting device and the data line, a first capacitor connected between the first node and the second node, and wherein the subpixel circuit of each of the several second subpixels arranged along the second direction comprises the drive transistor, the first switching transistor, the second switching transistor, the first capacitor, and a second capacitor connected between a third node of the drive transistor connected to the drive voltage line,and is connected to the second node, includes. According to one or more embodiments of the present disclosure, the capacitance of the first capacitor in the subpixel circuit of the at least one first subpixel can be greater than the capacitance of the first capacitor in the subpixel circuit of each of the several second subpixels. A pixel circuit according to one or more embodiments of the present disclosure can be configured to control a light-emitting device and can include a drive transistor configured to connect between a drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor configured to connect between a first node of the drive transistor and a data line, a second switching transistor configured to connect between a second node of the drive transistor connected to the light-emitting device and the data line, a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor connected to the drive voltage line.and is connected to the second node, include. The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be implemented by those skilled in the art by combining or modifying other embodiments. Therefore, content related to such combination and modification shall be interpreted as falling within the scope of this disclosure. It will be apparent to those skilled in the art that various modifications and variations of the present disclosure are possible. Therefore, the present disclosure is intended to cover the modifications and variations of this disclosure, including those of the appended claims and their equivalents. These and other modifications can be made to the embodiments, taking into account the description given above. In general, the terms used in the following claims are not to be interpreted as limiting the claims to the specific embodiments disclosed in the description and the claims, but rather as encompassing all possible embodiments together with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0197613

[0001]

Claims

Light-emitting display device comprising: a display panel (110) with multiple subpixels (SP1, SP2, SP3, SP4) connected to data lines (DL), gate lines (GL) and gate drive voltage lines (DVL); a data drive circuit (130) designed to supply data signals to the data lines (DL); and a gate drive circuit (120) designed to supply scanning signals (Scan1, Scan2) to the gate lines (GL), each of the several subpixels (SP1, SP2, SP3, SP4) comprising: a light-emitting device (ED); a drive transistor (DT) designed to connect between the drive voltage line (DVL) and the light-emitting device (ED) and to control a current flowing through the light-emitting device (ED); a first switching transistor (ST1) designed to connect between a first node (N1) of the drive transistor (DT) and the data line (DL);a second switching transistor (ST2) designed to connect between a second node (N2) of the drive transistor (DT), which is connected to the light-emitting device (ED), and the data line (DL); a first capacitor (Cst) connected between the first node (N1) and the second node (N2); and a second capacitor (Cds) connected between a third node (N3) of the drive transistor (DT), which is connected to the drive voltage line (DVL), and the second node (N2). Light-emitting display device according to claim 1, wherein a voltage of the second node (N2) corresponds to a capacitance of the second capacitor (Cds). Light-emitting display device according to claim 2, wherein a voltage of the second node (N2) is determined proportionally to a capacitance of the second capacitor (Cds). Light-emitting display device according to claim 1, wherein the second node (N2) is designed to be electrically floating when the second switching transistor (ST2) is switched off, in order to reflect an electrical property of the drive transistor (DT) based on the second capacitor (Cds), wherein the electrical property of the drive transistor (DT) preferably comprises at least one threshold voltage or mobility of the drive transistor (DT). Light-emitting display device according to claim 1, wherein each of the several subpixels (SP1, SP2, SP3, SP4) is driven according to a first period (P1), a second period (P2) and a third period (P3), and wherein the data drive circuit (130) is designed to supply a first data signal with an initialization voltage during the first period (P1) and to supply a second data signal with a data voltage that is higher than the initialization voltage during the second and third periods (P2, P3). Light-emitting display device according to claim 5, wherein the first period (P1) is an initialization period for setting the first node (N1) and the second node (N2) to the initialization voltage, wherein in the second period (P2) the data voltage is programmed simultaneously with the sampling of an electrical property of the drive transistor (DT), and wherein in the third period (P3) the light-emitting device (ED) is driven such that it emits light on the basis of the data voltage, wherein the programmed data voltage is preferably stored in the first capacitor (Cst), and wherein a sampling voltage (Vth sampling), which represents the electrical property of the drive transistor (DT), is stored on the basis of the second capacitor (Cds) in the second node (N2). Light-emitting display device according to claim 5, wherein the first switching transistor (ST1) is designed to be controlled by a first scanning signal (Scan1) supplied from the gate control circuit (120), and wherein the second switching transistor (ST2) is designed to be controlled by a second scanning signal (Scan2) supplied from the gate control circuit (120). Light-emitting display device according to claim 7, wherein the first period (P1) begins at a time at which the first data signal is supplied, overlaps with ON states of the first and second scanning signals (Scan1, Scan2) and ends at a time at which the second scanning signal (Scan2) is switched to an OFF state, wherein the first and the second scanning signals (Scan1, Scan2) are preferably switched to an ON state before the first period (P1). Light-emitting display device according to claim 7, wherein the second period (P2) begins at a time at which the second data signal is supplied, overlaps with an ON state of the first scanning signal (Scan1) and ends at a time at which the first scanning signal (Scan1) is switched to an OFF state, wherein the second scanning signal (Scan2) is preferably switched to an OFF state before the second period (P2). Light-emitting display device according to claim 7, wherein the third period (P3) begins at a time at which the first scanning signal (Scan1) is switched to an OFF state, during the third period (P3) the second data signal is maintained, and the third period (P3) ends at a time at which the first and second scanning signals (Scan1, Scan2) are switched to an ON state. Light-emitting display device according to claim 1, wherein the gate lines (GL) extend in a first direction (X), wherein the data lines (DL) and the gate drive voltage lines (DVL) extend in a second direction (Y) intersecting the first direction (X), wherein the multiple subpixels (SP1, SP2, SP3, SP4) are arranged in the first direction (X) or the second direction (Y), and wherein the drive voltage lines (DVL) are arranged within the multiple subpixels (SP1, SP2, SP3 and SP4). Light-emitting display device according to claim 11, wherein the multiple subpixels (SP1, SP2, SP3, SP4) comprise a first subpixel (SP1), a second subpixel (SP2), a third subpixel (SP3) and a fourth subpixel (SP4), and wherein the drive voltage line (DVL) is arranged between a second data line (DL2) of the second subpixel (SP2) and a third data line (DL3) of the third subpixel (SP3), wherein the second capacitor (Cds) is preferably a double-capacitance structure or a triple-capacitance structure that overlaps at least one section of the drive voltage line (DVL). Light-emitting display device according to claim 11, wherein the light-emitting device (ED) comprises a pixel electrode (AE), an emission layer and a common electrode, wherein the light-emitting device (ED) further comprises a common voltage line (CVL) connected to the common electrode, and wherein the common voltage line (CVL) extends in the second direction (Y) and is arranged to overlap at least one section of the data lines (DL). Light-emitting display device according to claim 1, wherein the display panel (110) comprises: a substrate (101); a first metal layer (M1) on the substrate (101); a first insulating layer (BF) on the first metal layer (M1); a semiconductor layer (ACT) on the first insulating layer (BF); a second insulating layer (GI) on the semiconductor layer (ACT); a second metal layer (M2) on the second insulating layer (GI); a third insulating layer (ILD, PAS) on the second metal layer (M2); and a third metal layer (M3) on or within the third insulating layer (ILD, PAS). Light-emitting display device according to claim 19, wherein at least one of the data lines (DL) and the drive voltage lines (DVL) is formed from the first metal layer (M1), wherein the drive transistor (DT) is formed from the semiconductor layer (ACT) and the second metal layer (M2), wherein the first capacitor (Cst) is formed from the first metal layer (M1), the semiconductor layer (ACT) contained in the drive transistor (DT), and the second metal layer (M2) contained in the drive transistor (DT), and wherein the second capacitor (Cds) is formed from the first metal layer (M1) contained in the drive voltage line (DVL), the semiconductor layer (ACT) overlapping the drive voltage line (DVL), and the second metal layer (M2) overlapping the drive voltage line (DVL). Light-emitting display device according to claim 15, wherein the second capacitor (Cds) is electrically connected to the second node (N2) of the drive transistor (DT) via a connecting line (CL) formed from the same material as the semiconductor layer (ACT), and / or the light-emitting display device further comprises a common voltage line (CVL) formed from the third metal layer (M3) and overlapping at least one section of the data lines (DL), wherein the second capacitor (Cds) is formed from the first metal layer (M1) contained in the drive voltage line (DVL), the semiconductor layer (ACT) overlapping the drive voltage line (DVL), the second metal layer (M2) overlapping the drive voltage line (DVL), and the third metal layer (M3) overlapping the drive voltage line (DVL). Light-emitting display device according to claim 14, wherein the third insulating layer (ILD, PAS) comprises an intermediate insulating layer (ILD) and a passivation layer (PAS), and wherein the third metal layer (M3) is arranged between the intermediate insulating layer (ILD) and the passivation layer (PAS). Light-emitting display device comprising: a display panel (110) with multiple subpixels (SP1, SP2, SP3, SP4) connected by data lines (DL), gate lines (GL) and gate drive voltage lines (DVL), wherein the multiple subpixels (SP1, SP2, SP3, SP4) comprise at least one first subpixel (SP1) arranged along a first direction (X) and multiple second subpixels (SP2) arranged along a second direction (Y) intersecting the first direction (X), wherein each of the multiple subpixels (SP1, SP2, SP3, SP4) comprises a light-emitting device (ED) and a subpixel circuit designed to drive the light-emitting device (ED), wherein the subpixel circuit of the at least one first subpixel (SP1) arranged along the first direction (X) comprises: a drive transistor (DT) designed tobetween the drive voltage line (DVL) and the light-emitting device (ED) and to control a current flowing through the light-emitting device (ED); a first switching transistor (ST1) designed to connect between a first node (N1) of the drive transistor (DT) and the data line (DL); a second switching transistor (ST2) designed to connect between a second node (N2) of the drive transistor (DT), which is connected to the light-emitting device (ED), and the data line (DL); and a first capacitor (Cst) connected between the first node (N1) and the second node (N2), wherein the subpixel circuit of each of the several second subpixels (SP2) arranged along the second direction (Y) comprises the drive transistor (DT), the first switching transistor (ST1), the second switching transistor (ST2), the first capacitor (Cst), and a second capacitor (Cds).which is connected between a third node (N3) of the drive transistor (DT), which is connected to the drive voltage line (DVL), and the second node (N2). Light-emitting display device according to claim 18, wherein the capacitance of the first capacitor (Cst) in the subpixel circuit of the at least one first subpixel (SP1) is greater than the capacitance of the first capacitor (Cst) in the subpixel circuit of each of the several second subpixels (SP2). Pixel circuit designed to control a light-emitting device (ED), the pixel circuit comprising: a drive transistor (DT) designed to connect between a drive voltage line (DVL) and the light-emitting device (ED) and to control a current flowing through the light-emitting device (ED); a first switching transistor (ST1) designed to connect between a first node (N1) of the drive transistor (DT) and a data line (DL); a second switching transistor (ST2) designed to connect between a second node (N2) of the drive transistor (DT), which is connected to the light-emitting device (ED), and the data line (DL); a first capacitor (Cst) connected between the first node (N1) and the second node (N2);and a second capacitor (Cds) connected between a third node (N3) of the drive transistor (DT), which is connected to the drive voltage line (DVL), and the second node (N2).

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