Overlaid delete block assignment

Abstract

A storage device comprising: a plurality of physical erase blocks (EBs) (518) physically subdivided into a first area (520) and a second area, the physical EBs (518) comprising: a plurality of data EBs (504) configured to store data from a user of the storage device; at least one first system EB (508) configured to store system management information for the data EBs (504); and at least one second system EB (510) configured to store metadata (606) including a physical address for the at least one first system EB (508) to locate the at least one first system EB (508);and a memory mapping module configured to scan the first area (520) and not the second area on at least one startup operation of the storage device, wherein: the at least one second system EB (510) is restricted to the first area (520); the at least one first system EB (508) and the data EBs (504) are not restricted to the first area (520); and the EBs (518) are block-erasable.

Description

GENERAL STATE OF THE ART Flash memory retains stored information without power and is therefore considered "non-volatile" memory. As such, flash memory has become increasingly popular for many types of devices, including removable storage devices and mobile computing devices. Unlike other non-volatile memories, which are one-time programmable (OTP), flash memory can be overwritten. Data can be stored in flash memory by erasing one or more blocks of memory cells within it and then writing data to one or more memory cells within those blocks. These blocks of memory cells are commonly referred to as erase blocks (EBs). The process of programming and erasing an erase block (EB) is called a program / erase cycle (P / E cycle).Some characteristics of flash memory tend to degrade with increasing program / erase (P / E) cycles. For example, flash memory may not be able to retain data indefinitely without power. Furthermore, the programming and erasing characteristics of flash memory can also degrade. Therefore, the lifespan of flash memory is limited by the maximum number of P / E cycles each EB can undergo. To extend the lifespan of flash memory, a flash file system (FFS) with an EB allocation scheme can be used. One of the functions of the EB allocation scheme is to perform a technique known as wear leveling (WL), where logical EBs are mapped to physical EBs. Specifically, logical EBs that are written to frequently are mapped to physical EBs with low P / E cycles, and logical EBs that are written to infrequently are mapped to physical EBs with high P / E cycles. The EB allocation scheme aims to distribute the P / E cycles evenly across the physical EBs so that no EB fails prematurely. Different EB allocation schemes result in different WL efficiencies, with WL efficiency being defined as the uniformity of the P / E cycle distribution across the physical EBs. Another function of an EB allocation scheme is to define how user data and system management information are allocated and stored among the EBs. The system management information includes, among other things, the physical location of user data within the flash memory. EBs that store user data can be referred to as data EBs. EBs that store system management information can be referred to as system EBs. The allocation of data EBs and system EBs dictates a mount latency for the FFS mount operation, which affects the flash memory boot time. When the flash memory starts, the mount operation typically involves locating the system EBs, which in turn point to the data EBs, so that user data can be made available to the user. The mount latency is the time required to complete the mount operation. Document US 10,120,792 B1 describes the programming of an embedded flash memory device. Document US 2012 / 0239,855 A1 relates to a semiconductor memory device with multilevel addressing. Document US 2004 / 0019,761 A1 describes a flash memory medium with NAND flash memory. Document US 2014 / 0181,376 A1 discloses a memory controller and a memory system. SUMMARY This document provides process, system, and computer program product implementation forms and / or combinations and subcombinations thereof for improving the lifetime of a flash memory by providing efficient wear compensation (WL) and enhancing the boot performance of the flash memory by reducing mount latency. One embodiment comprises an erase block allocation (EB allocation) method for a flash memory containing a plurality of physical EBs. A supersystem EB, comprising a plurality of pointers, is allocated to one of the physical EBs in a corresponding portion of the flash memory. Each of a plurality of system EBs and data EBs is allocated to one of the physical EBs not allocated to the supersystem EB. The system EBs store system management information, and the data EBs store user data. When the flash memory is powered on, the corresponding portion is sampled to locate the supersystem EB. The system EBs are then located using the pointers, and the data EBs are located using the system management information. One or more reserved EBs are also allocated to the physical EBs.Each of the reserved EBs is an empty physical EB used to reclaim a parent system EB, a system EB, or a data EB. If no reserved EB is available within the relevant part to reclaim the parent system EB, either a system EB or a data EB is reclaimed first to create a reserved EB within the relevant part. Another embodiment comprises a system with flash memory and an EB mapping module. The flash memory comprises a plurality of physical EBs. The EB mapping module maps a supersystem EB, comprising a plurality of pointers, to one of the physical EBs in a corresponding portion of the flash memory. The EB mapping module maps each of a plurality of system EBs and data EBs to one of the physical EBs that is not mapped to the supersystem EB. The system EBs store system management information, and the data EBs store user data. When the flash memory is powered on, the EB mapping module scans the corresponding portion to locate the supersystem EB. The EB mapping module then locates the EBs using the pointers and the data EBs using the system management information. The EB mapping module also maps one or more reserved EBs to the physical EBs.Each of the reserved EBs is an empty physical EB used to reclaim a supersystem EB, a system EB, or a data EB. If no reserved EB is available within the corresponding portion of flash memory to reclaim the supersystem EB, the EB allocation module will first reclaim either a system EB or a data EB to create a reserved EB within the corresponding portion. Another embodiment comprises a tangible, computer-readable device containing instructions stored thereon which, when executed by at least one computer device, cause the computer device to perform EB mapping operations. The EB mapping operations map a supersystem EB, comprising a plurality of pointers, to one of a plurality of physical EBs in a corresponding portion of the flash memory. The EB mapping operations map each of a plurality of system EBs and data EBs to one of the physical EBs not mapped to the supersystem EB. The system EBs store system management information, and the data EBs store user data. When the flash memory is powered on, the EB mapping operations scan the corresponding portion to locate the supersystem EB.The EB mapping operations then locate the EBs using pointers and the data EBs using system management information. The EB mapping operations also map one or more reserved EBs to the physical EBs. Each reserved EB is an empty physical EB used to reclaim a parent system EB, a system EB, or a data EB. If no reserved EB is available within the relevant part to reclaim the parent system EB, the EB mapping operations will first reclaim either a system EB or a data EB to create a reserved EB within the relevant part. Further features and advantages of the invention, as well as the structure and function of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It should be noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented here for illustrative purposes only. Additional embodiments will be understandable to those skilled in the art in the relevant field(s) based on the teachings contained herein. BRIEF DESCRIPTION OF THE FIGURES The accompanying drawings, which are included herein and form part of the patent specification, illustrate the present invention and, together with the description, serve to clarify the basic principles of the invention and to enable a person skilled in the relevant field(s) to manufacture and use the invention. Fig. 1 illustrates an erase block allocation scheme (EB allocation scheme) according to an exemplary embodiment. Fig. 2 illustrates EB erase counts and the boot time of an EB allocation scheme according to an exemplary embodiment. Fig. 3 illustrates an EB allocation scheme according to an exemplary embodiment. Fig. 4 illustrates EB erase counts and the boot time of an EB allocation scheme according to an exemplary embodiment. Fig. 5 illustrates an EB allocation scheme according to an exemplary embodiment.Figure 6 illustrates EB delete counts and the boot time of an EB mapping scheme according to an exemplary embodiment. Figure 7 is a representation of an addressing hierarchy of an EB mapping scheme according to an exemplary embodiment. Figure 8 illustrates garbage collection of a higher-level EB according to an exemplary embodiment. Figure 9 illustrates garbage collection of a higher-level EB according to an exemplary embodiment. Figure 10 illustrates garbage collection of a higher-level EB according to an exemplary embodiment. Figure 11 is a flowchart illustrating a garbage collection algorithm for a higher-level EB according to an exemplary embodiment. Figure 12 illustrates a comparison of EB delete counts and mount latencies of several EB mapping schemes according to different embodiments. Figure 13 is an exemplary computer system useful for implementing various embodiments. The features and advantages of the present invention become more readily apparent from the detailed description set forth below, when considered in conjunction with the drawings, in which the same reference numerals consistently denote corresponding elements. In the drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The drawing in which an element appears first is identified by the leftmost digit(s) in the reference numeral. DETAILED DESCRIPTION This patent specification discloses one or more embodiments incorporating the features of this invention. The disclosed embodiment(s) merely illustrate the invention. The scope of protection of the invention is not limited to the disclosed embodiment(s). The invention is defined by the attached patent claims. Furthermore, aspects can be implemented in software, hardware, or firmware, or a combination thereof. Embodiments of the invention can also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium can comprise any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer device). A machine-readable medium can include, for example, read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals; and others. Furthermore, firmware, software, routines, and instructions that perform certain operations can be described therein.However, it should be recognized that such descriptions are merely for convenience and that such processes actually result from computer devices, processors, controllers or other devices that execute the firmware, software, routines, instructions, etc. Split EB assignment scheme According to one embodiment, Fig. 1 illustrates an example of a split erase block allocation scheme (EB allocation scheme) 100 that can be incorporated into a flash file system (FFS) of a flash memory. The split erase EB allocation scheme 100 can be viewed as a logical allocation 102 or a physical allocation 112. Logical mapping 102 illustrates an exemplary arrangement of logical data EBs 104, logical reserved data EBs 106, logical system EBs 108, and logical reserved system EBs 110, where each EB is a block of memory cells. The split EB mapping scheme 100 maps logical data EBs 104 and logical reserved data EBs 106 to physical data EBs 114, and logical system EBs 108 and logical reserved system EBs 110 to physical system EBs 116. Physical mapping 112 illustrates an example of the resulting arrangement of physical data EBs 114 and physical system EBs 116. In a flash memory with an FFS using a shared EB mapping scheme, physical data EBs 114 and physical system EBs 116 typically occupy dedicated portions of the flash memory and do not share an EB, hence the term "shared." Furthermore, although not explicitly shown in Fig. 1, flash memory typically contains relatively fewer physical system EBs 116, including reserved system EBs, than data EBs. The logical data EBs 104 store user data, while the logical system EBs store system management information, including the physical location of the user data in flash memory. In the shared EB allocation scheme 100, logical reserved data EBs 106 are empty EBs used for garbage collection of logical data EBs 104, where garbage collection is a process of reclaiming memory cells that are no longer in use. During a garbage collection operation, one or more logical data EBs 104 can be reclaimed by transferring valid data within logical data EBs 104 to one or more logical reserved data EBs 106. Subsequently, the original logical data EBs 104 can be erased (i.e., reclaimed), creating new logical reserved data EBs 106.Similarly, one or more logical system EBs 108 can be reclaimed by transferring valid data within logical system EBs 108 into one or more logical system EBs 110. The original logical system EBs 108 can then be deleted, thereby creating new logically reserved system EBs 110. Figure 2 illustrates diagram 200 with exemplary erase counts corresponding to physical data EBs 114 and physical system EBs 116 after several program / erase (P / E) cycles. As shown by arrow 202, the erase counts for physical system EBs 116 can be relatively higher than the erase counts for physical data EBs 114, resulting in undesirable and unequal wear levels between the two. In this example, the shared EB allocation scheme 100 performs wear balancing (WL) of data EBs and system EBs independently on each part. Specifically, during garbage collection, logical data EBs that are frequently written to are allocated to reserved data EBs with low P / E cycles, and logical data EBs that are not frequently written to are allocated to reserved data EBs with high P / E cycles.Similarly, logical system EBs that are frequently written to are mapped to reserved system EBs with low P / E cycles, and logical system EBs that are infrequently written to are mapped to reserved system EBs with high P / E cycles. Given that there are relatively fewer physical system EBs, physical system EBs undergo higher P / E cycles than physical data EBs. However, the shared EB allocation scheme 100 allows a flash memory to have a relatively faster boot time. During a mount operation, only a specific portion of the flash memory needs to be sampled, as indicated by arrow 204, to locate valid system EBs. Therefore, the shared EB allocation scheme 100 provides reduced mount latency but inefficient WL across a flash memory. Unified EB assignment scheme According to one embodiment, Fig. 3 illustrates an exemplary unified EB mapping scheme 300, which can be considered a logical mapping 302 or a physical mapping 312. In contrast to the split EB mapping scheme 100, as shown by the logical mapping 302, the unified EB mapping scheme 300 includes a set of logical, shared, reserved EBs 306, instead of separate, reserved data EBs and reserved system EBs. The logical, shared, reserved EBs 306 can be used to collect either logical data EBs 304 or logical system EBs 308. Furthermore, the unified EB mapping scheme 300 maps logical data EBs 304, logical, shared, reserved EBs 306, and logical system EBs 308 to physical EBs 318.In contrast to the split EB assignment scheme 100, the unified EB assignment scheme 300 does not include a distinction between data EBs and system EBs in the physical assignment 312. In Fig. 4, Diagram 400 illustrates exemplary erase counts for physical EBs 318. As indicated above by arrow 402, the unified EB allocation scheme 300 usually results in a uniform wear across all EBs. The practically uniform wear results from the ability of the unified EB allocation scheme 300 to perform a WL operation on flash memory by mapping logical system EBs 308 or logical data EBs 304, which are frequently written to, to logical, shared, reserved EBs 306 with low erase counts, and logical system EBs 308 or logical data EBs 304, which are not frequently written to, to logical, shared, reserved EBs 306 with high erase counts. However, the disadvantage of the unified EB mapping scheme 300 is a relatively slower boot time, as indicated by arrow 404. This slower boot time is due to the fact that the unified EB mapping scheme 300 must sample all physical EBs 318 during a mount operation to locate valid system EBs. Thus, the unified EB mapping scheme 300 provides efficient WL but with longer mount latency. Overlaid EB assignment scheme According to an exemplary embodiment, a superimposed EB assignment scheme is now described with reference to Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. 12, which is capable of simultaneously providing reduced mount latency and efficient WL. Fig. 5 is a representation of an exemplary superimposed EB mapping scheme 500, which is similar to the unified EB mapping scheme 300 in Fig. 3, except that one of the EBs in flash memory is a modified system EB. This modified system EB is shown in Fig. 5 as a supersystem EB 510. As will be seen from the following description, the supersystem EB 510 allows a reduction in mount latency. In Fig. 5, as shown in the logical mapping 502, the superimposed EB mapping scheme includes a set of logical, shared, reserved EBs 506. The superimposed EB mapping scheme 500 can use the shared, reserved EBs not only for garbage collection of the data EBs and system EBs, but also for garbage collection of the supersystem EB 510.As in the unified EB mapping scheme 300, logical data EBs 504 and logical system EBs 508 can be mapped to any physical EBs 518, except that the superimposed EB mapping scheme 500 maps the supersystem EB 510 to a specific portion of the flash memory. In the physical mapping 512, this specific portion is shown as superimposed on the physical EBs 518 and is accordingly marked as the superimposed EB area 520. In Fig. 6, diagram 600 illustrates exemplary erase counts for physical EBs 518. Given that the superimposed EB allocation scheme 500 can perform a common WL operation on physical EBs 518 using the common, reserved EBs, uniform wear can be achieved, as indicated by arrow 602. This is similar to the unified EB allocation 300. However, unlike the unified EB allocation 300, the superimposed EB allocation scheme 500 can achieve a relatively fast boot time, as indicated by arrow 604. This is because, during a mount operation, the superimposed EB allocation scheme 500 only samples the superimposed EB range 520 to locate supersystem EB 510, which includes several pointers 606 pointing to valid system EBs. The pointer 606 can contain metadata, which may include address information for valid system EBs.Therefore, once the upper system EB 510 has been located, the pointers 606 can be used to locate valid system EBs among the physical EBs 518. Figure 7 illustrates an example addressing hierarchy 700 of a superimposed EB allocation scheme 500. As indicated by arrow 702, data EBs typically experience the highest write traffic or P / E cycles, followed by system EBs and the supersystem EB. When one or more data EBs are deleted, only the location information of the reclaimed EBs and the new data EBs within the system EBs is recorded. Therefore, compared to data EBs, it takes longer for system EBs to run out of free memory locations. Similarly, when system EBs are deleted, the pointers within the supersystem EB are updated to point to the new system EBs. Consequently, compared to system EBs, it takes longer for the supersystem EB to run out of free memory locations. This results in the addressing hierarchy 700. Figure 7 also illustrates how an example flash memory has relatively fewer system EBs compared to data EBs. Fewer system EBs not only implies a faster boot time but also more remaining EBs that can be used for data EBs. A flash memory with fewer system EBs can therefore provide more space for user data. However, fewer system EBs also implies that the system EBs can undergo higher P / E cycles than data EBs. Flash memory manufacturers and users must therefore usually trade off the number of system EBs against the allocation of data EBs, depending on their desire for operating speed (i.e., fewer system EBs and faster boot time) or uptime (i.e., more EBs and fewer P / E cycles). A person skilled in the art would recognize that if the storage capacity of a flash memory increases (i.e., the number of erase blocks increases), a supersystem erase block (EB) might not be able to store all the information needed to point to all valid system EBs. In such a case, a plurality of supersystem EBs can be used. The plurality of supersystem EBs can all be confined to a specific area of ​​the flash memory, similar to the superimposed EB area 520 in Fig. 5. During a mount operation, this specific area can be scanned to locate all the supersystem EBs that point to the valid system EBs. Alternatively, another modified system EB, for example, a super-supersystem EB, can be used to point to the multitude of supersystem EBs. The super-supersystem EB can be restricted to a specific region, while the supersystem EBs can be located anywhere in the flash memory. During a mount operation, this specific region can be sampled to locate the super-supersystem EB that points to the supersystem EBs, which in turn point to the valid system EBs. A person skilled in the art would further recognize that if the storage capacity of a flash memory increases even further, the tree concept with an EB pointing to a multitude of EBs can be extended without expanding the region to be sampled during a mount operation. Upper system EB waste collection algorithm In one example, within a superimposed EB assignment scheme 500, it is ensured that the upper-level system EB 510 is assigned to the superimposed EB area 520. As a result, the waste collection of the upper-level system EB 510 should be carried out according to a specific algorithm. Figures 8, 9 to 10 illustrate various exemplary scenarios that include such an algorithm for performing the waste collection of the upper-level system EB 510. According to one embodiment, Fig. 8 shows an exemplary garbage collection process 800 of the supersystem EB 510. The physical mapping 812 illustrates an exemplary allocation of data EBs, system EBs, shared reserved EBs, and supersystem EB 510 after several P / E cycles. In this scenario, the superimposed EB area 520 contains supersystem EB 510 and two shared reserved EBs. The supersystem EB 510 is marked as "OLD" because, for example, the supersystem EB 510 may be full (i.e., it may no longer have any free memory cells). In step 822, garbage collection can be performed by allocating one of the shared reserved EBs within the superimposed EB area 520 and transferring valid data from the "OLD" supersystem EB to the allocated shared reserved EB. Thus, a "NEW" upper system EB is formed and remains within the superimposed EB area 520, as required by the superimposed EB assignment scheme 500.In step 824, the "ALT" parent system EB can be deleted to create a common, reserved EB. According to one embodiment, Fig. 9 shows another exemplary waste collection process 900 of the supersystem EB 510. The physical mapping 912 illustrates an exemplary allocation of data EBs, system EBs, shared reserved EBs, and supersystem EB 510 after several P / E cycles. In this scenario, the superimposed EB area 520 contains supersystem EB 510 and two system EBs. Similar to the scenario in, for example, Fig. 8, the supersystem EB 510 can be full and marked "OLD". However, in this exemplary scenario, there is no shared reserved EB within the superimposed EB area 520 ready to perform waste collection of the "OLD" supersystem EB. One or more shared reserved EBs must first be created within the superimposed EB area 520.Therefore, in step 922, one or more shared, reserved EBs can be allocated outside the superimposed EB area 520 to reclaim one or more of the system EBs that are within the superimposed EB area 520. Figure 8 shows, but is not limited to, two system EBs being reclaimed. In step 924, one or more shared, reserved EBs can then be created by deleting the reclaimed system EBs. Subsequently, in step 926, one of the newly created shared, reserved EBs can be allocated to reclaim the "OLD" supersystem EB, thereby creating a "NEW" supersystem EB. In step 928, the "OLD" supersystem EB can be deleted to create a shared, reserved EB within the superimposed EB area 520. According to one embodiment, Fig. 10 shows another exemplary waste collection process 1000 of the supersystem EB 510. The physical mapping 1012 illustrates an exemplary allocation of data EBs, system EBs, shared reserved EBs, and supersystem EB 510 after several P / E cycles. In this exemplary scenario, the superimposed EB area 520 contains supersystem EB 510 and two data EBs. Similar to the scenario in, for example, Fig. 8, the supersystem EB 510 can be full and marked "OLD". However, in this exemplary scenario, there is no shared reserved EB within the superimposed EB area 520 ready to perform waste collection of the "OLD" supersystem EB. One or more shared reserved EBs must first be created within the superimposed EB area 520.Therefore, in step 1022, one or more shared, reserved EBs can be allocated outside the superimposed EB area 520 to reclaim one or more of the data EBs that are within the superimposed EB area 520. Figure 10 shows, but is not limited to, a data EB being reclaimed. In step 1024, one or more shared, reserved EBs can then be created by deleting the reclaimed data EBs. Subsequently, in step 1026, one of the newly created shared, reserved EBs can be allocated to reclaim the "OLD" parent system EB, thereby creating a "NEW" parent system EB. In step 1028, the "OLD" parent system EB can be deleted to create a shared, reserved EB within the superimposed EB area 520. Fig. 11 illustrates an algorithm 1100, which is used by the superimposed EB assignment scheme 500 to perform waste collection of a supersystem EB according to an exemplary embodiment. Fig. 11 is described with reference to Figs. 8, 9 to 10, but it should be understood that the algorithm 1100 is not limited to the exemplary embodiments illustrated in Figs. 8-10. As shown in Fig. 11, algorithm 1100 begins at step 1102, where the control transitions to step 1104. In step 1104, the locations of the shared, reserved EBs are retrieved, for example, in the form of a memory table (RAM table). In step 1106, algorithm 1100 determines whether one or more of the shared, reserved EBs are located within the superimposed EB area, as shown by the superimposed EB area 520 in Fig. 8-10. If one or more shared, reserved EBs exist within the superimposed EB area, algorithm 1100 continues with step 1108, in which one of the shared, reserved EBs is assigned to be the next higher-level EB. In step 1110, valid data is transferred from the old higher-level EB to the next higher-level EB. Steps 1108 and 1110 correspond to step 822 in Fig. 8. In step 1112, the old higher-level EB is deleted to create a shared, reserved EB. Step 1112 corresponds to step 824 in Fig. 8. If step 1106 determines that no shared, reserved EB is located within the superimposed EB area, algorithm 1100 continues with step 1116, in which the locations of the system EBs are retrieved, for example, in the form of a RAM table. In step 1118, algorithm 1100 determines whether one or more of the shared, reserved EBs are located within the superimposed EB area. If one or more system EBs exist within the superimposed EB domain, algorithm 1100 continues with step 1120. In step 1120, one or more of the system EBs are reclaimed to create one or more common, reserved EBs within the superimposed EB domain. Step 1120 corresponds to steps 922 and 924 in Fig. 9. Once one or more common, reserved EBs have been formed within the superimposed EB domain, algorithm 1100 executes steps 1108 to 1112 to reclaim the original supersystem EB. If step 1118 determines that no system EB exists within the superimposed EB area, algorithm 1100 proceeds to step 1122, where one or more data EBs within the superimposed EB area are reclaimed to create one or more shared, reserved EBs. Step 1122 corresponds to steps 1022 and 1024 in Fig. 10. Algorithm 1100 executes steps 1108 to 1112 to reclaim the old supersystem EB. Algorithm 1100 terminates at step 1114. Comparison of EB assignment schemes Fig. 12 provides a comparison between the split EB mapping scheme 100, unified EB mapping scheme 300 and superimposed EB mapping scheme 500 when applied to, but not limited to, one 64-megabyte (MB) NOR flash memory. Graph 1200 illustrates delete counts for the three schemes, while bar chart 1202 illustrates their mount latencies. Graph 1200 shows that the unified EB allocation scheme 300 and the superimposed EB allocation scheme 500 have similar delete counts on the EBs. However, in the split EB allocation scheme 100, some EBs have higher delete counts, as indicated by arrow 1204. This portion of the EBs corresponds to the system EBs, as previously described. In bar chart 1202, the split EB mapping scheme 100 and the superimposed EB mapping scheme 500 exhibit similar mount latencies, but the unified EB mapping scheme 300 has a higher mount latency. As previously described, during a mount operation, the split EB mapping scheme 100 and the superimposed EB mapping scheme 500 need to sample a smaller subset of EBs to locate valid system EBs, whereas the unified EB mapping scheme 300 needs to sample all EBs to locate the valid system EBs. This comparison confirms that the superimposed ER 500 mapping scheme provides both efficient WL and reduced mount latency. Although this comparison uses a 64 MB NOR flash memory, similar observations can be made for other flash memory devices, regardless of their storage capacity or type. Example computer system Various embodiments can be implemented, for example, using one or more known computer systems, such as the computer system 1300 shown in Fig. 13. The computer system 1300 can be any well-known computer capable of performing the functions described herein, such as computers available from International Business Machines, Apple, Sun, HP, Dell, Sony, Toshiba, etc. The Computer System 1300 comprises one or more processors (also known as central processing units or CPUs), such as a Processor 1304. The Processor 1304 is connected to a communication infrastructure or bus 1306. One or more 1304 processors can each be a graphics processing unit (GPU). In one embodiment, a GPU is a processor that is a specialized electronic circuit designed to rapidly process mathematically intensive applications on electronic devices. The GPU can have a highly parallel structure that is efficient for the parallel processing of large blocks of data, such as mathematically intensive data commonly found in computer graphics applications, images, and videos. The computer system 1300 also includes (a) user input / output device(s) 1303, such as monitors, keyboards, pointing devices, etc., which communicate with the communication infrastructure 1306 via (a) user input / output interface(s) 1302. The Computer System 1300 also includes a main or primary memory 1308, such as main memory (RAM). The main memory 1308 can include one or more levels of cache. The main memory 1308 contains control logic (i.e., computer software) and / or data stored within it. The 1300 computer system can also include one or more secondary storage devices or memory 1310. The secondary storage 1310 can, for example, include a hard disk 1312 and / or a removable storage device or removable storage drive 1314. The removable storage drive 1314 can be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, a tape backup device, and / or another storage device / drive. The removable storage drive 1314 can interact with a removable storage unit 1318. The removable storage unit 1318 comprises a computer-usable or -readable storage device containing computer software (control logic) and / or data. The removable storage unit 1318 can be a floppy disk, magnetic tape, compact disc, DVD, optical storage disk, and / or other computer data storage device. The removable storage drive 1314 reads from and / or writes to the removable storage unit 1318 in a well-known manner. According to one exemplary embodiment, the secondary memory 1310 may comprise other means, aids, or approaches to allow the computer system 1300 to access computer programs and / or other instructions and / or data. Such means, aids, or approaches may, for example, include a removable storage unit 1322 and an interface 1320. Examples of the removable storage unit 1322 and the interface 1320 may include a program cartridge and program interface (such as those found in video game devices), a removable memory chip (such as an EPROM or PROM) and an associated socket, a memory stick and a USB connector, a memory card and an associated memory card slot, and / or another removable storage unit and associated interface. The computer system 1300 may further include a communication or network interface 1324. The communication interface 1324 enables the computer system 1300 to communicate and interact with any combination of remote devices, remote networks, remote units, etc. (individually and collectively designated by reference numeral 1328). For example, the communication interface 1324 may allow the computer system 1300 to communicate with remote devices 1328 via a communication path 1326, which may be wired and / or wireless and may include any combination of LANs, WANs, the Internet, etc. Control logic and / or data may be transmitted to and from the computer system 1300 via the communication path 1326. In one embodiment, a tangible device or tangible manufactured article comprising a computer-usable or -readable medium containing control logic (software) stored thereon is also referred to as a computer program product or program storage device. This includes, but is not limited to, the computer system 1300, the main memory 1308, the secondary memory 1310, and the removable storage units 1318 and 1322, as well as tangible manufactured articles embodying a combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system 1300), causes such data processing devices to operate as described herein. Based on the teachings contained in these disclosures, those skilled in the relevant field(s) will recognize how to manufacture and use the invention using data processing devices, computer systems, and / or computer architectures that differ from those shown in Fig. 13. In particular, embodiments may operate with software, hardware, and / or operating system implementations that differ from those described herein. EXECUTION FORMS: 1. A method comprising: mapping a first type of erase block (EB), comprising a plurality of pointers, to a plurality of physical EBs in a corresponding part of a memory; and mapping a second and a third type of EB, respectively, to one of the physical EBs not mapped to the first type of EB, wherein the second type of EB stores system management information and the third type of EB stores user data. 2. A method according to embodiment 1, further comprising, when the memory is started, mapping the corresponding part to locate the first type of EB; locating the second type of EB using the pointers; and locating the third type of EB using the system management information. 3.Method according to embodiment 1, further comprising: allocating a fourth type of EBs to the physical EBs; wherein each of the fourth type of EBs is an empty physical EB used to reclaim one of the first type of EB, one of the second type of EBs, and one of the third type of EBs. 4. Method according to embodiment 3, further comprising, in response to the first type of EB being full and one or more of the fourth type of EBs being allocated within the relevant part, allocating one of the fourth type of EBs allocated within the relevant part to reclaim the first type of EB. 5.A method according to embodiment 3, further comprising, in response to the fact that the first type of EB is full, no fourth type of EB is allocated within the relevant part, and one or more of the second type of EB are allocated within the relevant area, the following: generating one or more of the fourth type of EB within the relevant part by allocating one or more of the fourth type of EB outside the relevant part in order to reclaim one or more of the second type of EB within the relevant part; and allocating one of the fourth type of EB generated within the relevant part in order to reclaim the first type of EB.A method according to embodiment 3, further comprising, in response to the fact that the first type of EB is full and no fourth type of EB and no second type of EB are allocated within the relevant area, the following: generating one or more of the fourth type of EB within the relevant part by allocating one or more of the fourth type of EB outside the relevant part in order to reclaim one or more of the third type of EB within the relevant part; and allocating one of the fourth type of EB generated within the relevant part in order to reclaim the first type of EB.A system comprising: a memory comprising a plurality of physical EBs; and an EB mapping module configured to: map a first type of EB comprising pointers to one of the physical EBs in a corresponding part of the memory, and map a second and third type of EB each to one of the physical EBs not mapped to the first type of EB, wherein: the second type of EB stores system management information and the third type of EB stores user data. 8. System according to embodiment 7, wherein the EB mapping module is further configured to, when the memory is started, scan the corresponding part to locate the first type of EB; locate the second type of EB using the pointers; and locate the third type of EB using the system management information. 9.System according to embodiment 7, wherein the EB allocation module is further configured to allocate a fourth type of EB to the physical EBs, each of the fourth type of EB being an empty physical EB used to reclaim one of the first type of EB, one of the second type of EB, and one of the third type of EB. 10. System according to embodiment 9, wherein the EB allocation module is further configured to allocate, in response to the first type of EB being full and one or more of the fourth type of EB being allocated within the corresponding part, one of the fourth type of EB being allocated within the corresponding part to reclaim the first type of EB. 11.System according to embodiment 9, wherein the EB allocation module is further configured to, in response to the fact that the first type of EB is full, no fourth type of EB is allocated within the relevant part, and one or more of the second type of EB are allocated within the relevant area, generate one or more of the fourth type of EB within the relevant part by allocating one or more of the fourth type of EB outside the relevant part in order to reclaim one or more of the second type of EB within the relevant part; and allocate one of the fourth type of EB generated within the relevant part in order to reclaim the first type of EB. 12.System according to embodiment 9, wherein the EB allocation module is further configured to, in response to the fact that the first type of EB is full and no fourth type of EB and no second type of EB are allocated within the relevant area, generate one or more of the fourth type of EB within the relevant part by allocating one or more of the fourth type of EB outside the relevant part in order to reclaim one or more of the third type of EB within the relevant part; and allocate one of the fourth type of EB generated within the relevant part in order to reclaim the first type of EB. 13.A tangible, computer-readable device comprising a plurality of physical EBs and containing instructions stored thereon, which, when executed by at least one computer device, cause the at least one computer device to perform EB mapping operations comprising: mapping a first type of EB comprising pointers to one of the physical EBs in a corresponding part of the computer-readable device; and mapping a second and a third type of EB, respectively, to one of the physical EBs not mapped to the first type of EB, wherein: the second type of EB stores system management information and the third type of EB stores user data.Computer-readable device according to embodiment 13, wherein the EB allocation operations further include, when the memory is started: scanning the appropriate portion to locate the second type of EB; locating the second type of EBs using the pointers; and locating the third type of EBs using the system management information. 15. Computer-readable device according to embodiment 13, wherein the EB allocation operations further include: allocating a fourth type of EB to each of the physical EBs, each of the fourth type of EB being an empty physical EB used to reclaim one of the second type of EBs, one of the third type of EBs, and one of the second type of EB. 16.Computer-readable device according to embodiment 15, wherein the EB allocation operations further comprise, in response to the fact that the first type of EB is full and one or more of the fourth type of EBs are allocated within the corresponding part, the following: allocating one of the fourth type of EBs allocated within the corresponding part to reclaim the first type of EB.17.Computer-readable device according to embodiment 15, wherein the EB allocation operations further comprise, in response to the fact that the first type of EB is full, no fourth type of EB is allocated within the relevant part, and one or more of the second type of EB are allocated within the relevant area, the following: generating one or more of the fourth type of EB within the relevant part by allocating one or more of the fourth type of EB outside the relevant part to reclaim one or more of the second type of EB within the relevant part; and allocating one of the fourth type of EB generated within the relevant part to reclaim the first type of EB. 18.Computer-readable device according to embodiment 15, wherein the EB allocation operations further comprise, in response to the fact that the first type of EB is full and no fourth type of EBs and no second type of EBs are allocated within the relevant area, the following: generating one or more of the fourth type of EBs within the relevant part by allocating one or more of the fourth type of EBs outside the relevant part in order to reclaim one or more of the third type of EBs within the relevant part; and allocating one of the fourth type of EBs generated within the relevant part in order to reclaim the first type of EB.

Claims

A storage device comprising: a plurality of physical erase blocks (EBs) (518) physically subdivided into a first area (520) and a second area, the physical EBs (518) comprising: a plurality of data EBs (504) configured to store data from a user of the storage device; at least one first system EB (508) configured to store system management information for the data EBs (504); and at least one second system EB (510) configured to store metadata (606) including a physical address for the at least one first system EB (508) to locate the at least one first system EB (508);and a memory mapping module configured to scan the first area (520) and not the second area on at least one startup operation of the storage device, wherein: the at least one second system EB (510) is restricted to the first area (520); the at least one first system EB (508) and the data EBs (504) are not restricted to the first area (520); and the EBs (518) are block-erasable. The storage device according to claim 1, wherein the storage device is a storage drive (1314) for a computer system (1300). The storage device according to claim 1, wherein the physical EBs (518) comprise flash memory. Storage device according to claim 1, wherein the storage mapping module is further configured such that, upon finding the second system EB (510), it finds the at least one first system EB (508) with the metadata (606). The storage device according to claim 1, wherein: the plurality of physical EBs (518) further comprises a plurality of the first system EBs (508), wherein the second system EB (510) contains first metadata, and at least one third system EB containing second metadata; wherein the at least one third system EB is not limited to the first area (520). The storage device according to claim 5, further comprising: a storage mapping module configured to scan the subset of physical EBs with the predetermined physical mapping in at least one start operation of the storage device to locate the second system EB (510), to locate the at least one third system EB using the first metadata of the second system EB (510), and to locate the first system EBs (508) using the second metadata of the at least one third system EB. The storage device according to claim 1, wherein: the data EBS (504), the first system EBS (508) and the second system EBS (510) each have a logical mapping to corresponding physical EBS (518). A method for operating a storage device, comprising: providing a plurality of physical erase blocks (EBs) (518), each physical EB (518) containing a plurality of non-volatile memory cells that can be erased as a single block, the EBs (518) being physically configured into a first area (520) and a second area; and, by actuating a memory mapping module of the storage device, scanning only the first area (520) for a second system EB (510), the second EB (510) being restricted to the first area (520), locating first system EBs (508) using metadata (606), including physical addresses for the system EBs from the second system EB (510), and locating data EBs (504) using system data from the first system EBs (508) to make user data stored in the storage device available to a user;wherein the first system EBs (508) and the data EBs (504) may be located inside or outside the first area (520), and the first system EBs (508) do not store any user data of the user.; Method according to claim 8, wherein the storage device is a storage drive (1314) for a computer system (1300). Method according to claim 8, wherein the physical EBs (518) comprise flash memory. Method according to claim 8, wherein the scanning of only the first area (520) is performed in a start operation of the storage device. Method according to claim 8, wherein the localization of the EBs of the first system (508) using metadata from the EB of the second system (510) comprises the localization of EBs of the third system using metadata from the EB of the second system (510), and the localization of the EBs of the first system (508) using metadata from the EBs of the third system. A system comprising: at least one processor (1304); at least one memory (1308) connected to the at least one processor (1304) via a communication infrastructure (1306);at least one storage device coupled to the communication infrastructure (1306) and containing multiple physical erase blocks (EB) (518), each containing non-volatile memory cells configured to be erased together, the physical EB (518) being physically configured into an overlay area (520) and a non-overlay area, and containing a plurality of data EBs (504) configured to store data from a user, first system EBs (508) configured to store system management information for the data EBs (504) and not storing data from the user, and at least one second system EB (510) configured to store metadata (606) for locating the first system EBs (508), including physical addresses for the first system EBs (508);wherein at least one second system EB (510) is restricted to the overlay region (520), and the data EBs (504) and the first system EBs (508) are not restricted to the overlay region (520), and a memory mapping module configured to scan only the overlay region (520) for the second system EB (510) in a predetermined operation, to locate the first system EBs (508) using metadata (606) from the at least one second system EB (510), and to locate data EBs (504) using system data from the first system EBs (508) in order to make data stored in the storage device available to a user of the system. The system according to claim 13, wherein: the physical EBs (518) further comprise at least one third system EB configured to store metadata for localizing the at least one second system EB (510); and the memory mapping module is configured to locate the at least one second system EB (510) using metadata from the at least one third system EB, and to locate the first EBs (508) using metadata (606) from the at least one second system EB (510) in the predetermined operation.

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