MANAGEMENT OF ELECTRIC FIELDS IN SEMICONDUCTOR DEVICES AND ASSOCIATED MANUFACTURING PROCESSES
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- ANALOG DEVICES INC
- Filing Date
- 2022-06-28
- Publication Date
- 2026-07-02
AI Technical Summary
GaN-based semiconductors face challenges in managing strong electric fields, limiting their use in high-frequency and high-power applications due to the need for additional circuit complexity in depletion mode devices.
The use of structured regions of different conductivity beneath the active GaN device, such as a GaN high electron mobility transistor (GaN-HEMT), utilizing a patterned layer of oxidized silicon as a backside field plate to manage electric fields effectively.
This approach reduces electric field intensity, enhancing the performance and efficiency of GaN-based devices by controlling electric fields through a conductive backside field plate, which is potentially cheaper than implanted silicon carbide.
Abstract
Description
PRIORITY CLAIM
[0001] This application claims priority to U.S. patent application Serial No. 17 / 504,391, filed October 18, 2021, which is hereby incorporated by reference in its entirety. AREA OF REVELATION
[0002] This document relates generally to, among other things, semiconductor devices and, more particularly, to techniques for constructing gallium nitride devices. BACKGROUND
[0003] Gallium nitride (GaN)-based semiconductors offer several advantages over other semiconductors as the material of choice for fabricating the next generation of transistors or semiconductor devices for use in both high-voltage and high-frequency applications. For example, GaN-based semiconductors exhibit a wide band gap, which allows devices made from these materials to exhibit a high breakdown electric field and be robust over a wide temperature range.
[0004] The two-dimensional electron gas (2DEG) channels formed by GaN-based heterostructures generally exhibit high electron mobility, making devices fabricated using these structures useful in power switching and amplification systems. However, GaN-based semiconductors are typically used to fabricate depletion-mode (or normally-on) devices, which may have limited use in many of these systems, such as due to the additional circuit complexity required to support such devices. SUMMARY OF REVELATION
[0005] Electric field management techniques in GaN-based semiconductors are described that utilize patterned regions of varying conductivity beneath the active GaN device, such as a GaN high electron mobility transistor (GaN HEMT). As an example, a patterned layer of oxidized silicon can be formed over a layer of silicon dioxide during or before heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for backside electric field management, because a silicon layer can be made conductive, for example, to act as a backside field plate.
[0006] In some aspects, this disclosure relates to a method of forming a compound semiconductor heterostructure transistor device, the method comprising: forming an insulator layer over a substrate; forming a crystal lattice layer over the insulator layer; implanting a material into the crystal lattice layer; selectively etching a region of the crystal lattice layer; forming a first semiconductor material layer over the crystal lattice layer; and forming a second semiconductor material layer over the first semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer.
[0007] In some aspects, this disclosure relates to a compound semiconductor heterostructure transistor device comprising: an insulator layer formed over a substrate; a crystal lattice layer formed over the insulator layer, wherein the crystal lattice layer includes an etched-away portion, and wherein a material is implanted into the crystal lattice layer; and a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the crystal lattice layer that has been oxidized.
[0008] In some aspects, this disclosure relates to a compound semiconductor heterostructure transistor device comprising: an insulator layer formed over a substrate; a silicon layer formed over the insulator layer, wherein the silicon layer includes an etched-away portion and wherein a material is implanted into the silicon layer; and a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the silicon layer that has been oxidized. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In the drawings, which are not necessarily to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example, but not limitation. Fig. 1A-1E illustrate an example process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. 2A-2E illustrate another example of a process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. 3A-3E illustrate another example of a process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. 4 is an example flowchart of a method 400 for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. DETAILED DESCRIPTION
[0010] Gallium nitride (GaN)-based semiconductors are an attractive option for high-frequency and high-power applications. However, GaN technology still presents challenges in managing the strong electric fields present within the device. Currently, top-side field plates (also called front-side field plates) are the primary technique used to reduce the electric field to protect the device. Silicon power devices can use both back-side and top-side field plates, which can be more effective for managing an electric field than using only top-side field plates.
[0011] This disclosure describes electric field management techniques in GaN-based semiconductors that utilize patterned regions of varying conductivity beneath the active GaN device, such as a GaN high electron mobility transistor (GaN-HEMT). As an example, a patterned layer of oxidized silicon may be formed over a layer of silicon dioxide during or before heteroepitaxy of GaN or another semiconductor material. These techniques may be useful for backside electric field management because, for example, a silicon layer may be made conductive to act as a backside field plate.
[0012] As used in this disclosure, a GaN-based compound semiconductor material may include a chemical combination of elements including GaN and one or more elements from different groups in the periodic table. Such chemical combinations may include a pairing of elements from Group 13 (i.e., the group including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl)) with elements from Group 15 (i.e., the group including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi)). Group 13 of the periodic table may also be referred to as Group III and Group 15 as Group V. In one example, a semiconductor device may be fabricated from GaN and aluminum indium gallium nitride (AlInGaN).
[0013] Heterostructures described herein can be formed as AlN / GaN / AlN heterostructures, InAlN / GaN heterostructures, AlGaN / GaN heterostructures, or heterostructures formed from other combinations of Group 13 and Group 15 elements. These heterostructures can form a two-dimensional electron gas (2DEG) at the interface of the compound semiconductors forming the heterostructure, such as at the interface of GaN and AlGaN. The 2DEG can form a conductive channel of electrons that can be controllably depleted, such as by an electric field formed by a buried layer of p-type material disposed below the channel. The conductive channel of electrons can also be controllably enriched, such as by an electric field formed by a gate terminal disposed above the channel, to control a current through the semiconductor device.Semiconductor devices formed using such conductive channels can include transistors with high electron mobility.
[0014] Fig. 1A-1E illustrate an example process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. 1A illustrates the starting materials that can be used in a first example flow. The example shown includes a substrate 100, an insulator layer 102 formed over the substrate 100, and a crystal lattice layer 104 formed over the insulator layer 102. Examples of the substrate 100 may include silicon-on-insulator (SOI), aluminum nitride (AlN), and polycrystalline silicon carbide (SiC). Examples of the insulator layer 102 may include silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3).
[0015] The crystal lattice layer 104 may include materials with a crystal lattice configured to allow the growth of another overlying crystal lattice. Examples of the crystal lattice layer 104 may include silicon and sapphire, which may allow the formation of another crystal lattice layer, such as a GaN layer, over the crystal lattice layer 104. A crystal lattice layer contrasts with an amorphous layer, which would not allow the growth of an overlying crystal lattice.
[0016] As previously mentioned, backside field plates can be used to manage the strong electric fields often present in GaN devices. As described below, and unlike other techniques, the techniques of this disclosure can utilize the crystal lattice layer 104 to form a backside field plate, which may be more cost-effective than, for example, implanted silicon carbide.
[0017] The conductivity of a backside field plate is a factor in controlling the electric fields in a GaN device. As indicated by the arrows 106 in Fig. 1A, a material may be implanted into the crystal lattice layer 104. In some examples, the material may be a dopant implanted to tune the conductivity of the crystal lattice layer 104 to achieve a desired sheet resistance to effectively control the electric fields in the device. Examples of dopants may include boron, nitrogen, and aluminum. In one non-limiting example, a dopant concentration range may be between about 1E12 cm -2 and about 1E18 cm -2 lay.
[0018] With reference to Fig. 1B, the process flow may include patterning a region of the crystal lattice layer 104 where a backside field plate is desired. Then, the patterned region may be selectively etched away, as shown at 108.
[0019] With reference to Fig. 1C, a first semiconductor material layer 110 may be formed over the crystal lattice layer 104. For example, the structure of Fig. 1B in a reactor, and a first semiconductor material layer 110 may be formed, e.g., grown, over the crystal lattice layer 104. In some examples, the first semiconductor material layer 110 may be GaN and may be formed in the reactor at an elevated temperature between, for example, about 800 degrees Celsius and about 1100 degrees Celsius.
[0020] At the elevated temperature, the crystal lattice layer 104 at the interface of the insulator layer 102 and the crystal lattice layer 104 may begin to oxidize. For example, the crystal lattice layer 104 may be silicon, and the insulator layer 102 may be silicon dioxide. In such an example, the silicon at the interface with the silicon dioxide may begin to oxidize at the elevated temperature in the reactor and may become silicon dioxide. As the growth of the first semiconductor material layer 110 progresses, more and more of the crystal lattice layer 104, e.g., silicon, becomes silicon dioxide. Eventually, most or all of the crystal lattice layer 104 in the region 112 may be oxidized, as shown in Fig. 1D. For example, most or all of a silicon layer in region 112 may become silicon dioxide. Such a technique is important because GaN, for example, cannot be grown directly on silicon dioxide.
[0021] With reference to Fig. 1D, the first semiconductor material layer 110 may be further formed. Then, a second semiconductor material layer 114 may be formed, e.g., grown, over the first semiconductor material layer 110 to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel 116 (represented by a dashed line), wherein the 2DEG channel is more conductive than both the first semiconductor material layer 110 and the second semiconductor material layer 114.
[0022] In one non-limiting example, the first semiconductor material layer 110, such as GaN, may have a thickness of about 100 nm to about 600 nm, and the second semiconductor material layer 114, such as AlGaN, may have a thickness of about 10 nm to about 30 nm. In some examples, a GaN growth on Si may include a nucleation layer such as AlN or AlGaN, or any superlattice with different aluminum content of AlGaN layers. In some examples, the crystal lattice layer, such as silicon, may have a thickness of less than about 100 nm so that there is not too large a step during etching.
[0023] As in Fig. As can be seen in Figure 1D, most or all of the crystal lattice layer 104 in region 112 has been consumed and converted into the insulator layer 102. For example, most or all of the silicon in region 112 has been consumed and converted into silicon dioxide. As a result, only the patterned region 118 of higher conductivity of the crystal lattice layer 104 remains. In this way, a patterned region 118 of higher conductivity can be created above an insulator, namely the insulator layer 102. The patterned region 118 of higher conductivity can be used as a backside field plate.
[0024] With reference to Fig. 1E shows a compound semiconductor heterostructure transistor device 120 with a backside field plate 128. The compound semiconductor heterostructure transistor device 120 may include a gate contact 122, e.g., a T-gate contact, a drain contact 124, and a source contact 126. The gate contact 122 may be in contact with the second semiconductor material layer 114. The drain contact 124 and the source contact 126 may be in contact with the second semiconductor material layer 114 or the 2DEG channel 116.
[0025] In some examples, it may be desirable to further promote oxidation at the interface between the crystal lattice layer 104 and the insulator layer 102. Therefore, it may be desirable to implant oxygen, as described below with reference to Fig. 2A-2E is shown and described.
[0026] Fig. 2A-2E illustrate another example of a process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. Figure 2A illustrates the starting materials that can be used in an exemplary flow. The example shown includes a substrate 200, an insulator layer 202 formed over the substrate 200, and a crystal lattice layer 204 formed over the insulator layer 202. The substrate 200, the insulator layer 202, and the crystal lattice layer 204 are similar to those in Fig. 1A-1E and are not described in detail again for the sake of brevity.
[0027] Instead of relying solely on elemental oxygen in the insulator layer, such as silicon dioxide, oxygen can be implanted into the crystal lattice layer 204, such as silicon, as indicated by the arrows 206 in Fig. 2A. The implanted oxygen may provide an additional source of oxygen to promote the oxidation of the crystal lattice layer 204 at the interface of the crystal lattice layer 204 and the insulator layer 202. The implantation may be tuned to provide a high concentration of oxygen, such as between about 1E12 cm -2 and about 1E19 cm -2 , at the interface of the crystal lattice layer 204 and the insulator layer 202, where oxidation is desired.
[0028] Fig. 2B is similar to Fig. 1B. The process flow may include patterning a region of the crystal lattice layer 204 where a backside field plate is desired. Then, the patterned region may be selectively etched away, as shown at 208.
[0029] Fig. 2C is similar to Fig. 1C and will not be described in detail again for the sake of brevity. At an elevated temperature, the crystal lattice layer 204 at the interface of the insulator layer 202 and the crystal lattice layer 204 may be formed due to oxygen in the insulator layer 202 and / or the implanted oxygen from Fig. 2A begin to oxidize. As before, most or all of the crystal lattice layer 204 in the region 212 may be oxidized, as shown in Fig. 2D. For example, most or all of a silicon layer in region 212 may become silicon dioxide.
[0030] Fig. 2D is similar to Fig. 1D and will not be described in detail again for the sake of brevity. The first semiconductor material layer 210 may further be formed. Then, a second semiconductor material layer 214 may be formed, e.g., grown, over the first semiconductor material layer 210 to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel 216 (represented by a dashed line), wherein the 2DEG channel is more conductive than both the first semiconductor material layer 210 and the second semiconductor material layer 214. As shown in Fig. As can be seen in Figure 2D, most or all of the crystal lattice layer 204 in the region 212 has been consumed and converted into the insulator layer 202. For example, most or all of the silicon in the region 212 has been consumed and converted into silicon dioxide. As a result, only the patterned region 218 of higher conductivity of the crystal lattice layer 204 remains. In this way, a patterned region 218 of higher conductivity can be created above an insulator, namely the insulator layer 202. The patterned region 218 of higher conductivity can be used as a backside field plate.
[0031] With reference to Fig. 2E shows a compound semiconductor heterostructure transistor device 220 with a backside field plate 228. The compound semiconductor heterostructure transistor device 220 may include a gate contact 222, e.g., a T-gate contact, a drain contact 224, and a source contact 226. The gate contact 222 may be in contact with the second semiconductor material layer 214. The drain contact 224 and the source contact 226 may be in contact with the second semiconductor material layer 214 or the 2DEG channel 216.
[0032] In some examples, it may be desirable to both tune the conductivity of a crystal lattice layer and further promote oxidation at the interface between the crystal lattice layer and the insulator layer. Therefore, it may be desirable to implant a dopant, as in Fig. 1A, and oxygen implantation as in Fig. 2A. An example of such a process flow is shown below with reference to Fig. 3A-3E shown and described.
[0033] Fig. 3A-3E illustrate another example of a process manufacturing flow for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. Fig. Figure 3A illustrates the starting materials that can be used in an exemplary flow. The example shown includes a substrate 300, a silicon dioxide layer 302 formed over the substrate 300, and a silicon layer 304 formed over the silicon dioxide layer 302. The substrate 300 is, for example, similar to the substrate 100 of Fig. 1A and the silicon dioxide layer 302 and the silicon layer 304 are examples of the insulator layer and the crystal lattice layer described previously and will not be described again in detail for the sake of brevity.
[0034] As indicated by arrows 306 in Fig. As illustrated in Figure 3A, a material may be implanted into silicon layer 304. In some examples, the material may be a dopant implanted to tune the conductivity of silicon layer 304 to achieve a desired sheet resistance to effectively control the electric fields in the device. Examples of dopants may include boron, nitrogen, and aluminum.
[0035] In addition, oxygen can be implanted into the silicon layer 304, as indicated by the arrows 307 in Fig. 3A. The implanted oxygen may provide an additional source of oxygen to promote the oxidation of the silicon layer 304 at the interface of the silicon layer 304 and the silicon dioxide layer 302, as previously described with reference to Fig. 2A is described.
[0036] With reference to Fig. 3B, the process flow may include patterning a region of silicon layer 304 where a backside field plate is desired. Then, the patterned region may be selectively etched away, as shown at 308.
[0037] Fig. 3C is similar to Fig. 1C and will not be described in detail again for the sake of brevity. At an elevated temperature, the silicon layer 304 at the interface of the silicon dioxide layer 302 and the silicon layer 304 may be exposed to oxygen in the silicon dioxide layer 302 and / or the implanted oxygen from Fig. 3A. As before, most or all of the silicon layer 304 in the region 312 may be oxidized, as shown in Fig. shown in 3D.
[0038] Fig. 3D is similar to Fig. 1D and will not be described in detail again for the sake of brevity. The first semiconductor material layer 310, e.g., GaN, may be further formed. Then, a second semiconductor material layer 314, e.g., AlGaN, may be formed, e.g., grown, over the first semiconductor material layer 310 to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel 316 (represented by a dashed line), wherein the 2DEG channel is more conductive than both the first semiconductor material layer 310 and the second semiconductor material layer 314. As shown in Fig. As can be seen in Figure 3D, most or all of the crystal lattice layer 304 in the region 312 has been consumed and converted into the insulator layer 302. For example, most or all of the silicon in the region 312 has been consumed and converted into silicon dioxide. As a result, only the patterned region 318 of higher conductivity of the crystal lattice layer 304 remains. In this way, a patterned region 318 of higher conductivity can be created above an insulator, namely the insulator layer 302. The patterned region 318 of higher conductivity can be used as a backside field plate.
[0039] With reference to Fig. 3E shows a compound semiconductor heterostructure transistor device 320 with a backside field plate 328. The compound semiconductor heterostructure transistor device 320 may include a gate contact 322, e.g., a T-gate contact, a drain contact 324, and a source contact 326. The gate contact 322 may be in contact with the second semiconductor material layer 314. The drain contact 324 and the source contact 326 may be in contact with the second semiconductor material layer 314 or the 2DEG channel 316.
[0040] Fig.4 illustrates an example flowchart of a method 400 for forming a compound semiconductor heterostructure transistor device according to various techniques of this disclosure. At block 402, the method 400 may include forming an insulator layer over a substrate. For example, the method 400 may include forming an insulator layer of silicon dioxide, silicon nitride, or aluminum oxide over a substrate of silicon-on-insulator, aluminum nitride, or polycrystalline silicon carbide.
[0041] At block 404, method 400 may include forming a crystal lattice layer over the insulator layer. For example, a layer of silicon or sapphire may be formed over the insulator layer.
[0042] At block 406, the method 400 may include implanting a material into the crystal lattice layer. In some examples, implanting the material may include implanting a dopant, such as boron, nitrogen, or aluminum, to adjust a conductivity of the crystal lattice layer. In some examples, implanting the material into the crystal lattice layer may include implanting oxygen into the crystal lattice layer to adjust a concentration of oxygen at an interface between the silicon dioxide layer and the crystal lattice layer. In some examples, implanting the material into the crystal lattice layer may include both implanting a dopant into the crystal lattice layer and implanting oxygen into the crystal lattice layer.
[0043] At block 408, the method 400 may include selectively etching a region of the crystal lattice layer.
[0044] At block 410, the method 400 may include forming a first semiconductor material layer over the crystal lattice layer. For example, a GaN layer may be formed over a silicon layer. In some examples, the method may include oxidizing the crystal lattice layer at an interface between the silicon dioxide layer and the crystal lattice layer.
[0045] At block 412, method 400 may include forming a second semiconductor material layer over the first semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer. For example, a layer of aluminum gallium nitride (AlGaN) may be formed over a layer of GaN.
[0046] The method 400 may include forming a gate contact in contact with the second semiconductor material layer, e.g., AlGaN, and forming drain and source contacts in contact with the second semiconductor material layer, e.g., AlGaN, or the 2DEG channel. Various comments
[0047] Each of the non-limiting aspects or examples described herein may stand alone or may be combined in various permutations or combinations with one or more of the other examples.
[0048] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the present inventors also contemplate examples that employ any combination or permutation of those elements shown or described (or one or more aspects thereof), either with reference to a specific example (or one or more aspects thereof) or with reference to other examples shown or described herein (or one or more aspects thereof).
[0049] In the event of any inconsistency between this document and any documents incorporated by reference, the usage in this document shall prevail.
[0050] Throughout this document, the terms "ein" and "eine" are used, as is customary in patent documents, to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more." Throughout this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise specified. Throughout this document, the terms " inklusive" and "in dem" are used as the simple English equivalents of the respective terms "umgreifend" and "wobei."Furthermore, in the following aspects, the terms "including" and "comprising" are open-ended terms, meaning that a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in an aspect is still considered within the scope of that aspect. Furthermore, in the following aspects, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.
[0051] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operative to configure an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be tangibly stored on one or more transient, non-transitory, or non-transitory tangible computer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or flash drives, random access memories (RAMs), read-only memories (ROMs), and the like.
[0052] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, as would be apparent to one of ordinary skill in the art upon reading the above description. The Abstract is provided in compliance with 37 CFR §1.72(b) to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of any aspects. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as an intent that any unclaimed disclosed feature is essential to any aspect.Rather, the inventive subject matter may lie in fewer than all features of a particular disclosed embodiment. Accordingly, the following aspects are hereby incorporated into the Detailed Description as examples or embodiments, each aspect standing on its own as a separate embodiment, and it is intended that such embodiments may be combined with one another in various combinations or permutations. The scope of the invention should be determined by reference to the appended aspects, along with the full scope of equivalents to which such aspects are entitled. QUOTES CONTAINED IN THE DESCRIPTION
[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature
[0000] US 17 / 504391
[0001]
Claims
[1] A method of forming a compound semiconductor heterostructure transistor device, the method comprising: Forming an insulator layer over a substrate; Forming a crystal lattice layer over the insulator layer; implanting a material into the crystal lattice layer; selectively etching a region of the crystal lattice layer; Forming a first semiconductor material layer over the crystal lattice layer; and Forming a second semiconductor material layer over the first semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer. [2] The method of claim 1, wherein the crystal lattice layer includes a silicon layer. [3] The method of claim 1, wherein forming an insulator layer over the substrate comprises: Forming a silicon dioxide layer over the substrate. [4] A method according to claim 3, comprising: Oxidizing the crystal lattice layer at an interface between the silicon dioxide layer and the crystal lattice layer. [5] The method of claim 1, wherein implanting the material into the crystal lattice layer comprises: Implanting a dopant into the crystal lattice layer to adjust the conductivity of the crystal lattice layer. [6] The method of claim 5, wherein the dopant comprises boron, nitrogen and / or aluminum. [7] The method of claim 1, wherein implanting the material into the crystal lattice layer comprises: Implanting oxygen into the crystal lattice layer to adjust a concentration of oxygen at an interface between the insulator layer and the crystal lattice layer. [8] The method of claim 1, wherein implanting the material into the crystal lattice layer comprises: implanting a dopant into the crystal lattice layer to adjust a conductivity of the crystal lattice layer; and Implanting oxygen into the crystal lattice layer to adjust a concentration of oxygen at an interface between the insulator layer and the crystal lattice layer. [9] The method of claim 1, wherein the first semiconductor material layer comprises gallium nitride and wherein the second semiconductor material layer comprises aluminum gallium nitride. [10] A method according to claim 1, comprising: Forming a gate contact in contact with the second semiconductor material layer; and Forming drain and source contacts in contact with the second semiconductor material layer or the 2DEG channel. [11] A compound semiconductor heterostructure transistor device comprising: an insulator layer formed over a substrate; a crystal lattice layer formed over the insulator layer, the crystal lattice layer including an etched-away portion, and a material implanted into the crystal lattice layer; and a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the crystal lattice layer that has been oxidized. [12] A compound semiconductor heterostructure transistor device according to claim 11, wherein the crystal lattice layer includes a silicon layer. [13] A compound semiconductor heterostructure transistor device according to claim 11, wherein the insulator layer includes a silicon dioxide layer. [14] The compound semiconductor heterostructure transistor device of claim 11, wherein the implanted material includes a dopant to adjust a conductivity of the crystal lattice layer. [15] A compound semiconductor heterostructure transistor device according to claim 14, wherein the dopant includes boron, nitrogen and / or aluminum. [16] The compound semiconductor heterostructure transistor of claim 11, wherein the implanted material includes oxygen to adjust a concentration of oxygen at an interface between the insulator layer and the crystal lattice layer. [17] The compound semiconductor heterostructure transistor of claim 11, wherein the first semiconductor material layer comprises gallium nitride and wherein the second semiconductor material layer comprises aluminum gallium nitride. [18] A compound semiconductor heterostructure transistor according to claim 11, comprising: a gate contact in contact with the second semiconductor material layer; and Drain and source contacts in contact with the second semiconductor material layer or the 2DEG channel. [19] A compound semiconductor heterostructure transistor device comprising: an insulator layer formed over a substrate; a silicon layer formed over the insulator layer, the silicon layer including an etched-away portion, and a material implanted into the silicon layer; and a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than both the first semiconductor material layer and the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the silicon layer that has been oxidized. [20] The compound semiconductor heterostructure transistor device according to claim 19, wherein a dopant is implanted into the silicon layer to adjust a conductivity of the silicon layer.