DISPLAY SUBSTRATE AND ITS MANUFACTURING METHOD, DISPLAY DEVICE

Abstract

A display substrate and a manufacturing method thereof, a display device. The display substrate comprises a fanout region (201). The fanout region (201) comprises a first junction region (211), an insulating dam region (213), and a second junction region (212). The fanout region (201) comprises a gate metal layer and a source-drain metal layer. The gate metal layer comprises one or more of the following: a first gate metal layer, a second gate metal layer, and a third gate metal layer. The source-drain metal layer comprises one or more of the following: a first source-drain metal layer and a second source-drain metal layer.The gate metal layer is provided with a current connection line (60), the source-drain metal layer is provided with a first current line (110), the first current line (110) is provided in the first transition region (211) and the second transition region (212), the first current line (110) in the first transition region (211) and the first current line (110) in the second transition region (212) are connected to each other via the current connection line (60).

Description

TECHNICAL FIELDThe present disclosure relates to the field of display technology, and is not limited thereto, and more particularly relates to a display substrate and its manufacturing method and a display device.PRIOR ARTOrganic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) are active light emitting display devices having advantages of self-lighting, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of the display technique, a display device having an OLED or a QLED as a light emitting device and a thin film transistor (TFT) for signal control has already become a main trend product in the display area.DISCLOSURE OF THE INVENTIONAn overview of the items described in detail here is given below. This summary is not intended to limit the scope of the claims.In one aspect, the present disclosure provides a display substrate, comprising: a display region and a bonding region located on a side of the display region, the bonding region comprising at least: a fanout region and a bending region, the fanout region being located between the display region and the bending region, the fanout region comprising at least: a first transition region, an insulating dam region, and a second transition region arranged in a direction away from the display region; the fanout region comprising a bonding structure layer provided on a substrate, the bonding structure layer comprising at least: a gate metal layer and a source-drain metal layer arranged on a side of the gate metal layer facing away from the substrate, wherein the gate metal layer comprises one or more of the following: a first gate metal layer, a second gate metal layer and a third gate metal layer, wherein the source-drain metal layer comprises one or more of the following: a first source-drain metal layer and a second source-drain metal layer, wherein the gate metal layer is provided with a power connection line, the source-drain metal layer is provided with a first power line, the power connection line is provided in the first transition region, the insulating dam region and the second transition region, the first power line is provided in the first transition region and the second transition region, the first power line is provided in the first transition region and the first power line is connected to one another in the second transition region via the power connection line.In an exemplary embodiment, the bond structure layer further includes a first planarization layer disposed on a substrate-opposite side of the first source-drain metal layer, the first power line being disposed on a substrate-opposite side of the first planarization layer, the first source-drain metal layer being provided with a first overlapping electrode and a second overlapping electrode, the first overlapping electrode being disposed in the first transition region, the second overlapping electrode being disposed in the second transition region, the first power line of the first transition region being connected to the first overlapping electrode, the first overlapping electrode being connected to a side of the power connection line that is near the display region, the first power line of the second transition region being connected to the second overlapping electrode, the second overlapping electrode being connected to a display-opposite side of the power connection line.In an exemplary embodiment, the bonding structure layer further includes an inorganic insulating layer disposed on a substrate opposite side of the power connection line and provided with a first connection opening and a second connection opening, wherein the first overlapping electrode is connected to the power connection line side near the display region through the first connection opening, the second overlapping electrode is connected to the opposite side of the power connection line from the display region through the second connection opening.In an exemplary embodiment, the first planarization layer is provided with a third connection opening, the first power line of the first junction region is connected to the first overlapping electrode through the third connection opening.In an exemplary embodiment, the first planarization layer is provided with a first separation groove, wherein the orthographic projection of the first separation groove on the substrate includes the orthographic projection of the insulating dam region on the substrate, the first planarization layer on the side of the first separation groove near the display region covers the edge of the first overlapping electrode on the side near the display region, the first planarization layer on the side away from the display region of the first separation groove covers the edge of the second overlapping electrode on the side away from the display region, the first separation groove exposes a surface of the first overlapping electrode on the side away from the display region, a surface of the second overlapping electrode on the side near the display region, and a surface of the inorganic insulating layer located between the first overlapping electrode and the second overlapping electrode.In an exemplary embodiment, the first current line of the first transition region engages the first overlapping electrode exposed in the first separation groove.In an exemplary embodiment, the first current line of the first transition region covers the edge of the first overlapping electrode on the side facing away from the display region.In an exemplary embodiment, the first current line of the second transition region engages the second overlapping electrode exposed in the first separation groove.In an exemplary embodiment, the first current line of the second transition region covers the edge of the second overlapping electrode on the side near the display region.In an exemplary embodiment, the bonding structure layer further includes a second planarization layer disposed on a substrate-opposite side of the second source-drain metal layer, the second planarization layer being provided with a second separation groove, the orthographic projection of the second separation groove on the substrate includes the orthographic projection of the isolation dam region on the substrate, the second planarization layer on the display region-opposite side of the second separation groove covers the edge of the first current line of the first transition region on the display region-opposite side, the second planarization layer on the display region-opposite side of the second separation groove covers the edge of the first current line of the second transition region on the side close to the display region.In an exemplary embodiment, the insulating dam region is provided with at least one insulating dam and at least one separating groove, wherein the insulating dam is arranged on the side of the inorganic insulating layer facing away from the display region, the separating groove is arranged on the side of the insulating dam lying close to the display region or on the side of the insulating dam facing away from the display region, the separating groove exposes the surface of the inorganic insulating layer.In an exemplary embodiment, the display substrate includes, in a plane perpendicular to the display substrate, at least: a first gate metal layer, a second gate metal layer and a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer provided sequentially on the substrate, the power connection line is provided in one or more of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the first power line is provided in the second source-drain metal layer.In an exemplary embodiment, the display substrate includes, in a plane perpendicular to the display substrate, at least: a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source-drain metal layer, which are sequentially provided on the substrate, the power connection line is provided in one or more of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the first power line is provided in the first source-drain metal layer.In another aspect, in the present disclosure, there is further provided a display device including the display substrate described above.In another aspect, the present disclosure further provides a manufacturing method for a display substrate, the display substrate including: a display region and a bonding region located on a side of the display region, the bonding region including at least: a fanout region and a bending region, the fanout region being located between the display region and the bending region, the fanout region including at least: a first transition region, an insulating dam region, and a second transition region, which are arranged in a direction away from the display region; the manufacturing method including:forming a bond structure layer on a substrate of the fanout region, the bond structure layer comprising at least: a gate metal layer and a source drain metal layer arranged on a side of the gate metal layer facing away from the substrate, wherein the gate metal layer comprises one or more of the following: a first gate metal layer, a second gate metal layer and a third gate metal layer, wherein the source drain metal layer comprises one or more of the following: a first source drain metal layer and a second source drain metal layer, wherein the gate metal layer is provided with a current connection line, the source drain metal layer is provided with a first current line, the current connection line is provided in the first transition region, the insulating dam region and the second transition region, the first power line in the first transition region and the second transition region is provided, the first power line in the first transition region and the first power line in the second transition region are connected to each other via the power connection line.After reading and understanding the drawings and the detailed description, other aspects are to be detected.BRIEF DESCRIPTION OF THE DRAWINGSThe figures serve to provide further understanding of the technical solutions of the present disclosure and form a part of the description, and are used in conjunction with the embodiments of the present disclosure to explain the technical solutions of the present disclosure; however, they do not constitute a limitation on the technical solutions of the present disclosure. The shapes and the sizes of the respective components in the figures do not reflect the real proportions and serve only to schematically explain the contents of the present disclosure. FIG. 1 is a schematic diagram of the structure of a display substrate according to the present disclosure; FIG. 2 is a schematic diagram of the structure of a display substrate; FIG. 3 is a schematic plan view of the structure of a display area in a display substrate; FIG. 4 is a schematic sectional view showing the structure of a display area in a display substrate; FIG. 5 is a schematic equivalent circuit diagram of a pixel driving circuit; FIG. 6 is a schematic plan view of the structure of a fanout region in a bond region; FIG. 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure; FIG. 8 is a schematic diagram after forming a first semiconductor layer pattern according to an embodiment of the present disclosure; FIG. 9 is a schematic diagram after forming a first conductive layer according to an embodiment of the present disclosure; FIG. 10 is a schematic diagram after forming a second conductive layer according to an embodiment of the present disclosure; FIG. 11 is a schematic diagram after forming a second semiconductor layer pattern according to an embodiment of the present disclosure; FIG. 12 is a schematic diagram after forming a third semiconductor layer pattern according to an embodiment of the present disclosure; FIG. 13 is a schematic diagram after forming a sixth insulating layer pattern according to an embodiment of the present disclosure; FIG. 14 is a schematic diagram after forming a fourth conductive layer pattern according to an embodiment of the present disclosure; FIG. 15 is a schematic diagram after forming a first planarization layer pattern according to an embodiment of the present disclosure; FIG. 16 is a schematic diagram after forming a fifth conductive layer pattern according to an embodiment of the present disclosure; FIG. 17 is a schematic diagram after forming a second planarization layer pattern according to an embodiment of the present disclosure; FIG. 18 is a schematic diagram after forming a conductive anode layer and a pixel defining layer pattern according to an embodiment of the present disclosure; FIG. 19 is a schematic diagram after forming an organic light emitting layer and a cathode pattern according to an embodiment of the present disclosure; FIG. 20 is a schematic diagram showing a bad GDS on a display substrate; FIG. 21 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure; FIG. 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure; FIG. 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure; FIG. 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure; FIG. 25 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure.Reference Number:10 Substrate; 11 First insulating layer; 12 Second insulating layer; 13 Third insulating layer; 14 Fourth insulating layer; 15 Fifth insulating layer; 16 Sixth insulating layer; 17 First planarization layer; 18 Second planarization layer 20 First transistor; 21 First active layer; 22 First gate electrode; 23 First source electrode; 24 First drain electrode; 30 Second transistor; 31 Second active layer; 32 Second gate electrode; 33 Second source electrode; 34 Second drain electrode; 40 Storage capacitor; 41 First electrode plate; 42 Second electrode plate; 50 Bonding structure layer; 51 Shield layer; 52 Anode connection electrode; 60 Current connection line; 61 First overlapping electrode; 62 Second overlapping electrode; 71 First connection opening; 72 Second connection opening; 73 third connection opening 81 first separation groove 82 second separation groove 91 anode 92 pixel definition layer 93 organic light emission layer; 94 cathode; 95 first encapsulation layer; 96 second encapsulation layer; 97 third packaging layer; 100 display area; 102 driver circuit layer; 103 light emission structure layer; 104 encapsulation structure layer; 110 first power line; 120 second power line; 200 bonding area; 201 fanout area; 211 first transition area; 212 second transition area 213 insulation dam area; 300 frame area; 310 first insulation groove; 320 second insulation groove; 330 third insulation groove; 340 fourth insulation groove; 401 first dam base; 402 second dam base; 403 third dam base; 404 fourth dam base; 405 fifth dam base; 410 first insulation dam; 420 second insulation dam.EMBODIMENTS OF THE INVENTIONIn order to more clearly illustrate the purpose, technical solutions, and advantages of the present disclosure, the following explains the exemplary embodiments of the present disclosure in detail in conjunction with the figures. It should be noted that the embodiments may be performed in various forms. A general person skilled in the art can easily understand a Tatche that the manner and content can be converted into various forms without departing from the concept and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents indicated in the following embodiments. The embodiments and the features of the embodiments in the present disclosure may be combined with each other arbitrarily in conflict-free cases.The figure scale in the present disclosure may serve as a reference in a practical process, but is not limited thereto. For example, the width-length ratio of a trench, the thicknesses and the distances of respective film layers, and the widths and the distances of respective signal lines may be set as needed actually. The number of pixels in a display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the figures, and the figures described in the present disclosure are only schematic structural representations, and a manner of operation of the present disclosure is not limited to the shapes or values or the like shown in the appended figures.In this specification, ordinal terms such as "first", "second", "third" or the like are used to avoid mixing of components, but are not to be understood as being limited in terms of quantity.In this specification, for convenience, terms "center", "top", "bottom", "front", "rear", "vertical", "horizontal", "top", "under", "inside", "outside" or the like indicating an orientation or a positional relationship are used to illustrate the positional relationships of the constituent elements with reference to the accompanying drawings; they are used solely for convenience of illustration of the present description as well as for convenience of illustration, and however, are not intended to indicate or imply that a device or element intended has a particular orientation or needs to be formed and operated in a particular orientation; therefore, they should not be construed as limiting the present disclosure. The positional relationship of the constituent elements accordingly varies depending on the description of the directions of the respective constituent elements. Therefore, this is not limited to the words and expressions described in the specification, but replacement may be suitably made as appropriate.Unless expressly stated and defined otherwise, technical terms "mounted", "connected" and "connected" should be understood broadly in the description. For example, it may be a fixed connection, a detachable connection or a one-piece connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection by means of an intermediate element or a connection within two elements. The specific meaning of the above terms in the present disclosure can be understood by a general person skilled in the art depending on the subject.In the present specification, a transistor is an element having at least three terminals, namely, a gate electrode, a drain electrode, and a source electrode. The transistor has a trench region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the trench region, and the source electrode. Note that in the present specification, the trench region refers to a region through which the current predominantly flows.In the present specification, a first pole may be a drain electrode and a second pole may be a source electrode, or a first pole may be a source electrode and a second pole may be a drain electrode. The functions of the "source" and the "drain" are sometimes interchanged when transistors having opposite polarities are used or when the current direction changes in the circuit operation, etc. Therefore, in the present specification, the "source electrode" and the "drain electrode" are interchangeable with each other.In the present specification, "an electrical connection" includes a case where constituent elements are connected to each other by an element having a certain electrical function. No special limitation is imposed on "an element having a certain electrical function" as long as it can perform the giving and receiving of electrical signals between connected constituent members. Examples of "an element having a certain electrical function" include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.In the present specification, the term "parallel" refers to a state in which the angle formed by two straight lines is above -10° and below 10°, and thus also includes a state in which the angle is above -5° and below 5°. Moreover, the term "perpendicular" refers to a state in which the angle formed by two straight lines is above 80° and below 100°, and thus also includes a state in which the angle is above 85° and below 95°.In the present specification, "film" and "layer" are interchangeable. For example, "conductive layer" may sometimes be replaced with "conductive film". Likewise, "insulating film" may sometimes be replaced with "insulating layer".Triangles, rectangles, trapezoids, pentagonals or hexagon or the like in the present specification are not meant in a strict sense, but may be approximate triangles, rectangles, trapezoids, pentagonals or hexagon or the like. Slight deformations may be present, caused by tolerances; and pitch angles, arc edges, as well as deformations or the like may be present.The terms "about" in the present specification refer to a value that is not strictly limited to a limit and may be within the scope of allowable process and measurement errors.FIG. 1 is a schematic diagram of the structure of a display device. As shown in FIG. 1, a display device may include: a timing controller, a data driver, a scan driver, a light emission driver, and a pixel array. The timing controller is connected to each of the data driver, the scan driver, and the light emission driver. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emission driver is connected to a plurality of light emission signal lines (E1 to Eo), respectively. The pixel array may include a plurality of subpixels Pxij, where i and j may be natural numbers. At least one subpixel Pxij may include: a circuit unit; and a light emitting unit connected to the circuit unit. The circuit unit may include at least one pixel driving circuit, the pixel driving circuit may be connected to each of the scan signal line, the light emission signal line, and the data signal line. In an exemplary embodiment, the timing controller may provide grayscale values suitable for the specifications of the data driver and control signals to the data driver, and may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, and the like to the scan driver, may provide a clock signal suitable for a specification of the light emission driver, an emission stop signal, and the like to the light emission driver. The data driver may generate a data voltage supplied to the data signal lines D 1, D 2, D3,..... and Dn using a grayscale value and a control signal received from the timing controller. For example, the data driver may perform sampling from the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D 1 to Dn in pixel lines, where n may be a natural number. The scan driver may generate a scan signal, which is supplied to the scan signal lines S 1, S 2, S3,..... and Sm, by a clock signal, a scan start signal and the like received from the timing controller. The scan driver may sequentially supply scan signals having power-on level pulses to the scan signal lines S 1 to Sm, for example. The scan driver may be, for example, in the form of a shift register and generate the scan signals by sequentially transmitting the scan start signals provided in the form of power-on level pulses to a circuit of a next stage under the control of the clock signal, where m may be a natural number. The light emission driver may generate an emission signal by a clock signal, an emission stop signal, and the like received from the timing controller, which is supplied to the light emission signal lines E 1, E 2, E E3,..... , and Eo. For example, the light emission driver may sequentially supply emission signals with cut-off level pulses to the light emission signal lines E 1 to Eo. The light emission driver may be configured in the form of a shift register, for example, and generate the emission signals by sequentially transmitting emission stop signals provided in the form of blocking level pulses to a next-stage circuit under the control of the clock signal, where o may be a natural number.FIG. 2 is a schematic diagram of the structure of a display substrate. As shown in FIG. 2, the display substrate may include a display region 100, a bonding region 200 on one side of the display region 100, and a frame region 300 on other sides of the display region 100. In an exemplary embodiment, the display region 100 may be a flat region including a plurality of subpixels Pxij forming a pixel array. The plurality of subpixels Pxij may be configured to display dynamic images or still images, the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate and therefore the display substrate may be deformable, for example, corrugated, bent, folded, or rolled.In an exemplary embodiment, the bond region 200 may include a fanout region 201, a bending region 202, and a driver chip region 203 arranged in a direction away from the display region. The fanout region 201 can comprise at least one data transmission line. A plurality of data transmission lines are configured to be connected to the data signal lines of the display area. The bending portion 202 may include at least one bending recess configured to bend the driver chip portion 203 toward the back side of the display portion. The driver chip portion may include at least one integrated circuit (IC) and a plurality of pins (PIN), and the integrated circuit is configured to be connected to a plurality of data transmission lines. The plurality of pins are configured to be bonded to an external flexible printed circuit (FPC).In an exemplary embodiment, the frame portion 300 may include a circuit portion, a power line portion, a crack dam portion, and a cutting portion that are arranged in a direction away from the display portion. The circuit portion may include at least a plurality of cascaded gate driver circuits, the gate driver circuits being connected to a plurality of sense lines in the display portion. The power line portion may include at least: a frame power supply that extends in a direction parallel to the edge of the display portion and is connected to the cathode in the display portion. The crack dam region may include at least a plurality of cracks. The cutting region may comprise at least cutting grooves. The cutting grooves are configured such that after the formation of all film layers of the display substrate, a cutter cuts along the cutting grooves.In an exemplary embodiment, the fanout region in the bonding region 200 and the power line region in the frame region 300 may be provided with first insulating dams and second insulating dams, the first insulating dams and the second insulating dams may extend in a direction parallel to the edge of the display region, forming an annular structure around the display region. The edge of the display area is an edge of the display area on a side close to the binding area or the frame area.FIG. 3 is a schematic plan view of the structure of a display area in a display substrate. As shown in FIG. 3, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a subpixel P 1 that emits light of a first color, a second subpixel P 2 that emits light of a second color, and a third subpixel P 3 that emits light of a third color. Each subpixel may each include a circuit unit and a light emitting unit. The circuit unit may at least include: a pixel driving circuit. The pixel driving circuit is connected to each of the scan signal line, the data signal line, and the light emission signal line. The pixel driving circuit is configured to receive the data voltage transmitted from the data signal line and output the corresponding current to the light emitting unit under the control of the scan signal line and the light emitting signal line. The light emitting unit of each subpixel may at least comprise: a light emitting device. The light emitting device is each connected to the pixel driving circuit of the same subpixel, and the light emitting device is configured to emit light having a corresponding brightness in response to a current output from the pixel driving circuit of the same subpixel.In an exemplary embodiment, the first subpixel P 1 may be a green subpixel (G) that emits green light, the second subpixel P 2 may be a blue subpixel (B) that emits blue light, the third subpixel P 3 may be a red subpixel (R) that emits red light. In an exemplary embodiment, the shape of the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal. The three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a " "- manner, or the like, which is not to be limited in the present disclosure.In an exemplary embodiment, the pixel unit may include four subpixels. The four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or square, or the like, which is not to be limited in the present disclosure.FIG. 4 is a schematic sectional view of the structure of a display area in a display substrate, and illustrates the structure of three sub-pixels in the display area. As shown in FIG. 4, the display area in the plane perpendicular to the display substrate may include: a driver circuit layer 102 provided on the substrate 10; a light emitting structure layer 103 provided on a side of the driver circuit layer 102 facing away from the substrate 10; and an encapsulation structure layer 104 provided on a side of the light emitting structure layer 103 facing away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as touch control pattern layers or the like, which are not limited in the present disclosure.In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driver circuit layer 102 may include multiple circuit units, one circuit unit may include at least: a pixel driver circuit. The light emitting structure layer 103 may include a plurality of light emitting units, a light emitting unit may include at least: an anode, an organic light emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, the organic light emitting layer emits light in a corresponding color under driving of the anode and the cathode. The encapsulation structure layer 104 may at least include: a first packaging layer, a second packaging layer, and a third packaging layer, which are arranged in a stacked manner. The first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked layer structure, whereby it can be ensured that external water vapor cannot enter the light emitting structure layer 103.FIG. 5 is a schematic equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driver circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit may include seven transistors (a first transistor T 1 to a seventh transistor T 7) and a storage capacitor C, the pixel driving circuit is connected to six signal lines (a data signal line D, a first scan signal line S 1, a second scan signal line S 2, a light emission signal line E, a first power line VDD, and an initial signal line INIT), respectively.In an exemplary embodiment, the pixel driving circuit may include a first node N 1, a second node N 2, and a third node N 3. In this case, the first node N 1 is in each case connected to a first pole of the third transistor T 3, a second pole of the fourth transistor T 4 and a second pole of the fifth transistor T 5; the second node N 2 is in each case connected to a second pole of the first transistor, a first pole of the second transistor T 2, a gate electrode of the third transistor T 3 and a first end of the storage capacitor C; the third node N 3 is in each case connected to a second pole of the second transistor T 2, a second pole of the third transistor T 3 and a first pole of the sixth transistor T 6.In an exemplary embodiment, the first end of the storage capacitor C is connected to the second node N 2, a second end of the storage capacitor C is connected to the first power line VDD.In an exemplary embodiment, a gate electrode of the first transistor T 1 is connected to the second scan signal line S 2, a first pole of the first transistor T 1 is connected to the initial signal line INIT, a second pole of the first transistor is connected to the second node N 2. When an on-level scan signal is applied to the second scan signal line S 2, the first transistor T 1 transmits the first initial voltage to the gate electrode of the third transistor T 3 to initialize the charge amount of the gate electrode of the third transistor T 3.In an exemplary embodiment, a gate electrode of the second transistor T 2 is connected to the first scan signal line S 1, the first pole of the second transistor T 2 is connected to the second node N 2, the second pole of the second transistor T 2 is connected to the third node N 3. When the turn-on level scan signal is applied to the first scan signal line S 1, the second transistor T 2 connects the gate electrode of the third transistor T 3 to the second pole.The gate electrode of the third transistor T 3 is connected to the second node N 2, i.e. the gate electrode of the third transistor T 3 is connected to the first end of the storage capacitor C, the first pole of the third transistor T 3 is connected to the first node N 1, the second pole of the third transistor T 3 is connected to the third node N 3. The third transistor T 3 may be referred to as a driver transistor, the third transistor T 3 determines the magnitude of the driver current flowing between the first power line VDD and the second power line VSS depending on the potential difference between its gate electrode and the first pole.The gate electrode of the fourth transistor T 4 is connected to the first scan signal line S 1, the first pole of the fourth transistor T 4 is connected to the data signal line D, the second pole of the fourth transistor T 4 is connected to the first node N 1. The fourth transistor T 4 may be referred to as a switching transistor, a sense transistor, or the like. When the power-on level scan signal is applied to the first scan signal line S 1, the fourth transistor T 4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.The gate electrode of the fifth transistor T 5 is connected to the light emission signal line E, the first pole of the fifth transistor T 5 is connected to the first power line VDD, the second pole of the fifth transistor T 5 is connected to the first node N 1. The gate electrode of the sixth transistor T 6 is connected to the light emission signal line E, the first pole of the sixth transistor T 6 is connected to the third node N 3, the second pole of the sixth transistor T 6 is connected to a first pole of a light emitting device EL. The fifth transistor T 5 and the sixth transistor T 6 may be referred to as a light emitting transistor. When the turn-on level light emission signal is applied to the light emission signal line E, the fifth transistor T 5 and the sixth transistor T 6 cause the light emitting device EL to emit light by forming a driving current path between the first power line VDD and the second power line VSS.The gate electrode of the seventh transistor T 7 is connected to the first scan signal line S 1, the first pole of the seventh transistor T 7 is connected to an initial signal line INIT, the second pole of the seventh transistor T 7 is connected to the first pole of the light emitting device EL. When the turn-on level scan signal is applied to the first scan signal line S 1, the seventh transistor T 7 transmits the second initial voltage to the first terminal of the light emitting device, so that the charge amount accumulated in the first terminal of the light emitting device EL is initialized.In an exemplary embodiment, the light emitting device EL may be an OLED including a first pole (anode), an organic light emitting layer, and a second pole (cathode) stacked; or may be a QLED including a first pole (anode), a quantum dot light emitting layer, and a second pole (cathode) stacked.In an exemplary embodiment, the second pole of the light emitting unit EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low level signal, the signal of the first power line VDD is a continuously provided high level signal.In an exemplary embodiment, the first transistor T 1 to the seventh transistor T 7 may be P-type transistors or N-type transistors. By using transistors of a same type in the pixel driving circuit, the process flow can be simplified, the process difficulties of the display panel are reduced, the product yield is increased. In some possible implementations, the first transistor T 1 to the seventh transistor T 7 may include P-type transistors and N-type transistors.In an exemplary embodiment, the first transistor T 1 to the seventh transistor T 7 may use low-temperature polysilicon thin film transistors or oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors. An active layer of a low-temperature polysilicon thin film transistor uses low-temperature polysilicon (LTPS), and an active layer of an oxide thin film transistor uses an oxide semiconductor (oxide). Low temperature polysilicon thin film transistors have advantages of high mobility and rapid charging, and oxide thin film transistors have advantages of low leakage current. Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, so that advantages of the two can be utilized, whereby low-frequency driving can be enabled, power consumption can be reduced, and display quality can be improved.In an example embodiment, taking as an example that the seven transistors in the pixel driver circuit in FIG. 5 are all P-type transistors, the operation of the pixel driver circuit may include:a first phase, referred to as a reset phase. The signal of the second scan signal line S 2 is a low level signal, the signals of the first scan signal line S 1 and the light emission line E are high level signals. The signal of the second scan signal line S 2 is a low level signal so that the first transistor S 1 is turned on, and the signal of the initial signal line INIT is provided to the second node N 2, the storage capacitor C is initialized, the original data voltage in the storage capacitor is erased. The signals of the first scan signal line S 1 and the light emission line E are high level signals, the second transistor T 2, the fourth transistor T 4, the fifth transistor T 5, the sixth transistor T 6, and the seventh transistor T 7 are turned off. In this phase, OLED emits no light.a second phase, referred to as a data write phase or threshold compensation phase. The signal of the first scan signal line S 1 is a low level signal, the signals of the second scan signal line S 2 and the light emission line E are high level signals, the data signal line DL outputs a data voltage. Since, in this phase, the first end of the storage capacitor C is at a low level, the third transistor T 3 is turned on. The signal of the first scan signal line S 1 is a low level signal, so that the second transistor T 2, the fourth transistor T 4, and the seventh transistor T 7 are turned on. Turning on the second transistor T 2 and the fourth transistor T 4 causes the data voltage output from the data signal line D to be supplied to the second node N 2 via the first node N 1, the turned-on third transistor T 3, the third node N 3, the turned-on second transistor T 2, and the difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T 3 is introduced into the storage capacitor C, the voltage of the second end (namely, the second node N 2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output from the data signal line D and Vth is the threshold voltage of the third transistor T 3. The seventh transistor T 7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first pole of the OLED, thereby initializing (resetting) the first pole of the OLED, erasing its internal prestored voltage, and completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S 2 is a high level signal, so that the first transistor T 1 is turned off. The signal of the light emission line E is a high level signal, so that the fifth transistor T 5 and the sixth transistor T 6 are turned off.a third phase called a light emission phase. The signal of the light emission signal line E is a low level signal, the signals of the first scan signal line S 1 and the second scan signal line S 2 are high level signals. The signal of the light emission signal line E is a low level signal such that the fifth transistor T 5 and the sixth transistor T 6 are turned on, and the power supply voltage output from the first power line VDD provides a driving voltage to the first pole of the OLED via the turned-on fifth transistor T 5, the transistor T 3, and the sixth transistor T 6 to drive the OLED to emit light.During the driving operation of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the second node N 2 is Vd-|Vth|, the driving current of the third transistor T 3 is: where I is the driving current flowing through the third transistor T 3, i.e., a driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T 3, Vth is the threshold voltage of the third transistor T 3, Vd is the data voltage output from the data signal line D, Vdd is the power supply voltage output from the first power line VDD.FIG. 6 is a schematic plan view of the structure of a fanout region in a bond region. In an exemplary embodiment, the bond region may be located on a side of the display region in a plane parallel to the display substrate, the bond region may include at least one fanout region 201 near the display region. As shown in FIG. 6, the fanout region 201 may be provided with at least a first power line 110, a second power line 120, and a plurality of communication lines (not shown). The plurality of data transmission lines are configured to connect the data signal lines of the display area 100. The first power line 110 is connected to the high voltage power line of the display area 100 and configured to provide high voltage signals to a plurality of circuit units of the display area 100. The second power line 120 is connected to the low voltage power line of the frame portion and configured to provide low voltage signals to a plurality of light emitting units of the display portion 100.In an exemplary embodiment, the fanout region 201 may include at least a first transition region 211, an insulating dam region 213, and a second transition region 212 arranged sequentially in a direction away from the display region 100. The first transition region 211 is connected to the display region 100 and is configured as a region where the cathode extends. The insulation dam portion 213 is connected to the first transition portion 211, and is configured as a portion where an insulation dam (Dam) and a separation groove (slot) are provided. The second transition region 212 is connected to the insulating dam region 213 and is configured as a region outside the packaging structure.In an exemplary embodiment, the cathode in the light emitting structure layer is formed by an open mask (OPM) to reduce cost and increase production capacity. As a rule, the opening on the cathode shadow shell (shadow) exposes the display region and its peripheral region, so that a cathode is formed in the first transition region 211 of the fanout region 201 and the edge of the cathode facing away from the display region is located in the central region of the first transition region 211.In an exemplary embodiment, the insulating dam region 213 may include at least: a first groove region B 1, a first dam region C 1, a second groove region B 2, a second dam region C 2, and a third groove region B 3 which are sequentially arranged in a direction away from the display region 100. The first groove portion B 1 is configured to provide a first separation groove 310. The second groove portion B 2 is configured to provide a second separation groove 320. The third groove portion B 3 is configured to provide a third separation groove 330. The first dam region C 1 is configured to provide a first isolation dam 410. The second dam region C 2 is configured to provide a second isolation dam 420.In an exemplary embodiment, the distance of the first insulating dam 410 from the edge of the display region is smaller than the distance of the second insulating dam 420 from the edge of the display region, i.e. the second insulating dam 420 is arranged on a side of the first insulating dam 410 facing away from the display region 100. The first separation groove 310 may be disposed on the side of the first isolation dam 410 near the display area, the second separation groove 320 may be disposed between the first isolation dam 410 and the second isolation dam 420, the third separation groove 330 may be disposed on a side of the second isolation dam 420 facing away from the display area 100.In an exemplary embodiment, the first isolation dam 410 and the second isolation dam 420 may be a dam structure stacked from a plurality of organic layers; the first isolation dam 410 and the second isolation dam 420 are configured to prevent the organic encapsulation layer from leaking. The organic layers in the first separation groove 310, the second separation groove 320, and the third separation groove 330 are removed, thereby exposing the surface of the first power line 110 or the second power line 120, thus improving the encapsulation effect of the inorganic encapsulation layer.In an exemplary embodiment, the first isolation dam 410, the second isolation dam 420, the first separation groove 310, the second separation groove 320, and the third separation groove 330 may extend in a direction parallel to the edge of the display area to form an annular structure around the display area 100. The edge of the display area is an edge on a side of the display area close to the binding area or the frame area.The research reveals that the first current line in the fanout region 201 can lead to the short-circuit failure of the cathode (cathode). In the display substrate with a narrowed lower frame, if the process margin (margin) for the edge of the cathode opening on the cathode shadow shell used for manufacturing the cathode is insufficient or the process parameters fluctuate greatly, the edge of the cathode protrudes beyond the first transition region and extends to the region where the first separation groove 310 is located. Since the organic layer in the first separation groove 310 is removed and the surface of the first power line 110 is exposed, the cathode extending into the first separation groove 310 interferes with the first power line 110, resulting in the cathode short circuit and, as a result, poor display of the display substrate is produced. Further research reveals that the edges of the first power line 110 and of the second power line 120 could still form water vapor transmission paths in the fanout region 201. When a gap or a crack occurs in the packaging structure layer, the water vapor in the atmosphere may enter the water vapor transmission path and the light emitting device along the gap or the crack. As water vapor enters the light emitting device continuously along the water vapor transmission path, the failure area is thus gradually increased, and thus a poor display of the display substrate is produced, which is referred to as a growing dark spot (growth dark spot, abbreviated as GDS).The present disclosure provides a display substrate comprising a display area and a bonding area located on a side of the display area, the bonding area comprising at least: a fanout area and a bending area, the fanout area being located between the display area and the bending area, the fanout area comprising at least: a first transition area, an insulating dam area, and a second transition area arranged in a direction away from the display area; the fanout area comprising a bonding structure layer provided on a substrate comprising at least: a gate metal layer and a source-drain metal layer arranged on a side of the gate metal layer facing away from the substrate, the gate metal layer comprising one or more of: a first gate metal layer, a second gate metal layer and a third gate metal layer that can be arranged one after the other in the direction away from the substrate, wherein the source-drain metal layer comprises one or more of the following: a first source-drain metal layer and a second source-drain metal layer that can be arranged one after the other in the direction away from the substrate, wherein the gate metal layer is provided with a power connection line, the source-drain metal layer is provided with a first power line, the power connection line is provided in the first transition region, the insulating dam region and the second transition region, the first power line is provided in the first transition region and the second transition region, the first power line in the first transition region and the first power line in the second transition region are connected to each other via the power connection line.In an exemplary embodiment, the bond structure layer further includes a first planarization layer disposed on a substrate-opposite side of the first source-drain metal layer, the first power line being disposed on a substrate-opposite side of the first planarization layer, the first source-drain metal layer being provided with a first overlapping electrode and a second overlapping electrode, the first overlapping electrode being disposed in the first transition region, the second overlapping electrode being disposed in the second transition region, the first power line of the first transition region being connected to the first overlapping electrode, the first overlapping electrode being connected to a side of the power connection line that is near the display region, the first power line of the second transition region being connected to the second overlapping electrode, the second overlapping electrode being connected to a display-opposite side of the power connection line.In an exemplary embodiment, the bonding structure layer further includes an inorganic insulating layer disposed on a substrate opposite side of the power connection line and provided with a first connection opening and a second connection opening, wherein the first overlapping electrode is connected to the power connection line side near the display region through the first connection opening, the second overlapping electrode is connected to the opposite side of the power connection line from the display region through the second connection opening.In an exemplary embodiment, the insulating dam portion is provided with at least one insulating dam and at least one separating groove, the insulating dam being disposed on the side of the inorganic insulating layer facing away from the display portion, the separating groove being disposed on the side of the insulating dam close to the display portion or on the side of the insulating dam facing away from the display portion, and the separating groove exposing the surface of the inorganic insulating layer.FIG. 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, showing a cross-sectional structure along the A-A direction of FIG. 6 In a plane parallel to the display substrate, the display substrate may include at least: a display region 100 and a fanout region 201 located on a side of the display region 100. As shown in FIG. 7, the fanout region 201 may include at least a first transition region 211, an insulating dam region 213, and a second transition region 212 that are sequentially arranged in a direction away from the display region 100. The insulation dam portion 213 is configured to provide at least one insulation dam and at least one separation groove.In an exemplary embodiment, the insulating dam region 213 may include at least: a first groove region B 1, a first dam region C 1, a second groove region B 2, a second dam region C 2, and a third groove region B 3 which are sequentially arranged in a direction away from the display region 100. The first groove portion B 1 is configured to provide a first separation groove 310. The second groove portion B 2 is configured to provide a second separation groove 320. The third groove portion B 3 is configured to provide a third separation groove 330. The first dam region C 1 is configured to provide a first isolation dam 410. The second dam region C 2 is configured to provide a second isolation dam 420.In an exemplary embodiment, the display region 100 may include, in a plane perpendicular to the display substrate, at least one of a driver circuit layer 102 disposed on the substrate 10, a light emitting structure layer 103 disposed on a side of the driver circuit layer 102 facing away from the substrate 10, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 facing away from the substrate 10.In an exemplary embodiment, the driver circuit layer 102 may include at least a first insulating layer 11 provided on the substrate 10, a first semiconductor layer provided on a substrate-opposite side of the first insulating layer 11, a second insulating layer 12 provided on the substrate-opposite side of the first semiconductor layer, a first gate metal layer provided on a substrate-opposite side of the second insulating layer 12, a third insulating layer 13 provided on a substrate-opposite side of the first gate metal layer, a second gate metal layer provided on a substrate-opposite side of the third insulating layer 13, a fourth insulating layer 14 provided on a substrate-opposite side of the second gate metal layer, a second semiconductor layer provided on a substrate-opposite side of the fourth insulating layer 14, a fifth insulating layer 15 provided on a substrate-opposite side of the second semiconductor layer, a third gate metal layer provided on a substrate-opposite side of the fifth insulating layer 15, a sixth insulating layer 16 provided on a substrate-opposite side of the third gate metal layer, a first source-drain metal layer provided on a substrate-opposite side of the sixth insulating layer 16, a first planarization layer 17 provided on a substrate-opposite side of the first source-drain metal layer, a second source-drain metal layer provided on a substrate-opposite side of the first planarization layer, a second planarization layer 18 provided on a substrate-opposite side of the second source-drain metal layer.In an exemplary embodiment, the first semiconductor layer may include at least one first active layer; the first gate metal layer may include at least one first gate electrode and a first electrode plate; the second gate metal layer may include at least one second electrode plate and a shield layer; the second semiconductor layer may include at least one second active layer; the third gate metal layer may include at least one second gate electrode; the first source-drain metal layer may include at least one first source electrode, a first drain electrode, a second source electrode, and the second drain electrode; the second source-drain metal layer may include at least one anode connection electrode; the first active layer, the first gate electrode, the first source electrode and the first drain electrode form a first transistor 20 of the low temperature polysilicon; the second active layer, the second gate electrode, the second source electrode and the second drain electrode form a second transistor 30 made of oxide, and the first electrode plate and the second electrode plate form a storage capacitor 40. In an exemplary embodiment, the first transistor 20 may be a driving transistor of the pixel driving circuit, the second transistor 30 may be a switching transistor of the pixel driving circuit.In an exemplary embodiment, the light emitting structure layer 103 may include at least an anode 91, a pixel defining layer 92, an organic light emitting layer 93, and a cathode 94. the anode 91 is connected to the first drain electrode of the first transistor 20 via an anode connection electrode, the organic light emitting layer 93 is connected to the anode 91, the cathode 94 is connected to the organic light emitting layer 93, the organic light emitting layer 93 emits light in respective colors under driving of the anode 91 and the cathode 94.In an exemplary embodiment, the encapsulation structure layer 104 may include at least: a first packaging layer 95, a second packaging layer 96, and a third packaging layer 97, which are arranged in a stacked manner. The first packaging layer 95 and the third packaging layer 95 may be made of inorganic materials, and the second packaging layer 96 may be made of inorganic materials, the second encapsulation layer 96 is disposed between the first encapsulation layer 95 and the third encapsulation layer 97 to form an inorganic material / organic material / inorganic material stacked layer structure, whereby it can be ensured that external water vapor cannot enter the light emitting structure layer 103.In an exemplary embodiment, the fanout region 201 of the bond region may comprise at least one bond structure layer 50 arranged on the substrate 10 and one composite encapsulation layer arranged on a side of the bond structure layer 50 facing away from the substrate in a plane perpendicular to the display substrate.In an exemplary embodiment, the bond structure layer 50 may include at least: a gate metal layer and a source-drain metal layer disposed on a side of the gate metal layer opposite the substrate. The gate metal layer may include at least a third gate metal layer, the source-drain metal layer may include at least: a first source-drain metal layer and a second source-drain metal layer. A power connection line 60 is provided in the third gate metal layer, a first overlapping electrode 61 and a second overlapping electrode 62 are provided in the first source-drain metal layer, a first power line 110 is provided in the second source-drain metal layer.In an exemplary embodiment, the bond structure layer 50 may further include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, a sixth insulating layer 16, a first planarization layer 17, and a second planarization layer 18. The first insulating layer 11 is disposed on the substrate 10, the second insulating layer 12 is disposed on the substrate-opposite side of the first insulating layer 11, the third insulating layer 13 is disposed on the substrate-opposite side of the second insulating layer 12, the fourth insulating layer 14 is disposed on the substrate-opposite side of the third insulating layer 13, the fifth insulating layer 15 is disposed on the substrate-opposite side of the fourth insulating layer 14, the power connection line 60 is disposed on the substrate-opposite side of the fifth insulating layer 15, the sixth insulating layer 16 is disposed on the substrate-opposite side of the power connection line 60, the first overlapping electrode 61 and the second overlapping electrode 62 are disposed on the substrate-opposite side of the sixth insulating layer 16, the first planarization layer 17 is disposed on the substrate-opposite side of the first overlapping electrode 61 and the second overlapping electrode 62, the first power line 110 is disposed on a substrate-opposite side of the first planarization layer 17, the second planarization layer 18 is disposed on a substrate-opposite side of the first power line 110.In an exemplary embodiment, the power connection line 60 may be located in a portion of the first transition region 211, the entire portion of the isolation dam region 213, and a portion of the second transition region 212, i.e., the power connection line 60 may extend from the first transition region 211, through the isolation dam region 213, to the second transition region 212.In an exemplary embodiment, the first power line 110 may be located in each of the first transition region 211 and the second transition region 212, the first overlapping electrode 61 may be located in the first transition region 211, the second overlapping electrode 62 may be located in the second transition region 212, the first power line 110 of the first transition region 211 is connected to the first overlapping electrode 61, the first overlapping electrode 61 is connected to a side of the power connection line 60 (part located in the first transition region 211) close to the display region, the first power line 110 of the second transition region 212 is connected to the second overlapping electrode 62, the second overlapping electrode 62 is connected to a side of the power connection line 60 (part located in the second transition region 212) facing away from the display region, the first power line 210 passes through the insulation dam region 213 through the first overlapping electrode 61, respectively, the power connection line 60 and the second overlapping electrode 62, thereby forming a first power line that crosses the isolation dam area 213 through a switching fabric.In an exemplary embodiment, a first connection hole and a second connection hole may be provided on the sixth insulating layer 16 covering the power connection line 60; the first overlapping electrode 61 may be connected to the side of the power connection line 60 near the display area through the first connection hole, the second overlapping electrode 62 may be connected to the side of the power connection line opposite from the display area through the second connection hole.In an exemplary embodiment, a third connection opening may be provided on the first planarization layer 17 covering the first overlapping electrode 61; the first power line 110 of the first junction region 211 may be connected to the first overlapping electrode 61 through the third connection opening.In an exemplary embodiment, a first separation groove may be provided on the first planarization layer 17; the first separation groove exposes a partial surface of the first overlapping electrode 61 on the opposite side from the display region, a partial surface of the second overlapping electrode 62 on the side close to the display region, and a surface of the sixth insulating layer 16 located between the first overlapping electrode 61 and the second overlapping 62 electrode; the orthographic projection of the first separation groove on the substrate includes the orthographic projection of the insulating dam region 213 on the substrate.In an exemplary embodiment, the first planarization layer 17 on the side of the first separation groove near the display region covers the edge of the first overlapping electrode 61 on the side near the display region, and the first planarization layer 17 on the side of the first separation groove opposite to the display region covers the edge of the second overlapping electrode 62 on the side opposite to the display region.In an exemplary embodiment, the first power line 110 of the first transition portion 211 engages with the first overlapping electrode 61 exposed in the first separation groove; the first power line 110 of the first transition portion 211 covers the edge of the first overlapping electrode 61 on the opposite side from the display portion.In an exemplary embodiment, the first power line 110 of the second transition portion 212 engages with the second overlapping electrode 62 exposed in the first separation groove; the first power line 110 of the second transition portion 212 covers the edge of the second overlapping electrode 62 on the side close to the display portion.In an exemplary embodiment, a second separation groove may be provided on the second planarization layer 18, the orthographic projection of the second separation groove on the substrate may be within the perimeter of the orthographic projection of the first separation groove on the substrate, the orthographic projection of the second separation groove on the substrate includes the orthographic projection of the isolation dam region 213 on the substrate.In an exemplary embodiment, the second planarization layer 18 on the side of the second separation groove near the display region may cover the edge of the first power line 110 of the first transition region 211 on the side opposite to the display region, the second planarization layer 18 on the side opposite to the display region of the second separation groove may cover the edge of the first power line 110 of the second transition region 212 on the side near the display region.In an exemplary embodiment, at least one insulating dam and at least one insulating groove are provided in the second separating groove, the insulating dam may be provided on the side of the sixth insulating layer 16 facing away from the display region, the separating groove may be disposed on the side of the insulating dam close to the display region or on the side of the insulating dam facing away from the display region, the separating groove exposes the surface of the sixth insulating layer 16.In an exemplary embodiment, a first insulating dam 410 located in the first dam region C 1 and a second insulating dam 420 located in the second dam region C 2 may be included in the second separation groove, the distance between the second insulating dam 420 and the display region 100 is greater than the distance between the first insulating dam 410 and the display region 100, the distance between the surface of the second insulating dam 420 on a side facing away from the substrate and the substrate is greater than the distance between the surface of the first insulating dam 410 on a side facing away from the substrate and the substrate.In an exemplary embodiment, a first separating groove 310 located in the first groove region B 1, a second separating groove 320 located in the second groove region B 2, and a third separating groove 330 located in the third groove region B 3 may be included in the second separating groove, i.e., the first separating groove 310 is located on the side of the first insulating dam 410 located near the display region, the second separating groove 320 is located between the first insulating dam 410 and the second insulating dam 420, the third separating groove 330 is located on the side of the second insulating dam 420 remote from the display region. The organic material layers in the first separation groove 310, the second separation groove 320, and the third separation groove 330 are removed, exposing the sixth insulating layer 16, such that the first encapsulation layer 95 in the packaging structure layer overlaps the sixth insulating layer 16 in the first separation groove 310, the second separation groove 320, and the third separation groove 330, respectively.In an exemplary embodiment, the first isolation dam 410 may include a second dam base and a fourth dam base that are arranged in a stacked manner. The second bank base and the second planarization layer may be disposed on a same layer and synchronously formed by a same patterning process. The fourth bank base and the pixel definition layer may be disposed on one and the same layer and synchronously formed by one and the same patterning process.In an exemplary embodiment, the second isolation dam 420 may include a first dam base, a third dam base, and a fifth dam base that are arranged in a stacked manner. The first bank base and the first planarization layer may be disposed on one and the same layer and may be synchronously formed by one and the same patterning process. The third bank base and the second planarization layer may be disposed on a same layer and synchronously formed by a same patterning process. The fifth bank base and the pixel definition layer may be disposed on one and the same layer and synchronously formed by one and the same patterning process.In an exemplary embodiment, the current connection line 60 of the fanout region 201 and the second gate electrode of the display region may be disposed on one and the same layer and synchronously formed by one and the same patterning process.In an exemplary embodiment, the first overlapping electrode 61 and the second overlapping electrode 62 of the fanout region 201 and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode of the display region may be disposed on one and the same layer and synchronously formed by one and the same patterning process.In an exemplary embodiment, the first power line 110 of the fanout region 201 and the anode connection electrode of the display region may be disposed on one and the same layer and synchronously formed by one and the same patterning process.As follows, a manufacturing process of the display substrate according to an exemplary embodiment will be explained, for example. The "patterning process" mentioned in the present disclosure includes treatments such as applying a photoresist, exposing a mask, developing, etching, and peeling off the photoresist or the like for a metallic material, an inorganic material, or a transparent conductive material, and includes treatments such as applying an organic material, exposing a mask, developing, or the like for an organic material. As the deposition, one or more of sputtering, vapor deposition, or chemical vapor deposition may be used, as the application, one or more of spray coating, spin coating, and inkjet printing may be used, and as the etching, one or more of dry etching or wet etching may be used, which is not limited in the present disclosure. "Film" refers to a thin film made of a material by deposition, application, or other method on the substrate. If the "film" does not need a patterning process throughout the manufacturing process, the "film" may also be referred to as a "layer.". If the "film" still needs a patterning process throughout the manufacturing process, the "film" will be referred to as "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the expression "A and B are provided on one and the same layer" means that A and B are simultaneously formed by the same patterning process, and the "thickness" of a film layer is a dimension of the film layer in a direction perpendicular to a display substrate. The phrase "the orthographic projection of B is within the scope of an orthographic projection of A" and the phrase "the orthographic projection of A includes the orthographic projection of B" mean, in exemplary embodiments of the present disclosure, that the boundary of the orthographic projection of B falls within the scope of the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A and the boundary of the orthographic projection of B overlap.In an exemplary embodiment, the manufacturing method of the display substrate may include the following operations:(1) forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include depositing a first insulating film and a first semiconductor film on a substrate 10 in sequence, patterning the first semiconductor film by a patterning process to form a first insulating layer 11 covering the entire substrate 10 and the first semiconductor layer pattern provided on the first insulating layer 11, wherein the first semiconductor layer pattern may be provided in the display region 100 and include at least one first active layer 21, as illustrated in FIG. 8.In an exemplary embodiment, patterning the first semiconductor film by a patterning process may include: forming an amorphous silicon film (a-si film) on the first insulating film first, performing dehydrogenation treatment of the amorphous silicon film, crystallizing the dehydrated amorphous silicon film to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern. The presence of a large amount of hydrogen in amorphous silicon leads to defects in subsequent processes, and thus a hydrogen extraction process must be performed after the formation of the amorphous silicon film. The crystallization process is a process for crystallizing amorphous silicon into polycrystalline silicon (p-si). For example, the crystallization process may be performed by an excimer laser annealing (ELA) process. Since the annealing process used to form the polysilicon could damage the oxide, the first active layer of the low temperature polysilicon is formed prior to the formation of the second active layer of the metal oxide.In an exemplary embodiment, the first insulating layer may prevent materials in the substrate from diffusing into other film layer structures and degrading the quality of the display substrate in subsequent processes.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bond region may include the first insulating layer 11 disposed on the substrate 10.(2) forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive film pattern may include depositing a second insulating film and a first conductive film sequentially on the substrate on which the foregoing pattern is formed, patterning the first conductive film by a patterning process to form a second insulating layer 12 covering the first semiconductor film pattern and the first conductive film pattern provided on the second insulating layer 12, wherein the first conductive film pattern may be provided in the display region 100, and at least may include a gate electrode 22 and a first electrode plate 41 as illustrated in FIG. 9. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal layer (GATE 1).In an exemplary embodiment, the orthographic projection of the first gate electrode 22 on the substrate may be within the scope of the orthographic projection of the first active layer 21 on the substrate.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bond region may include the first insulating layer 11 and the second insulating layer 12 stacked on the substrate 10.(3) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive film pattern may include depositing a third insulating film and a second conductive film sequentially on the substrate on which the foregoing pattern is formed, patterning the second conductive film by a patterning process to form a third insulating film 13 covering the first conductive film pattern and the second conductive film pattern provided on the third insulating film 13, wherein the second conductive film pattern may be provided in the display region 100, and at least may include a second electrode plate 42 and a shield film 51 considered as a second transistor shield structure, as illustrated in FIG. 10. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal layer (GATE 2).In an exemplary embodiment, the orthographic projection of the second electrode plate 42 on the substrate overlaps at least partially with the orthographic projection of the first electrode plate 41 on the substrate, the first electrode plate 41 and the second electrode plate 42 form a storage capacitor of the pixel driving circuit.After this patterning process, the fanout region 201 of the bonding region may include the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 stacked on the substrate 10.(4) forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include depositing a fourth insulating film and a second semiconductor film sequentially on a substrate on which the foregoing pattern is formed, patterning the second semiconductor film by a patterning process to form a fourth insulating layer 14 covering the entire substrate 10 and the second semiconductor layer pattern provided on the fourth insulating layer 14, wherein the second semiconductor layer pattern may be provided in the display region 100 and include at least one second active layer 31, as illustrated in FIG. 11.In an exemplary embodiment, the orthographic projection of the second active layer 31 on the substrate may be within the scope of the orthographic projection of the shielding layer 51 on the substrate.In an exemplary embodiment, the second semiconductor film may use an oxide, and the oxide may be one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), Aluminum gallium nitride (AlGaN) and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor film may use indium gallium zinc oxide (IGZO). The electron mobility of indium gallium zinc oxide (IGZO) is higher than that of the amorphous silicon.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bond region may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 stacked on the substrate 10.(5) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive film pattern may include: depositing a fifth insulating film and a third conductive film sequentially on a substrate on which the foregoing pattern is formed; patterning the third conductive film by a patterning process around a fifth insulating film 15 covering the second semiconductor film pattern and the third conductive film pattern provided on the fifth insulating film 15, wherein the third conductive film pattern may at least include a second gate electrode 32 and a power connection line 60 as illustrated in FIG. 12. In example embodiments, the third conductive layer may be referred to as a third gate metal layer (GATE 3).In an exemplary embodiment, the second gate electrode 32 may be located in the display region 100, the orthographic projection of the second gate electrode 32 on the substrate may be located within the scope of an orthographic projection of the second active layer 31 on the substrate.In an exemplary embodiment, the power connection line 60 may be located in the bond area in the fanout region 210, the power connection line 60 is configured to be connected to the subsequently formed first and second overlapping electrodes.In an exemplary embodiment, the fanout region 210 in the bond region may at least include: a first transition region 211, an insulating dam region 213, and a second transition region 212 arranged sequentially in a direction away from the display region 100. The first transition region 211 is connected to the display region 100 and is configured as a region where the cathode extends. The insulating dam portion 213 is connected to the first transition portion 211 and is configured as a portion in which insulating dams and separation grooves are provided. The second transition region 212 is connected to the insulating dam region 213 and configured as a region outside the encapsulation structure layer. In an exemplary embodiment, the power connection line 60 may be located in a portion of the first transition region 211 on the side opposite from the display region, in the entire region of the insulating dam region 213, and in a portion of the second transition region 212 on the side close to the display region, i.e., the power connection line 60 may extend from the first transition region 211, across the insulating dam region 213, to the second transition region 212, and the power connection line 60 is configured as a relay connection line through which the first power line passes through the insulating dam region 213.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bonding region may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15, and the current connection line 60 stacked on the substrate 10.(6) forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating film pattern may include: depositing a sixth insulating film on the substrate on which the foregoing pattern is formed, patterning the sixth insulating film by a patterning process to form a sixth insulating film 16 covering the third conductive film pattern. The sixth insulating layer 16 is provided with a plurality of through holes and a plurality of connection holes as shown in FIG. 13.In an exemplary embodiment, a plurality of through holes may be located in the display region 100, the plurality of through holes may include at least: first through holes K 1 each located at two ends of the first active layer 21, and second through holes K 2 each located at two ends of the second active layer 31.In an exemplary embodiment, the orthographic projections of the first through-holes K 1 on the substrate may be within the perimeter of the orthographic projection of the first active layer 21 on the substrate; the sixth insulating layer 16, the fifth insulating layer 15, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 in the first through-holes K 1 are etched away, and the surface of the first active layer 21 is exposed; the first through-holes K 1 are configured such that subsequently formed first source electrode and first drain electrode are connected to the first active layer 21 through the through-holes, respectively. The orthographic projections of the second through-holes K2 on the substrate may be etched away within the circumference of the orthographic projection of the second active layer 31 on the substrate; the sixth insulating layer 16 and the fifth insulating layer 15 in the second through-holes K2 are etched away, and the surface of the second active layer 31 is exposed; the second through-holes K2 are configured such that subsequently formed second source electrode and second drain electrode are connected to the second active layer 31 through the through-holes, respectively.In an exemplary embodiment, the plurality of connection openings may be located in the fanout region 201, the plurality of connection openings may at least include: a first connection opening 71 located in the first transition region 211 and a second connection opening 72 located in the second transition region 212. The sixth insulating film 16 in the first connection hole 71 is etched away, and the surface of the power connection line 60 on the side near the display area is exposed. The sixth insulating film 16 in the second connection hole 72 is etched away, and the surface of the power connection line 60 on the opposite side from the display area is exposed. In an exemplary embodiment, the first connection hole 71 and the second connection hole 72 are configured such that a subsequently formed overlapping electrode is connected to the power connection line 60 through the connection hole.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bonding region may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15, the power connection line 60, and the sixth insulating layer 16 stacked on the substrate 10.(7) forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive film pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed; patterning the fourth conductive film by a patterning process to form the fourth conductive film pattern on the sixth insulating layer 16, wherein the fourth conductive film pattern may include at least a first source electrode 23, a first drain electrode 24, a second source electrode 33, a second drain electrode 34, a first overlapping electrode 61, and a second overlapping electrode 62, as shown in FIG. 14. In example embodiments, the third conductive layer may be referred to as a first source-drain metal layer (SD 1).In an exemplary embodiment, the first source electrode 23, the first drain electrode 24, the second source electrode 33, and the second drain electrode 34 may be located in the display region 100, the first source electrode 23 and the first drain electrode 24 are connected to the first active layer 21 through the first through holes K 1, respectively, the second source electrode 33 and the second drain electrode 34 are connected to the second active layer 31 through the second through holes K 2, respectively.In example embodiments, the first overlapping electrode 61 and the second overlapping electrode 62 may be located in the fanout region 201. The first overlapping electrode 61 may be located in the first transition region 211 of the fanout region 201, the first overlapping electrode 61 is connected to a side near the display region through the first connection opening 71. The second overlapping electrode 62 can be located in the second transition region 212 of the fanout region 201, the second overlapping electrode 62 being connected to the side of the power connection line 60 facing away from the display region by the second connection opening 72.In an exemplary embodiment, the first active layer 21, the first gate electrode 22, the first source electrode 23, and the first drain electrode 24 form a first transistor 20, the first transistor 20 is a low-temperature polysilicon thin film transistor; the second active layer 31, the second gate electrode 32, the second source electrode 33, and the second drain electrode 34 form a second transistor 30, the second transistor 30 is an oxide thin film transistor; the first electrode plate 41 and the second electrode plate 42 form a storage capacitor 40.In an exemplary embodiment, after this patterning process, the fanout region 201 of the bond region may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14, the fifth insulating layer 15, the current connection line 60, the sixth insulating layer 16, and the first source-drain metal layer stacked on the substrate 10. The first source-drain metal layer may include a first overlapping electrode 61 and a second overlapping electrode 62.(8) forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a first planarization film on the substrate on which the foregoing pattern is formed; patterning the first planarization film by a patterning process to form a pattern of a first planarization (PLN) layer 17 covering the fourth conductive layer, as illustrated in FIG. 15.In an exemplary embodiment, the pattern of the first planarization layer 17 may include at least a third through hole K 3, a third connection hole 73, a first separation groove 81, and a first bank base 401.In an exemplary embodiment, the third through hole K 3 may be located in the display region 100, the first planarization layer 17 in the third through hole K 3 is removed, the surface of the first drain electrode of the first transistor 20 is exposed, the third through hole K 3 is configured such that a subsequently formed anode connection electrode is connected to the first drain electrode through the through hole.In an exemplary embodiment, the first separation groove 81 may be located in the fanout region 201, the orthographic projection of the first separation groove 81 on the substrate may include the orthographic projection of the insulating dam region 213 on the substrate, the first planarization film in the first separation groove 81 is removed, the surfaces of the sixth insulating layer 16, the first overlapping electrode 61, and the second overlapping electrode 62 are exposed, respectively.In an exemplary embodiment, the first planarization layer 17 on the side of the first separation groove 81 close to the display region 100 covers a portion and the edge of the first overlapping electrode 61 on the side close to the display region 100, the first separation groove 81 exposes the surface of the portion of the first overlapping electrode 61 on the side opposite to the display region 100.In an exemplary embodiment, the first planarization layer 17 on the opposite side of the first separation groove 81 from the display region 100 covers a portion and the edge of the second overlapping electrode 62 on the opposite side from the display region 100, the first separation groove 81 exposes the surface of the portion of the second overlapping electrode 62 on the side close to the display region 100.In an exemplary embodiment, the third connection hole 73 may be located on the first planarization layer 17 covering the first overlapping electrode 61; the first planarization film in the third connection hole 73 is removed, the surface of the first overlapping electrode 61 is exposed; the third connection hole 73 is configured such that the subsequently formed first power line is connected to the first overlapping electrode 61 through the third connection hole 73.In an exemplary embodiment, the first dam base 401 may be located in the area where the first separation groove 81 is located. The insulating dam region 213 may include at least: a first groove region B 1, a first dam region C 1, a second groove region B 2, a second dam region C 2, and a third groove region B 3 which are sequentially arranged in a direction away from the display region 100. The first bank base 401 may be located in the second bank area C 2. The first bank base 401 is disposed on a substrate-opposite side of the sixth insulating layer 16. The first bank base 401 is formed as a bank base of the second insulating bank.In the exemplary embodiment, other regions in the first separation groove 81 expose the surface of the sixth insulating layer 16 besides the first bank base 401.After this patterning process, the bond region fanout region 201 may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15, the power connection line 60, the sixth insulating layer 16, the first source-drain metal layer, and the first planarization layer 17 stacked on the substrate 10. The first source-drain metal layer may include the first overlapping electrode 61 and the second overlapping electrode 62. The first planarization layer 17 is provided with the first separation groove 81, the first separation groove 81 exposes the surface of the sixth insulating layer 16, and the first bank base 401 is formed in the first separation groove 81.(9) forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive film pattern may include: depositing a fifth conductive film on the substrate on which the foregoing pattern is formed; patterning the fifth conductive film by a patterning process to form the fifth conductive film pattern on the first planarization layer 17, wherein the fifth conductive film pattern may include at least: an anode connection electrode 52 and the first power line 110, as shown in FIG. 16. In example embodiments, the fifth conductive layer may be referred to as a second source-drain metal layer (SD 2).In an exemplary embodiment, the anode connection electrode 52 may be located in the display region 100, the anode connection electrode 52 is connected to the first drain electrode of the first transistor 20 via the third through hole K 3, the anode connection electrode 52 is configured to be connected to a subsequently formed anode.In an exemplary embodiment, the first power line 110 may be located in the display region 100 and the first transition region 211 and the second transition region 212 of the fanout region 201, respectively; the first power line 110 located in the display region 100 is connected to the first power line of the pixel driving circuit; the first power line 110 located in the first transition region 211 of the fanout region 201 is connected to the first overlapping electrode 61; the first power line 110 located in the second transition region 212 of the fanout region 201 is connected to the second overlapping electrode 62.In an exemplary embodiment, in the first transition region 211 of the fanout region 201, the first power line 110 is connected to the first overlapping electrode 61 through the third connection hole 73, extends in the direction away from the display substrate 100, and engages with the first overlapping electrode 61 exposed in the first separation groove 81, and the first power line 110 wraps around the edge of the first overlapping electrode 61 on the side opposite to the display region 100.In an exemplary embodiment, in the second transition region 212 of the fanout region 201, the first power line 110 engages with the second overlapping electrode 62 exposed in the first separation groove 81, and the first power line 110 wraps around the edge of the second overlapping electrode 62 on the side facing away from the display region 100.In an exemplary embodiment, according to the present disclosure, the first current line 110 wraps the edge of the first overlapping electrode 61 on the opposite side from the display region 100 and wraps the edge of the second overlapping electrode 62 on the opposite side from the display region 100, whereby not only the first overlapping electrode 61 and the second overlapping electrode 62 can be effectively protected, but also the peel strength of the film layers can be increased and the product quality is improved. In the present disclosure, the first power line 110 is connected to the first overlapping electrode 61 through the third connection hole 73 and the first separation groove 81, respectively, whereby not only the connection reliability can be improved, but also the process quality of forming the first planarization layer can be increased using the third connection hole 73 as the vent hole.In the exemplary embodiment, since the first power line 110 of the fanout portion 201 is connected to the first overlapping electrode 61 and the second overlapping electrode 62, respectively, and the first overlapping electrode 61 and the second overlapping electrode 62 are connected to the power connection line 60, respectively, the first power line 110 of the first transition portion 211 is allowed to be connected to the first power line 110 of the second transition portion 212 via the first overlapping electrode 61, the power connection line 60, and the second overlapping electrode 62.In an exemplary embodiment, in the first transition region 211, the first power line 110 located on the SD 2 layer is relayed to the power connection line 60 located on the GATE 3 layer by the first overlapping electrode 61 located on the SD 1 layer. After the power connection line 60 located on the GATE3 layer passes through the isolation dam region 213 and enters the second transition region 212, the first power line 110 located on the SD2 layer is relayed by the second overlapping electrode 62 located on the SD1 layer, thereby forming the first power line 110 passing through the isolation dam region 213 through a switching fabric.After this patterning process, the fanout region 201 of the bond region may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15, the power connection line 60, the sixth insulating layer 16, the first source-drain metal layer, the first planarization layer 17, and the second source-drain metal layer stacked on the substrate 10. The first source-drain metal layer may include the first overlapping electrode 61 and the second overlapping electrode 62, the second source-drain metal layer may include the first power line 110. The first power line 110 passes through the insulation dam portion 213 via the first overlapping electrode 61, the power connection line 60, and the second overlapping electrode 62.(10) forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: depositing a second planarization film on the substrate on which the foregoing pattern is formed; patterning the second planarization film by a patterning process to form the pattern of a second planarization layer 18 covering the fifth conductive layer, as illustrated in FIG. 17.In an exemplary embodiment, the pattern of the second planarization layer 18 may include at least: a fourth through hole K 4, a second separation groove 82, and a second bank base 402, and a third bank base 403.In an exemplary embodiment, the fourth through hole K 4 may be located in the display region 100, the second planarization layer 18 in the fourth through hole K 4 is removed, the surface of the first anode connection electrode 52 is exposed, the fourth through hole K 4 is configured such that a subsequently formed anode is connected to the first anode connection electrode 52 through the through hole.In an exemplary embodiment, the second separation groove 82 may be located in the fanout region 201, the orthographic projection of the second separation groove 82 on the substrate may include the orthographic projection of the isolation dam region 213 on the substrate, the orthographic projection of the second separation groove 82 on the substrate may include the orthographic projection of the first separation groove 81 on the substrate, the first planarization film in the second separation groove 82 is removed, the surface of the sixth insulating layer 16 of the isolation dam region 213 is exposed.In an exemplary embodiment, the second planarization layer 18 on the side of the second separation groove 82 near the display region 100 covers the edge of the first power line 100 located in the first transition region 211 on the side opposite to the display region 100, the second planarization layer 18 on the side opposite to the display region 100 of the second separation groove 82 covers the edge of the first power line 100 located in the second transition region 212 on the side close to the display region 100, thereby allowing the second planarization layer 18 to envelop the edges of the first power line 100, enhancing peel strength of the film layers, and improving product quality.In an exemplary embodiment, the second bank base 402 and the third bank base 403 may be located in the area where the second separation groove 82 is located. The second bank base 402 may be located in the first bank region C 1, the second bank base 402 may be disposed on a substrate-opposite side of the sixth insulating layer 16. The second dam base 402 is formed as a dam base of the first insulating dam. The third bank base 403 may be located in the second bank region C 2, the third bank base 403 may be disposed on a substrate-opposite side of the first bank base 401. The third bank base 403 is formed as another bank base of the second insulating bank.After this patterning process, the bond region fanout region 201 may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15, the power connection line 60, the sixth insulating layer 16, the first source-drain metal layer, the first planarization layer 17, the second source-drain metal layer, the second planarization layer 18, which are stacked on the substrate 10. The first source-drain metal layer may include a first overlapping electrode 61 and a second overlapping electrode 62. The second source-drain metal layer may include the first power line 110. The first power line 110 passes through the insulating dam region 213 via the first overlapping electrode 61, the power connection line 60, and the second overlapping electrode 62, The second planarization layer 18 is provided with the second separation groove 82, the second separation groove 82 exposes the surface of the sixth insulating layer 16, and the second separation groove 82 forms the first dam base 401, the second dam base 402, and the third dam base 403.Until now, on the substrate 10, the patterns of the driving pattern layer 102 of the display region 100 and the bonding pattern layer 50 of the fanout region 201 are completed. The driver pattern layer 102 of the display region 100 may include at least a first transistor 20, a second transistor 30, and a storage capacitor 40 forming a pixel driver circuit. The bonding structure layer 50 of the fanout region 201 may include at least one of an insulating layer 11 to a fifth insulating layer 15 provided on the substrate 10, a power connection line 60 provided on a substrate-opposite side of the fifth insulating layer 15, a sixth insulating layer 16 provided on a substrate-opposite side of the power connection line 60, a first overlapping electrode 61 and a second overlapping electrode 62 provided on a substrate-opposite side of the sixth insulating layer 16 and each connected to the power connection line 60, a first planarization layer 17 provided on a substrate-opposite side of the first overlapping electrode 61 and the second overlapping electrode 62, a first power line 110 provided on a substrate-opposite side of the first planarization layer 17 and each connected to the first overlapping electrode 61 and the second overlapping electrode 62, a second planarization layer 18 provided on a substrate-opposite side of the first power line 110 and provided with a second separation groove 82, the second separation groove 82 exposing the surface of the sixth insulating layer 16.In exemplary embodiments, the substrate may be a rigid substrate or a flexible substrate, and the flexible substrate may take a multilayer structure. For example, the substrate may include: a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked. The first and second flexible material layers may be made of a material such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated soft polymer film or the like. The first and second inorganic material layers may be made of silicon nitride (SiNx), or silicon oxide (SiOx), or the like, in order to increase water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers (barrier layers). Amorphous silicon (a-si) can be used as the material of the semiconductor layer.In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may use one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as buffer layer (buffer layers), the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be referred to as gate insulating layers (GI layers), the sixth insulating layer may be referred to as interlayer insulating layer (ILD layer). The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may use one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Ti / Al / Ti, or the like. The first planarization layer and the second planarization layer may be made of organic materials such as resin or polyimide, or the like.In an exemplary embodiment, the third conductive layer may be made of the metal molybdenum (Mo) or an alloy material of molybdenum, and has characteristics of not reacting with a wet etching solution.(11) forming a conductive anode layer and a pixel defining layer pattern. In an exemplary embodiment, forming an anode conductive layer and a pixel defining layer pattern may include: first depositing a transparent conductive film on a substrate on which the foregoing pattern is formed, patterning the transparent conductive film by a patterning process to form a pattern of the anode 91 on the second planarization layer 18, and then depositing a pixel defining film, patterning the pixel defining film by a patterning process to form a pixel defining layer 92, a fourth bank base 404, a fifth bank base 405, a first insulating groove 310, a second insulating groove 320, and a third insulating groove 330, as illustrated in FIG. 18.In an exemplary embodiment, the anode 91 may be located in the display region 100, the anode 91 is connected to the anode connection electrode 52 via the fourth through hole K 4. Since the anode connection electrode 52 is connected to the first drain electrode of the first transistor 20 via the through hole, connection of the anode 91 to the pixel driving circuit is enabled.In an exemplary embodiment, the pixel definition layer 92 may be located in the display region 100 and the first transition region 211 of the fanout region 201. The pixel defining layer 92 of the display region 100 is provided with a pixel opening, the pixel defining layer 92 in the pixel opening is removed, the surface of the anode 91 is exposed. The pixel defining layer 92 of the first transition region 211 extends to the second separation groove 82, and covers the side wall of the second separation groove 82 on the side near the display region.In an exemplary embodiment, the fourth bank base 404 and the fifth bank base 405 may be located in the area where the second separation groove 82 is located. The fourth bank base 404 may be located in the first bank region C 1, the fourth bank base 404 may be disposed on a substrate-opposite side of the second bank base 402, the fourth bank base 404 is configured as another bank base of the first isolation bank, the second bank base 402 and the fourth bank base 404 constitute the first isolation bank 410. The fifth bank base 405 may be located in the second bank region C 2, the fifth bank base 405 may be disposed on a substrate-opposite side of the third bank base 403, the fifth bank base 405 is configured as another bank base of the second isolation bank, the first bank base 401, the third bank base 403, and the fifth bank base 405 constitute the second isolation bank 420. In an exemplary embodiment, the distance between the first insulating dam 410 and the display region 100 is smaller than the distance between the second insulating dam 420 and the display region 100, the distance between the surface of the first insulating dam 410 on the side facing away from the substrate and the substrate is smaller than the distance between the surface of the second insulating dam 420 on the side facing away from the substrate and the substrate.In an exemplary embodiment, the first isolation groove 310 may be located in the first groove region B 1, i.e., between the first isolation dam 410 and the first transition region 211. The first planarization layer, the second planarization layer, and the pixel defining layer in the first isolation groove 310 are removed, exposing the sixth isolation layer 16.In an exemplary embodiment, the second isolation groove 320 may be located in the second groove region B 2, i.e., between the first isolation dam 410 and the second isolation dam 420. The first planarization layer and the second planarization layer and the pixel defining layer in the second isolation groove 320 are removed, thereby exposing the sixth isolation layer 16.In an exemplary embodiment, the third isolation groove 330 may be located in the third groove region B 3, i.e., between the second isolation dam 420 and the second transition region 212. The first planarization layer and the second planarization layer and the pixel defining layer in the third isolation groove 330 are removed, thereby exposing the sixth isolation layer 16.In an exemplary embodiment, the transparent conductive layer may be a single-layer structure or a multilayer composite structure. The single-layer structure may use indium tin oxide ITO or indium zinc oxide IZO, and the multilayer composite structure may use ITO / Al / ITO or the like. The pixel defining layer may be made of polyimide, acrylic, polyethylene terephthalate or the like.(12) forming an organic light emitting layer and a cathode pattern. In an exemplary embodiment, forming an organic light emitting layer and a cathode pattern may include: first, forming an organic light emitting layer 93 by vapor deposition or inkjet printing on the substrate on which the foregoing pattern is formed, then forming a cathode 94 by vapor deposition using an open mask, as shown in FIG. 19.In an exemplary embodiment, the organic light emitting layer 93 may be formed in a pixel opening provided to the pixel defining layer 92, thereby enabling connection between the organic light emitting layer 93 and the anode 91.In an exemplary embodiment, the organic light emitting layer 93 may include a light emitting layer (EML), and one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layers, hole transport layers, electron blocking layers, hole blocking layers, electron transport layers, and electron injection layers of all light emitting units may be a respective common layer bonded together, and the light emitting layers of adjacent subpixels may have a small overlap or be isolated from each other.In an exemplary embodiment, the cathode 94 may be located in the display region 100 and the first transition region 211 of the fanout region 201, wherein the cathode 94 in the display region 100 overlaps the organic light emitting layer 93, the distance between the edge of the cathode 94 in the first transition region 211 on the region facing away from the display region 100 and the edge of the display region is smaller than the distance between the first separating groove 310 and the edge of the display region, i.e. the width of the cathode 94 in the first transition region 211 is smaller than the width of the first transition region 211.In an exemplary embodiment, the cathode may be made of one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy of one or more of the foregoing metals.(14) forming a packaging structure layer pattern. In an exemplary embodiment, forming a package structure layer pattern may include: first forming a first encapsulation layer 95 by depositing on the substrate on which the foregoing pattern is formed, and then forming a second encapsulation layer 96 by inkjet printing, then forming a third encapsulation layer 97 by depositing, thereby forming a stack structure of the first encapsulation layer 95, the second encapsulation layer 96, and the third encapsulation layer 97 as shown in FIG. 7.In an exemplary embodiment, the first encapsulation layer 95 may be made of inorganic material, covers the cathode 94 in the display region 100, covers the first insulating groove 310, the second insulating groove 320, and the third insulating groove 330 in the fanout region 201, respectively, and covers the first support dam 410 and the second support dam 420, respectively. The second encapsulation layer 96 may be made of organic material and is arranged in the display region 100 and in the region of the fanout region 201 in which the first insulating dam 410 is situated close to the display region. The third encapsulation layer 97 can consist of inorganic material and covers the first encapsulation layer 95 and the second encapsulation layer 96.In an exemplary embodiment, since the plurality of insulating grooves expose the sixth inorganic material insulating layer, the first inorganic material encapsulating layer directly covers the sixth insulating layer, whereby not only the peel strength of the film layers can be increased, but also the water vapor propagating path is effectively blocked, and thus it is ensured that external water vapor cannot pass to the display area, the packaging effect is highly improved.In a display substrate, as the first power line located on the SD2 layer in the bonding region, an integral structure directly crossing the fanout region is employed. Because the first planarization layer, the second planarization layer, and the pixel definition layer (the organic material layer) are removed in a plurality of separation grooves, the plurality of separation grooves expose the surface of the first power line. Although a distance is provided between the cathode edge and the separation groove in the design sense, in the case that the process margin for the edge of the cathode opening is insufficient or the process parameters fluctuate relatively greatly, the cathode extends to the region in which the separation groove is located. As a result, the cathode engages the first power line and results in a cathode short circuit.In a display substrate provided in an exemplary embodiment of the present disclosure, the first power line of the bonding region is provided as a relay structure, and the first power line located on the SD2 layer passes through a plurality of separation grooves via the power connection line located on the GATE3 layer, therefore, the plurality of separation grooves do not expose the first power line and the power connection line but expose an inorganic insulating layer covering the power connection line; even when the cathode extends to the region where the separation groove is located, the cathode is not connected to the first power line and the power connection line, whereby not only a cathode short circuit and poor display of the display substrate are effectively avoided, but also the process margin can be increased, and production quality and production efficiency can be improved.The switching fabric provided in an exemplary embodiment of the present disclosure is that the first power line located on the SD2 layer is connected to each of the first overlapping electrode and the second overlapping electrode located on the SD1 layer, the first overlapping electrode and the second overlapping electrode located on the SD1 layer are connected to each of the power connection line located on the GATE3 layer, thus enabling the first power line of the first junction region and the first power line of the second junction region to be connected to each other via the first overlapping electrode, the power connection line, and the second overlapping electrode, the switching fabric is simple, the connection is reliable, and the process quality is increased.In an exemplary embodiment of the present disclosure, the edges of the first overlapping electrode and the second overlapping electrode are covered by the first power line 110, and the edges of the first power line are covered by the second planarization layer, the edge of the second planarization layer is covered by the pixel defining layer, thereby increasing peel strength of the film layers and improving product quality.In an exemplary embodiment of the present disclosure, a plurality of separation grooves are provided in the insulation dam region, the organic material layers in the separation grooves are removed, thereby blocking the penetration path in which the water vapor is guided to the display region along the organic material layer, and reducing the risk of occurrence of a packaging failure, preventing poor display of the display substrate, and enhancing display quality.FIG. 20 is a schematic diagram showing a GDS failure on a display substrate. In a display substrate, since the organic material layers are removed in a plurality of separation grooves, the edges of the first power line 110 are exposed in the plurality of separation grooves. In a first power line 110 using a Ti / Al / Ti multilayer composite structure, in the subsequent process of etching the anode, the edge of the first power line 110 is corroded by the anode etching solution. Since the etching solution etches Al faster than Ti, a lateral recess is formed in the edge of the corroded first power line 110. The Ti layer over the Al layer protrudes from the Al layer by a certain distance, and a "troche" structure is formed as shown in FIG. 20. In the subsequent process of forming the first encapsulation layer 95 and the third encapsulation layer 97 by the chemical vapor deposition (CVD), the "cluster" structure blocks the vapor deposition particles, so that the lateral depression cannot be filled with an encapsulation material, thus forming a cavity 501. Subsequently, when cracks 502 occur in the first encapsulation layer 95 and the third encapsulation layer 97, external water vapor may enter the cavity 501 through the cracks 502, thereby flowing the water vapor around the edge of the first power line 110 and spreading to the display area, thus resulting in a GDS failure in the display area due to the water and oxygen erosion.In a display substrate provided in an exemplary embodiment of the present disclosure, the first power line of the bonding region is provided as a relay structure, the first power line located on the SD2 layer passes through the insulation dam region via the power connection line located on the GATE3 layer, the power connection line is covered with an inorganic insulating layer, therefore, in the separation grooves, neither the edge of the first power line nor the edge of the power connection line is exposed, the edge of the first power line and the edge of the power connection line are not corroded by the anode etching solution, and no void will occur, whereby a relatively good morphology of the first packaging layer and the third packaging layer can be ensured, a GDS failure is effectively prevented, poor display of the display substrate is effectively prevented, and yield and product reliability are increased.In an exemplary embodiment, the GATE3 layer may be made of the metal molybdenum (Mo) or an alloy material of molybdenum. Therefore, the current connection line reacts with the anode etching solution, whereby the GDS failure can be further avoided and the process margin is increased.In the present disclosure, a GATE3 layer inherent in the LTPO display substrate is employed as a switching structure, therefore, the manufacturing process can be realized using existing sophisticated manufacturing apparatuses, the existing process is little improved, it can be well compatible with the existing manufacturing apparatus, the process is easy to implement, easy to perform, has high production efficiency, low production cost, and high yield. Since the structure and process routes in which power lines pass through the insulating dam are relatively familiar, there is a high possibility of a cathode short-circuit failure and a GDS failure in the display substrate. Therefore, the solution of the present disclosure has wide application prospects and can be applied to display substrates having an arbitrary number of separation grooves.The structure of the display substrate and its manufacturing process in the present disclosure are merely exemplified. In example embodiments, corresponding structures may be changed as needed, and the patterning processes may be added or reduced. For example, as the second power line of the binding area, a switching structure may be employed, the second power line located on the SD2 layer crosses the isolation dam area via the power connection line located on the GATE3 layer; also, for example, there may be one, or two, or more isolation grooves of the isolation dam area. The display substrate may further be, for example, a dual source-drain conductive layer (2SD) structure or a single source-drain conductive layer (1SD) structure. In a single source-drain conductive layer structure, the first power line and the second power line may be disposed on the SD 1 layer, the power connection line may be disposed on the GATE 3 layer, the first power line of the first junction portion and the first power line of the second junction portion are connected to each other by the first power connection line, the second power line of the first junction portion and the second power line of the second junction portion are connected to each other by the second power connection line. In another example, in the first transition region, the first power line is provided on the SD2 layer, in the second transition region, the first power line is provided on the SD1 layer, the second transition region is not provided with an SD2 layer, etc., which is not to be limited in the present disclosure.FIG. 21 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the first transition region. The main structure of the display substrate in this embodiment is substantially the same as the structure of the display substrate shown in FIG. 7. The difference is that the first power line 110 located on the SD2 layer is connected to the first overlapping electrode 61 only via the third connection hole 73 in the first transition region 211, the first power line 110 does not extend in a direction away from the display region, the first power line 110 and the first overlapping electrode 61 are turned on on one side, the edge of the first overlapping electrode 61 on the side away from the display region is covered by the first planarization layer 17.In example embodiments, the connection structure of the first overlapping electrode in the first transition region with the power connection line, the connection structure of the first power line in the second transition region with the second overlapping electrode, the connection structure of the second overlapping electrode in the second transition region with the power connection line may be substantially the same as the above embodiments, allowing the first power line of the SD2 layer to be relayed through the SD1 layer to the GATE3 layer, to cross over multiple isolation grooves, and thereafter returning the GATE3 layer through the SD1 layer to the SD2 layer again.The display substrate according to the exemplary embodiment of the present disclosure can not only effectively avoid short circuit situations and poor display of the display substrate, but also the connection structure of the first power line in the first transition region with the first overlapping electrode is simplified, the process quality can be improved.FIG. 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the first transition region. The main configuration of the display substrate in this exemplary embodiment is substantially the same as the structure of the display substrate shown in FIG. 7. The difference is that the first current line 110 located on the SD2 layer extends in a direction away from the display area 100 in the first transition area 211, overlaps the exposed first overlapping electrode 61 in the first separation groove, and the first current line 110 wraps around the edge of the first overlapping electrode 61 on the side away from the display area.In the exemplary embodiment, since the first planarization layer 17 is not provided with a third connection opening for connecting the first power line 110 and the first overlapping electrode 61, the first planarization layer 17 is removed as much as possible in the first transition region 211 (i.e., the area of the first separation groove is enlarged), whereby water vapor storage of organic material can be reduced and GDS failure is further prevented.In an exemplary embodiment, the surface of the first overlapping electrode 61 exposed due to the removal of the first planarization layer 17 is protected by the first current line 110 overlapping the surface of the first overlapping electrode 61.In an exemplary embodiment, as the connection structure of the first power line in the second transition region with the second overlapping electrode, a structure in which the first planarization layer is removed as much as possible may be used.The display substrate according to the exemplary embodiments of the present disclosure can effectively avoid not only the short circuit situations and poor display of the display substrate, but also the water vapor storage of organic material can be reduced and further GDS failure can be prevented by removing the first planarization layer as much as possible.FIG. 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the insulating dam portion. The main configuration of the display substrate in this exemplary embodiment is substantially the same as that of the display substrate shown in FIG. 7. The difference is that the insulation dam portion is provided with three insulation dams and four separation grooves.In an exemplary embodiment, the insulating dam region may include at least: a first groove region B 1, a first dam region C 1, a second groove region B 2, a second dam region C 2, and a third groove region B 3 which are sequentially arranged in a direction away from the display region. The first groove portion B 1 is configured to provide a first separation groove 310. The second groove portion B 2 is configured to provide a second separation groove 320. The third groove portion B 3 is configured to provide a third separation groove 330. The first bank region C 1 is configured to provide a first sub-bank 410- 1, a second sub-bank 410- 2, and a fourth separation groove 340. The second dam region C 2 is configured to provide a second isolation dam 420.In an exemplary embodiment, the second sub-bank 410- 2 may be substantially the same on a side of the first sub-bank 410- 1 opposite to the display region 100, the structures of the first sub-bank 410- 1 and the second sub-bank 410- 2 may be substantially the same including a second bank base and a fourth bank base that are arranged in a stacked manner. The second bank base may be disposed on a same layer as the second planarization layer, the fourth bank base may be disposed on a same layer as the pixel definition layer, the first sub-bank 410- 1 and the second bank 410- 2 form a first double ring-shaped insulating bank. The second isolation dam 420 may be disposed on a side of the second sub-dam 410- 2 facing away from the display region 100, the structure of the second isolation dam 420 may be substantially the same as the above embodiment.In an exemplary embodiment, the first separation groove 310 may be disposed on the side of the first sub-dam 410- 1 near the display region, the second separation groove 320 may be disposed between the second sub-dam 410- 2 and the second isolation dam 420, the third separation groove 330 may be disposed on the side of the second isolation dam 420 away from the display region 100, the fourth separation groove 340 may be disposed between the first sub-dam 410- 1 and the second sub-dam 410- 2. The organic layers in the first separation groove 310, the second separation groove 320, the third separation groove 330, and the fourth separation groove 340 are removed, thereby exposing the surface of the sixth insulating layer 16. Therefore, the first inorganic material encapsulation layer 95 is directly laid on the sixth insulating layer 16 in the separation grooves.The display substrate according to the exemplary embodiment of the present disclosure can effectively avoid not only short circuit situations and poor display of the display substrate, and by disposing three insulating dams and four separating grooves, the water vapor diffusion path is blocked to the maximum extent and the packaging effect is improved to the maximum extent, the display quality is improved.FIG. 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the fanout region. The main structure of the display substrate in this exemplary embodiment is substantially the same as the structure of the display substrate shown in FIG. 7. The difference is that the gate metal layer in the bond structure layer 50 may include a second gate metal layer, the current connection line 60 is disposed in the second gate metal layer.In an exemplary embodiment, the bond structure layer 50 may further include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, a sixth insulating layer 16, a first planarization layer 17, and a second planarization layer 18. The first insulating layer 11 is disposed on the substrate 10, the second insulating layer 12 is disposed on the substrate-opposite side of the first insulating layer 11, the third insulating layer 13 is disposed on the substrate-opposite side of the second insulating layer 12, the power connection line 60 is disposed on the substrate-opposite side of the third insulating layer 13, the fourth insulating layer 14 is disposed on the substrate-opposite side of the power connection line 60, the fifth insulating layer 15 is disposed on the substrate-opposite side of the fourth insulating layer 14, the sixth insulating layer 16 is disposed on the substrate-opposite side of the fifth insulating layer 15, the first overlapping electrode 61 and the second overlapping electrode 62 are disposed on the substrate-opposite side of the sixth insulating layer 16, the first planarization layer 17 is disposed on the substrate-opposite side of the first overlapping electrode 61 and the second overlapping electrode 62, the first power line 110 is disposed on the substrate-opposite side of the first planarization layer 17, the second planarization layer 18 is disposed on the substrate-opposite side of the first power line 110.In an exemplary embodiment, the fourth insulating layer 14, the fifth insulating layer 15, and the sixth insulating layer 16 covering the power connection line 60 may be provided with a first connection opening and a second connection opening, the first overlapping electrode 61 may be connected to the side of the power connection line 60 near the display region through the first connection opening, the second overlapping electrode 62 may be connected to the side of the power connection line opposite to the display region through the second connection opening.In exemplary embodiments, the connection structure of the first power line 110 with the first overlapping electrode 61 and the second overlapping electrode 62, the structure of the first planarization layer 17, and the structure of the second planarization layer 18 may be the same as those in the above embodiments, which is not repeated here.In an exemplary embodiment, the current connection line 60 of the fanout region 201 and the second electrode plate of the display region may be disposed on one and the same layer and may be synchronously formed by one and the same patterning process.In this exemplary embodiment, short circuit situations and poor display of the display substrate are effectively avoided by disposing the power connection line on the second gate metal layer and covering the power connection line with the fifth insulating layer and the sixth insulating layer.In one possible implementation, the gate metal layer in the bond structure layer 50 may include a first gate metal layer, the current connection line 60 may be disposed in the first gate metal layer. The third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15, and the sixth insulating layer 16 covering the power connection line 60 may be provided with a first connection opening and a second connection opening, the first overlapping electrode 61 may be connected to the side of the power connection line 60 near the display region through the first connection opening, the second overlapping electrode 62 may be connected to the side of the power connection line opposite to the display region through the second connection opening.FIG. 25 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the fanout region. The main structure of the display substrate in this exemplary embodiment is substantially the same as the structure of the display substrate shown in FIG. 7. The difference is that the gate metal layer in the bond pattern layer 50 includes a second gate metal layer and a third gate metal layer that are sequentially arranged in a direction away from the substrate, the current connection lines 60 are respectively arranged in the second gate metal layer and the third gate metal layer, and the current connection line 60 in the third gate metal layer is connected to the current connection line 60 in the second gate metal layer via a through hole, thereby forming a double-layered current connection line structure.In exemplary embodiments, the connection structure of the first power line 110 with the first overlapping electrode 61 and the second overlapping electrode 62, the structure of the first planarization layer 17, and the structure of the second planarization layer 18 may be the same as in the above embodiments, which is not repeated here.In this exemplary embodiment, short circuit situations and poor display of the display substrate are effectively avoided, and connection reliability can be increased by disposing the current connection lines in the second gate metal layer and the third gate metal layer.In one possible implementation, the gate metal layer in the bond structure layer 50 may include a first gate metal layer, a second gate metal layer, and a third gate metal layer that are sequentially arranged in a direction away from the substrate; the power connection lines 60 are respectively provided in the first gate metal layer, the second gate metal layer, and the third gate metal layer, and the power connection line 60 in the third gate metal layer is connected via a through hole to the power connection line 60 in the second gate metal layer, the power connection line 60 in the second gate metal layer is connected via a through hole to the power connection line 60 in the first gate metal layer, thereby forming a three-layered power connection line structure.In other possible implementations, the current connection lines 60 may be provided in the first gate metal layer and the second gate metal layer, respectively, or provided in the first gate metal layer and the third gate metal layer, respectively, which is not to be limited in the present disclosure.An exemplary embodiment of the present disclosure further provides a manufacturing method of a display substrate. In an exemplary embodiment, the display substrate includes a display area and a bonding area located on a side of the display area, the bonding area including at least: a fanout area and a bending area, the fanout area being located between the display area and the bending area, the fanout area including at least: a first transition area, an insulating dam area, and a second transition area arranged in a direction away from the display area; the manufacturing method including:forming a bond structure layer on a substrate of the fanout region, the bond structure layer comprising at least: a gate metal layer and a source drain metal layer arranged on a side of the gate metal layer facing away from the substrate, wherein the gate metal layer comprises one or more of the following: a first gate metal layer, a second gate metal layer and a third gate metal layer, wherein the source drain metal layer comprises one or more of the following: a first source drain metal layer and a second source drain metal layer, wherein the gate metal layer is provided with a current connection line, the source drain metal layer is provided with a first current line, the current connection line is provided in the first transition region, the insulating dam region and the second transition region, the first power line in the first transition region and the second transition region is provided, the first power line in the first transition region and the first power line in the second transition region are connected to each other via the power connection line.The present disclosure further provides a display device including a display substrate as described above. The display device may be a mobile phone, a tablet computer, a television, a display, a notebook, a digital picture frame, a navigation device, or any other product or component having a display function.Although the embodiments disclosed in the present disclosure are as described above, the disclosure content relates only to embodiments that serve to facilitate understanding of the present disclosure and does not aim to limit the present invention. Any person skilled in the art is allowed to make any modifications and changes in the form and details of the implementations without departing from the spirit and scope of the disclosure. The scope of the present invention, however, still needs to be based on the scope defined by the appended claims.

Claims

A display substrate comprising a display area and a bond area located on a side of the display area, the bond area comprising at least: a fanout area and a bend area, the fanout area being located between the display area and the bend area, the fanout area comprising at least: a first transition area, an insulating dam area, and a second transition area arranged in a direction away from the display area; wherein the fanout area comprises a bond structure layer provided on a substrate comprising at least: a gate metal layer and a source-drain metal layer arranged on a side of the gate metal layer facing away from the substrate, the gate metal layer comprising one or more of: a first gate metal layer, a second gate metal layer and a third gate metal layer, the source-drain metal layer comprising one or more of the following: a first source-drain metal layer and a second source-drain metal layer, the gate metal layer being provided with a power connection line, the source-drain metal layer being provided with a first power line, the power connection line being provided in the first transition region, the insulating dam region and the second transition region, the first power line being provided in the first transition region and the second transition region, the first power line in the first transition region and the first power line in the second transition region being connected to one another via the power connection line.The display substrate of claim 1, wherein the bond structure layer further comprises a first planarization layer disposed on a substrate-opposite side of the first source-drain metal layer, the first power line is disposed on a substrate-opposite side of the first planarization layer, the first source-drain metal layer is provided with a first overlapping electrode and a second overlapping electrode, the first overlapping electrode is disposed in the first transition region, the second overlapping electrode is disposed in the second transition region, the first power line of the first transition region is connected to the first overlapping electrode, the first overlapping electrode is connected to a side of the power connection line that is near the display region, the first power line of the second transition region is connected to the second overlapping electrode, the second overlapping electrode is connected to a display-opposite side of the power connection line.The display substrate according to claim 2, wherein the bonding structure layer further comprises an inorganic insulating layer that is disposed on a side of the power connection line opposite to the substrate and that is provided with a first connection opening and a second connection opening, wherein the first overlapping electrode is connected to the side of the power connection line close to the display area through the first connection opening, the second overlapping electrode is connected to the side of the power connection line opposite to the display area through the second connection opening.The display substrate according to claim 2, wherein the first planarization layer is provided with a third connection opening, the first current line of the first junction region is connected to the first overlapping electrode through the third connection opening.The display substrate according to claim 2, wherein the first planarization layer is provided with a first separation groove, the orthographic projection of the first separation groove on the substrate includes the orthographic projection of the insulating dam region on the substrate, the first planarization layer on the side of the first separation groove near the display region covers the edge of the first overlapping electrode on the side near the display region, the first planarization layer on the side away from the display region of the first separation groove covers the edge of the second overlapping electrode on the side away from the display region, the first separation groove exposes a surface of the first overlapping electrode on the side away from the display region, a surface of the second overlapping electrode on the side near the display region, and a surface of the inorganic insulating layer located between the first overlapping electrode and the second overlapping electrode.The display substrate of claim 5, wherein the first current line of the first transition region overlaps the first overlapping electrode exposed in the first separation groove.The display substrate of claim 6, wherein the first current line of the first transition region covers the edge of the first overlapping electrode on the side opposite to the display region.The display substrate of claim 5, wherein the first current line of the second transition region overlaps the second overlapping electrode exposed in the first separation groove.The display substrate according to claim 8, wherein the first current line of the second junction region covers the edge of the second overlapping electrode on the side close to the display region.The display substrate according to claim 2, wherein the bonding structure layer further comprises a second planarization layer disposed on a substrate-opposite side of the second source-drain metal layer, the second planarization layer is provided with a second separation groove, the orthographic projection of the second separation groove on the substrate includes the orthographic projection of the isolation dam region on the substrate, the second planarization layer on the display region-opposite side of the second separation groove covers the edge of the first power line of the first transition region on the display region-opposite side, the second planarization layer on the display region-opposite side of the second separation groove covers the edge of the first power line of the second transition region on the side close to the display region.The display substrate according to claim 1, wherein the insulating dam region is provided with at least one insulating dam and at least one separating groove, the insulating dam is disposed on the opposite side of the inorganic insulating layer from the display region, the separating groove is disposed on the side of the insulating dam close to the display region or on the opposite side of the insulating dam from the display region, the separating groove exposes the surface of the inorganic insulating layer.The display substrate according to any one of claims 1 to 11, wherein the display substrate comprises, in a plane perpendicular to the display substrate, at least: a first gate metal layer, a second gate metal layer and a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer provided sequentially on the substrate, the current connection line is provided in one or more of the first gate metal layer, the second gate metal layer and the third gate metal layer, the first current line is provided in the second source-drain metal layer.The display substrate according to any one of claims 1 to 11, wherein the display substrate comprises, in a plane perpendicular to the display substrate, at least: a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source-drain metal layer provided sequentially on the substrate, the power connection line is provided in one or more of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the first power line is provided in the first source-drain metal layer.A display device comprising a display substrate according to any one of claims 1 to 13.A manufacturing method for a display substrate, comprising: a display area and a bonding area located on a side of the display area, the bonding area comprising at least: a fanout area and a bending area, the fanout area being located between the display area and the bending area, the fanout area comprising at least: a first transition area, an insulating dam area, and a second transition area arranged in a direction away from the display area; the manufacturing method comprising: forming a bonding structure layer on a substrate of the fanout area, comprising at least: a gate metal layer and a source-drain metal layer arranged on a side of the gate metal layer facing away from the substrate, the gate metal layer comprising one or more of: a first gate metal layer, a second gate metal layer and a third gate metal layer, the source-drain metal layer comprising one or more of the following: a first source-drain metal layer and a second source-drain metal layer, the gate metal layer being provided with a power connection line, the source-drain metal layer being provided with a first power line, the power connection line being provided in the first transition region, the insulating dam region and the second transition region, the first power line being provided in the first transition region and the second transition region, the first power line in the first transition region and the first power line in the second transition region being connected to one another via the power connection line.

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