PIXEL CIRCUIT AND DRIVING METHOD THEREFOR, DISPLAY BASEBOARD AND DISPLAY DEVICE

Abstract

A pixel circuit, a driving method therefor, a display base plate, and a display device are provided, wherein the pixel circuit comprises a node control subcircuit, a memory subcircuit, a driver subcircuit, and a light emission control subcircuit; wherein the memory subcircuit is electrically connected to a second node (N2) and a first power supply line (VDD), respectively, and is configured to charge the second node (N2) when a first scanning signal line (Gate1) has a valid level signal.

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates, among other things, to the field of display technology, and more particularly to a pixel circuit and a driving method therefor, a display base plate, and a display device. BACKGROUND OF THE INVENTION

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting and display devices that feature self-illumination, wide viewing angles, high contrast, low power consumption, ultra-high response speed, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays (FLDs) using OLEDs or QLEDs as light-emitting devices and controlling signals through thin-film transistors (TFTs) have become mainstream products in the current display field. SUMMARY OF THE INVENTION

[0003] The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a pixel circuit configured to drive a light-emitting device to emit light, and comprising a node control subcircuit, a storage subcircuit, a driver subcircuit, and a light emission control subcircuit; wherein the node control subcircuit is electrically connected to a first node, a second node, a third node, a fourth node, a first scanning signal line, a second scanning signal line, a first initial signal line, a second initial signal line, a reset signal line, a data signal line, and a first power supply line, and is configured to provide the signal of the first initial signal line or the third node to the first node, the signal of the second initial signal line to the fourth node, and the signal of the data signal line to the second node under the control of the reset signal line, the first scanning signal line, and the second scanning signal line; wherein the storage subcircuit is electrically connected to the second node and the first power supply line, respectively, and is configured to charge the second node when the first scan signal line has a valid level signal; wherein the driver subcircuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to provide a drive current to the third node under the control of the first node and the second node; wherein the light emission control subcircuit is electrically connected to a light emission signal line, the first power supply line, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the light emission signal line; wherein a first electrode of the light-emitting device is connected to the fourth node and a second electrode of the light-emitting device is connected to a second power supply line.

[0005] In an exemplary embodiment, a period in which the signal of the reset signal line has a valid level signal comprises a first period and a second period, wherein the first period is before the second period; a period in which the signal of the first sensing signal line has a valid level signal comprises a third period and a fourth period, wherein the third period is before the fourth period; a period in which the signal of the second sensing signal line has a valid level signal comprises a fifth period and a sixth period, wherein the fifth period is before the sixth period; wherein the second period at least partially overlaps with the third period and the fourth period at least partially overlaps with the fifth period; wherein the signal of the light emission signal line has an invalid level signal when the signals of the reset signal line, the first scanning signal line, and the second scanning signal line have valid level signals, and the signals of the reset signal line, the first scanning signal line, and the second scanning signal line have invalid level signals when the signal of the light emission signal line has a valid level signal.

[0006] In an exemplary embodiment, the node control subcircuit comprises a reset subcircuit, a write subcircuit, a compensation subcircuit, and an energy storage subcircuit; wherein the reset subcircuit is electrically connected to the reset signal line, the first initial signal line, the second initial signal line, the first node, and the fourth node, respectively, and is configured to provide the signal of the first initial signal line to the first node and the signal of the second initial signal line to the fourth node under the control of the reset signal line; wherein the write subcircuit is electrically connected to each of the first scanning signal line, the data signal line, and the second node and is configured to provide the signal of the data signal line to the second node under the control of the first scanning signal line; wherein the compensation subcircuit is electrically connected to each of the second scanning signal line, the first node, and the third node and is configured to provide the signal of the third node to the first node under the control of the second scanning signal line; wherein the energy storage subcircuit is electrically connected to the first node and the first power supply line, respectively, and is configured to store the voltage difference of the signal between the first node and the first power supply line.

[0007] In an exemplary embodiment, the reset subcircuit is further connected to the first scan signal line and configured to provide the signal of the first initial signal line to the first node and the signal of the second initial signal line to the fourth node under the control of the reset signal line and the first scan signal line.

[0008] In an exemplary embodiment, the reset subcircuit comprises a first transistor and a seventh transistor, the write subcircuit comprises a fourth transistor, the compensation subcircuit comprises a second transistor, and the energy storage subcircuit comprises a first capacitor. wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node.

[0009] In an exemplary embodiment, the reset subcircuit comprises a first transistor, a seventh transistor, and an eighth transistor; the write subcircuit comprises a fourth transistor; the compensation subcircuit comprises a second transistor; and the energy storage subcircuit comprises a first capacitor. wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line and a second electrode of the first transistor is electrically connected to a first electrode of the eighth transistor; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein a control electrode of the eighth transistor is electrically connected to the first scanning signal line and a second electrode of the eighth transistor is electrically connected to the first node; wherein one end of the first capacitor is electrically connected to the first node and the other end of the first capacitor is electrically connected to the first power supply line.

[0010] In an exemplary embodiment, the memory subcircuit comprises a second capacitor; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node.

[0011] In an exemplary embodiment, the node control subcircuit comprises a first transistor, a second transistor, a fourth transistor, a seventh transistor, and a first capacitor; the memory subcircuit comprises a second capacitor; the driver subcircuit comprises a third transistor; and the light emission control subcircuit comprises a fifth transistor and a sixth transistor. wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line and a second electrode of the first transistor is electrically connected to the first node; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the fifth transistor is electrically connected to the light emission signal line, a first electrode of the fifth transistor is electrically connected to the first power supply line, and a second electrode of the fifth transistor is electrically connected to the second node; wherein a control electrode of the sixth transistor is electrically connected to the light emission signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the fourth node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node.

[0012] In an exemplary embodiment, the node control subcircuit comprises a first transistor, a second transistor, a fourth transistor, a seventh transistor, an eighth transistor, and a first capacitor; the memory subcircuit comprises a second capacitor; the driver subcircuit comprises a third transistor; and the light emission control subcircuit comprises a fifth transistor and a sixth transistor; wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to a first electrode of the eighth transistor; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the fifth transistor is electrically connected to the light emission signal line, a first electrode of the fifth transistor is electrically connected to the first power supply line, and a second electrode of the fifth transistor is electrically connected to the second node; wherein a control electrode of the sixth transistor is electrically connected to the light emission signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the fourth node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein a control electrode of the eighth transistor is electrically connected to the first scanning signal line and a second electrode of the eighth transistor is electrically connected to the first node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node.

[0013] In a second aspect, the present disclosure provides a display base plate, the display base plate comprising a substrate and a drive circuit layer and a light-emitting structure layer sequentially arranged on the substrate, the drive circuit layer comprising the above-described pixel circuit, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of reset signal lines, a plurality of first power supply lines, and a plurality of data signal lines, the light-emitting structure layer comprising a light-emitting device.

[0014] In an exemplary embodiment, the drive circuit layer comprises: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially stacked on the substrate, wherein the pixel circuit comprises: a plurality of transistors, a first capacitor, and a second capacitor, wherein the first capacitor and the second capacitor each comprise a first electrode plate and a second electrode plate; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors and the first electrode plate of the second capacitor; wherein the first conductive layer comprises at least: a reset signal line, a light emission signal line, control electrodes for the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: a second initial signal line, the second electrode plate of the first capacitor, and the second electrode plate of the second capacitor; wherein the third conductive layer comprises at least: a first scanning signal line and a second scanning signal line; wherein the fourth conductive layer comprises at least: a first initial signal line, a first power supply line, and a data signal line.

[0015] In an exemplary embodiment, the pixel circuit comprises first to seventh transistors, wherein the active layer of each of the transistors may comprise a first region, a second region, and a channel region located between the first region and the second region; wherein the length of the first region of the active layer of the third transistor along a first direction is greater than the length of the second region of the active layer of the third transistor along the first direction, wherein the first region of the active layer of the third transistor is in turn used as the first electrode plate of the second capacitor.

[0016] In an exemplary embodiment, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor, and the second electrode plate of the second capacitor of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row; wherein the length of the second electrode plate of the first capacitor along a second direction is smaller than the length of the second electrode plate of the second capacitor along the second direction, wherein the first direction and the second direction intersect.

[0017] In an exemplary embodiment, the second electrode plate of the second capacitor comprises a capacitor body portion extending along the second direction, and a first connection block and a second connection block extending along the first direction; wherein the first connection block and the second connection block are each connected to the capacitor body portion, wherein the first connection block and the second connection block are arranged parallel to each other and are located on a side of the capacitor body portion facing away from the second electrode plate of the first capacitor; wherein an orthographic projection of the capacitor body portion onto the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the first connection block onto the substrate partially overlaps with an orthographic projection of the active layers of the second transistors located between the control electrodes of the second transistors onto the substrate, and wherein an orthographic projection of the second connection block onto the substrate partially overlaps with an orthographic projection of the active layer of the third transistor onto the substrate; wherein, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the capacitor body portion, and wherein the second connection block of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row.

[0018] In an exemplary embodiment, the length of the first power supply line along the first direction is greater than the length of the data signal line along the first direction and greater than the length of the first initial signal line along the first direction, wherein the length of the first initial signal line along the first direction is greater than the length of the data signal line along the first direction.

[0019] In an exemplary embodiment, the drive circuit layer comprises a cap layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer, wherein the pixel circuit comprises a plurality of transistors, a first capacitor, and a second capacitor, wherein the first capacitor comprises a first electrode plate and a second electrode plate, and the second capacitor comprises a first electrode plate, a second electrode plate, and a third electrode plate; wherein the cover layer comprises at least: the first electrode plate of the second capacitor, the cover layer being configured to transmit a high voltage power supply signal; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors, the second electrode plate of the second capacitor, a first initial signal line, and a second initial signal line; wherein the first conductive layer comprises at least: a light emission signal line, control electrodes of the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: the second electrode plate of the first capacitor and the third electrode plate of the second capacitor; wherein the third conductive layer comprises at least: two reset signal lines, a first scanning signal line, and a second scanning signal line; wherein the fourth conductive layer may comprise: a first power supply line and a data signal line.

[0020] In an exemplary embodiment, the plurality of transistors comprises first to eighth transistors, wherein the cap layer further comprises a first cap structure, a second cap structure, a first cap connection structure, a second cap connection structure, a third cap connection structure, and a fourth cap connection structure, wherein the first electrode plate of the second capacitor is again used as the second cap structure; wherein the first cover connection structure and the second cover structure are each located on two opposite sides of the first cover structure and are connected to the first cover structure, wherein the second cover connection structure is located on a side of the second cover structure facing away from the first cover structure and is connected to the second cover structure, wherein the third cover connection structure and the fourth cover connection structure are each located on the other two opposite sides of the first cover structure, wherein the third cover connection structure is connected to the second cover structure and the fourth cover connection structure is connected to the first cover structure; wherein an orthographic projection of the first capping structure onto the substrate at least partially overlaps with an orthographic projection of the channel region of the active layer of the third transistor onto the substrate, wherein an orthographic projection of the second capping structure onto the substrate at least partially overlaps with an orthographic projection of the second electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the third capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the first transistor onto the substrate, and wherein an orthographic projection of the fourth capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the seventh transistor onto the substrate.

[0021] In an exemplary embodiment, the second cover structure of the Nth column of subpixels in a row is located on a side of the first cover structure of the Nth column of subpixels in the same row that is close to the first cover structure of the N+1th column of subpixels, wherein the first cover connection structure of the Nth column of subpixels in a row is located on a side of the first cover structure of the Nth column of subpixels in the same row that is close to the first cover structure of the N-1th column of subpixels and is connected to the fourth cover connection structure of the N-1th column of subpixels.The second cover connection structure of the Nth column of subpixels in a row is connected to the first cover connection structure of the N+1th column of subpixels in the same row; wherein the third cover connection structure of the Mth row of subpixels in a column is located on a side of the first cover structure 11 of the Mth row of subpixels in the same column that is close to the first cover structure of the M-1th row of subpixels and is connected to the fourth cover connection structure of the M-1th row of subpixels, wherein the fourth cover connection structure of the Mth row of subpixels in a column is located on a side of the first cover structure 11 of the Mth row of subpixels in the same column that is close to the first cover structure of the M+1th row of subpixels and is connected to the fifth cover connection structure of the M+1th row of subpixels.

[0022] In an exemplary embodiment, for the same subpixel, the second electrode plate of the first capacitor and the third electrode plate of the second capacitor are connected to each other; wherein, for subpixels in the same row, the third electrode plate of the second capacitor of the Nth column of subpixels is located on a side of the second electrode plate of the first capacitor of the Nth column of subpixels close to the second electrode plate of the first capacitor of the N+1th column of subpixels and is connected to the second electrode plate of the first capacitor of the N+1th column of subpixels; wherein the length of the second electrode plate of the first capacitor along the second direction is smaller than the length of the third electrode plate of the second capacitor along the second direction.

[0023] In a third aspect, the present disclosure provides a display device comprising the display base plate described above.

[0024] In an exemplary embodiment, the display device further comprises a gate driver circuit, wherein the gate driver circuit comprises a number K+2 of cascaded shift registers, where K is the total number of rows of pixel circuits; wherein the first-stage shift register is connected to a reset signal line connected to the first row of pixel circuits; the second-stage shift register is connected to a first scan signal line connected to the first row of pixel circuits and to a reset signal line Reset connected to the second row of pixel circuits, respectively;the shift register of the i-th stage is respectively connected to a second scanning signal line connected to the i-2-th row of pixel circuits, to a first scanning signal line connected to the i-1-th row of pixel circuits, and to a reset signal line Reset connected to the i-th row of pixel circuits; the shift register of the K+1-th stage is respectively connected to a second scanning signal line connected to the K-1-th row of pixel circuits and to a first scanning signal line connected to the K-th row of pixel circuits; and the shift register of the K+2-th stage is respectively connected to a second scanning signal line connected to the K-th row of pixel circuits, where i=3, 4, ..., K;

[0025] In a fourth aspect, the present disclosure further provides a method of driving a pixel circuit configured to drive the pixel circuit described above, the method comprising: Providing the signal from the first initial signal line or the third node to the first node, the signal from the second initial signal line to the fourth node, and the signal from the data signal line to the second node by the node control subcircuit under the control of the reset signal line, the first scan signal line, and the second scan signal line; loading the second node by the memory subcircuit when the first scan signal line has a valid level signal; Providing the drive current to the third node by the drive subcircuit under the control of the first node and the second node; Providing the signal from the first power supply line to the second node and the signal from the third node to the fourth node through the light emission control subcircuit under the control of the light emission signal line.

[0026] Further aspects become clear after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are provided for further understanding of the technical solutions of the present disclosure, and are used as part of the description to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, but they do not limit the technical solutions of the present disclosure.

[0028] It shows Fig. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure; Fig. 2 a schematic structural representation of a node control subcircuit; Fig. 3 is a schematic structural diagram of another node control subcircuit; Fig. 4 an equivalent circuit diagram of a pixel circuit; Fig. 5 an equivalent circuit diagram of another pixel circuit; Fig. 6 a runtime diagram of the Fig. 4 and Fig. 5 provided pixel circuits; Fig. 7 is a schematic structural diagram of a display base plate provided by an embodiment of the present disclosure; Fig. 8 is a second schematic structural diagram of a display base plate provided by an embodiment of the present disclosure; Fig. 9 a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the semiconductor layer; Fig. 10 is a schematic representation of the pattern of the first conductive layer of the Fig. 7 provided display base plate; Fig. 11 a schematic representation of the Fig. 7 provided display base plate after formation of the patterns of the first conductive layer; Fig. 12 is a schematic representation of the pattern of the second conductive layer of the Fig. 7 provided display base plate; Fig. 13 a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the second conductive layer; Fig. 14 a schematic representation of the Fig. 7 provided display base plate after formation of the third insulating layer; Fig. 15 a schematic representation of the pattern of the third conductive layer of the Fig. 7 provided display base plate; Fig. 16 a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the third conductive layer; Fig. 17 a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the fourth insulating layer; Fig. 18 is a schematic representation of the pattern of the fourth conductive layer of the Fig. 7 provided display base plate; Fig. 19 a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the fourth conductive layer; Fig. 20 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the cover layer; Fig. 21 is a schematic representation of the pattern of the semiconductor layer of Fig. 8 provided display base plate; Fig. 22 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the semiconductor layer; Fig. 23 is a schematic representation of the pattern of the first conductive layer of Fig. 8 provided display base plate; Fig. 24 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the first conductive layer; Fig. 25 is a schematic representation of the pattern of the second conductive layer of the Fig. 8 provided display base plate; Fig. 26 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the second conductive layer; Fig. 27 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the fourth insulating layer; Fig. 28 is a schematic representation of the pattern of the third conductive layer of the Fig. 8 provided display base plate; Fig. 29 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the third conductive layer; Fig. 30 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the fifth insulating layer; Fig. 31 is a schematic representation of the pattern of the fourth conductive layer of the Fig. 8 provided display base plate; Fig. 32 a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the fourth conductive layer; Fig. 33 a schematic connection diagram of a gate driver circuit. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be explained in detail below in conjunction with the drawings. It should be noted that embodiments can be implemented in many different forms. It will be readily understood by those skilled in the art that the nature and content can be varied into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of some well-known functions and well-known components are omitted from the present disclosure. The drawings of the embodiments of the present disclosure refer only to the structures included in the embodiments of the present disclosure. For other structures, reference is made to the general configurations.

[0030] The scales of the drawings in the present disclosure may be used as references in actual processes, but are not limited thereto. For example, a width-to-length ratio of a channel, a thickness of each film layer, and a distance between each film layer, as well as a width of each signal line and a distance between each signal line, can be adjusted according to actual requirements. The number of pixels in the display base plate and the number of subpixels in each pixel are not limited to those shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and an embodiment of the present disclosure is not limited to the shapes, values, or the like shown in the drawings.

[0031] In the description, ordinal numbers such as "first," "second," and "third," etc., are provided to avoid confusion between components. They are not intended to define quantities.

[0032] In the description, for convenience, words indicating orientations or positional relationships, such as "center," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inside," "outside," etc., are used to describe the positional relationship between components with reference to the drawings. They are not intended to indicate or imply that the device or element mentioned must have a particular orientation and be constructed and operated in a particular orientation, but merely for convenience in explaining the description and simplifying the explanation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationship between components will change accordingly depending on the direction of the individual components described.Therefore, it is not limited to the words and expressions described in the description and can be replaced as appropriate depending on the situation.

[0033] In this description, terms such as "install," "connect," and "couple" are intended to be interpreted broadly unless otherwise expressly stated and limited in the text. For example, the connection may be a fixed connection, a detachable connection, or a one-piece connection; the connection may be a mechanical connection or an electrical connection; the connection may be a direct connection or an indirect connection via an intermediate part; or the connection may be an internal communication between two elements. Those skilled in the art will understand the specific meanings of the above terms in the present disclosure depending on the specific situation.

[0034] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. Between the drain electrode (drain electrode connection portion, drain region, or drain electrode) and the source electrode (source electrode connection portion, source region, or source electrode), the transistor has a channel region, and current can flow through the drain electrode, the channel region, and the source electrode. It should be noted that in this specification, the channel region refers to a region through which current predominantly flows.

[0035] In the description, the first electrode may be the drain electrode and the second electrode may be the source electrode, or alternatively, the first electrode may be the source electrode and the second electrode may be the drain electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when transistors with opposite electrode dearity are used or when the current direction changes during circuit operation. Therefore, in this description, "source electrode" and "drain electrode" are interchangeable.

[0036] The description should include a circumstance in the case of "electrical connection" where components are connected using elements with a specific electrical effect. "Elements with a specific electrical effect" are not particularly limited, as long as they can send and receive electrical signals between the connected components. Examples of "elements with a specific electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, electrical resistors, inductors, capacitors, other elements with various functions, etc.

[0037] In this description, "parallel" refers to a state in which the angle formed by two straight lines is above -10° and below 10°, and thus also to a state in which the angle is above -5° and below 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is above 80° and below 100°, and thus also to a state in which the angle is above 85° and below 95°.

[0038] In this description, "membrane" and "layer" are interchangeable. For example, in some cases, "electrically conductive layer" can be replaced with "electrically conductive membrane." Likewise, in some cases, "insulating membrane" can be replaced with "insulating layer."

[0039] In this specification, the term "arranged in a same layer" refers to structures formed by patterning two (or more than two) structures through the same patterning process, where their materials may be the same or different. For example, the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.

[0040] The triangles, rectangles, trapezoids, pentagons, or hexagons in this description are not strictly triangles, rectangles, trapezoids, pentagons, or hexagons, and may approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc. Minor deformations may be present due to tolerances, including rounded corners, arcs, and deformations, etc.

[0041] The word “approximately” in this disclosure refers to a value that does not strictly restrict the limit and allows for process and measurement errors.

[0042] As OLED technology matures, related products are widely used in products provided by major mobile phone manufacturers, and their application areas are constantly expanding. To meet the needs of specialized users, high refresh rates are required for display products. High refresh rates result in insufficient loading time in the pixel circuit, resulting in poor display effects.

[0043] Fig. 1 shows a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. As in Fig. 1, the pixel circuit provided by the embodiment of the present disclosure is configured to drive a light-emitting device to emit light, and includes a node control subcircuit, a storage subcircuit, a driver subcircuit, and a light emission control subcircuit.

[0044] As in Fig. 1, the node control subcircuit is electrically connected to a first node N1, a second node N2, a third node N3, a fourth node N4, a first scanning signal line Gate1, a second scanning signal line Gate2, a first initial signal line INIT1, a second initial signal line INIT2, a reset signal line Reset, a data signal line Data, and a first power supply line VDD, respectively, and is configured to supply the signal from the first initial signal line INIT1 or from the third node N3 to the first node N1, the signal from the second initial signal line INIT2 to the fourth node N4, and the signal from the data signal line Data to the second node N2 under the control of the reset signal line Reset, the first scanning signal line Gate1, and the second scanning signal line Gate2.The memory subcircuit is electrically connected to the second node N2 and to the first power supply line VDD, respectively, and is configured to charge the second node N2 when the first scan signal line Gate1 has a valid level signal. The driver subcircuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a drive current to the third node N3 under the control of the first node N1 and the second node N2.The light emission control subcircuit is electrically connected to the light emission signal line EM, the first power supply line VDD, the second node N2, the third node N3 and the fourth node N4, respectively, and is configured to supply the signal from the first power supply line VDD to the second node N2 and the signal from the third node N3 to the fourth node N4 under the control of the light emission signal line EM, wherein a first electrode of the light-emitting device is connected to the fourth node N4 and a second electrode of the light-emitting device is connected to the second power supply line VSS.

[0045] In an exemplary embodiment, a high voltage power supply signal is continuously provided by the first power supply line VDD and a low voltage power supply signal is continuously provided by the second power supply line VSS.

[0046] In an exemplary embodiment, the initial signals of the first initial signal line INIT1 and the second initial signal line INIT2 may be the same or different. If the initial signals of the first initial signal line INIT1 and the second initial signal line INIT2 are the same, the first initial signal line INIT1 and the second initial signal line INIT2 may represent the same signal line or different signal lines, and no limitations are imposed by the present disclosure.

[0047] In an exemplary embodiment, the light-emitting component is electrically connected to the fourth node N4 and the second power supply line VSS.

[0048] In an exemplary embodiment, the light-emitting device may be an organic electroluminescent diode (OLED) comprising a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) arranged one above the other. For example, the anode of the organic light-emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light-emitting diode is electrically connected to the second power supply line VSS.

[0049] In an exemplary embodiment, the organic light-emitting layer may comprise a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) arranged one on top of the other.In an exemplary embodiment, the hole injection layers of all subpixels may be interconnected into a common layer, the electron injection layers of all subpixels may be interconnected into a common layer, the hole transport layer of all subpixels may be interconnected into a common layer, the electron transport layer of all subpixels may be interconnected into a common layer, and the hole blocking layer of all subpixels may be interconnected into a common layer, wherein the light emitting layers of adjacent subpixels may slightly overlap with each other or be insulated from each other, wherein the electron blocking layers of adjacent subpixels may slightly overlap with each other or be insulated from each other.

[0050] The embodiments of the present disclosure provide a pixel circuit. In the present disclosure, by providing the memory subcircuit such that the second node N2 is charged when the first scanning signal line Gate1 has a valid level signal, it can be discharged after the first scanning signal line Gate1 has a valid level signal, which extends the charging time of the first node N1 while ensuring the high refresh rate of the display product, thereby improving the display effect of the display product.

[0051] In an exemplary embodiment, a period in which the signal of the reset signal line Reset has a valid level signal comprises a first period and a second period, wherein the first period is before the second period; a period in which the signal of the first scanning signal line Gate1 has a valid level signal comprises a third period and a fourth period, wherein the third period is before the fourth period; a period in which the signal of the second scanning signal line Gate2 has a valid level signal comprises a fifth period and a sixth period, wherein the fifth period is before the sixth period; wherein the second period at least partially overlaps with the third period and the fourth period at least partially overlaps with the fifth period.For example, the second period and the third period may be the same period, and the fourth period and the fifth period may be the same period.

[0052] In an exemplary embodiment, the signal of the light emission signal line EM has an invalid level signal when the signals of the reset signal line Reset, the first scanning signal line Gate1 and the second scanning signal line Gate2 have valid level signals, and the signals of the reset signal line Reset, the first scanning signal line Gate1 and the second scanning signal line Gate2 have invalid level signals when the signal of the light emission signal line EM has a valid level signal.

[0053] Fig. 2 shows a schematic structural representation of a node control subcircuit. As in Fig. 2, in an exemplary embodiment, the node control subcircuit may include a reset subcircuit, a write subcircuit, a compensation subcircuit, and an energy storage subcircuit.

[0054] As in Fig. 2, the reset subcircuit is electrically connected to a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, a first node N1, and a fourth node N4, respectively, and is configured to provide the signal from the first initial signal line INIT1 to the first node N1 and the signal from the second initial signal line INIT2 to the fourth node N4 under the control of the reset signal line Reset. The write subcircuit is electrically connected to a first scan signal line Gate1, a data signal line Data, and a second node N2, respectively, and is configured to provide the signal from the data signal line Data to the second node N2 under the control of the first scan signal line Gate1.The compensation subcircuit is electrically connected to a second scanning signal line Gate2, a first power supply line VDD, the first node N1, and a third node N3, and is configured to provide the signal from the third node N3 to the first node N1 under the control of the second scanning signal line Gate2. The energy storage subcircuit is electrically connected to the first node N1 and the first power supply line VDD, and is configured to store the voltage difference of the signal between the first node N1 and the first power supply line VDD.

[0055] Fig. 3 shows a schematic structural diagram of another node control subcircuit. As in Fig. 3, in an exemplary embodiment, the reset subcircuit is also connected to the first scan signal line Gate1 and configured to provide the signal from the first initial signal line INIT1 to the first node N1 and the signal from the second initial signal line INIT2 to the fourth node N4 under the control of the reset signal line Reset and the first scan signal line Gate1.

[0056] Fig. 4 is an equivalent circuit diagram of a pixel circuit. As in Fig. As shown in Figure 4, in an exemplary embodiment, the reset subcircuit may include a first transistor T1 and a seventh transistor T7. The write subcircuit may include a fourth transistor T4. The compensation subcircuit may include a second transistor T2. The energy storage subcircuit may include a first capacitor C1.

[0057] As in Fig. 4, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.The control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. One end of the first capacitor C1 is electrically connected to the first power supply line VDD, and the other end of the first capacitor C1 is electrically connected to the first node N1.

[0058] Fig. 5 shows an equivalent circuit of another pixel circuit. As in Fig. As shown in Figure 5, in an exemplary embodiment, the reset subcircuit may include a first transistor T1, a seventh transistor T7, and an eighth transistor T8. The write subcircuit may include a fourth transistor T4. The compensation subcircuit may include a second transistor T2. The energy storage subcircuit may include a first capacitor C1.

[0059] As in Fig. As shown in Figure 5, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the eighth transistor T8. The control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.The control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The control electrode of the eighth transistor T8 is electrically connected to the first scan signal line Gate1, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first power supply line VDD.

[0060] As in Fig. 4 and Fig. As shown in Figure 5, in an exemplary embodiment, the memory subcircuit may include a second capacitor C2. One end of the second capacitor C2 is electrically connected to the first power supply line VDD, and the other end of the second capacitor C2 is electrically connected to the second node N2.

[0061] As in Fig. 4, in an exemplary embodiment, the node control subcircuit may include a first transistor T1, a second transistor T2, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The memory subcircuit may include a second capacitor C2. The driver subcircuit may include a third transistor T3. The light emission control subcircuit may include a fifth transistor T5 and a sixth transistor T6. Here, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.The control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Date, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.The control electrode of the fifth transistor T5 is electrically connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light emission signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.One end of the first capacitor C1 is electrically connected to the first power supply line VDD, and the other end of the first capacitor C1 is electrically connected to the first node N1. One end of the second capacitor C2 is electrically connected to the first power supply line VDD, and the other end of the second capacitor C2 is electrically connected to the second node N2.

[0062] According to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. If the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). If the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0063] In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or N-type transistors. By using the same type of transistors in the pixel driver circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the product yield can be improved. In some possible embodiments, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0064] In an exemplary embodiment, low-temperature polysilicon thin-film transistors or oxide thin-film transistors, or low-temperature polysilicon thin-film transistors and oxide thin-film transistors, can be used for the first to seventh transistors T1 to T7. Low-temperature polysilicon (LTPS) is used for the active layer of the low-temperature polysilicon thin-film transistor, and oxide semiconductor (oxide) is used for the active layer of the oxide thin-film transistor. Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.By integrating the low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display base plate, the low-temperature polycrystalline oxide (LTPO) display base plate is formed, thereby utilizing the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0065] As in Fig. 5, in an exemplary embodiment, the node control subcircuit may include a first transistor T1, a second transistor T2, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The memory subcircuit may include a second capacitor C2. The driver subcircuit may include a third transistor T3. The light emission control subcircuit may include a fifth transistor T5 and a sixth transistor T6. Here, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the eighth transistor T8.The control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.The control electrode of transistor T5 is electrically connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light emission signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.The control electrode of the eighth transistor T8 is electrically connected to the first scanning signal line Gate1, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. One end of the first capacitor C1 is electrically connected to the first power supply line VDD, and the other end of the first capacitor C1 is electrically connected to the first node N1. One end of the second capacitor C2 is electrically connected to the first power supply line VDD, and the other end of the second capacitor C2 is electrically connected to the second node N2. For the present disclosure, the arrangement of the eighth transistor can prevent current leakage from the first node N1 and improve the reliability of the pixel circuit.

[0066] In an exemplary embodiment, the first to eighth transistors T1 to T8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driver circuit can simplify the process flow, reduce the process complexity of the display panel, and improve product yield. In some possible embodiments, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0067] In an exemplary embodiment, low-temperature polysilicon thin-film transistors or oxide thin-film transistors, or low-temperature polysilicon thin-film transistors and oxide thin-film transistors, can be used for the first to eighth transistors T1 to T8. Low-temperature polysilicon (LTPS) is used for the active layer of the low-temperature polysilicon thin-film transistor, and oxide semiconductor (oxide) is used for the active layer of the oxide thin-film transistor. Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.By integrating the low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display base plate, the low-temperature polycrystalline oxide (LTPO) display base plate is formed, thereby utilizing the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0068] In an exemplary embodiment, the third transistor T3 can be referred to as a driver transistor. The third transistor T3 determines a driver current flowing between the first power supply line VDD and the second power supply line VSS depending on the potential difference between the first electrode and the control electrode of the third transistor T3.

[0069] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as light-emitting transistors. When the signal of the light-emitting signal line EM is a valid level signal, the light-emitting device is driven to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS through the fifth transistor T5 and the sixth transistor.

[0070] An exemplary structure of the node control subcircuit, the memory subcircuit, the driver subcircuit and the light emission control subcircuit is shown in Fig. 4 and Fig. 5. Those skilled in the art can easily understand that the embodiment of the node control subcircuit, the memory subcircuit, the driver subcircuit, and the light emission control subcircuit is not limited thereto.

[0071] Fig. 6 shows a runtime diagram of the Fig. 4 and Fig. 5 provided pixel circuit, for example, where all transistors in the pixel circuit are considered as P-type transistors.

[0072] In an exemplary embodiment, a data voltage can be output through the data signal line Data in a second stage S2 and / or a third stage S3. In Fig. 6, for example, illustrates that a data voltage is output through the data signal line Data in the second stage S2 and the third stage S3.

[0073] In an exemplary embodiment, the display base plate on which the pixel circuit is located includes at least one gate drive circuit, the at least one gate drive circuit being electrically connected to at least one of the first scanning signal line, the second scanning signal line, the light emission signal line, and the reset signal line, the gate drive circuit including a plurality of shift registers. When a cascade relationship exists between a plurality of shift registers, the data voltage can be output through the data signal line Data only in the third stage S3 or the second stage S2. Crosstalk between signals can be avoided by outputting the data voltage through the data signal line Data in the third stage S3 or the second stage S2, whereby the display effect of the display base plate on which the pixel circuit is located can be improved.

[0074] The working process of the pixel circuit in Fig. 4 may include: A first stage S1 is called an initialization stage, in which the signal of the reset signal line Reset is a low level signal and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the light emission signal line EM are high level signals.When the reset signal line Reset is a low level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 via the turned on first transistor T1, whereby the first node N1 is initialized (reset) and its internal pre-stored voltage is cleared, thus completing the initialization, and the signal of the second initial signal line INIT2 is written to the fourth node N4 via the turned on seventh transistor T7, whereby the fourth node N4 is initialized (reset) and its internal pre-stored voltage is cleared, thus completing the initialization.When the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the light-emitting signal line EM are high, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0075] A second stage S2 is called a charging stage, in which the signals of the reset signal line Reset and the first scanning signal line Gate1 are low-level signals, the signals of the second scanning signal line Gate2 and the light emission signal line EM are high-level signals, and the data voltage is output through the data signal line Data.When the reset signal line Reset is a low level signal, the first transistor T1 and the seventh transistor T7 are permanently turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 via the turned on first transistor T1, whereby the first node N1 is permanently initialized (reset) and its internal pre-stored voltage is cleared and the initialization is completed, and the signal of the second initial signal line INIT2 is written to the fourth node N4 via the turned on seventh transistor T7, whereby the fourth node N4 is permanently initialized (reset) and its internal pre-stored voltage is cleared and the initialization is completed.When the signal of the first scanning signal line Gate1 is low, the fourth transistor T4 is turned on, and the signal of the data signal line Data is written to the second node N2 via the turned-on fourth transistor N4 to charge the second capacitor C2. When the signals of the second scanning signal line Gate2 and the light emission signal line EM are high, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0076] A third stage S3 is called the data write stage, where the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the signals of the reset signal line Reset and the light-emission signal line EM are high-level signals, and the data voltage is output through the data signal line Data. At this time, the first node N1 has a low-level signal, and the third transistor T3 is turned on.When the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the second transistor T2 and the fourth transistor T4 are turned on, and the first node N1 is charged by the data voltage output from the data signal line Data. The data voltage output from the data signal line Data is written to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. When the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.In this phase, the voltage of the first node N1 is less than Vd-|Vth|, which means that the third transistor T3 is permanently switched on and no light is emitted by the light-emitting device L.

[0077] A fourth stage S4 is called a discharge stage, in which the signal of the second scanning signal line Gate2 is a low level signal and the signals of the first scanning signal line Gate1, the reset signal line Reset, and the light emission signal line EM are high level signals. The third transistor T3 is permanently turned on. When the signal of the second scanning signal line Gate2 is a low level signal, the fourth transistor T4 is permanently turned on, and the first node N1 continues to be charged through the second capacitor C2, and the signal of the second node N2 is supplied to the first node N1 via the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.When the signals of the first scanning signal line Gate1, the reset signal line Reset, and the light-emitting signal line EM are high, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0078] A fifth stage S5 is called the light-emitting stage, where the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the reset signal line are high-level signals. When the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the reset signal line are high-level signals, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.When the signal of the light emission signal line EM is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and a drive voltage is provided to the first electrode of the light-emitting device L by the power supply voltage output from the first power supply line VDD via the turned-on fifth transistor T5, the second node N2, the third transistor T3, the third node N3, the turned-on sixth transistor T6 and the fourth node N4, thus driving the light-emitting device L to emit light.

[0079] During the pixel circuit drive operation, the drive current flowing through the third transistor T3 (driver transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the drive current of the third transistor T3 is: I=K*(Vgs−Vth)2=K*[(Vdd−Vd+|Vth|)−Vth]2=K*[Vdd−Vd]2 where I is the drive current flowing through the third transistor T3, i.e. the drive current by which the light-emitting device L is driven, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vdd is the output voltage of the first power supply line VDD.

[0080] For the present disclosure, by arranging the second capacitor C2, the first node N1 can be further charged in the fourth stage S4 after the third stage, ie, the data write stage, thereby prolonging the charging time of the first node N1 and effectively solving the problem of insufficient charge of the pixel circuit.

[0081] In an exemplary embodiment, as shown in Figures 5 and 6, the operation of the pixel circuit may be Fig. 5 Include the following: A first stage S1 is called the initialization stage, in which the signal of the reset signal line Reset is a low level signal, and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the light-emitting signal line EM are high level signals. When the reset signal line Reset is a low level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the signal of the second initial signal line INIT2 is written to the fourth node N4 via the turned-on seventh transistor T7, thereby initializing (resetting) the fourth node N4, clearing its internal prestored voltage, and completing initialization.When the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the light-emitting signal line EM are high, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0082] A second stage S2 is called a charging stage, in which the signals of the reset signal line Reset and the first scanning signal line Gate1 are low-level signals, the signals of the second scanning signal line Gate2 and the light emission signal line EM are high-level signals, and the data voltage is output through the data signal line Data.When the reset signal line Reset is a low level signal, the first transistor T1 and the seventh transistor T7 are permanently turned on, and when the signal of the first scan signal line Gate1 is a low level signal, the eighth transistor T8 is turned on and the signal of the first initial signal line INIT1 is written to the first node N1 via the turned on first transistor T1 and the turned on eighth transistor T8, thereby permanently initializing (resetting) the first node N1 and clearing its internal pre-stored voltage and completing the initialization, and the signal of the second initial signal line INIT2 is written to the fourth node N4 via the turned on seventh transistor T7, thereby permanently initializing (resetting) the fourth node N4 and clearing its internal pre-stored voltage and completing the initialization.When the signal of the first scanning signal line Gate1 is low, the fourth transistor T4 is turned on, and the signal of the data signal line Data is written to the second node N2 via the turned-on fourth transistor N4 to charge the second capacitor C2. When the signals of the second scanning signal line Gate2 and the light emission signal line EM are high, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0083] A third stage S3 is called the data write stage, where the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the signals of the reset signal line Reset and the light-emission signal line EM are high-level signals, and the data voltage is output through the data signal line Data. When the first node N1 has a low-level signal, the third transistor T3 is turned on.When the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, and the first node N1 is charged by the data voltage output from the data signal line Data. The data voltage output from the data signal line Data is written to the first node N1 via the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. When the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.In this phase, the voltage of the first node N1 is less than Vd-|Vth|, which means that the third transistor T3 is permanently switched on and no light is emitted by the light-emitting device L.

[0084] A fourth stage S4 is called a discharge stage, in which the signal of the second scanning signal line Gate2 is a low level signal and the signals of the first scanning signal line Gate1, the reset signal line Reset, and the light emission signal line EM are high level signals. The third transistor T3 is permanently turned on. When the signal of the second scanning signal line Gate2 is a low level signal, the fourth transistor T4 is permanently turned on, and the first node N1 continues to be charged through the second capacitor C2, and the signal of the second node N2 is supplied to the first node N1 via the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.When the signals of the first scanning signal line Gate1, the reset signal line Reset, and the light-emitting signal line EM are high, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. During this phase, no light is emitted by the light-emitting device L.

[0085] A fifth stage S5 is called the light-emitting stage, where the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the reset signal line are high-level signals. When the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, and the reset signal line are high-level signals, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.When the signal of the light emission signal line EM is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and a drive voltage is provided to the first electrode of the light-emitting device L by the power supply voltage output from the first power supply line VDD via the turned-on fifth transistor T5, the second node N2, the third transistor T3, the third node N3, the turned-on sixth transistor T6 and the fourth node N4, thus driving the light-emitting device L to emit light.

[0086] During the pixel circuit drive operation, the drive current flowing through the third transistor T3 (driver transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the drive current of the third transistor T3 is: I=K*(Vgs−Vth)2=K*[(Vdd−Vd+|Vth|)−Vth]2=K*[Vdd−Vd]2 where I is the drive current flowing through the third transistor T3, i.e. the drive current by which the light-emitting device L is driven, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vdd is the output voltage of the first power supply line VDD.

[0087] For the present disclosure, by disposing the second capacitor C2, the first node N1 can be further charged in the fourth stage S4 after the third stage, that is, the data writing stage, thereby prolonging the charging time of the first node N1 and effectively solving the problem of insufficient charge of the pixel circuit, whereby the display effect of display products can be improved.

[0088] An embodiment of the present disclosure also provides a display base plate. Fig. 7 shows a first schematic structural diagram of a display base plate provided by an embodiment of the present disclosure. Fig. Figure 8 shows a second schematic structural diagram of a display base plate provided by an embodiment of the present disclosure. As shown in Figures 7 and 8, the display base plate may include a substrate, a drive circuit layer, and a light-emitting structure layer provided sequentially on the substrate, wherein the drive circuit layer includes a pixel circuit, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of first scanning signal lines Gate1, a plurality of second scanning signal lines Gate2, a plurality of reset signal lines Reset, a plurality of first power supply lines VDD, and a plurality of data signal lines Data, and wherein the light-emitting structure layer includes a light-emitting device. Fig. 7 is the display base plate, which is Fig. 4 provided pixel circuit, taken as an example and illustrated. In Fig. 8 is the display base plate, which is Fig. 5 provided pixel circuit, taken as an example and illustrated.

[0089] The pixel circuit is a pixel circuit provided in any of the above embodiments. The implementation principles and effects of the pixel circuit are similar and will not be described repeatedly here.

[0090] In an exemplary embodiment, the display base plate may further include an encapsulation structure layer disposed on a side of the light-emitting structure layer facing away from the substrate. The display base plate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.

[0091] In an exemplary embodiment, the display base plate may comprise a plurality of subpixels in a plane parallel to the display base plate, wherein at least one subpixel may comprise a pixel circuit and a light-emitting device, wherein the pixel circuit is configured to output a corresponding current to the connected light-emitting device, whereby light with a corresponding brightness is emitted by the light-emitting device.

[0092] In an exemplary embodiment, multiple subpixels may include multiple pixel rows and multiple pixel columns. Multiple subpixels arranged consecutively in the horizontal direction may be referred to as pixel rows, and multiple subpixels arranged consecutively in the vertical direction may be referred to as pixel columns. Multiple pixel rows and multiple pixel columns form a pixel array in a matrix arrangement.

[0093] In an exemplary embodiment, a pixel unit is formed by the plurality of subpixels, wherein the pixel unit may comprise a first subpixel, a second subpixel, and a third subpixel, or may comprise a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel.

[0094] When the pixel unit comprises a first subpixel, a second subpixel, and a third subpixel, in an exemplary embodiment, the first subpixel may be a red subpixel (R) emitting red light, the second subpixel may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light, wherein the shape of the three subpixels may be a triangle, a rectangle, a rhombus, a pentagon, or a hexagon, etc., and is not limited in this disclosure. The first subpixel, the second subpixel, and the third subpixel may be arranged one behind the other in the pixel row direction and offset from one another in the pixel column direction to form a subpixel layout in the shape of a triangle.For example, a first subpixel in an odd-numbered row may be located between adjacent second and third subpixels in an even-numbered row, or a first subpixel in an even-numbered row may be located between adjacent second and third subpixels in an odd-numbered row. In another example, a second subpixel in the odd-numbered row may be located between adjacent first and third subpixels in the even-numbered row, or a second subpixel in the even-numbered row may be located between adjacent first and third subpixels in the odd-numbered row. In yet another example, a third subpixel in the odd-numbered row may be located between adjacent first and second subpixels in the even-numbered row, or a third subpixel in the even-numbered row may be located between adjacent first and second subpixels in the odd-numbered row.

[0095] In an exemplary embodiment, when the pixel unit comprises a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, the first subpixel may be a red subpixel (R) emitting red light, the second subpixel may be a blue subpixel (B) emitting blue light, and the third and fourth subpixels may be green subpixels (G) emitting green light. The shape of the three subpixels may be a triangle, a rectangle, a rhombus, a pentagon, or a hexagon, etc., and is not limited in this disclosure. In an exemplary embodiment, the four subpixels may be arranged horizontally, vertically, or in a square, which is not limited in this disclosure. The four subpixels may be arranged in a square to form a GGRB pixel array.In another exemplary embodiment, the four subpixels may be arranged in a diamond shape to form an RGGB pixel array.

[0096] In an exemplary embodiment, the packaging structure layer may comprise a first packaging layer, a second packaging layer, and a third packaging layer arranged stacked on top of one another. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, thereby ensuring that external water vapor cannot penetrate the light-emitting structure layer.

[0097] In an exemplary embodiment, the display base plate may be a low-temperature poly-silicon (LTPS) display base plate or a low-temperature polycrystalline oxide (LTPO) display base plate.

[0098] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, where the rigid substrate may be one or more of, but is not limited to, glass and conductive foil, and the flexible substrate may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, or textile fibers. In an exemplary embodiment, the light-emitting structural layer comprises an anode layer, a pixel definition layer, an organic structural layer, and a cathode layer stacked on top of each other on the substrate. The anode layer comprises an anode, the organic structural layer comprises an organic light-emitting layer, and the cathode layer comprises a cathode.

[0099] In an exemplary embodiment, the drive circuit layer comprises a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer stacked on top of each other on the substrate, wherein the pixel circuit comprises a plurality of transistors, a first capacitor, and a second capacitor, wherein the first capacitor and the second capacitor each comprise a first electrode plate and a second electrode plate; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors and the first electrode plate of the second capacitor; wherein the first conductive layer comprises at least: a reset signal line, a light emission signal line, control electrodes for the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: a second initial signal line, the second electrode plate of the first capacitor, and the second electrode plate of the second capacitor; wherein the third conductive layer comprises at least: a first scanning signal line and a second scanning signal line; wherein the fourth conductive layer comprises at least: a first initial signal line, a first power supply line, and a data signal line.

[0100] In an exemplary embodiment, the pixel circuit comprises first to seventh transistors, wherein the active layer of each of the transistors may comprise a first region, a second region, and a channel region located between the first region and the second region; wherein the length of the first region of the active layer of the third transistor along a first direction is greater than the length of the second region of the active layer of the third transistor along the first direction, wherein the first region of the active layer of the third transistor is in turn used as the first electrode plate of the second capacitor.

[0101] In an exemplary embodiment, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor, and the second electrode plate of the second capacitor of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row; wherein the length of the second electrode plate of the first capacitor along a second direction is smaller than the length of the second electrode plate of the second capacitor along the second direction, wherein the first direction and the second direction intersect.

[0102] In an exemplary embodiment, the second electrode plate of the second capacitor comprises a capacitor body portion extending along the second direction, and a first connection block and a second connection block extending along the first direction; wherein the first connection block and the second connection block are each connected to the capacitor body portion, wherein the first connection block and the second connection block are arranged parallel to each other and are located on a side of the capacitor body portion facing away from the second electrode plate of the first capacitor; wherein an orthographic projection of the capacitor body portion onto the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the first connection block onto the substrate partially overlaps with an orthographic projection of the active layers of the second transistors located between the control electrodes of the second transistors onto the substrate, and wherein an orthographic projection of the second connection block onto the substrate partially overlaps with an orthographic projection of the active layer of the third transistor onto the substrate; wherein, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the capacitor body portion, and wherein the second connection block of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row.

[0103] In an exemplary embodiment, the length of the first power supply line along the first direction is greater than the length of the data signal line along the first direction and greater than the length of the first initial signal line along the first direction, wherein the length of the first initial signal line along the first direction is greater than the length of the data signal line along the first direction.

[0104] In an exemplary embodiment, the drive circuit layer comprises a cap layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer, wherein the pixel circuit comprises a plurality of transistors, a first capacitor, and a second capacitor, wherein the first capacitor comprises a first electrode plate and a second electrode plate, and the second capacitor comprises a first electrode plate, a second electrode plate, and a third electrode plate; wherein the cover layer comprises at least: the first electrode plate of the second capacitor, the cover layer being configured to transmit a high voltage power supply signal; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors, the second electrode plate of the second capacitor, a first initial signal line, and a second initial signal line; wherein the first conductive layer comprises at least: a light emission signal line, control electrodes of the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: the second electrode plate of the first capacitor and the third electrode plate of the second capacitor; wherein the third conductive layer comprises at least: two reset signal lines, a first scanning signal line, and a second scanning signal line; wherein the fourth conductive layer may comprise: a first power supply line and a data signal line.

[0105] In an exemplary embodiment, the plurality of transistors comprises first to eighth transistors, wherein the cap layer further comprises a first cap structure, a second cap structure, a first cap connection structure, a second cap connection structure, a third cap connection structure, and a fourth cap connection structure, wherein the first electrode plate of the second capacitor is again used as the second cap structure; wherein the first cover connection structure and the second cover structure are each located on two opposite sides of the first cover structure and are connected to the first cover structure, wherein the second cover connection structure is located on a side of the second cover structure facing away from the first cover structure and is connected to the second cover structure, wherein the third cover connection structure and the fourth cover connection structure are each located on the other two opposite sides of the first cover structure, wherein the third cover connection structure is connected to the second cover structure and the fourth cover connection structure is connected to the first cover structure; wherein an orthographic projection of the first capping structure onto the substrate at least partially overlaps with an orthographic projection of the channel region of the active layer of the third transistor onto the substrate, wherein an orthographic projection of the second capping structure onto the substrate at least partially overlaps with an orthographic projection of the second electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the third capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the first transistor onto the substrate, and wherein an orthographic projection of the fourth capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the seventh transistor onto the substrate.

[0106] In an exemplary embodiment, the second cover structure of the Nth column of subpixels in a row is located on a side of the first cover structure of the Nth column of subpixels in the same row that is close to the first cover structure of the N+1th column of subpixels, the first cover connection structure of the Nth column of subpixels in a row is located on a side of the first cover structure of the Nth column of subpixels in the same row that is close to the first cover structure of the N-1th column of subpixels and is connected to the fourth cover connection structure of the N-1th column of subpixels, the second cover connection structure of the Nth column of subpixels in a row being connected to the first cover connection structure of the N+1th column of subpixels in the same row;wherein the third cover connection structure of the M-th row of subpixels in a column is located on a side of the first cover structure 11 of the M-th row of subpixels in the same column that is close to the first cover structure of the M-1-th row of subpixels and is connected to the fourth cover connection structure of the M-1-th row of subpixels, wherein the fourth cover connection structure of the M-th row of subpixels in a column is located on a side of the first cover structure of the M-th row of subpixels in the same column that is close to the first cover structure of the M+1-th row of subpixels and is connected to the fifth cover connection structure of the M+1-th row of subpixels;

[0107] In an exemplary embodiment, for the same subpixel, the second electrode plate of the first capacitor and the third electrode plate of the second capacitor are connected to each other; wherein, for subpixels in the same row, the third electrode plate of the second capacitor of the Nth column of subpixels is located on a side of the second electrode plate of the first capacitor of the Nth column of subpixels close to the second electrode plate of the first capacitor of the N+1th column of subpixels and is connected to the second electrode plate of the first capacitor of the N+1th column of subpixels; wherein the length of the second electrode plate of the first capacitor along the second direction is smaller than the length of the third electrode plate of the second capacitor along the second direction.

[0108] A manufacturing process of the display base plate is described below by way of example. The "patterning process" mentioned in the present disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist removal for metal materials, inorganic materials, or transparent conductive materials, and includes coating, mask exposure, and development for organic materials. Deposition may be performed by one or more of the following processes: sputtering, evaporation, and chemical vapor deposition; coating may be performed by one or more of the following processes: spray coating, spin coating, and inkjet printing; and etching may be performed by one or more of the following processes: dry etching and wet etching, which is not limited in the present disclosure."Film" refers to a layer of film formed from a specific material on a substrate through deposition, coating, or other processes. If the patterning process for the "film" is not required in the overall manufacturing process, the "film" may also be referred to as a "layer." If the patterning process for the "film" is required in the overall manufacturing process, the film before the patterning process is referred to as a "film" and after the patterning process is referred to as a "layer." The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are arranged on the same layer" means that A and B are formed simultaneously through the same patterning process, and a "thickness" of the film layer is the dimension of the film layer in a direction perpendicular to the display base plate.In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within a boundary of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that a boundary of the orthographic projection of B falls within a range of a boundary of the orthographic projection of A or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0109] The manufacturing process of Fig. The display base plate provided in Figure 7 is described below using a pixel circuit with one row and two columns as an example. The manufacturing process of the display base plate provided by an exemplary embodiment may include the following: (1) Forming the pattern of a semiconductor layer on a substrate. In an exemplary embodiment, forming the pattern of a semiconductor layer may include: sequentially depositing semiconductor films on the substrate, patterning the semiconductor film by a patterning process, and forming the pattern of the semiconductor layer, as in Fig. 9, where Fig. 9 shows a schematic representation of the display base plate shown in FIG:7 after formation of the pattern of the semiconductor layer.

[0110] In an exemplary embodiment, as in Fig. 9, the pattern of the semiconductor layer of each subpixel may include at least: an active layer T11 of the first transistor to an active layer T71 of the seventh transistor.

[0111] In an exemplary embodiment, as in Fig. 9, the active layer T11 of the first transistor to an active layer T61 of the sixth transistor are an integral structure connected to each other.

[0112] In an exemplary embodiment, as in Fig. 9, in the first direction X, the active layer T21 of the second transistor and the active layer T61 of the sixth transistor may be located on a same side of the active layer T31 of the third transistor in this subpixel, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on another same side of the active layer T31 of the third transistor in this subpixel, and the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in this subpixel.In the second direction Y, the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor and the active layer T71 of the seventh transistor may be located on a same side of the active layer T31 of the third transistor in this subpixel, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on another side of the active layer T31 of the third transistor in this subpixel.

[0113] In an exemplary embodiment, as in Fig. 9, the active layer T11 of the first transistor may have a shape of "n", the active layer T21 of the second transistor may have a shape of "L", the active layer T31 of the third transistor may have a shape of "Ω", and the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may have a shape of "I".

[0114] In an exemplary embodiment, as in Fig. As shown in Figure 9, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor may be used as the first region T21_1 of the active layer T21 of the second transistor; the first region T31_1 of the active layer T31 of the third transistor may be used simultaneously as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor; the second region T31_2 of the active layer T31 of the third transistor may be used simultaneously as the second region T21_2 of the active layer T21 of the second transistor and the first region T61_1 of the active layer T61 of the sixth transistor.the second region T61_2 of the active layer T61 of the sixth transistor may be used as the second region T71_2 of the active layer T71 of the seventh transistor, and the first region T11_1 of the active layer T11 of the first transistor, the first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51_1 of the active layer of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor may be arranged independently of each other.

[0115] In an exemplary embodiment, as in Fig. 9, the first region T31_1 of the active layer T31 of the third transistor (also the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) may have a shape of a stripe structure extending along the second direction Y, and the length of this first region along the first direction X is greater than the length of the first region T41_1 of the active layer T41 of the fourth transistor and the first region T51_1 of the active layer T51 of the fifth transistor along the first direction.

[0116] (2) Forming the pattern of a first conductive layer. In an exemplary embodiment, forming the pattern of a first conductive layer may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the previous pattern was formed; patterning the first conductive film by a patterning process and forming the first insulating layer covering the pattern of the semiconductor layer and the pattern of a first conductive layer located on the first insulating layer, as shown in FIGS. Fig. 10 and Fig. 11, where Fig. 10 shows a schematic representation of the pattern of the first conductive layer of the Fig. 7 provided display base plate and Fig. 11 in a schematic representation of the Fig. 7 after the pattern of the first conductive layer has been formed. In exemplary embodiments, the first conductive layer may be referred to as a first gate metal layer (GATE1).

[0117] In an exemplary embodiment, the pattern of the first conductive layer of each subpixel may include at least: a reset signal line Reset, a light emission signal line EM, a control electrode T12 of the first transistor to a control electrode T72 of the seventh transistor, and a first electrode plate C11 of the first capacitor.

[0118] In an exemplary embodiment, as in Fig. 10 and Fig. As shown in Figure 11, the shape of the first electrode plate C11 of the first capacitor may be rectangular, and the corners of the rectangular shape may be rounded, wherein an orthographic projection of the first electrode plate C11 of the first capacitor onto the substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode plate C11 of the first capacitor may simultaneously serve as the control electrode T32 of the third transistor T3.

[0119] In an exemplary embodiment, as in Fig. 10 and Fig. As shown in Figure 11, the shape of the reset signal line Reset may be a line shape extending along the first direction X, and the reset signal line Reset may be located on a side of the first electrode plate C11 of the first capacitor facing away from the light-emitting signal line EM. The region where the reset signal line Reset overlaps with the active layer of the first transistor T1 serves as the control electrode T12 of the first transistor, and the region where the reset signal line Reset overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor. Since the active layer T11 of the first transistor may be in the form of an "n", there are two regions where the reset signal line Reset overlaps with the active layer of the first transistor, that is, the first transistor has two control electrodes T12, and the first transistor has a double-gate structure.

[0120] In an exemplary embodiment, the shape of the light emission signal line EM may be a line shape extending along the first direction X, wherein the region in which the light emission signal line EM overlaps with the active layer of the fifth transistor T5 serves as the control electrode T52 of the fifth transistor T5, wherein the region in which the light emission signal line EM overlaps with the active layer of the sixth transistor T6 serves as the control electrode T62 of the sixth transistor T6.

[0121] In an exemplary embodiment, as in Fig. 10 and Fig. 11, the control electrode T22 of the second transistor T2 and the control electrode T42 of the fourth transistor T4 may be located on a side of the first electrode plate C11 of the first capacitor close to the reset signal line Reset, and the control electrode T42 of the fourth transistor of that pixel may be located on a side of the control electrode T22 of the second transistor T2 of that subpixel close to the control electrode T22 of the second transistor T2 in the adjacent column of subpixels.

[0122] In an exemplary embodiment, as in Fig. 10 and Fig. 11, the control electrode T22 of the second transistor may include a first electrode connection portion T22A and a second electrode connection portion T22B, and the first electrode connection portion T22A is located on a side of the second electrode connection portion T22B facing away from the control electrode T42 of the fourth transistor, wherein the first electrode connection portion T22A represents a line shape extending along the first direction X, wherein the second electrode connection portion T22B represents a line shape extending along the second direction Y. Orthographic projections of the first electrode connection portion T22A and the second electrode connection portion T22B onto the substrate partially overlap with an orthographic projection of the active layer T21 of the second transistor onto the substrate.Therefore, there are two overlapping regions where the control electrode T22 of the second transistor overlaps with the active layer T21 of the second transistor, i.e., there are two control electrodes T22 of the second transistor and the second transistor represents a double-gate structure.

[0123] In an exemplary embodiment, the shape of the control electrode T42 of the fourth transistor may be a line shape extending along the first direction X.

[0124] In an exemplary embodiment, the reset signal line Reset and the light emission signal line EM may be provided with equal widths or unequal widths, and may be straight lines or broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure.

[0125] In an exemplary embodiment, the first conductive layer may be used as a shield after the formation of the pattern of the first conductive layer to perform a conductive process for the semiconductor layer, wherein the channel regions of the first to seventh transistors T1 to T7 are formed by the region of the semiconductor layer covered by the first conductive layer, and the region of the semiconductor layer not covered by the first conductive layer becomes conductive, that is, the first and second regions of the active layer of the first to seventh transistors all become conductive, and the first conductive region of the active layer of the third transistor (which is also used as the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) may simultaneously serve as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor,the second electrode T54 of the fifth transistor and the first electrode plate C21 of the second capacitor are used, and the second conductive region T31_2 of the active layer T31 of the third transistor (which is also used as the second region T21_1 of the active layer T21 of the second transistor and the first region T61_1 of the active layer T61 of the sixth transistor) is also used simultaneously as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor.

[0126] (3) Forming the pattern of a second conductive layer. In an exemplary embodiment, forming the pattern of a second conductive layer may include: depositing a film of a second insulating layer and a second conductive film on the substrate on which the previous pattern was formed; patterning the second conductive film using a patterning process; and forming the pattern of the second conductive layer on the second insulating layer. As in Fig. 12 and Fig. 13 shown, shows Fig. 12 is a schematic representation of the pattern of the second conductive layer of the Fig. 7 provided display base plate; shows Fig. 13 a schematic representation of the Fig. 7 after the formation of the pattern of the second conductive layer. In exemplary embodiments, the second conductive layer may be referred to as a second gate metal layer (GATE2).

[0127] In an exemplary embodiment, as in Fig. 12 and Fig. 13, the pattern of the second conductive layer of each subpixel may include at least: a second initial signal line INIT2, a second electrode plate C12 of the first capacitor, and a second electrode plate C12 of the second capacitor.

[0128] In an exemplary embodiment, as in Fig. 12 and Fig. 13, the second electrode plate C12 of the first capacitor and the second electrode plate C22 of the second capacitor are an integral structure connected to each other.

[0129] In an exemplary embodiment, as in Fig. 12 and Fig. As shown in Figure 13, the shape of the second electrode plate C12 of the first capacitor may be rectangular, and the corners of the rectangular shape may be rounded, wherein an orthographic projection of the second electrode plate C12 of the first capacitor onto the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the first capacitor onto the substrate. The opening V0 is provided on the second electrode plate C12 of the first capacitor. The shape of the opening V0 may be rectangular and located in the center of the second electrode plate C12 of the first capacitor, so that a ring structure is formed by the second electrode plate C12 of the first capacitor.The opening exposes the second insulating layer covering the first electrode plate of the first capacitor, and the orthographic projection of the first electrode plate of the first capacitor onto the substrate includes an orthographic projection of the opening V0 onto the substrate.

[0130] In an exemplary embodiment, as in Fig. 12 and Fig. 13, the second electrode plate C22 of the second capacitor may include a capacitor body portion C22_1, a first connection block C22_2, and a second connection block C22_3 connected to each other. The shape of the capacitor body portion C22_1 may be a line shape extending along the second direction Y, and the shapes of the first connection block C22_2 and the second connection block C22_3 may be a line shape extending along the first direction X. The first connection block C22_2 and the second connection block C22_3 may be located on a side of the capacitor body portion C22_1 facing away from the second electrode plate C12 of the first capacitor, and the first connection block C22_2 and the second connection block C22_3 are arranged along the second direction Y, that is,the second electrode plate C22 of the second capacitor may be a form of comb structure, wherein the capacitor body portion C22_1 may be used as the back of the comb structure, and the first connection block C22_2 and the second connection block C22_3 may each be used as comb teeth of the comb structure.

[0131] In an exemplary embodiment, as in Fig. 12 and Fig. 13, an orthographic projection of the capacitor body portion C22_1 onto the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the second capacitor onto the substrate.

[0132] In an exemplary embodiment, as in Fig. 12 and Fig. As shown in Figure 13, an orthographic projection of the first connection block C22_2 onto the substrate at least partially overlaps with an orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor onto the substrate. Because the orthographic projection of the first connection block onto the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor onto the substrate, the active layer of the second transistor located between the control electrodes of the second transistor can be covered and shielded by the first connection block, thereby effectively preventing current leakage and thus improving the reliability of the display base plate.

[0133] In an exemplary embodiment, as in Fig. 12 and Fig. 13, an orthographic projection of the second connection block C22_3 onto the substrate at least partially overlaps with an orthographic projection of the second region of the active layer of the third transistor (which is also used as the second region of the active layer of the second transistor and the first region of the active layer of the sixth transistor) onto the substrate.

[0134] In an exemplary embodiment, as shown in the Fig. 12 and Fig. 13, the virtual straight line extending along the first direction X does not pass through the second electrode plate C12 of the first capacitor and the first connection block C22_2 at the same time, while the virtual straight line extending along the first direction passes through the second electrode plate C12 of the first capacitor and the first connection block C22_2.

[0135] In an exemplary embodiment, as in Fig. 12 and Fig. As shown in Figure 13, the second electrode plate C12 of the first capacitor is connected to the capacitor body portion of the second electrode plate C22 of the second capacitor in this subpixel. The second connection block of this subpixel is connected to the second electrode plate C12 of the first capacitor of the adjacent subpixel.

[0136] In an exemplary embodiment, as in Fig. 12 and Fig. 13, the length of the second electrode plate C12 of the first capacitor along the second direction Y is smaller than the length of the second electrode plate C22 of the second capacitor along the second direction Y. In an exemplary embodiment, the length of the first connection block C22_2 along the second direction Y may be the same as or different from the length of the second connection block C22_3 along the second direction Y, which is not limited in this disclosure.

[0137] In an exemplary embodiment, as in Fig. 12 and Fig. As shown in Figure 13, the second initial signal line INIT2 may represent a line shape extending along the first direction X, and the second initial signal line INIT2 may be located on a side of the reset signal line facing away from the first electrode plate of the first capacitor. An orthographic projection of the second initial signal line INIT2 onto the substrate may partially overlap with the orthographic projections of the active layers of the seventh transistor and the first transistor onto the substrate.

[0138] In an exemplary embodiment, the second electrode plates C12 of the first capacitors of the subpixels arranged along the first direction X are connected to the second electrode plates C22 of the second capacitors of the adjacent subpixels so that the signals flowing through the second electrode plates C12 of the first capacitors and the second electrode plates C22 of the second capacitors of the subpixels arranged in the first direction X are the same, which can improve the uniformity of the display of the display base plate.

[0139] (4) Forming the pattern of a third insulating layer. In an exemplary embodiment, forming the pattern of a third insulating layer may include: depositing a third insulating film on the substrate on which the previous pattern was formed; patterning the third insulating film using a patterning process; and forming the third insulating layer covering the second conductive layer, wherein the third insulating layer is provided with a plurality of vias, as in Fig. 14 shown. Fig. 14 shows a schematic representation of the Fig. 7 provided display base plate after the formation of the third insulating layer.

[0140] In an exemplary embodiment, as in Fig. 14, the plurality of vias of the third insulating layer of each subpixel may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0141] In an exemplary embodiment, an orthographic projection of the first via V1 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the first transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the first via V1 such that the surface of the first region of the active layer of the first transistor is exposed, wherein the first via V1 is configured such that the first subsequently formed electrode of the first transistor T1 is connected therethrough to the first region of the active layer of the first transistor.

[0142] In an exemplary embodiment, an orthographic projection of the second via V2 onto the substrate lies within the boundary of the orthographic projection of the second region (which is also used as the first region of the active layer of the second transistor) of the active layer of the first transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the second via V2 such that the surface of the second region (which is also used as the first region of the active layer of the second transistor) of the active layer of the first transistor is exposed, wherein the second via V2 is configured such thatthat through it the second subsequently formed electrode (which is also used as the first electrode of the second transistor) of the first transistor T1 is connected to the first region (which is also used as the first region of the active layer of the second transistor) of the active layer of the first transistor.,

[0143] In an exemplary embodiment, an orthographic projection of the third via V3 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the fourth transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the third via V3 such that the surface of the first region of the active layer of the fourth transistor is exposed, wherein the third via V3 is configured such that the first subsequently formed electrode of the fourth transistor is connected therethrough to the first region of the active layer of the fourth transistor.

[0144] In an exemplary embodiment, an orthographic projection of the fourth via V4 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the fifth transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the fourth via V4 such that the surface of the first region of the active layer of the fifth transistor is exposed, wherein the fourth via V4 is configured such that the first subsequently formed electrode of the fifth transistor is connected therethrough to the first region of the active layer of the fifth transistor.

[0145] In an exemplary embodiment, an orthographic projection of the fifth via V5 onto the substrate lies within the boundary of the orthographic projection of the second region (which is also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the fifth via V5 such that the surface of the second region (which is also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor is exposed, wherein the fifth via V5 is configured such thatthat through it the second subsequently formed electrode (which is also used as the second electrode of the seventh transistor) of the sixth transistor T1 is connected to the second region (which is also used as the second region of the active layer of the sixth transistor) of the active layer of the sixth transistor.,

[0146] In an exemplary embodiment, an orthographic projection of the sixth via V6 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the seventh transistor onto the substrate, wherein the first insulating layer and the second insulating layer have been etched away from the sixth via V6 such that the surface of the first region of the active layer of the seventh transistor is exposed, wherein the sixth via V6 is configured such that the first subsequently formed electrode of the seventh transistor is connected therethrough to the first region of the active layer of the seventh transistor.

[0147] In an exemplary embodiment, an orthographic projection of the seventh via V7 onto the substrate lies within the boundary of the orthographic projection of the second electrode connection portion of the control electrode of the second transistor onto the substrate, wherein the second insulating layer has been etched away from the seventh via V7 such that the surface of the control electrode of the second transistor is exposed, wherein the seventh via V7 is configured such that the second subsequently formed scanning signal line is connected therethrough to the control electrode of the second transistor.

[0148] In an exemplary embodiment, an orthographic projection of the eighth via V8 onto the substrate lies within the boundary of the orthographic projection of the opening onto the substrate, wherein the second insulating layer has been etched away from the eighth via V8 such that the surface of the first electrode plate (which is also used as the control electrode of the third transistor) of the first capacitor is exposed, wherein the eighth via V8 is configured such that the second subsequently formed electrode (which is also used as the first electrode of the second transistor) of the first transistor is connected therethrough to the first electrode plate (which is also used as the control electrode of the third transistor) of the first capacitor.

[0149] In an exemplary embodiment, an orthographic projection of the ninth via V9 onto the substrate lies within the boundary of the orthographic projection of the control electrode of the fourth transistor onto the substrate, wherein the second insulating layer has been etched away from the ninth via V9 such that the surface of the control electrode of the fourth transistor is exposed, wherein the ninth via V9 is configured such that the first subsequently formed scan signal line is connected therethrough to the control electrode of the fourth transistor.

[0150] In an exemplary embodiment, an orthographic projection of the tenth via V10 onto the substrate lies within the boundary of the orthographic projection of the second initial signal line INIT2 onto the substrate, wherein the tenth via V10 exposes the surface of the second initial signal line INIT2. The tenth via V10 is configured to connect the first subsequently formed electrode of the seventh transistor to the second initial signal line INIT2.

[0151] In an exemplary embodiment, an orthographic projection of the eleventh via V11 onto the substrate lies within the boundary of the orthographic projection of the second electrode plate (also used as the second electrode plate of the second capacitor) of the first capacitor onto the substrate, wherein the eleventh via V11 exposes the surface of the second electrode plate (also used as the second electrode plate of the second capacitor) of the first capacitor. The eleventh via V11 is configured to connect the first subsequently formed electrode of the fifth transistor to the second electrode plate (also used as the second electrode plate of the second capacitor) of the first capacitor.In an exemplary embodiment, there may be a plurality of eleventh vias V11, wherein the plurality of eleventh vias V11 may be arranged sequentially along the second direction Y to improve connection reliability.

[0152] In an exemplary embodiment, a virtual straight line extending in the second direction may pass through the second via V2 and the eighth via V8.

[0153] In an exemplary embodiment, a virtual straight line extending in the second direction may pass through the fourth via V4 and the ninth via V9.

[0154] In an exemplary embodiment, a virtual straight line extending in the second direction passes through the fifth via V5 and the seventh via V7.

[0155] In an exemplary embodiment, a virtual straight line extending in the second direction passes through the sixth via V6 and the tenth via V10.

[0156] (5) Forming a third conductive layer. In an exemplary embodiment, forming a third conductive layer may include: depositing a third conductive film on the substrate on which the previous pattern was formed; patterning the third conductive film using a patterning process; and forming the third conductive layer disposed on the third insulating layer as in Fig. 15 and Fig. 16, where Fig. 15 a schematic representation of the pattern of the third conductive layer of the Fig. 7 provided display base plate and Fig. 16 a schematic representation of the Fig. 7 after the pattern of the third conductive layer has been formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal layer (SD1).

[0157] In an exemplary embodiment, as in Fig. 15 and Fig. 16, the pattern of the third conductive layer of each subpixel may include at least: a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T43 of the fourth transistor, a first electrode T53 of the fifth transistor, a second electrode T64 of the sixth transistor, a first electrode T73 and a second electrode T74 of the seventh transistor, the first scanning signal line Gate1 and the second scanning signal line Gate2.

[0158] In an exemplary embodiment, as in Fig. 15 and Fig. 16, the second electrode T14 of the first transistor may simultaneously serve as the first electrode T23 of the second transistor, and the second electrode T64 of the sixth transistor may simultaneously serve as the second electrode T74 of the seventh transistor, wherein the first electrode T13 of the first transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor may be arranged separately from each other.

[0159] In an exemplary embodiment, as in Fig. 15 and Fig. 16, the first electrode T13 of the first transistor, the first electrode T43 of the fourth transistor, and the first electrode T73 of the seventh transistor may be located on a side of the first scanning signal line Gate1 opposite from the second scanning signal line Gate2, and the first electrode T43 of the fourth transistor and the first electrode T73 of the seventh transistor may be located on both sides of the first electrode T13 of the first transistor, respectively.

[0160] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the second electrode T14 (also used as the first electrode T23 of the second transistor) of the first transistor, the first electrode T53 of the fifth transistor, and the second electrode T64 (also used as the second electrode T74 of the seventh transistor) of the sixth transistor may be located on a side of the second scanning signal line Gate2 opposite from the first scanning signal line Gate1. The second electrode T64 (also used as the second electrode T74 of the seventh transistor) of the sixth transistor and the first electrode T53 of the fifth transistor are respectively located on both sides of the second electrode T14 (also used as the first electrode T23 of the second transistor) of the first transistor.

[0161] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the shape of the first electrode T13 of the first transistor may represent a block structure. An orthographic projection of the first electrode T13 of the first transistor onto the substrate may partially overlap with orthographic projections of the first via and the reset signal line RESET onto the substrate. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor via the first via.

[0162] In an exemplary embodiment, as in Fig. 15 and Fig. 16, the shape of the second electrode T14 (which is also used as the first electrode T23 of the second transistor) of the first transistor may represent a linear shape extending along the second direction Y. An orthographic projection of the second electrode T14 (which is also used as the first electrode T23 of the second transistor) of the first transistor onto the substrate may partially overlap with orthographic projections of the second via, the eighth via, the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor onto the substrate.The second electrode T14 (which is also used as the first electrode T23 of the second transistor) of the first transistor is connected through the second via to the second region (which is also used as the first region of the active layer of the second transistor) of the active layer of the first transistor and is connected through the eighth via to the first electrode plate of the first capacitor.

[0163] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the shape of the first electrode T43 of the fourth transistor may represent a linear shape extending along the second direction Y. An orthographic projection of the first electrode T43 of the fourth transistor onto the substrate at least partially overlaps with orthographic projections of the third via and the reset signal line Reset onto the substrate. The first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor via the third via.

[0164] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the shape of the first electrode T53 of the fifth transistor may be a linear shape extending along the second direction Y. An orthographic projection of the first electrode T53 of the fifth transistor onto the substrate may at least partially overlap with orthographic projections of the fourth via, the eleventh via, the light emission signal line EM, and the second electrode plate (also used as the second electrode plate of the second capacitor) of the first capacitor onto the substrate. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor via the fourth via and is connected to the second electrode plate (also used as the second electrode of the second capacitor) of the first capacitor via the eleventh via.

[0165] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) may form a block structure. An orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) onto the substrate may at least partially overlap with orthographic projections of the fifth via and the light emission signal line EM onto the substrate. The second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) is connected to the second region (also used as the second region of the active layer of the seventh transistor) of the sixth transistor's active layer through the fifth via V5.

[0166] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the first electrode T73 of the seventh transistor may have a linear shape extending along the second direction Y. An orthographic projection of the first electrode T73 of the seventh transistor onto the substrate at least partially overlaps with orthographic projections of the sixth via, the tenth via, the reset signal line Reset, and the second initial signal line INIT2 onto the substrate. The first electrode of the seventh transistor is connected to the first region of the active layer of the seventh transistor via the sixth via V6 and to the second initial signal line INIT2 via the tenth via.

[0167] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the shape of the first scanning signal line Gate1 may represent a line shape extending along the first direction X, wherein the first scanning signal line Gate1 may be located on a side of the second scanning signal line Gate2 that is close to the first electrode T13 of the first transistor. An orthographic projection of the first scanning signal line Gate1 onto the substrate may at least partially overlap with orthographic projections of the ninth via and the control electrode of the fourth transistor onto the substrate. The first scanning signal line Gate1 is connected to the control electrode of the fourth transistor via the ninth via.

[0168] In an exemplary embodiment, as in Fig. 15 and Fig. As shown in Figure 16, the shape of the second scanning signal line Gate2 may be a line shape extending along the first direction X, wherein the second scanning signal line Gate2 may be located on a side of the first scanning signal line Gate1 close to the first electrode T53 of the fifth transistor. An orthographic projection of the second scanning signal line Gate2 onto the substrate may at least partially overlap with orthographic projections of the seventh via, the second electrode connection portion of the control electrode of the second transistor, and the capacitor body portion of the second electrode plate of the second capacitor onto the substrate. The second scanning signal line Gate2 is connected to the control electrode of the second transistor via the seventh via.

[0169] In an exemplary embodiment, the first scanning signal line Gate1 and the second scanning signal line Gate2 may be provided with equal widths or unequal widths and may be straight lines or broken lines, which can not only facilitate the layout of the pixel structures but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure.

[0170] (6) Forming the pattern of a fourth insulating layer. In an exemplary embodiment, forming the pattern of a fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the previous pattern was formed, patterning the fourth insulating film using a patterning process, and forming the fourth insulating layer covering the third conductive layer, wherein the third insulating layer is provided with a plurality of vias, as in Fig. 17 shown. Fig. 17 shows a schematic representation of the Fig. 7 provided display base plate after formation of the pattern of the fourth insulating layer.

[0171] In an exemplary embodiment, as in Fig. 17, the plurality of vias of the fourth insulating layer of each subpixel may include at least: a twelfth via V12, a thirteenth via V13, a fourteenth via V14, and a fifteenth via V15.

[0172] In an exemplary embodiment, an orthographic projection of the twelfth via V12 onto the substrate lies within the boundary of the orthographic projection of the first electrode of the first transistor onto the substrate, wherein the surface of the first electrode of the first transistor is exposed by the twelfth via V12, wherein the twelfth via V12 is configured such that the subsequently formed first initial signal line is connected to the first electrode of the first transistor via this via.

[0173] In an exemplary embodiment, an orthographic projection of the thirteenth via V13 onto the substrate lies within the boundary of the orthographic projection of the first electrode of the fourth transistor onto the substrate, wherein the surface of the first electrode of the fourth transistor is exposed by the thirteenth via V13, wherein the thirteenth via V13 is configured such that the subsequently formed data signal line is connected to the first electrode of the fourth transistor through this via.

[0174] In an exemplary embodiment, an orthographic projection of the fourteenth via V14 onto the substrate lies within the boundary of the orthographic projection of the first electrode of the fifth transistor onto the substrate, wherein the surface of the first electrode of the fifth transistor is exposed by the fourteenth via V14, wherein the fourteenth via V14 is configured such that the subsequently formed first power supply line is connected to the first electrode of the fifth transistor via this via.

[0175] In an exemplary embodiment, an orthographic projection of the fifteenth via V15 onto the substrate lies within the boundary of the orthographic projection of the second electrode (which is also used as the second electrode of the seventh transistor) of the sixth transistor onto the substrate, wherein the surface of the second electrode (which is also used as the second electrode of the seventh transistor) of the sixth transistor is exposed through the fifteenth via V15, wherein the fifteenth via V15 is configured such that the subsequently formed connection electrode is to be connected through this via to the second electrode (which is also used as the second electrode of the seventh transistor) of the sixth transistor.

[0176] (7) Forming the pattern of a fourth conductive layer. In an exemplary embodiment, forming the pattern of a fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the previous pattern was formed, and patterning the fourth conductive film using a patterning process and forming the pattern of the fourth conductive layer as in Fig. 18 and Fig. 19 shown. Fig. Figure 18 shows a schematic representation of the pattern of the fourth conductive layer of the Fig. 7 provided display base plate, and Fig. 19 shows a schematic representation of the Fig. 7 after the formation of the pattern of the fourth conductive layer. In exemplary embodiments, the fourth conductive layer may be referred to as a second source-drain metal layer (SD2).

[0177] In an exemplary embodiment, as in Fig. 18 and Fig. 19, the pattern of the fourth conductive layer of each subpixel may include at least: a first initial signal line INIT1, a connection electrode VL, a first power supply line VDD, and a data signal line Data.

[0178] In an exemplary embodiment, as in Fig. 18 and Fig. 19, the connection electrode VL may be located on a side of the first initial signal line INIT1 facing away from the first initial signal line INIT1, wherein the first power supply line VDD is located between the first initial signal line INIT1 and the data signal line Data.

[0179] In an exemplary embodiment, as in Fig. 18 and Fig. 19, the shape of the connection electrode VL may be a stripe shape. An orthographic projection of the connection electrode VL onto the substrate overlaps with an orthographic projection of the fifteenth via onto the substrate. The connection electrode VL is connected through the fifteenth via to the second region (also used as the second region of the seventh active layer) of the sixth active layer, which is used as the second electrode (also used as the second electrode of the seventh transistor T7) of the sixth transistor T6. In an exemplary embodiment, the connection electrode VL is configured to be connected to a subsequently formed anode.

[0180] In an exemplary embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the shape of the first initial signal line INIT1 may be a line shape in which its main portion extends along the second direction Y. The orthographic projection of the first initial signal line INIT1 onto the substrate at least partially overlaps with the orthographic projections of the second via, the eighth via, the twelfth via, and the second electrode (also used as the first electrode of the second transistor) of the first transistor onto the substrate. The first initial signal line INIT1 is connected to the first electrode of the first transistor via the twelfth via.The orthographic projection of the first initial signal line onto the substrate at least partially overlaps with the orthographic projection of the eighth via onto the substrate, thereby preventing other signals from interfering with the first node, effectively improving the stability of the first node. The orthographic projection of the first initial signal line onto the substrate partially overlaps with the orthographic projection of the twelfth via onto the substrate, resulting in the active layer of the first transistor between the control electrodes of the first transistors being covered and shielded by the first initial signal line, effectively preventing current leakage and thus improving the reliability of the display base plate.

[0181] In an exemplary embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the first initial signal line is located on the fourth conductive layer, and the main portion of the first initial signal line extends along the second direction. Since the signal of the first initial signal line is input to the display area through a chip located in the bonding area, the first initial signal line, whose main portion extends along the second direction, is designed as the shortest path. The first initial signal line can be input directly from the bottom. This contributes to speeding up the initialization of the first node.

[0182] In an exemplary embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the shape of the main portion of the first power supply line VDD may be a line shape extending along the second direction Y. An orthographic projection of the first power supply line VDD onto the substrate overlaps with the orthographic projections of the ninth via, the fourteenth via, the control electrode of the fourth transistor, the second electrode plate of the first capacitor, and the capacitor body portion of the second electrode plate of the second capacitor onto the substrate. The first power supply line VDD is connected to the first electrode of the fifth transistor via the fourteenth via, thereby writing the current signal to the first electrode of the fifth transistor.The first electrode of the fifth transistor is connected to the second electrode plate of the first capacitor and the second electrode plate of the second capacitor, whereby the first electrode of the fifth transistor, the second electrode plate of the first capacitor and the second electrode plate of the second capacitor have the same potential.

[0183] In an exemplary embodiment, as in Fig. 18 and Fig. 19, the orthographic projection of the first power supply line VDD onto the substrate is located between the orthographic projection of the eighth via onto the substrate and an orthographic projection of the data signal line Data onto the substrate, so that the area between the first node and the data signal line Data is shielded and separated by the first power supply line VDD, thereby effectively preventing the effects of the jump of the data signal line Data on the first node, thereby preventing the occurrence of signal crosstalk and increasing the reliability of the display substrate.

[0184] In an exemplary embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the shape of the data signal line Data may be a linear shape in which its body portion extends along the second direction Y. The orthographic projection of the data signal line Data onto the substrate at least partially overlaps with the orthographic projections of the thirteenth vias, the capacitor body portion of the second electrode plate of the second capacitor, and the control electrode of the fourth transistor onto the substrate. The data signal line Data is connected to the first electrode of the fourth transistor via the thirteenth via.

[0185] In an exemplary embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the data signal line Data is located on the fourth conductive layer, which can reduce the parasitic capacitance between the data signal line Data and the underlying conductive film layer, thus contributing to saving charging time and power consumption.

[0186] In an exemplary embodiment, the first initial signal line INIT1, the data signal line Data, and the first power supply line VDD can be configured with equal or unequal widths, and can be straight lines or broken lines. This can not only facilitate the layout of the pixel structures but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure. For example, the width of the first power supply line VDD can be larger than the width of the data signal line Data and larger than the width of the first initial signal line INIT1, and the width of the first initial signal line INIT1 can be larger than the width of the data signal line Data.

[0187] (8) Forming the pattern of a planarization layer. In an exemplary embodiment, forming the pattern of a planarization layer may include coating a planarization film on the substrate on which the previous pattern was formed, patterning the planarization film using a patterning process, and forming the planarization layer covering the pattern of the fourth conductive layer.

[0188] Now the drive circuit layer of the Fig. 7 provided on the substrate. In a plane parallel to the display base plate, the drive circuit layer may include a plurality of pixel circuits. The drive circuit layer may further include: a first scanning signal line, a second scanning signal line, a light emission signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power supply line. In a plane perpendicular to the display base plate, the drive circuit layer may be arranged on the substrate, and the substrate may include a first flexible layer, a barrier layer, a conductive base layer, and a second flexible layer stacked on top of one another.

[0189] The drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, and a planarization layer, which are sequentially disposed on the substrate. The semiconductor layer may include at least the active layers of the first to seventh transistors and the first electrode plate of the second capacitor. The first conductive layer may include at least a reset signal line, a light-emitting signal line, and control electrodes of the first to seventh transistors, and the first electrode plate of the first capacitor. The second conductive layer may include at least the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, and the second initial signal line.The third conductive layer may include at least a first scanning signal line and a second scanning signal line. The fourth conductive layer may include at least the first initial signal line, the data signal line, the first power supply line, and a connection electrode.

[0190] In an exemplary embodiment, one or more metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), may be used for the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, wherein the layers may represent a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. One or more materials of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) may be used for the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, wherein the layers may represent a single-layer structure or a multi-layer composite structure.The first insulating layer may be referred to as the buffer layer, the second and third insulating layers may be referred to as the gate insulating layer (GI), the fourth insulating layer may be referred to as the interlayer insulating layer (ILD), and the fifth insulating layer may be referred to as the passivation layer (PVX). The planarization layer may be made of organic materials, such as resin.

[0191] The manufacturing process of Fig. The display base plate provided in Figure 8 is described below using a pixel circuit with one row and two columns as an example. The manufacturing process of the display base plate provided by an exemplary embodiment may include the following: (1) Forming the pattern of a cap layer on a substrate. In an exemplary embodiment, forming the pattern of the cap layer may include: sequentially depositing a conductive shielding film on the substrate, patterning the conductive shielding film using a patterning process, and forming the pattern of the cap layer, as in Fig. 20 shown. Fig. 20 shows a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the cover layer.

[0192] In an exemplary embodiment, as in Fig. 20, the pattern of the cap layer of each subpixel may include at least a first cap structure 11, a second cap structure 12, a first cap connection structure 13, a second cap connection structure 14, a third cap connection structure 15, a fourth cap connection structure 16, and the first electrode plate C21 of the second capacitor, wherein the second cap structure 12 is also used as the first electrode plate C21 of the second capacitor.

[0193] In an exemplary embodiment, the cover layer is configured to transmit a high voltage power supply signal therethrough.

[0194] In an exemplary embodiment, as in Fig. 20, for the same subpixel, the first cap connection structure 13 and the second cap structure 12 are each located on opposite sides of the first cap structure 11 and are connected to the first cap structure 11. The second cap connection structure 14 is located on a side of the second cap structure 12 (which is also used as the first electrode plate C21 of the second capacitor) facing away from the first cap structure 11 and is connected to the second cap structure 12 (which is also used as the first electrode plate C21 of the second capacitor).The third cover connection structure 15 and the fourth cover connection structure 16 are respectively located on the other two opposite sides of the first cover structure 11, and the third cover connection structure 15 is connected to the second cover structure 12 (which is also used as the first electrode plate of the second capacitor C21), and the fourth cover connection structure 16 is connected to the first cover structure 11.

[0195] In an exemplary embodiment, as in Fig. As shown in Figure 20, the second capping structure 12 (also used as the first electrode plate C21 of the second capacitor) of the Nth column of subpixels in a same row is located on a side of the first capping structure of the same subpixel close to the first capping structure 11 of the N+1th column of subpixels, and the first capping connection structure 13 of the Nth column of subpixels in a same row is located on a side of the first capping structure 11 of the same subpixel close to the first capping structure 11 of the N-1th column of subpixels and is connected to the fourth capping connection structure 14 of the N-1th column of subpixels. The second capping connection structure 14 of the Nth column of subpixels in a same row is connected to the first capping connection structure 13 of the N+1th column of subpixels.

[0196] In an exemplary embodiment, as in Fig. 20, the third cover connection structure 15 of the M-th row of subpixels in a same column is located on a side of the first cover structure 11 of the same subpixel that is close to the first cover structure 11 of the M-1-th row of subpixels and is connected to the fourth cover connection structure 16 of the M-1-th row of subpixels. The fourth cover connection structure 16 of the M-th row of subpixels in a same column is located on a side of the first cover structure 11 of the same subpixel that is close to the first cover structure 11 of the M+1-th row of subpixels and is connected to the fifth cover connection structure 15 of the M+1-th row of subpixels.

[0197] In an exemplary embodiment, as in Fig. 20, a virtual straight line extending along the second direction Y passes through the third cover connection structure 15 and the fourth cover connection structure 16.

[0198] In an exemplary embodiment, as in Fig. 20, the shape of the first cover structure 11 may be a rectangle, and the corners of the rectangle may be rounded. The shape of the second cover structure 12 may be a line shape extending along the second direction Y. The shape of the first cover connection structure 13 and the shape of the second cover connection structure 14 may be a line shape extending along the first direction X. The shape of the main part of the third cover connection structure 15 may be a broken line extending along the second direction Y. The shape of the fourth cover connection structure 16 may be a line shape extending along the second direction Y.

[0199] In an exemplary embodiment, as in Fig. 20, the length of the first cover structure 11 along the first direction X is greater than the length of the second cover structure 12 along the first direction X, and the length of the first cover structure 11 along the second direction Y is smaller than the length of the second cover structure 12 along the second direction Y.

[0200] In exemplary embodiments, the shapes of the capping layers may be the same in multiple subpixels.

[0201] In an exemplary embodiment, the capping layers of all subpixels are integrally connected to each other and form a mesh shape, whereby it can be ensured that the capping layers in the display base plate have an equal potential, which improves the uniformity of the display substrate and avoids poor display quality of the display base plate, thus ensuring the display effect of the display base plate.

[0202] (2) Forming the pattern of a semiconductor layer. In an exemplary embodiment, forming the pattern of a semiconductor layer may include: depositing a first insulating film and a semiconductor film on the substrate on which the previous pattern was formed; patterning the semiconductor film using a patterning process; forming a first insulating layer covering the pattern of the covering layer, and forming the pattern of the semiconductor layer on the first insulating layer, as in Fig. 21 and Fig. 22 shown. Fig. 21 shows a schematic representation of the pattern of the semiconductor layer of the Fig. 8 provided display base plate. Fig. 22 shows a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the semiconductor layer.

[0203] In an exemplary embodiment, as in Fig. 21 and Fig. 22, the pattern of the semiconductor layer of each subpixel may include at least: an active layer T11 of the first transistor to an active layer T81 of the eighth transistor.

[0204] In an exemplary embodiment, as in Fig. 21 and Fig. 22, the active layer T11 of the first transistor to the active layer T81 of the eighth transistor are integrally connected to each other.

[0205] In an exemplary embodiment, as in Fig. 21 and Fig. 22, in the first direction X, the active layer T21 of the second transistor and the active layer T61 of the sixth transistor T61 may be located on a same side of the active layer T31 of the third transistor in this subpixel, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on a same side of the active layer T31 of the third transistor in this subpixel, and the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in this subpixel.In the second direction Y, the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor and the active layer T81 of the eighth transistor may be located on a same side of the active layer T31 of the third transistor in this subpixel, and the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor may be located on another side of the active layer T31 of the third transistor in this subpixel.

[0206] In an exemplary embodiment, as in Fig. 21 and Fig. As shown in Figure 22, the active layer T11 of the first transistor may represent a "T" shape, the active layer T21 of the second transistor may represent a horizontally inverted "7" shape, and the shape of the active layer T31 of the third transistor may represent an "Ω" shape. The shapes of the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T81 of the eighth transistor may represent an "I" shape, and the shape of the active layer T71 of the seventh transistor may represent a "I" shape.

[0207] In an exemplary embodiment, as in Fig. 21 and Fig. As shown in Figure 22, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor may serve as the first region T81_1 of the active layer T81 of the eighth transistor, the second region T81_2 of the active layer T81 of the eighth transistor may serve as the first region T21_1 of the active layer T21 of the second transistor, the first region T31_1 of the active layer T31 of the third transistor may simultaneously serve as the second region T41_2 of the active layer T41 of the fourth transistor and as the second region T51_2 of the active layer T51 of the fifth transistor.the second region T31_2 of the active layer T31 of the third transistor can simultaneously serve as the second region T21_2 of the active layer T21 of the second transistor and as the first region T61_1 of the active layer T61 of the sixth transistor, the second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor, and the first region T11_1 of the active layer T11 of the first transistor, the first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51 of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor can be arranged separately from each other.

[0208] In an exemplary embodiment, as in Fig. 21 and Fig. 22, the first region T11_1 of the active layer T11 of the first transistor comprises a first connecting portion T11_1A extending along the first direction X and a second connecting portion T11_1B extending along the second direction Y.

[0209] In an exemplary embodiment, as in Fig. 21 and Fig. As shown in Figure 22, the first regions T11_1 of the active layers T11 of the first transistors of adjacent subpixels located in the same row are interconnected. The first connecting portions T11_1A of the first regions T11_1 of the active layers T11 of the first transistors of adjacent subpixels located in the same row are interconnected.

[0210] In an exemplary embodiment, as in Fig. 21 and Fig. 22, the first region T71_1 of the active layer T71 of the seventh transistor comprises a third connection portion T71_1A extending in the first direction X and a fourth connection portion T71_1B extending in the second direction Y.

[0211] In an exemplary embodiment, as in Fig. 21 and Fig. As shown in Figure 22, the first regions T71_1 of the active layers T71 of the seventh transistors of adjacent subpixels located in the same row are interconnected. The third connecting portions T71_1A of the first regions T71_1 of the active layers T71 of the seventh transistors of adjacent subpixels located in the same row are interconnected.

[0212] In an exemplary embodiment, as in Fig. 21 and Fig. As shown in Figure 22, the orthographic projection of the first capping structure onto the substrate at least partially overlaps with an orthographic projection of the channel region of the active layer T31 of the third transistor onto the substrate. The orthographic projection of the second capping structure onto the substrate at least partially overlaps with an orthographic projection of the first region T31_1 of the active layer T31 of the third transistor (the second region T41_2 of the active layer T41 of the fourth transistor and the second region T41_2 of the active layer T51 of the fifth transistor) onto the substrate. The orthographic projections of the third capping connection structure onto the substrate at least partially overlap with an orthographic projection of the first region T11_1 of the active layer T11 of the first transistor onto the substrate.The orthographic projection of the fourth cover connection structure onto the substrate overlaps at least partially with an orthographic projection of the first region T71_1 of the active layer T71 of the seventh transistor onto the substrate.

[0213] In the present disclosure, the orthographic projection of the first capping structure onto the substrate at least partially overlaps with the orthographic projection of the channel region of the active layer T31 of the third transistor onto the substrate, which can improve the performance of the third transistor, ie, the driver transistor, and thus improve the reliability of the display base plate.

[0214] (3) Forming the pattern of a first conductive layer. In an exemplary embodiment, forming the pattern of a first conductive layer may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the previous pattern was formed; patterning the first conductive film using a patterning process; forming a second insulating layer covering the pattern of the semiconductor layer, and forming the pattern of the first conductive layer located on the second insulating layer, as shown in FIGS. Fig. 23 and Fig. 24 shown. Fig. Figure 23 shows a schematic representation of the pattern of the first conductive layer of the Fig. 8 provided display base plate. Fig. 24 shows a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the first conductive layer. In exemplary embodiments, the first conductive layer may be referred to as a first gate metal layer (GATE1).

[0215] In an exemplary embodiment, the pattern of the first conductive layer of each subpixel may include at least: a light emission signal line EM, a control electrode T12 of the first transistor to a control electrode T82 of the eighth transistor, and a first electrode plate C11 of the first capacitor.

[0216] In an exemplary embodiment, as in Fig. 23 and Fig.As shown in Figure 24, the shape of the first electrode plate C11 of the first capacitor may be a rectangle, and the corners of the rectangle may be rounded, wherein the orthographic projection of the first electrode plate C11 of the first capacitor onto the substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode plate C11 of the first capacitor may simultaneously serve as the control electrode T32 of the third transistor T3.

[0217] In an exemplary embodiment, as Fig. 23 and Fig. 24, the shape of the light emission signal line EM may be a line shape extending along the first direction X, the region where the light emission signal line EM overlaps with the active layer of the fifth transistor T5 serving as the control electrode T52 of the fifth transistor T5, and the region where the light emission signal line EM overlaps with the active layer of the sixth transistor T6 serving as the control electrode T62 of the sixth transistor T6.

[0218] In an exemplary embodiment, as in Fig. 23 and Fig. 24, the control electrode T12 of the first transistor T1, the control electrode T22 of the second transistor T2, the control electrode T42 of the fourth transistor T4, and the control electrode T82 of the eighth transistor T8 may be located on a side of the first electrode plate C11 of the first capacitor remote from the light emission signal line EM, the control electrode T42 of the fourth transistor T4 and the control electrode T82 of the eighth transistor T8 may be located on a side of the control electrode T22 of the second transistor T2 remote from the first electrode plate C11 of the first capacitor, and the control electrode T12 of the first transistor T1 may be located on a side of the control electrode T42 of the fourth transistor T4 and the control electrode T82 of the eighth transistor T8 remote from the first electrode plate C11 of the first capacitor.The control electrode of the seventh transistor T72 is located on a side of the light emission signal line EM facing away from the first electrode plate C11 of the first capacitor.

[0219] In an exemplary embodiment, as in Fig. 23 and Fig. 24, the shape of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be a line shape extending along the first direction X.

[0220] In an exemplary embodiment, as in Fig. 23 and Fig. As shown in Figure 24, the control electrode T42 of the fourth transistor may simultaneously serve as the control electrode T82 of the eighth transistor. The shape of the control electrode T42 of the fourth transistor (which is also used as the control electrode T82 of the eighth transistor) may be a line shape extending along the first direction X.

[0221] In an exemplary embodiment, as in Fig. 23 and Fig. As shown in Figure 24, the control electrode T22 of the second transistor may include a first electrode connecting portion T22A extending in the first direction X and a second electrode connecting portion T22B extending in the second direction Y. Orthographic projections of the first electrode connecting portion T22A and the second electrode connecting portion T22B onto the substrate partially overlap with the orthographic projection of the active layer of the second transistor onto the substrate. Therefore, there are two regions where the control electrode T22 of the second transistor overlaps with the active layer T21 of the second transistor, i.e., there are two control electrodes T22 of the second transistor, and the second transistor represents a double-gate structure.

[0222] In an exemplary embodiment, after the formation of the pattern of the first conductive layer, the first conductive layer can be used as a cap to perform a conductive process for the semiconductor layer, wherein the channel regions of the first T1 to eighth transistors T8 are formed by the region of the semiconductor layer covered by the first conductive layer, and the region of the semiconductor layer not covered by the first conductive layer becomes conductive, that is, the first regions and the second regions of the active layers of the first to eighth transistors all become conductive. The already conductive first region T11_1 of the active layer T11 of the first transistor can simultaneously serve as the first electrode T13 of the first transistor and the first initial signal line INIT1.The already conductive second region T11_2 (also used as the first region T81_1 of the active layer T81 of the eighth transistor) of the active layer T11 of the first transistor can simultaneously serve as the second electrode T14 of the first transistor and the first electrode T83 of the eighth transistor. The already conductive first region T31_1 (also used as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) of the active layer T31 of the third transistor can simultaneously serve as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode plate C22 of the second capacitor.The already conductive second region T31_2 (also used as the second region T21_2 of the active layer T21 of the second transistor and the first region T61_1 of the active layer T61 of the sixth transistor) of the active layer T31 of the third transistor can simultaneously serve as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor. The already conductive first region T71_1 of the active layer T71 of the seventh transistor can simultaneously serve as the first electrode T73 of the seventh transistor and the second initial signal line INIT2.

[0223] In an exemplary embodiment, the first initial signal line INIT1, the second initial signal line INIT2, and the light emission signal line EM may be provided with equal widths or with unequal widths, and may be a line or a broken line, which can not only facilitate the layout of the pixel structures but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure.

[0224] (4) Forming the pattern of a second conductive layer. In an exemplary embodiment, forming the pattern of a second conductive layer may include: depositing a third insulating layer film and a second conductive film on the substrate on which the previous pattern was formed, patterning the second conductive film using a patterning process, and forming the pattern of the second conductive layer on the third insulating layer, as shown in FIGS. Fig. 25 and Fig. 26 shown. Fig. Figure 25 shows a schematic representation of the pattern of the second conductive layer of the Fig. 8 provided display base plate. Fig. 26 shows a schematic representation of the Fig. 8 after the pattern of the second conductive layer has been formed. In exemplary embodiments, the second conductive layer may be referred to as a second gate metal layer (GATE2).

[0225] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the pattern of the second conductive layer of each subpixel includes at least: a second electrode plate C12 of the first capacitor, a third electrode plate C23 of the second capacitor, and a shield electrode 21.

[0226] In an exemplary embodiment, as in Fig. 25 and Fig. 26, for the same subpixel, the second electrode plate C12 of the first capacitor and the third electrode plate C23 of the second capacitor are connected to each other, and the shield electrode 21 is provided separately.

[0227] In an exemplary embodiment, as in Fig. 25 and Fig. 26, for the subpixels in the same row, the third electrode plate C23 of the second capacitor of the Nth column of subpixels is located on a side of the second electrode plate C12 of the first capacitor of the Nth column of subpixels that is close to the second electrode plate C12 of the first capacitor of the N+1th column of subpixels, and is connected to the second electrode plate C12 of the first capacitor of the N+1th column of subpixels. By connecting the third electrode plate C23 of the second capacitor of the Nth column of subpixels to the second electrode plate C12 of the first capacitor of the N+1th column of subpixels, the signals flowing through the second electrode plate C12 of the first capacitor and the third electrode plate C23 of the second capacitor of the subpixels arranged and adjacent along the first direction X can be equal, which can improve the display uniformity of the display base plate.

[0228] In an exemplary embodiment, the second capacitor comprises a first electrode plate located in the capping layer, a second electrode plate located in the semiconductor layer, and a third electrode plate located in the second conductive layer, wherein the first electrode plate and the third electrode plate are both used for transmitting high voltage power supply signals.In the present disclosure, by providing the second capacitor to include a first electrode plate located in the cap layer, a second electrode plate located in the semiconductor layer, and a third electrode plate located in the second conductive layer, the second capacitor can store more charges, which increases the charging performance of the second capacitor, can prolong the charging time of the first node in the pixel circuit, improves the performance of the display base plate, and contributes to achieving a high refresh rate.

[0229] In an exemplary embodiment, as in Fig. 25 and Fig. As shown in Figure 26, the second electrode plate C12 of the first capacitor may include a capacitor body portion C12A and a connecting portion C12B that are connected to each other. The connecting portion C12B and the third electrode plate C23 of the second capacitor are located on opposite sides of the capacitor body portion C12A, respectively, and are each connected to the capacitor body portion C12A. The connecting portion C12B of the N+1th column of subpixels is connected to the third electrode plate C23 of the second capacitor of the Nth column of subpixels.

[0230] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the shape of the capacitor body portion C12A may be a rectangle, and the corners of the rectangle may be rounded. An orthographic projection of the capacitor body portion C12A onto the substrate at least partially overlaps with an orthographic projection of the first electrode plates of the first capacitor onto the substrate. The capacitor body portion C12A is provided with an opening V0. The shape of the opening V0 may be rectangular and located in the center of the capacitor body portion C12A, such that a ring structure is formed by the capacitor body portion C12A. The opening V0 exposes the third insulating layer covering the first electrode plate of the first capacitor, and the orthographic projection of the first electrode plate of the first capacitor onto the substrate includes an orthographic projection of the opening V0 onto the substrate.

[0231] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the shape of the connecting portion C12B may be a line shape extending along the first direction X.

[0232] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the shape of the third electrode plate C23 of the second capacitor may represent a broken line extending along the second direction X. An orthographic projection of the third electrode plate C23 of the second capacitor onto the substrate at least partially overlaps with an orthographic projection of the second electrode plate of the second capacitor onto the substrate.

[0233] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the length of the second electrode plate C12 of the first capacitor along the second direction Y is smaller than the length of the third electrode plate C23 of the second capacitor along the second direction Y.

[0234] In an exemplary embodiment, as in Fig. 25 and Fig. As shown in Figure 26, for subpixels in the same column, the shield electrode 21 of the M+1th row of subpixels is located on a side of the second electrode plate C12 of the first capacitor of the M+1th row of subpixels that is close to the second electrode plate C12 of the first capacitor of the Mth row of subpixels. For the subpixels in the same row, the shield electrode 21 of the N+1th column of subpixels is electrically connected to the third electrode plate C23 of the second capacitor of the Nth column of subpixels.

[0235] In an exemplary embodiment, as in Fig. 25 and Fig. 26, the shield electrode 21 may have a block shape. An orthographic projection of the shield electrode 21 onto the substrate at least partially overlaps with an orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor onto the substrate. By at least partially overlapping the orthographic projection of the shield electrode 21 onto the substrate with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor onto the substrate, the active layer of the second transistor located between the control electrodes of the second transistor can be covered and shielded by the shield electrode, whereby current leakage can be effectively prevented and thus the reliability of the display base plate is improved.

[0236] (5) Forming the pattern of a fourth insulating layer. In an exemplary embodiment, forming the pattern of a fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the previous pattern was formed, patterning the fourth insulating film using a patterning process, and forming the fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer is provided with a plurality of vias, as in Fig. 27 shown. Fig. 27 shows a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the fourth insulating layer.

[0237] In an exemplary embodiment, as in Fig. 27, the plurality of vias of the fourth insulating layer of each subpixel may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0238] In an exemplary embodiment, an orthographic projection of the first via V1 onto the substrate lies within the boundary of the orthographic projection of the first region (which is also used as the second region of the active layer of the eighth transistor) of the active layer T21 of the second transistor onto the substrate.The materials of the second insulating layer and the third insulating layer in the first via V1 are etched away, thereby exposing the surface of the first region (which is also used as the second region of the active layer of the eighth transistor) of the active layer of the second transistor, wherein the first via V1 is configured such that the first subsequently formed electrode (which is also used as the second electrode of the eighth transistor) of the second transistor is connected therethrough to the first region (which is also used as the second region of the active layer of the eighth transistor) of the active layer of the second transistor.

[0239] In an exemplary embodiment, an orthographic projection of the second via V2 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the fourth transistor onto the substrate. The materials of the second insulating layer and the third insulating layer in the second via V2 are etched away, thereby exposing the surface of the first region of the active layer of the fourth transistor, wherein the second via V2 is configured to connect the first subsequently formed electrode of the fourth transistor to the first region of the active layer of the fourth transistor.

[0240] In an exemplary embodiment, an orthographic projection of the third via V3 onto the substrate lies within the boundary of the orthographic projection of the first region of the active layer of the fifth transistor onto the substrate. The materials of the second insulating layer and the third insulating layer in the third via V3 are etched away, thereby exposing the surface of the first region of the active layer of the fifth transistor, wherein the third via V3 is configured to connect the first subsequently formed electrode of the fifth transistor to the first region of the active layer of the fifth transistor.

[0241] In an exemplary embodiment, an orthographic projection of the fourth via V4 onto the substrate lies within the boundary of the orthographic projection of the second region (which is also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor onto the substrate.The materials of the second insulating layer and the third insulating layer in the fourth via V1 are etched away, thereby exposing the surface of the second region (which is also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor, wherein the fourth via V4 is configured such that the second subsequently formed electrode (which is also used as the second electrode of the seventh transistor) of the sixth transistor is connected therethrough to the second region (which is also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor.

[0242] In an exemplary embodiment, an orthographic projection of the fifth via V5 onto the substrate lies within the boundary of the orthographic projection of the control electrode of the first transistor onto the substrate. The material of the third insulating layer in the fifth via V5 is etched away, thereby exposing the surface of the control electrode of the first transistor, wherein the fifth via V5 is configured such that one of the subsequently formed reset signal lines is connected therethrough to the control electrode of the first transistor.

[0243] In an exemplary embodiment, an orthographic projection of the sixth via V6 onto the substrate lies within the boundary of the orthographic projection of the control electrode of the second transistor onto the substrate. The material of the third insulating layer in the sixth via V6 is etched away, thereby exposing the surface of the control electrode of the second transistor, wherein the sixth via V6 is configured to connect the subsequently formed scanning signal line to the control electrode of the second transistor.

[0244] In an exemplary embodiment, an orthographic projection of the seventh via V7 onto the substrate lies within the boundary of the orthographic projection of the opening onto the substrate. The material of the third insulating layer in the seventh via V7 is etched away, thereby exposing the surface of the first electrode plate (also used as the control electrode of the third transistor) of the first capacitor, wherein the seventh via V7 is configured such that the first subsequently formed electrode (also used as the second electrode of the eighth transistor) of the second transistor is connected therethrough to the first electrode plate (also used as the control electrode of the third transistor) of the first capacitor.

[0245] In an exemplary embodiment, an orthographic projection of the eighth via V8 onto the substrate lies within the boundary of the orthographic projection of the control electrode (also used as the control electrode of the eighth transistor) of the fourth transistor onto the substrate. The material of the third insulating layer in the eighth via V8 is etched away, exposing the surface of the control electrode (also used as the control electrode of the eighth transistor) of the fourth transistor, wherein the eighth via V8 is configured to connect the subsequently formed second scan signal line to the control electrode (also used as the control electrode of the eighth transistor) of the fourth transistor.

[0246] In an exemplary embodiment, an orthographic projection of the ninth via V9 onto the substrate lies within the boundary of the orthographic projection of the control electrode of the seventh transistor onto the substrate. The material of the third insulating layer in the ninth via V9 is etched away, thereby exposing the surface of the control electrode of the seventh transistor, wherein the ninth via V9 is configured to connect another reset signal line of the subsequently formed reset signal lines to the control electrode of the seventh transistor.

[0247] (6) Forming a third conductive layer. In an exemplary embodiment, forming a third conductive layer may include depositing a third conductive film on the substrate on which the preceding pattern was formed, patterning the third conductive film using a patterning process, and forming the third conductive layer disposed on the fourth insulating layer, as shown in Fig. 28 and Fig. 29 shown. Fig. Figure 28 shows a schematic representation of the pattern of the third conductive layer of the Fig. 8 provided display base plate. Fig. 29 shows a schematic representation of the Fig. 8 after the pattern of the third conductive layer has been formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal layer (SD1).

[0248] In an exemplary embodiment, as in Fig. 28 and Fig. 29, the pattern of the third conductive layer of each subpixel may include at least two reset signal lines Reset, the first scanning signal line Gate1, the second scanning signal line Gate2, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the second electrode T74 of the seventh transistor, and the second electrode T84 of the eighth transistor. The first electrode T23 of the second transistor may simultaneously serve as the second electrode T84 of the eighth transistor, and the second electrode T64 of the sixth transistor may simultaneously serve as the second electrode T74 of the seventh transistor. The first electrode T43 of the fourth transistor and the first electrode T53 of the fifth transistor may be arranged separately from each other.

[0249] In an exemplary embodiment, as in Fig. 28 and Fig. 29, the first electrode T43 of the fourth transistor may be located between one of the reset signal lines Reset and the first scan signal line Gate1.The first electrode T23 (also used as the second electrode T84 of the eighth transistor) of the second transistor, the first electrode T53 of the fifth transistor, and the second electrode T64 (also used as the second electrode T74 of the seventh transistor) of the sixth transistor may be located between the second scanning signal line Gate2 and another reset signal line Reset, wherein the first electrode T23 (also used as the second electrode T84 of the eighth transistor) of the second transistor may be located on a side of the first electrode T53 of the fifth transistor close to the second scanning signal line Gate2, wherein the second electrode T64 (also used as the second electrode T74 of the seventh transistor) of the sixth transistor may be located on a side of the first electrode T53 of the fifth transistor remote from the second scanning signal line Gate2.The first scanning signal line Gate1 and the second scanning signal line Gate2 are located between the two reset signal lines Reset, and the first scanning signal line Gate1 is located on a side of the second scanning signal line Gate2 close to the first electrode T43 of the fourth transistor.

[0250] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the reset signal line Reset located near the first scanning signal line Gate1 may include a signal main portion 22 extending along the first direction X and a signal connection block 23 extending along the second direction Y. The signal connection block 23 is located on a side of the signal main portion 22 near the first scanning signal line Gate1. An orthographic projection of the signal connection block 23 onto the substrate partially overlaps with the orthographic projection of the fifth via onto the substrate. The reset signal line Reset located near the first scanning signal line is connected to the control electrode of the first transistor via the fifth via.

[0251] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the shape of the reset signal line Reset located near the second scanning signal line Gate2 may be a line shape extending along the first direction X. An orthographic projection of the reset signal line Reset located near the second scanning signal line Gate2 onto the substrate partially overlaps with the orthographic projection of the ninth via onto the substrate. The reset signal line Reset located near the second scanning signal line Gate2 is connected to the control electrode of the seventh transistor via the ninth via.

[0252] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the shape of the main portion of the first scanning signal line Gate1 may be a line shape extending along the first direction X. An orthographic projection of the first scanning signal line Gate1 onto the substrate partially overlaps with the orthographic projection of the eighth via onto the substrate. The first scanning signal line Gate1 is connected to the control electrode (also used as the control electrode of the eighth transistor) of the fourth transistor via the eighth via.

[0253] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the shape of the main portion of the second scanning signal line Gate2 may be a line shape extending along the first direction X. An orthographic projection of the second scanning signal line Gate2 onto the substrate partially overlaps with the orthographic projection of the sixth via onto the substrate. The second scanning signal line Gate2 is connected to the control electrode of the second transistor via the sixth via.

[0254] In an exemplary embodiment, as in Fig. 28 and Fig. 29, the shape of the first electrode T23 (which is also used as the second electrode T84 of the eighth transistor) of the second transistor may represent a line shape extending along the second direction Y. An orthographic projection of the first electrode T23 (which is also used as the second electrode T84 of the eighth transistor) of the second transistor onto the substrate at least partially overlaps with the orthographic projections of the first via and the seventh via onto the substrate.The first electrode T23 (which is also used as the second electrode T84 of the eighth transistor) of the second transistor is connected through the first via to the first region (which is also used as the second region of the active layer of the eighth transistor) of the active layer of the second transistor and through the seventh via to the first electrode plate (which is also used as the control electrode of the third transistor) of the first capacitor.

[0255] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the first electrode T43 of the fourth transistor can be configured in the form of a block. An orthographic projection of the first electrode T43 of the fourth transistor onto the substrate at least partially overlaps with the orthographic projection of the second via onto the substrate. The first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor via the second via.

[0256] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the shape of the first electrode T53 of the fifth transistor may be a "T-shape" with irregular edges. An orthographic projection of the first electrode T53 of the fifth transistor onto the substrate may partially overlap with the orthographic projections of the third via, the light-emitting signal line, the second electrode plate of the first capacitor, and the third electrode plate of the second capacitor onto the substrate. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor via the third via.

[0257] In an exemplary embodiment, as in Fig. 28 and Fig. 29, the first electrodes T53 of the fifth transistors of adjacent subpixels located in the same row are connected to each other.

[0258] In an exemplary embodiment, as in Fig. 28 and Fig. As shown in Figure 29, the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) may form a block structure. An orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) onto the substrate may partially overlap with the orthographic projections of the fourth via and the light-emitting signal line onto the substrate. The second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) is connected to the second region (also used as the second region of the active layer of the seventh transistor) of the active layer of the sixth transistor through the fourth via.

[0259] In an exemplary embodiment, the two reset signal lines Reset, the first scanning signal line Gate1, and the second scanning signal line Gate2 may be provided with equal or unequal widths, and may be straight lines or broken lines. This can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure.

[0260] (7) Forming the pattern of a fifth insulating layer. In an exemplary embodiment, forming the pattern of a fifth insulating layer may include: depositing a fifth insulating film on the substrate on which the previous pattern was formed, patterning the fifth insulating film using a patterning process, and forming the fifth insulating layer covering the third conductive layer, wherein the fifth insulating layer is provided with a plurality of vias, as in Fig. 30 shown. Fig. 30 shows a schematic representation of the Fig. 8 provided display base plate after formation of the pattern of the fifth insulating layer.

[0261] In an exemplary embodiment, as in Fig. 30, the plurality of vias of the fifth insulating layer of each subpixel includes at least: a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0262] In an exemplary embodiment, an orthographic projection of the tenth via V10 onto the substrate lies within the boundary of the orthographic projection of the first electrode of the fourth transistor onto the substrate, wherein the surface of the first electrode of the fourth transistor is exposed by the tenth via V10, wherein the tenth via V10 is configured such that a subsequently formed data signal line is connected therethrough to the first electrode of the fourth transistor.

[0263] In an exemplary embodiment, an orthographic projection of the eleventh via V11 onto the substrate lies within the boundary of the orthographic projection of the first electrode of the fifth transistor onto the substrate, wherein the fourteenth via V14 exposes the surface of the first electrode of the fifth transistor, wherein the eleventh via V11 is configured such that a subsequently formed first power supply line is connected therethrough to the first electrode of the fifth transistor.

[0264] In an exemplary embodiment, an orthographic projection of the twelfth via V12 onto the substrate lies within the boundary of the orthographic projection of the third electrode plate of the second capacitor onto the substrate, wherein the third insulating layer and the fourth insulating layer in the twelfth via V12 are etched away such that the surface of the third electrode plate of the second capacitor is exposed. The twelfth via V12 is configured such that the subsequently formed first power supply line is connected therethrough to the third electrode plate of the second capacitor.

[0265] (8) Forming the pattern of a fourth conductive layer. In an exemplary embodiment, forming the pattern of a fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the previous pattern was formed, patterning the fourth conductive film using a patterning process, and forming the pattern of the fourth conductive layer as in Fig. 31 and Fig. 32 shown. Fig. 31 shows a schematic representation of the pattern of the fourth conductive layer of the Fig. 8 provided display base plate. Fig. 32 shows a schematic representation of the Fig. 8 after the pattern of the fourth conductive layer has been formed. In exemplary embodiments, the fourth conductive layer may be referred to as a second source-drain metal layer (SD2).

[0266] In an exemplary embodiment, as in Fig. 31 and Fig. 32, the pattern of the fourth conductive layer of each subpixel may include at least: the first power supply line VDD and the data signal line Data.

[0267] In an exemplary embodiment, as in Fig. 31 and Fig. As shown in Figure 32, the shape of the main portion of the first power supply line VDD may be a line shape extending along the second direction Y, wherein an orthographic projection of the first power supply line VDD onto the substrate overlaps with the orthographic projections of the eleventh via and the twelfth via onto the substrate. The first power supply line VDD is connected to the first electrode of the fifth transistor via the eleventh via and to the third electrode plate of the second capacitor via the twelfth via, thereby realizing the writing of the power supply signal to the first electrode of the fifth transistor and the third electrode plate of the second capacitor.Because the second electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor, the signals of the first electrode of the fifth transistor, the second electrode plate of the first capacitor and the third electrode plate of the second capacitor are therefore high-voltage power supply signals and have an equal potential.

[0268] In an exemplary embodiment, as in Fig. 31 and Fig. 32, the shape of the data signal line Data may be a line shape in which its main portion extends along the second direction Y, wherein an orthographic projection of the data signal line Data onto the substrate at least partially overlaps with the orthographic projections of the tenth via and the capacitor body portion of the third electrode plate of the second capacitor onto the substrate. The data signal line Data is connected to the first electrode of the fourth transistor via the tenth via. The data signal line Data is located in the fourth conductive layer, which can reduce the parasitic capacitance between the data signal line Data and the underlying conductive film layer, thereby reducing the load on the data signal line Data, which has a positive effect on charging time and power consumption.

[0269] In an exemplary embodiment, the data signal line Data and the first power supply line VDD may be provided with equal or unequal widths, and may be straight lines or broken lines. This can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between signal lines, and is not limited in this disclosure. For example, the width of the first power supply line VDD may be greater than the width of the data signal line Data.

[0270] (9) Forming the pattern of a planarization layer. In an exemplary embodiment, forming the pattern of a planarization layer may include coating a planarization film on the substrate on which the previous pattern was formed, patterning the planarization film using a patterning process, and forming the planarization layer covering the pattern of the fourth conductive layer.

[0271] Now the drive circuit layer of the Fig. 8 provided on the substrate. In a plane parallel to the display base plate, the drive circuit layer may include a plurality of pixel circuits. The drive circuit layer may further include: a first scanning signal line, a second scanning signal line, a light emission signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power supply line. In a plane perpendicular to the display base plate, the drive circuit layer may be arranged on the substrate, wherein the substrate may include a first flexible layer, a barrier layer, a conductive base layer, and a second flexible layer arranged stacked on top of one another.

[0272] The drive circuit layer may include a cap layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, and a planarization layer, which are sequentially disposed on the substrate. The cap layer may include a first electrode plate of the second capacitor. The semiconductor layer may include at least active layers of the first to eighth transistors, a second electrode plate of the second capacitor, a first initial signal line, and a second initial signal line. The first conductive layer may include at least one light-emitting signal line, control electrodes of the first to seventh transistors, and a first electrode plate of the first capacitor.The second conductive layer may include at least a second electrode plate of the first capacitor and a third electrode plate of the second capacitor. The third conductive layer may include at least a first scanning signal line, a second scanning signal line, and a reset signal line. The fourth conductive layer may include at least a data signal line and a first power supply line.

[0273] In an exemplary embodiment, one or more metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), may be used for the cover layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, wherein the layers may represent a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. One or more materials of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) may be used for the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, wherein the layers may represent a single-layer structure or a multi-layer composite structure.The first insulating layer may be referred to as the buffer layer, the second and third insulating layers may be referred to as the gate insulating layer (GI), the fourth insulating layer may be referred to as the interlayer insulating layer (ILD), and the fifth insulating layer may be referred to as the passivation layer (PVX). The planarization layer may be made of organic materials, such as resin.

[0274] In an exemplary embodiment, after the drive circuit layer is formed, a light-emitting structure layer is formed on the drive circuit layer. The manufacturing process of the light-emitting structure layer may include the following operations.

[0275] (10) Forming the pattern of an anode conductive layer. In an exemplary embodiment, forming the pattern of an anode conductive layer may include: depositing an anode conductive film on the substrate on which the previous pattern was formed, patterning the anode conductive film using a patterning process, and forming the anode conductive layer disposed on a second planarization layer, wherein the anode conductive layer comprises at least a plurality of anode patterns.

[0276] In exemplary embodiments, a single-layer structure, for example indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure, for example ITO / Ag / ITO, etc., is used for the anode conductive layer.

[0277] (11) Forming the pattern of a pixel definition layer. In an exemplary embodiment, forming the pattern of a pixel definition layer may include coating a pixel definition film on the substrate on which the above pattern was formed, patterning the pixel definition film using a patterning process, and forming the pixel definition layer, wherein the pixel definition layer is provided with each subpixel having a pixel opening, wherein the pixel definition film in the pixel opening is removed to expose the anode in that subpixel.

[0278] In an exemplary embodiment, the subsequent manufacturing process may include: first, forming an organic light-emitting layer using an evaporation or inkjet printing method; then, forming a cathode on the organic light-emitting layer; and then, forming an encapsulation structure layer, wherein the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked on top of one another.An inorganic material may be used for the first encapsulation layer and the third encapsulation layer, and an organic material may be used for the second encapsulation layer, wherein the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer so that it can be ensured that no external water vapor can penetrate into the light-emitting structure layer.

[0279] The display base plate provided in the embodiments of the present disclosure may be suitable for display products having any resolution.

[0280] An embodiment of the present disclosure also provides a driving method for a pixel circuit configured to drive the pixel circuit. The driving method for the pixel circuit provided by an embodiment of the present disclosure may include the following steps: Step 100: Under the control of a reset signal line, a first scanning signal line, and a second scanning signal line, a node control subcircuit provides the signal of a first initial signal line or a third node to a first node, the signal of a second initial signal line to a fourth node, and the signal of a data signal line to a second node.

[0281] Step 200: A memory subcircuit charges the second node when the first scan signal line has a valid level signal.

[0282] Step 300: Under the control of the first node and the second node, a driver subcircuit supplies a drive current to the third node. A light emission control subcircuit, under the control of a light emission signal line, supplies the signal of a first power supply line to the second node and the signal of the third node to the fourth node.

[0283] An embodiment of the present disclosure also provides a display device comprising a display base plate.

[0284] The display base plate is a display base plate provided in any of the above embodiments. The implementation principles and implementation effects of the display base plate are similar and will not be described again here.

[0285] In an exemplary embodiment, the display device may be any product or component with a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a laptop, a digital photo frame, a navigation device, etc.

[0286] In an exemplary embodiment, the display device further comprises a gate driver circuit. The gate driver circuit comprises a number K+2 of cascaded shift registers GOA, where K is the total number of rows of pixel circuits. The gate driver circuit may be located in a non-display area of ​​the display device.

[0287] In an exemplary embodiment, Fig. 33 is a schematic connection diagram of a gate driver circuit. As in Fig. 33, the first-stage shift register GOA(1) is connected to a reset signal line Reset connected to the first row of pixel circuits R(1); the second-stage shift register GOA(2) is connected to a first scanning signal line Gate1 connected to the first row of pixel circuits R(1) and a reset signal line Reset connected to the second row of pixel circuits R(2), respectively; the i-th stage shift register GOA(i) is connected to a second scanning signal line Gate2 connected to the i-2-th row of pixel circuits R(i-2), a first scanning signal line Gate1 connected to the i-1-th row of pixel circuits R(i-1), and a reset signal line Reset connected to the i-th row of pixel circuits R(i);the K+1-th stage shift register GOA(K+1) is connected to a second scanning signal line Gate2 connected to the K-1-th row of pixel circuits R(K-1), and to a first scanning signal line Gate1 connected to the K-th row of pixel circuits R(K), respectively; and the K+2-th stage shift register GOA(K+2) is connected to a second scanning signal line Gate2 connected to the K-th row of pixel circuits R(K), respectively, where i=3, 4, ..., K. In ; Fig. 33, only seven cascaded shift registers are shown, which does not mean that the gate driver circuit comprises only seven cascaded shift registers.

[0288] In the present disclosure, by connecting the gate drive circuit to the reset signal line, the first scanning signal line, and the second scanning signal line, respectively, the area occupied by the circuits located in the non-display region can be reduced, thus achieving a narrow frame. In the present disclosure, a high-frequency or even ultra-high-frequency display can be effectively realized by utilizing the pixel circuit, the structure of the display base plate, and the drive mode of the gate drive circuit, and by using the drive mode that combines the above pixel circuit and pixel layout design with the GOA.

[0289] The drawings in this disclosure refer only to the structures related to the embodiments of the disclosure. Other structures may refer to common designs.

[0290] In the drawings used to describe embodiments of the present disclosure, the thicknesses and dimensions of layers or microstructures are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it may be "directly on" or "directly under" the other element, or an intermediate element may be present therebetween.

[0291] Although the embodiments disclosed in the present disclosure are as described above, the contents are merely the embodiments used to facilitate understanding, not to limit the present disclosure. Anyone skilled in the art to which this disclosure relates may make any modifications and changes in the form and details of the embodiments without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of this disclosure must be determined by the scope defined by the appended claims.

Claims

[1] A pixel circuit configured to drive a light-emitting device to emit light, and comprising a node control subcircuit, a storage subcircuit, a driver subcircuit, and a light emission control subcircuit; wherein the node control subcircuit is electrically connected to a first node, a second node, a third node, a fourth node, a first scanning signal line, a second scanning signal line, a first initial signal line, a second initial signal line, a reset signal line, a data signal line, and a power supply line, respectively, and is configured to provide the signal of the first initial signal line or the third node to the first node, the signal of the second initial signal line to the fourth node, and the signal of the data signal line to the second node under the control of the reset signal line, the first scanning signal line, and the second scanning signal line; wherein the storage subcircuit is electrically connected to the second node and the first power supply line, respectively, and is configured to charge the second node when the first scan signal line has a valid level signal; wherein the driver subcircuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to provide a drive current to the third node under the control of the first node and the second node; wherein the light emission control subcircuit is electrically connected to a light emission signal line, the first power supply line, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the light emission signal line; wherein a first electrode of the light-emitting device is connected to the fourth node and a second electrode of the light-emitting device is connected to a second power supply line. [2] The pixel circuit according to claim 1, wherein a period in which the signal of the reset signal line has a valid level signal comprises a first period and a second period, the first period being before the second period; wherein a period in which the signal of the first scanning signal line has a valid level signal comprises a third period and a fourth period, the third period being before the fourth period; wherein a period in which the signal of the second scanning signal line has a valid level signal comprises a fifth period and a sixth period, the fifth period being before the sixth period, the second period at least partially overlapping with the third period and the fourth period at least partially overlapping with the fifth period;wherein the signal of the light emission signal line has an invalid level signal when the signals of the reset signal line, the first scanning signal line, and the second scanning signal line have valid level signals, and the signals of the reset signal line, the first scanning signal line, and the second scanning signal line have invalid level signals when the signal of the light emission signal line has a valid level signal; [3] The pixel circuit of claim 1, wherein the node control subcircuit comprises a reset subcircuit, a write subcircuit, a compensation subcircuit, and an energy storage subcircuit; wherein the reset subcircuit is electrically connected to the reset signal line, the first initial signal line, the second initial signal line, the first node, and the fourth node, respectively, and is configured to provide the signal of the first initial signal line to the first node and the signal of the second initial signal line to the fourth node under the control of the reset signal line; wherein the write subcircuit is electrically connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the signal of the data signal line to the second node under the control of the first scan signal line; wherein the compensation subcircuit is electrically connected to each of the second scanning signal line, the first node, and the third node and is configured to provide the signal of the third node to the first node under the control of the second scanning signal line; wherein the energy storage subcircuit is electrically connected to the first node and the first power supply line, respectively, and is configured to store the voltage difference of the signal between the first node and the first power supply line. [4] The pixel circuit according to claim 3, wherein the reset sub-circuit is further connected to the first scanning signal line and is configured to provide the signal of the first initial signal line to the first node and the signal of the second initial signal line to the fourth node under the control of the reset signal line and the first scanning signal line. [5] The pixel circuit of claim 3, wherein the reset subcircuit comprises a first transistor and a seventh transistor, wherein the write subcircuit comprises a fourth transistor, wherein the compensation subcircuit comprises a second transistor, and wherein the energy storage subcircuit comprises a first capacitor; wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node. [6] The pixel circuit of claim 4, wherein the reset subcircuit comprises a first transistor, a seventh transistor, and an eighth transistor, wherein the write subcircuit comprises a fourth transistor, wherein the compensation subcircuit comprises a second transistor, and wherein the energy storage subcircuit comprises a first capacitor; wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to a first electrode of the eighth transistor; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein a control electrode of the eighth transistor is electrically connected to the first scanning signal line and a second electrode of the eighth transistor is electrically connected to the first node; wherein one end of the first capacitor is electrically connected to the first node and the other end of the first capacitor is electrically connected to the first power supply line. [7] The pixel circuit of claim 1, wherein the memory subcircuit comprises a second capacitor; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node. [8] The pixel circuit of claim 1, wherein the node control subcircuit comprises a first transistor, a second transistor, a fourth transistor, a seventh transistor, and a first capacitor, wherein the storage subcircuit comprises a second capacitor, wherein the driver subcircuit comprises a third transistor, and wherein the light emission control subcircuit comprises a fifth transistor and a sixth transistor; wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the fifth transistor is electrically connected to the light emission signal line, a first electrode of the fifth transistor is electrically connected to the first power supply line, and a second electrode of the fifth transistor is electrically connected to the second node; wherein a control electrode of the sixth transistor is electrically connected to the light emission signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the fourth node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node. [9] The pixel circuit of claim 1, wherein the node control subcircuit comprises a first transistor, a second transistor, a fourth transistor, a seventh transistor, an eighth transistor, and a first capacitor; wherein the storage subcircuit comprises a second capacitor; wherein the driver subcircuit comprises a third transistor; and wherein the light emission control subcircuit comprises a fifth transistor and a sixth transistor; wherein a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to a first electrode of the eighth transistor; wherein a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; wherein a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; wherein a control electrode of the fifth transistor is electrically connected to the light emission signal line, a first electrode of the fifth transistor is electrically connected to the first power supply line, and a second electrode of the fifth transistor is electrically connected to the second node; wherein a control electrode of the sixth transistor is electrically connected to the light emission signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the fourth node; wherein a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; wherein a control electrode of the eighth transistor is electrically connected to the first scanning signal line and a second electrode of the eighth transistor is electrically connected to the first node; wherein one end of the first capacitor is electrically connected to the first power supply line and the other end of the first capacitor is electrically connected to the first node; wherein one end of the second capacitor is electrically connected to the first power supply line and the other end of the second capacitor is electrically connected to the second node. [10] A display base plate comprising: a substrate and a drive circuit layer and a light-emitting structure layer sequentially arranged on the substrate, wherein the drive circuit layer comprises the pixel circuit according to any one of claims 1 to 9, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of reset signal lines, a plurality of first power supply lines and a plurality of data signal lines, wherein the light-emitting structure layer comprises a light-emitting device. [11] The display base plate according to claim 10, wherein the drive circuit layer comprises: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially stacked on the substrate, wherein the pixel circuit comprises: a plurality of transistors, a first capacitor, and a second capacitor, the first capacitor and the second capacitor each comprising a first electrode plate and a second electrode plate; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors and the first electrode plate of the second capacitor; wherein the first conductive layer comprises at least: a reset signal line, a light emission signal line, control electrodes for the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: a second initial signal line, the second electrode plate of the first capacitor, and the second electrode plate of the second capacitor; wherein the third conductive layer comprises at least: a first scanning signal line and a second scanning signal line; wherein the fourth conductive layer comprises at least: a first initial signal line, a first power supply line, and a data signal line. [12] The display base plate according to claim 11, wherein the pixel circuit comprises first to seventh transistors, wherein the active layer of each of the transistors may include a first region, a second region, and a channel region located between the first region and the second region; wherein the length of the first region of the active layer of the third transistor along a first direction is greater than the length of the second region of the active layer of the third transistor along the first direction, wherein the first region of the active layer of the third transistor is in turn used as the first electrode plate of the second capacitor. [13] The display base plate according to claim 11, wherein, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor, and the second electrode plate of the second capacitor of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row; wherein the length of the second electrode plate of the first capacitor along a second direction is smaller than the length of the second electrode plate of the second capacitor along the second direction, the first direction and the second direction intersecting. [14] The display base plate according to claim 13, wherein the second electrode plate of the second capacitor comprises a capacitor body portion extending along the second direction, a first connection block and a second connection block extending along the first direction; wherein the first connection block and the second connection block are each connected to the capacitor body portion, wherein the first connection block and the second connection block are arranged parallel to each other and are located on a side of the capacitor body portion facing away from the second electrode plate of the first capacitor; wherein an orthographic projection of the capacitor body portion onto the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the first connection block onto the substrate partially overlaps with an orthographic projection of the active layers of the second transistors located between the control electrodes of the second transistors onto the substrate, and wherein an orthographic projection of the second connection block onto the substrate partially overlaps with an orthographic projection of the active layer of the third transistor onto the substrate; wherein, for the same pixel circuit, the second electrode plate of the first capacitor is connected to the capacitor body portion, and wherein the second connection block of the pixel circuit located in the Nth column is connected to the second electrode plate of the first capacitor of the pixel circuit located in the N+1th column in the same row. [15] The display base plate according to claim 11, wherein the length of the first power supply line along the first direction is greater than the length of the data signal line along the first direction and greater than the length of the first initial signal line along the first direction, and wherein the length of the first initial signal line along the first direction is greater than the length of the data signal line along the first direction. [16] The display base plate according to claim 10, wherein the drive circuit layer comprises a cover layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer, wherein the pixel circuit comprises a plurality of transistors, a first capacitor, and a second capacitor, wherein the first capacitor comprises a first electrode plate and a second electrode plate, and the second capacitor comprises a first electrode plate, a second electrode plate, and a third electrode plate; wherein the cover layer comprises at least: the first electrode plate of the second capacitor, wherein the cover layer is configured to transmit a high-voltage power supply signal; wherein the semiconductor layer comprises at least: active layers of a plurality of transistors, the second electrode plate of the second capacitor, a first initial signal line, and a second initial signal line; wherein the first conductive layer comprises at least: a light emission signal line, control electrodes of the plurality of transistors, and the first electrode plate of the first capacitor; wherein the second conductive layer comprises at least: the second electrode plate of the first capacitor and the third electrode plate of the second capacitor; wherein the third conductive layer comprises at least: two reset signal lines, a first scanning signal line, and a second scanning signal line; wherein the fourth conductive layer comprises at least: a first power supply line and a data signal line. [17] The display base plate according to claim 16, wherein the plurality of transistors comprise first to eighth transistors, wherein the cap layer further comprises a first cap structure, a second cap structure, a first cap connection structure, a second cap connection structure, a third cap connection structure, and a fourth cap connection structure, wherein the first electrode plate of the second capacitor is again used as the second cap structure; wherein the first cover connection structure and the second cover structure are each located on two opposite sides of the first cover structure and are connected to the first cover structure, wherein the second cover connection structure is located on a side of the second cover structure facing away from the first cover structure and is connected to the second cover structure, wherein the third cover connection structure and the fourth cover connection structure are each located on the other two opposite sides of the first cover structure, wherein the third cover connection structure is connected to the second cover structure and the fourth cover connection structure is connected to the first cover structure; wherein an orthographic projection of the first capping structure onto the substrate at least partially overlaps with an orthographic projection of the channel region of the active layer of the third transistor onto the substrate, wherein an orthographic projection of the second capping structure onto the substrate at least partially overlaps with an orthographic projection of the second electrode plate of the second capacitor onto the substrate, wherein an orthographic projection of the third capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the first transistor onto the substrate, and wherein an orthographic projection of the fourth capping connection structure onto the substrate at least partially overlaps with an orthographic projection of the active layer of the seventh transistor onto the substrate. [18] The display base plate according to claim 17, wherein the second cover structure of the N-th column of subpixels in a row is located on a side of the first cover structure of the N-th column of subpixels in the same row that is close to the first cover structure of the N+1-th column of subpixels, the first cover connection structure of the N-th column of subpixels in a row is located on a side of the first cover structure of the N-th column of subpixels in the same row that is close to the first cover structure of the N-1-th column of subpixels and is connected to the fourth cover connection structure of the N-1-th column of subpixels, the second cover connection structure of the N-th column of subpixels in a row is connected to the first cover connection structure of the N+1-th column of subpixels in the same row;wherein the third cover connection structure of the M-th row of subpixels in a column is located on a side of the first cover structure 11 of the M-th row of subpixels in the same column that is close to the first cover structure of the M-1-th row of subpixels and is connected to the fourth cover connection structure of the M-1-th row of subpixels, wherein the fourth cover connection structure of the M-th row of subpixels in a column is located on a side of the first cover structure of the M-th row of subpixels in the same column that is close to the first cover structure of the M+1-th row of subpixels and is connected to the fifth cover connection structure of the M+1-th row of subpixels; [19] The display base plate according to claim 16, wherein, for the same subpixel, the second electrode plate of the first capacitor and the third electrode plate of the second capacitor are connected to each other; wherein, for subpixels in the same row, the third electrode plate of the second capacitor of the Nth column of subpixels is located on a side of the second electrode plate of the first capacitor of the Nth column of subpixels close to the second electrode plate of the first capacitor of the N+1th column of subpixels and is connected to the second electrode plate of the first capacitor of the N+1th column of subpixels; wherein the length of the second electrode plate of the first capacitor along the second direction is smaller than the length of the third electrode plate of the second capacitor along the second direction. [20] A display device comprising the display base plate according to any one of claims 10 to 19. [21] The display device according to claim 20, further comprising a gate drive circuit, wherein the gate drive circuit comprises a number K+2 of cascaded shift registers, where K is the total number of rows of pixel circuits; wherein the first-stage shift register is connected to a reset signal line connected to the first row of pixel circuits; the second-stage shift register is connected to a first scan signal line connected to the first row of pixel circuits and to a reset signal line Reset connected to the second row of pixel circuits, respectively;the shift register of the i-th stage is respectively connected to a second scanning signal line connected to the i-2-th row of pixel circuits, to a first scanning signal line connected to the i-1-th row of pixel circuits, and to a reset signal line Reset connected to the i-th row of pixel circuits; the shift register of the K+1-th stage is respectively connected to a second scanning signal line connected to the K-1-th row of pixel circuits and to a first scanning signal line connected to the K-th row of pixel circuits; and the shift register of the K+2-th stage is respectively connected to a second scanning signal line connected to the K-th row of pixel circuits, where i=3, 4, ..., K; [22] A method of driving a pixel circuit configured to drive the pixel circuit according to any one of claims 1 to 9, the method comprising: Providing the signal from the first initial signal line or the third node to the first node, the signal from the second initial signal line to the fourth node and the signal from the data signal line to the second node through the node control subcircuit under the control of the reset signal line, the first scan signal line and the second scan signal line; loading the second node by the memory subcircuit when the first scan signal line has a valid level signal; Providing the drive current to the third node by the drive subcircuit under the control of the first node and the second node; Providing the signal from the first power supply line to the second node and the signal from the third node to the fourth node through the light emission control subcircuit under the control of the light emission signal line.

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