Methods and devices for image segmentation on small datasets

Abstract

Methods, apparatus, and systems for semantic image segmentation using small data sets are disclosed. An example apparatus comprises: at least one memory, machine-readable instructions, and processor circuitry for instantiating or executing the machine-readable instructions to identify a gradient vector flow associated with an input image and / or generate a spatial feature map based on pixels of the input image using a two-stream neural network architecture and / or generate a field feature map based on the gradient vector flow using the two-stream neural network architecture and / or fuse the spatial feature map and the field feature map and / or output a segmented image of the input image based on the fused feature map.

Description

FIELD OF THE DISCLOSUREThis disclosure relates generally to image data processing, and more particularly to methods, systems, and apparatus for image segmentation on small data sets.BACKGROUNDImage segmentation focuses on reducing a digital image into different subgroups (e.g., image segments) to reduce the complexity of the image to enable further processing and / or evaluation. Image segmentation techniques may include threshold based segmentation, edge based segmentation, region based segmentation, cluster based segmentation, and / or artificial neural network based segmentation.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is an example environment in which image segmentation including image segmentation circuitry may be performed. FIG. 2 is an exemplary basic architecture of a UNET convolutional neural network used as part of the image segmentation circuit of FIG. 1. FIG. 3 is an exemplary visualization of the relationship between gradient vector flow (GVF) and pixel motion analysis performed as part of image segmentation using the image segmentation circuit of FIG. 1. FIG. 4 is an example of an output associated with using different neural networks to image segment a cardiac diagnostic-based imaging dataset, including the results associated with image segmentation performed using a two-stream network of the image segmentation circuit of FIG. 1. FIG. 5 is a block diagram of an example implementation of the image segmentation circuit of FIG. 1. FIG. 6 is a flow diagram illustrating machine readable instructions executable to implement the example image segmentation circuit of FIG. 1 to segment image data in accordance with teachings disclosed herein. FIG. 7 is a flow diagram illustrating machine readable instructions executable to implement the example image segmentation circuit of FIG. 1 to generate spatial feature maps and field feature maps in accordance with teachings disclosed herein. FIG. 8 is a flowchart illustrating example machine readable instructions and / or operations executable by an example processor circuit to train a neural network to determine RGB and / or gradient vector flow (GVF) weights. FIG. 9 is a block diagram of an example processing platform structured to execute the instructions of FIG. 5 to implement the example image segmentation circuit of FIG. 1 to perform image segmentation according to teachings disclosed herein. FIG. 10 is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and / or the example operations of FIG. 8 to implement the example first data processing system of FIG. 5. FIG. 11 is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and / or the example operations of FIG. 8 to implement the example second data processing system of FIG. 5. FIG. 12 is a block diagram of an example implementation of the processor circuit of FIGS. 9, 10, and / or 11. FIG. 13 is a block diagram of another example implementation of the processor circuit of FIGS. 9, 10, and / or 11. FIG. 14 is a block diagram of an example software distribution platform (e.g., one or more servers) for distributing software (e.g., software corresponding to the example machine readable instructions of FIGS. 6, 7, and / or 8) to client devices associated with end users and / or consumers (e.g., for licenseing, sale, and / or use), retailers (e.g., for sale, resale, license, and / or underlization), and / or original equipment manufacturers (OEM) (e.g., for inclusion in products to be distributed to retailers and / or other end users, such as direct customers).In general, throughout the one or more drawings and the accompanying written description, the same reference numerals are used to refer to the same or similar parts. The figures are not to scale. Unless specifically stated otherwise, descriptors such as "first / r / s", "second / r / s", "third / r / s", etc. are used herein without any meaning attributable to or otherwise indicating any meaning of priority, physical order, arrangement in a list and / or order in any way, but are used merely as labels and / or arbitrary labels to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor "first / r / s" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to with a different descriptor, such as "second / r / s" or "third / r / s.". In such cases, it will be appreciated that such descriptors are used merely to uniquely identify those elements that might otherwise share the same label, for example.As used herein, the term "in communication," including variations thereof, encompasses direct communication and / or indirect communication via one or more intermediary components, and does not require direct physical (e.g., wired) communication and / or constant communication, but rather additionally includes targeted communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.As used herein, "processor circuit" is defined to include (i) one or more special purpose electrical circuitry structured to perform one or more special operations and one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general purpose semiconductor-based circuitry programmable with instructions to perform special operations and one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuits include programmable microprocessors, field programmable gate arrays (FPGA) that can instantiate instructions, central processor units (CPU), graphics processor units (GPU), digital signal processors (DSP), XPU, or microcontrollers, and integrated circuits such as application specific integrated circuits (ASIC). For example, an XPU may be implemented by a heterogeneous data processing system that includes multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and / or a combination thereof) and one or more application programming interfaces (APIs) that may assign one or more computing tasks to one or more of the multiple types of the processing circuitry best suited for executing the one or more computing tasks.DETAILED DESCRIPTIONSemantic image segmentation is a highly relevant task in visual inspection systems, medical image analyses, robot perception and / or image compression. For example, image segmentation may be used to partition an image into multiple segments. In some examples, image segmentation is considered an essential component in digital image processing used to separate the image into different segments and / or special areas. Advances in image segmentation can be attributed to deeper and larger convolutional neural network (CNN) models that can be used to learn a hierarchical representation of input data. Training deeper and larger CNN models, however, requires training datasets of high quality and / or large scale size without the problems associated with overfitting may occur. Moreover, for some applications such as medical image analyses and / or defect inspection systems, it may be difficult to build large-scale datasets because the imaging data is acquired by dedicated sensors. For example, compared to wild type images, data captured by dedicated sensors is rare, making such data acquisition expensive (e.g., finding wafer-based defects using the e-beam wafer defect inspection system). Using data sets that are expensive to acquire results in increased costs associated with constructing large-scale training data sets. As a result, the segmentation performed by using CNN trained on smaller datasets is lower compared to a segmentation performed based on the training by using large-scale datasets (e.g., when natural images, etc., are used).In some examples, transfer learning may be used to enable training of lower models with smaller records. Transfer learning is a method for machine learning in which a model developed for a task is reused as a starting point for a model at a second task. For example, deep learning transfer learning may be used to implement pre-trained models as a starting point for computer vision tasks and / or natural language processing tasks given the large number of resources (e.g., computational and / or time-based resources) needed to develop neural network models in such tasks. In some examples, pre-trained models (e.g., VGG16, Resnet50 models trained on ImageNet) may be widely used in a backbone of the image segmentation task. However, since such deeper models are trained on ImageNet (e.g., the images are all natural images), the characteristics of such images differ from the data acquired by dedicated imaging systems.Methods and apparatus for image segmentation on small data sets are disclosed herein. For example, a two-stream UNET architecture may be used for image segmentation with a small dataset. In examples disclosed herein, the UNET architecture is an encoding-decoding CNN model used to generate one or more spatial feature maps and / or field feature maps for automatic segmentation at a given input image. In examples disclosed herein, the two-stream network includes one spatial stream (e.g., associated with generating a spatial feature map), and the other is referred to as a vector stream (e.g., associated with generating a field feature map). For example, input of the spatial stream may include an intensity value of the pixels (e.g., either RGB or grayscale level), and input of the vector field may include a gradient vector flow (GVF) because GVF is considered to be one of the best low-level pixel-wise features and greatly enhances original active contour models acting as an external force. In examples disclosed herein, the spatial feature map and the field feature map are merged to generate an image segmentation output.Although examples disclosed herein are discussed in connection with image segmentation, disclosed examples are more generally applicable to image analysis. Thus, for example, although examples disclosed herein relate to a UNET-based architecture, examples disclosed herein are more generally applicable to a neural network architecture. Examples disclosed herein apply, for example, to any other type of image segmentation task and / or image analysis task.FIG. 1 is example environment 100 in which image segmentation including image segmentation circuit 110 may be performed. In the example of FIG. 1, environment 100 includes input image 105. The features of the input image 105 may include one or more example pixel intensity values 115 (e.g., either RGB or grayscale level) and example gradient vector flow (GVF) 120. In the example of FIG. 1, the one or more pixel intensity values 115 and the GVF 120 may serve as input to a UNET architecture of the image segmentation circuit 110 to generate spatial feature map 125 and / or field feature map 130, as described in more detail in connection with FIG. 5. In some examples, the image segmentation circuit 110 generates a spatial feature map 125 by using the one or more pixel intensity values 115 by applying one or more filters and / or feature detectors to the input image or feature map output of the previous layers of the neural network (e.g., associated with the UNET CNN architecture). In some examples, the image segmentation circuit 110 generates a field feature map 130 by using the GVF 120, as described in more detail in connection with FIG. 5. For example, the GVF 120 represents a vector field generated by a process that smoothes and diffuses an input vector field, thereby generating a vector field from images pointing at object edges from a distance. For example, during the process of image segmentation, the position of object edges may aid in segmenting objects by using active contours that are attracted to edges. In the example of FIG. 1, the image segmentation circuit 110 merges the spatial feature map 125 and the field feature map 130 by using fusion step 135 to obtain final image segmentation result 140.In the example of FIG. 1, the backbone of each stream (e.g., a spatial stream and a vector stream) of the two-stream UNET architecture for image segmentation using small data sets is a basic UNET model, which will be described in more detail in connection with FIG. 2. For example, spatial feature maps and field feature maps 125, 130 are generated by each of the UNET-based architectures, where the spatial feature map 125 is generated by a CNN having a base UNET architecture by using RGB values for images as input, where weights of the RGB stream are learned during training, as described in more detail in connection with FIGS. 5 and 8. Moreover, the field feature map 130 may be generated by another CNN with a basic UNET architecture, wherein GVF values of the input image 105 serve as input, wherein weights of the GVF stream are learned during training, as described in more detail in connection with FIGS. 5 and 8. In particular, the two-stream network shown in the example of FIG. 1 may be applied in applications associated with action detection in videos. In some examples, the two-stream network may be associated with a human-based visual cortex that includes a ventral stream and a dorsal stream. For example, similar to the two-stream network, the ventral stream deals with object identity (e.g., object recognition), while the dorsal stream deals with spatial relationships without consideration of semantics (e.g., motion analysis).FIG. 2 is an example base architecture 200 of a UNET convolutional neural network used as part of the image segmentation circuit 110 of FIG. 1. In particular, the UNET architecture 200 enables the segmentation of images of specific sizes (e.g., 512x512) that can be calculated within a short time frame by using a graphics processing unit (GPU). For example, UNET architecture 200 uses the concept of full convolutional networks, capturing both the features of the context and the location. For example, UNET architecture 200 uses successive contract layers immediately followed by upsampling operators to achieve higher resolution outputs on the input images. As shown in the example of FIG. 2, the UNET architecture is a U-shaped structure that forms a complete convolutional network with an initial contract path followed by an expanding path. For example, the flow of image processing through architecture 200 may be represented using various operations, including input 205, output 210, pooling 215 (e.g., max. Pooling 2*2), Up-convolution 220 (e.g., Up-convolution 2*2), Folds 225, 230 (e.g., Convolution 3*3, Convolution 1*1, etc.), and Copy and Cut processing step 235. In the example of FIG. 2, architecture 200 includes operations associated with an input image passed through the model beginning with input image tile 240, followed by convolutional layers with a rectified linear unit (ReLU) activation function. The architecture 200 includes multi-channel feature maps 245, 250, 255, 260, 265, 270, 275 having different numbers of channels associated with each of the feature maps. For example, image size may be reduced (e.g., from 572x572 to 568x568) by using folds that reduce overall dimensionality. In addition, the architecture 200 may include an encoding block (e.g., by a constant reduction in image size by using max. In addition, the method of achieving pooling layers and an increasing number of filters present in the coding architecture) may include a decoding block (e.g., including a decreasing number of filters with gradual upsampling in the layers). Additionally, the architecture 200 includes skip connections to preserve any loss of previous layers and allow for faster model convergence, resulting in final output segmentation map 245.FIG. 3 is an example visualization 300 of the relationship between gradient vector flow (GVF) 305 and motion analysis associated with one or more pixels 310, 312 that is performed as part of image segmentation by using the image segmentation circuit 110 of FIG. 1. In the example of FIG. 3, each pixel 310, 312 of an image may be considered a component of an object, where pixel-based motion patterns are associated with forces pushing the objects along a direction of a given force. For example, the pixels 310, 312 may move stepwise under the GVF 305 from a current position to boundary 315 of the object. In particular, the aim of image segmentation is to identify boundaries of the objects. As such, GVF-based patterns may represent how components move to the boundary 315 of a given object, so features from the GVF patterns may be used to derive boundaries in a given input image. As described in connection with FIG. 1, the field feature map 130 includes temporal information that can be used to track the movement of the pixels 310, 312. For example, the pixel motion over time (e.g., t=1, t=2, etc.) may be tracked for different pixels 310, 312 identified in the input image 105 (e.g., a 0, a 2, a 3, etc.). For example, a first pixel 310 may move in the following order: a0→a1→a2→a3at time t=0, t=1, t=2, and t=3, respectively, while a second pixel 312 may move from b0→b1→b2→b3at time t=0, t=1, t=2, and t=3, respectively.FIG. 4 is an example of output 400 associated with using different neural networks to image segment a cardiac diagnostic-based imaging dataset, including the results associated with image segmentation performed using a two-stream network of the image segmentation circuit 110 of FIG. 1. In the example of FIG. 4, methods and apparatus disclosed herein may be used to perform image segmentation associated with an automated cardiac diagnostic dataset. For example, magnetic resonance imaging (MRI) datasets acquired from different patients may be used as part of an image segmentation performance test. For example, each patient scan may be labeled with ground truth indicia for a left ventricle (LV), a right ventricle (RV), and / or a myocardium (MYO). Various example methods of image segmentation 405 (e.g., R50 UNET, R50 ATTNUNET, VIT-CUP, R50 VIT, TRANSUNET, SWIN-UNET, MT-UNET, etc.) may be compared to a two-stream network-based image segmentation method disclosed in the examples described herein. For example, image segmentation of cardiac-based data sets may be evaluated using a measure of a dice similarity coefficient (e.g., average dice percentage 410). The dice similarity coefficient is a spatial overlap index and a reproducibility validation metric that can be used to evaluate a segmentation model. The dice coefficient may represent a measure of overlap between two masks (e.g., true mask versus predicted mask), where 1 indicates perfect overlap while 0 indicates no overlap. For example, a mask corresponds to a classification of image pixels as either 1 or 0, where 1 corresponds to a presence of the mask and 0 corresponds to a absence of the mask. Such masking enables identification of one or more specific areas and / or one or more objects of an image. As such, a true mask corresponds to an accurate and / or verified representation of the positions of the region and / or object, whereas a predicted mask corresponds to the predicted position of the region and / or object. In examples disclosed herein, the predicted mask corresponds to an area where a cardiac area is predicted to be based on image segmentation, whereas the true mask corresponds to a cardiac area that has been verified to include the area of interest (e.g., the right ventricle, etc.). As such, prediction accuracy may be determined by comparing the true mask to the predicted mask (e.g., where a greater alignment of the true mask and the predicted mask indicates a greater prediction accuracy). In the example of FIG. 4, dice similarity coefficients are included for different cardiac regions (e.g., RV 415, MYO 420, LV 425), showing a higher average dice overall coefficient (90.90%) when using the two-stream network image segmentation method disclosed herein compared to other existing image segmentation techniques.FIG. 5 is a block diagram of an example implementation of the image segmentation circuit 110 of FIG. 1 The example image segmentation circuit 110 of FIG. 5 may be instantiated by processor circuitry, such as a central processing unit executing instructions (e.g., creating an instance, creating for any amount of time, materializing, implementing, etc.). Additionally or alternatively, the image segmentation circuit 110 of FIG. 5 may be instantiated by an ASIC or an FPGA (e.g., creating an instance, creating for any amount of time, materializing, implementing, etc.) structured to perform operations corresponding to the instructions. It will be appreciated that some or all of the circuits of FIG. 5 may thus be instantiated at the same time or at different times. For example, some or all of the circuits may be instantiated in one or more threads executing concurrently on hardware and / or in series on hardware. Moreover, in some examples, some or all of the circuits of FIG. 5 may be implemented by microprocessor circuits executing instructions to implement one or more virtual machines and / or containers.In the illustrated example, the image segmentation circuit 110 includes image data receiving circuit 505, vector field identification circuit 510, spatial feature map generation circuit 515, field feature map generation circuit 520, data fusion initialization circuit 525, segmented image identification circuit 530, and data storage 535. In some examples, the data storage 525 is located outside the image segmentation circuit 110 at a location accessible by the image segmentation circuit 110. In the example of FIG. 5, the image data receiving circuit 505, the vector field identifying circuit 510, the spatial feature map generating circuit 515, the field feature map generating circuit 520, the data fusion initializing circuit 525, the segmented image identifying circuit 530, and / or the data storage 535 are in communication using example bus 540.The image data receiving circuit 505 receives image data based on the input image 105 of FIG. 1, for example, the image data receiving circuit 505 identifies image-based information, such as one or more pixel intensity values 115 (e.g., either RGB or grayscale level). In some examples, the image data receiver circuit 505 identifies a size of the input image 105. For example, in image segmentation, the input image 105 may be partitioned into multiple segments to simplify representation of the image and reduce the complexity of image analysis (e.g., identification of objects within the image, etc.). In some examples, each pixel in the input image 105 may be assigned a label, such that pixels with the same label may be characterized as pixels sharing certain characteristics.The vector field identifying circuit 510 identifies the gradient vector flow (GVF) 120 associated with the input image 105. For example, the GVF 120 represents a vector diffusion-based model that can be used to calculate the image gradient in a specified direction. In some examples, GVF may be used to propagate the gradient vector from the object boundary to the rest of the image. As described in connection with FIG. 3, GVF-based patterns may represent how components move to the boundary 315 of FIG. 3 of a given object, such that features from the GVF patterns may be used to derive boundaries in the input image 105.Spatial feature map generation circuit 515 generates spatial feature map 125 of FIG. 1. for example, spatial feature map generation circuit 515 includes the spatial stream (e.g., associated with generating a spatial feature map) as part of the two-stream network of FIG. 1. For example, spatial feature map generation circuit 515 generates spatial feature map 125 using the convolutional neural network architecture described in connection with FIG. 2. The input of the spatial stream may include an intensity value of the pixels (e.g., either RGB or grayscale level) identified by using the image data receiving circuit 505. For example, the spatial feature map generation circuit 515 generates the spatial feature map 125 by using RGB values for images as input, wherein weights of the RGB stream are learned during training. For example, spatial feature map generation circuit 515 executes one or more neural network models to determine weights associated with the RGB stream.While in the example of FIG. 5, the spatial feature map generation circuit 515 executes a neural network model, the spatial feature map generation circuit 515 may use other types of neural network models to identify weights associated with the RGB stream that are used to generate the spatial feature map 125 of FIG. 1. As shown in FIG. 5, first data processing system 550 trains a neural network to generate a spatial UNET map generation model based on training data associated with one or more RGB value inputs. The example first data processing system 550 may include neural network processor 560. In examples disclosed herein, neural network processor 560 implements a neural network. The example first data processing system 550 of FIG. 5 includes neural network trainer 558. The example neural network trainer 558 of FIG. 5 performs training of the neural network implemented by the neural network processor 560. The example first data processing system 550 of FIG. 3 includes training controller 556. The training controller 556 instructs the neural network trainer 558 to perform training of the neural network based on training data 554. In the example of FIG. 5, the training data 554 used by the neural network trainer 558 to train the neural network is stored in database 552. The example database 552 of the illustrated example of FIG. 5 is implemented by any memory, storage device, and / or storage disk for storing data, such as flash memory, magnetic media, optical media, etc. Moreover, the data stored in the example database 552 may be in any data format, such as binary data, comma-limited data, tab-limited data, Structured Query Language (SQL) structures, image data, etc. Although the illustrated example database 552 is illustrated as a single element, the database 552 and / or any other data storage elements described herein may be implemented by any number and / or types of memories.In the example of FIG. 5, the training data 554 may include data representing the input image 105 (e.g., RGB values). The neural network trainer 558 may train the neural network implemented by the neural network processor 560 by using the training data 554. Based on the RGB values in the training data 554, the neural network trainer 558 trains the neural network to identify RGB weights associated with image data received by the image segmentation circuit 110. One or more spatial UNET generation models 564 are generated as a result of neural network training. The one or more spatial UNET Figure 564 generation models are stored in database 562. The databases 552, 562 may be the same storage device or different storage devices. Spatial feature map generation circuit 515 executes the one or more spatial UNET generation models 564 to generate spatial feature map 125 of FIG. 1.The field feature map generation circuit 520 generates the field feature map 130 of FIG. 1, for example, the field feature map generation circuit 520 includes the vector stream (e.g., associated with the generation of a field feature map) as part of the two-stream network of FIG. 1. For example, the field feature map generation circuit 520 generates the field feature map 130 by using the convolutional neural network architecture described in connection with FIG. 2. The input of the vector stream may include the GVF identified by using the vector field identification circuit 510. For example, the field feature map generation circuit 520 generates the field feature map 130 by using GVF values for images as input, wherein weights of the GVF stream are learned during training. For example, the field feature map generation circuit 520 executes one or more neural network models to determine weights associated with the GVF stream.While in the example of FIG. 5, the field feature map generation circuit 520 executes a neural network model, the field feature map generation circuit 520 may use other types of neural network models to identify weights associated with the GVF stream that are used to generate the field feature map 130 of FIG. 1. As shown in FIG. 5, second data processing system 570 trains a neural network to generate a generation model for UNET field mapping based on training data associated with one or more GVF value inputs. The example second data processing system 570 may include neural network processor 580. In examples disclosed herein, neural network processor 580 implements a neural network. The example second data processing system 570 of FIG. 5 includes neural network trainer 578. The example neural network trainer 578 of FIG. 5 performs training of the neural network implemented by the neural network processor 580. The example second data processing system 570 of FIG. 5 includes training controller 576. The training controller 576 instructs the neural network trainer 578 to perform training of the neural network based on training data 574. In the example of FIG. 5, the training data 574 used by the neural network trainer 578 to train the neural network is stored in database 572. The example database 572 of the illustrated example of FIG. 5 is implemented by any memory, storage device, and / or storage disk for storing data, such as flash memory, magnetic media, optical media, etc. Moreover, the data stored in the example database 572 may be in any data format, such as binary data, comma-limited data, tab-limited data, structured query language (SQL) structures, image data, etc. Although the illustrated example database 572 is illustrated as a single element, the database 572 and / or any other data storage elements described herein may be implemented by any number and / or types of memories.In the example of FIG. 5, the training data 574 may include data representing the input image 105 (e.g., GVF). The neural network trainer 578 may train the neural network implemented by the neural network processor 580 by using the training data 574. Based on the GVFs in the training data 574, the neural network trainer 578 trains the neural network to identify GVF weights associated with image data received by the image segmentation circuit 110. One or more generation models for UNET field mapping 584 are generated as a result of neural network training. The one or more UNET field map generation models 584 are stored in database 582. The databases 572, 582 may be the same storage device or different storage devices. The field feature map generation circuit 520 executes the one or more UNET field map generation models 584 to generate the field feature map 130 of FIG. 1.The data fusion initialization circuit 525 fuses the spatial feature map 125 generated by using the spatial feature map generation circuit 515 with the field feature map 130 generated by using the field feature map generation circuit 520. For example, the UNET architecture used to generate the spatial feature map 125 and / or the field feature map 130 may be based on the base UNET architecture 200 shown in connection with FIG. 2. In some examples, the UNET architecture used may exclude the last output layer of the base UNET, and may instead be developed as a spatial and / or vector field feature extractor. For example, the UNET architecture has a total of 23 convolutional layers, including a final convolutional layer with a 1×1 convolution. In examples disclosed herein, both streams in architecture 22 have convolutional layers and 64 output channels, where a kernel size of the spatial and / or vector field feature extractors is 3×3, with a step size of one. The data fusion initialization circuit 525 fuses the spatial feature map and the field feature map, with the output fusion layer being a mask of the segmentation results. In some examples, data fusion initialization circuit 525 may perform fusion by using sum fusion and / or matrix fusion and / or link fusion and / or convolutional fusion.Segmented image recognition circuit 530 outputs image segmentation results based on the output of data fusion initialization circuit 525. For example, segmented image recognition circuit 530 may output a mask associated with image segmentation. In some examples, segmented image recognition circuit 530 identifies the accuracy of the obtained results by comparing the output mask to a true mask. In some examples, segmented image recognition circuit 530 outputs data associated with various regions of original input image 105 of FIG. 1, such as classification of the regions and / or objects within the image based on the segmentation results (e.g., identification of the left ventricle, right ventricle, myocardium, using cardiac data as described in connection with FIG. 4 ).Data storage 535 may be used to store any information associated with image data receiving circuitry 505, vector field identifying circuitry 510, spatial feature map generation circuitry 515, field feature map generation circuitry 520, data fusion initialization circuitry 525, segmented image recognition circuitry 530. The example data storage 535 of the illustrated example of FIG. 5 may be implemented by any memory, storage device, and / or storage disk for storing data, such as flash memory, magnetic media, optical media, etc. Moreover, the data stored in the example data storage 535 may be in any data format, such as binary data, comma-limited data, tab-limited data, structured query language (SQL) structures, image data, etc.In some examples, the apparatus includes means for receiving image data. For example, the means for receiving image data may be implemented by the image data receiving circuit 505. In some examples, the image data receiving circuit 505 may be instantiated by a processor circuit, such as the example processor circuit 912 of FIG. 9. For example, the image data receiving circuit 505 may be instantiated by the example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 610 of FIG. 6. In some examples, the image data receiving circuit 505 may be instantiated by a hardware logic circuit implemented by an ASIC, XPU, or the FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the image data receiving circuit 505 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the image data receiving circuit 505 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and / or execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.In some examples, the apparatus includes means for identifying a vector field. For example, the means for identifying a vector field may be implemented by the vector field identifying circuit 510. In some examples, the example vector field identification circuit 510 may be instantiated by processor circuitry, such as the example processor circuitry 912 of FIG. 9. For example, vector field identification circuit 510 may be instantiated by example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 610 of FIG. 6. In some examples, the vector field identification circuit 510 may be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the vector field identification circuit 510 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the vector field identification circuit 510 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and / or execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.In some examples, the apparatus includes means for generating a spatial feature map. For example, the spatial feature map generation means may be implemented by the spatial feature map generation circuit 515. In some examples, spatial feature map generation circuit 515 may be instantiated by processor circuitry, such as example processor circuit 912 of FIG. 9. For example, spatial feature map generation circuit 515 may be instantiated by example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 715 of FIG. 7. In some examples, spatial feature map generation circuit 515 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, spatial feature map generation circuit 515 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the spatial feature map generation circuit 515 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and / or execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.In some examples, the apparatus includes means for generating a field feature map. For example, the means for generating a field feature map may be implemented by the field feature map generation circuit 520. In some examples, the field feature map generation circuit 520 may be instantiated by a processor circuit, such as the example processor circuit 912 of FIG. 9. For example, the field feature map generation circuit 520 may be instantiated by the example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 735 of FIG. 7. In some examples, the field feature map generation circuit 520 may be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the field feature map generation circuit 520 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the field feature map generation circuit 520 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and / or execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.In some examples, the device includes means for fusing data. For example, the means for merging data may be implemented by the data fusion initialization circuit 525. In some examples, data fusion initialization circuit 525 may be instantiated by processor circuitry, such as example processor circuit 912 of FIG. 9. For example, the data fusion initialization circuit 525 may be instantiated by the example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 620 of FIG. 6. In some examples, the data fusion initialization circuit 525 may be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the data fusion initialization circuit 525 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the data fusion initialization circuit 525 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and / or to execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.In some examples, the apparatus includes means for identifying a segmented image. For example, the segmented image identifying means may be implemented by the segmented image identifying circuit 530. In some examples, segmented image identification circuit 530 may be instantiated by processor circuitry, such as example processor circuit 912 of FIG. 9. For example, segmented image identification circuit 530 may be instantiated by example microprocessor 1200 of FIG. 12 executing machine-executable instructions, such as those implemented at least by block 623 of FIG. 6. In some examples, segmented image identification circuit 530 may be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or FPGA circuit 1300 of FIG. 13 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, segmented image identification circuitry 530 may be instantiated by any other combination of hardware, software, and / or firmware. For example, segmented image identification circuit 530 may be implemented by at least one or more hardware circuits (e.g., processor circuit, discrete and / or integrated analog and / or digital circuit, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all machine readable instructions and / or execute some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are equally suitable.While an example manner of implementing the image segmentation circuit 110 of FIG. 1 is illustrated in FIG. 5, one or more of the elements, processes, and / or devices illustrated in FIG. 5 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Further, the example image data receiving circuit 505, the example vector field identifying circuit 510, the example spatial feature map generating circuit 515, the example field feature map generating circuit 520, the example data fusion initialization circuit 525, the example segmented image identifying circuit 530, and / or, more generally, the example image segmenting circuit 110 of FIG. 1 may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, any of the image data receiving circuit 505, the vector field identification circuit 510, the spatial feature map generation circuit 515, the field feature map generation circuit 520, the data fusion initialization circuit 525, the segmented image identification circuit 530, and / or, more generally, the example image segmentation circuit 110 of FIG. 1, could be implemented by processor circuitry, one or more analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPU), digital signal processors (DSP), application specific integrated circuits (ASIC), programmable logic devices (PLD), and / or field programmable logic devices (FPLD) such as field programmable gate arrays (FPGA). Moreover, the example image segmentation circuit 110 of FIG. 1 may include one or more elements, processes, and / or devices in addition to or in place of those illustrated in FIG. 5, and / or may include more than one of any or all of the illustrated elements, processes, and devices.While an example manner of implementing the first data processing system 550 is illustrated in FIG. 5, one or more of the elements, processes, and / or devices illustrated in FIG. 5 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Further, the example neural network processor 560, the example trainer 558, the example training controller 556, the example database 552, 562, and / or, more generally, the example first data processing system 550 of FIG. 3 may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, any of the neural network processor 560, the example trainer 558, the example training controller 556, the example database 552, 562, and / or, more generally, the example first data processing system 550 of FIG. 5 could be implemented by processor circuitry, one or more analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPU), digital signal processors (DSP), application specific integrated circuits (ASIC), programmable logic devices (PLD), and / or field programmable logic devices (FPLD) such as field programmable gate arrays (FPGA). Further, the example first computing system 550 of FIG. 5 may include one or more elements, processes, and / or devices in addition to or in place of those illustrated in FIG. 5, and / or may include more than one of any or all of the illustrated elements, processes, and devices.While an example manner of implementing the second data processing system 570 is illustrated in FIG. 5, one or more of the elements, processes, and / or devices illustrated in FIG. 5 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Further, the example neural network processor 580, the example trainer 578, the example training controller 576, the example database 572, 582, and / or, more generally, the example second data processing system 570 of FIG. 5 may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, any of the neural network processor 580, the example trainer 578, the example training controller 576, the example database 572, 582, and / or, more generally, the example second data processing system 570 of FIG. 5 could be implemented by processor circuitry, one or more analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPU), digital signal processors (DSP), application specific integrated circuits (ASIC), programmable logic devices (PLD), and / or field programmable logic devices (FPLD) such as field programmable gate arrays (FPGA). Further, the example second computing system 570 of FIG. 5 may include one or more elements, processes, and / or devices in addition to or in place of those illustrated in FIG. 5 and / or may include more than one of any or all of the illustrated elements, processes, and devices.Flowcharts illustrating example machine readable instructions that may be executed to configure a processor circuit to implement the image segmentation circuit 110 of FIG. 1 are shown in FIGS. 6-8. The machine readable instructions may be one or more executable programs or one or more portions of an executable program for execution by processor circuitry, such as the processor circuitry 912, 1012, 1112 shown in the example processor platform 900, 1000, 1100 discussed below in connection with FIGS. 9, 10, 11 and / or the example processor circuitry discussed below in connection with FIGS. 12 and / or 13. The program may be embodied in software stored on one or more non-transitory computer readable storage media such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., random access memory (RAM) of any type, etc.), or a non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, a HDD, an SSD, etc.) coupled to a processor circuit placed in one or more hardware devices, However, the entire program and / or portions thereof could alternatively be executed by one or more hardware devices other than the processor circuit, and / or embodied in firmware or dedicated hardware. The machine readable instructions may be distributed across and / or executed by two or more hardware devices (e.g., a server and a client hardware device). The client hardware device may be implemented by, for example, an endpoint client hardware device (e.g., a hardware device connected to a user) or an intermediate client hardware device (e.g., a radio access network (RAN) gateway that may enable communication between a server and an endpoint client hardware device). Similarly, the non-transitory computer readable storage media may include one or more media placed in one or more hardware devices. Although the example program is described with reference to the flowcharts illustrated in FIGS. 6-8, many other methods of implementing the example image segmentation circuit 110 of FIG. 1 may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., a processor circuit, a dedicated and / or integrated analog and / or digital circuit, an FPGA, an ASIC, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The processor circuitry may be distributed to different network locations and / or locally to one or more hardware devices (e.g., a single core processor (e.g., a single core CPU), etc.), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.) in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, a CPU and / or an FPGA placed in the same package (e.g., the same integrated circuit (IC) package or in two or more separate packages, etc.).The machine readable instructions described herein may be stored in a compressed format and / or an encrypted format and / or a fragmented format and / or a compiled format and / or an executable format and / or a packaged format, etc. Machine-readable instructions as described herein may be stored as data or data structure (e.g., as portions of instructions, code, representations of code, etc.) that may be used to generate, produce, and / or produce machine-executable instructions. For example, the machine readable instructions may be fragmented and stored in one or more storage devices and / or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, edge devices, etc.). The machine readable instructions may require installation and / or modification and / or adjustment and / or update and / or combination and / or augmentation and / or configuration and / or decryption and / or decompression and / or decapsulation and / or distribution and / or reallocation and / or compilation, etc., to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of machine-executable instructions that implement one or more operations that together may form a program such as that described herein.In another example, the machine readable instructions may be stored in a state where they may be read by a processor circuit, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine readable instructions in a particular computing device or other device. In another example, the machine readable instructions may be required to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and / or the one or more corresponding programs may be executed in whole or in part. Thus, machine-readable media as used herein may include machine-readable instructions and / or one or more programs, regardless of the particular format or state of the machine-readable instructions and / or the one or more programs, when stored or otherwise idle or transition.The machine readable instructions described herein may be represented by any prior, current, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.As mentioned above, the example operations of FIGS. 6-8 may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored in one or more non-transitory computer and / or machine readable media, such as optical storage devices, magnetic storage devices, a HDD, a flash memory, a read only memory (ROM), a CD, a DVD, a cache, a RAM of any type, a register, and / or any other storage device or disk on which information is stored for any duration (e.g., for extended periods, permanently, for short periods, for temporarily buffering, and / or for caching of the information). As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine readable medium, and non-transitory machine readable storage medium are expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and transmission media. The terms "computer readable storage device" and "machine readable storage device" as used herein are defined to include any physical (mechanical and / or electrical) structure for storing information, but to exclude propagating signals and transmission media. Examples of non-transitory computer readable storage devices and / or machine readable storage devices include random access memory of any type, read only memory of any type, solid state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as mechanical and / or electrical equipment, hardware, and / or circuitry, which may or may not be configured by computer readable instructions, machine readable instructions, etc., and / or manufactured to execute computer readable instructions, machine readable instructions, etc."Including" and "comprising" (and all forms and times thereof) are used herein as open terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprises, including, having, etc.) as a preamble or within a claim recitation of any type, it will be understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, the term "at least," when used as a transition term in, for example, a preamble of a claim, is open in the same manner as the terms "comprising" and "including" are open. The term "and / or," when used in a form such as A, B, and / or C, for example, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in connection with the description of structures, components, articles, objects, and / or things, the term "at least one of A and B" is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the term "at least one of A or B" as used herein in connection with describing structures, components, objects, and / or things, is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in connection with describing the execution or execution of processes, instructions, actions, activities, and / or steps, the term "at least one of A and B" is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the term "at least one of A or B," as used herein in connection with describing the execution or execution of processes, instructions, actions, activities, and / or steps, is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used herein, references in the singular (e.g., "a", "a", "first / r / s", "second / r / s", etc.) do not exclude a plural. The term "a" object, as used herein, refers to one or more of that object. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Moreover, although individually listed, multiple means, elements, or method actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, they may be combined, and inclusion in different examples or claims does not imply that a combination of features is not possible and / or advantageous.FIG. 6 is a flow diagram illustrating example machine readable instructions and / or operations 600 that may be executed and / or instantiated by processor circuitry to implement the example image segmentation circuit 110 of FIG. 1. The machine readable instructions and / or operations 600 of FIG. 6 begin at block 605, at which the image data receiving circuit 505 receives the input image 105 of FIG. 1. In the example of FIG. 6, the image data receiving circuit 505 identifies image-based information, such as one or more pixel intensity values 115 (e.g., either RGB or grayscale level), while the vector field identifying circuit 510 identifies the gradient vector flow (GVF) 120 associated with the input image 105 (block 610). Spatial feature map generation circuit 515 and field feature map generation circuit 520 generate spatial feature map 125 of FIG. 1 and field feature map 130 of FIG. 1, respectively, as described in more detail in connection with FIG. 7 (block 615). For example, spatial feature map generation circuit 515 and field feature map generation circuit 520 generate FIGS. 125, 130 based on the identified pixels (e.g., RGB data) and / or gradient vector flow data of input image 105 that serve as inputs to a two-stream neural network (e.g., based on a UNET architecture). In the example of FIG. 6, the data fusion initialization circuit 525 fuses the resulting spatial feature map and field feature map (block 620). The segmented image recognition circuit 530 identifies a mask of the segmentation results based on the output of the data fusion initialization circuit 525 (block 623). The image segmentation circuit 110 outputs the segmented image and / or mask identified as part of the image segmentation, including specific regions of interest (e.g., left ventricle, right ventricle of a cardiac image dataset).FIG. 7 is a flowchart illustrating example machine readable instructions and / or operations 615 that may be executed and / or instantiated by processor circuitry to implement the example image segmentation circuit 110 of FIG. 1. The machine readable instructions and / or operations 615 of FIG. 7 begin at block 705, where the spatial feature map generation circuit 515 determines whether training of the convolutional neural network associated with the UNET architecture 200 of FIG. 2 is needed to identify weights associated with the RGB stream or the spatial stream (block 705). If training is needed, the spatial feature map generation circuit 515 initiates training of the neural network as described in connection with FIG. 8 (block 710). When training is complete, the spatial feature map generation circuit 515 generates the spatial feature map 125 by using the trained neural network (block 715). The output of the spatial feature map 125 represents an output generated by using the spatial stream of the two-stream neural network (block 720). The field feature map generation circuit 520 generates a field feature map in association with the generation of the spatial feature map as part of the two-stream network. For example, the field feature map generation circuit 520 determines whether training is required to identify the stream associated with the GVF stream or the temporal stream (block 725). If training is needed, the field feature map generation circuit 520 initiates training of the neural network as described in connection with FIG. 8 (block 730). When training is complete, the field feature map generation circuit 520 generates the field feature map 130 by using the trained neural network (block 735). The output of the field feature map 130 represents an output generated by using the temporal stream of the two-stream neural network (block 740).FIG. 8 is a flowchart illustrating example machine readable instructions and / or operations 800 that may be executed and / or instantiated by an example processor circuit to train a neural network to determine RGB and / or gradient vector flow (GVF) weights. For example, FIG. 8 illustrates example machine readable instructions executable to implement elements of the example first data processing system 550 and the example second data processing system 570 to cause the data processing system 550, 570 to train the convolutional neural network associated with the UNET architecture. For example, trainer 558, 578 accesses training data 554, 574 (block 805). The training data may include existing weights associated with RGB values and / or gradient vector flows of an image. The trainer 558, 578 identifies data features represented by the training data 554, 574 (block 810). The training controller 556, 576 instructs the trainer 558, 578 to perform training of the neural network (e.g., a convolutional neural network) by using the training data 554, 574 to generate a UNET-based spatial feature map generation model 564 and / or a UNET-based field feature map generation model 584 (block 815). In some examples, additional training is performed to refine models 564, 584 (block 820).FIG. 9 is a block diagram of example processing platform 900 structured to execute and / or instantiate the machine readable instructions and / or operations of FIG. 5 to implement the example image segmentation circuit 110 of FIG. 1. The processor platform 900 may include, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet such as an iPadTM), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, This may be a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing device.The processor platform 900 of the illustrated example includes processor circuitry 912. The processor circuit 912 of the illustrated example is hardware. For example, the processor circuit 912 may be implemented by one or more integrated circuits, logic circuits, FPGA, microprocessors, CPU, GPU, DSP, and / or microcontrollers of any desired family or manufacturer. The processor circuit 912 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuit 912 implements the image data receiving circuit 505, the vector field identifying circuit 510, the spatial feature map generating circuit 515, the field feature map generating circuit 520, the data fusion initializing circuit 525, and / or the segmented image identifying circuit 530.The processor circuit 912 of the illustrated example includes local memory 913 (e.g., a cache, registers, etc.). The processor circuit 912 of the illustrated example is in communication with a main memory including volatile memory 914 and nonvolatile memory 916 through bus 918. The volatile memory 914 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 916 may be implemented by flash memory and / or any other desired type of storage device. Access to main memory 914, 916 of the illustrated example is controlled by memory controller 917.The processor platform 900 of the illustrated example also includes interface circuitry 920. The interface circuit 920 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a peripheral component interconnect PCI) interface, and / or a peripheral component interconnect express PCIe) interface.In the illustrated example, one or more input devices 922 are connected to the interface circuit 920. The one or more input devices 922 enable a user to input data and / or commands to the processor circuit 912. The one or more input devices 922 may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a key, a mouse, a touch screen, a track pad, a track ball, an isopot device, and / or a voice recognition system.One or more output devices 924 are also connected to the interface circuit 920 of the illustrated example. The output devices 924 may be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a haptic output device, a printer, and / or speaker. The interface circuit 920 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit such as a GPU.The interface circuit 920 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to enable data exchange with external machines (e.g., computing devices of any type) through network 926. The communication may be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a wireless line-of-sight system, a mobile telephone system, an optical connection, etc.The processor platform 900 of the illustrated example also includes one or more mass storage devices 928 for storing software and / or data. Examples of such mass storage devices 928 include magnetic storage devices, optical storage devices, floppy disk drives, HDD, CD, Blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.Machine-executable instructions 932, which may be implemented by the machine-readable instructions of FIGS. 6 and / or 8, may be stored in the mass storage device 928, in the volatile memory 914, in the non-volatile memory 916, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.FIG. 10 is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and / or the example operations of FIG. 8 to implement the example first data processing system 550 of FIG. 5. Processor platform 1000 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet such as a iPad™), a personal digital assistant (PDA), an Internet appliance, or any other type of computing device.The processor platform 1000 of the illustrated example includes processor 1012. The processor 1012 of the illustrated example is hardware. For example, processor 1012 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPU, DSP, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements the example neural network processor 560, the example trainer 558 and the example training controller 556.The processor 1012 of the illustrated example includes local memory 1013 (e.g., a cache). The processor 1012 of the illustrated example is in communication with a main memory including volatile memory 1014 and nonvolatile memory 1016 via bus 1018. The volatile memory 1014 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of random access memory device. The non-volatile memory 1016 may be implemented by flash memory and / or any other desired type of storage device. Access to main memory 1014, 1016 is controlled by a memory controller.The processor platform 1000 of the illustrated example also includes interface circuitry 1020. The interface circuit 1020 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth interface, a near-field communication (NFC) interface, and / or a PCI express interface.In the illustrated example, one or more input devices 1022 are connected to the interface circuit 1020. The one or more input devices 1022 enable a user to input data and / or commands to the processor 1012. The one or more input devices may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a key, a mouse, a touch screen, a track pad, a track ball, an isopot device, and / or a voice recognition system.One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. The output devices 1024 may be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or speaker. The interface circuit 1020 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.The interface circuit 1020 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable the exchange of data with external machines (e.g., computing devices of any type) over the network 1026. The communication may take place, for example, via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular radio system, etc.The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include floppy disk drives, hard disks, CD drives, Blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, and Digital Versatile Disk (DVD) drives.Machine-executable instructions 1032, which may be implemented by the machine-readable instructions of FIG. 8, may be stored in the mass storage device 1028, volatile memory 1014, non-volatile memory 1016, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.FIG. 11 is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and / or the example operations of FIG. 8 to implement the example second data processing system 570 of FIG. 5. Processor platform 1100 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet such as a iPad™), a personal digital assistant (PDA), an Internet appliance, or any other type of computing device.The processor platform 1100 of the illustrated example includes processor 1112. The processor 1112 of the illustrated example is hardware. For example, processor 1112 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPU, DSP, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements the example neural network processor 570, the example trainer 578, and the example training controller 576.The processor 1112 of the illustrated example includes local memory 1113 (e.g., a cache). The processor 1112 of the illustrated example is in communication with a main memory including volatile memory 1114 and nonvolatile memory 1116 via bus 1118. The volatile memory 1114 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of random access memory device. The non-volatile memory 1116 may be implemented by flash memory and / or any other desired type of storage device. Access to main memory 1114, 1116 is controlled by a memory controller.The processor platform 1100 of the illustrated example also includes interface circuitry 1120. The interface circuit 1120 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth interface, a near-field communication (NFC) interface, and / or a PCI express interface.In the illustrated example, one or more input devices 1122 are connected to the interface circuit 1120. The one or more input devices 1122 enable a user to input data and / or commands to the processor 1112. The one or more input devices may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a key, a mouse, a touch screen, a track pad, a track ball, an isopot device, and / or a voice recognition system.One or more output devices 1124 are also connected to the interface circuit 1120 of the illustrated example. The output devices 1124 may be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or speaker. The interface circuit 1120 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.The interface circuit 1120 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable the exchange of data with external machines (e.g., computing devices of any type) via network 1126. The communication may take place, for example, via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular radio system, etc.The processor platform 1100 of the illustrated example also includes one or more mass storage devices 1128 for storing software and / or data. Examples of such mass storage devices 1128 include floppy disk drives, hard disks, CD drives, Blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, and Digital Versatile Disk (DVD) drives.Machine-executable instructions 1132, which may be implemented by the machine-readable instructions of FIG. 8, may be stored in the mass storage device 1128, the volatile memory 1114, the non-volatile memory 1116, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.FIG. 12 is block diagram 1200 of an example implementation of the processor circuit 912, 1012, 1112 of FIGS. 9, 10, and / or 11. The microprocessor 1200 may be, for example, a general-purpose microprocessor (for example, a general-purpose microprocessor circuit). Microprocessor 1200 executes some or all of the machine readable instructions of the flowcharts of FIGS. 6, 7, and / or 8 to effectively instantiate the circuit of FIGS. 1 and / or 5 as logic circuitry for performing the operations corresponding to those machine readable instructions. In some such examples, the circuit of FIGS. 1 and / or 5 is instantiated by the hardware circuitry of microprocessor 1200 in combination with the instructions. For example, the microprocessor 1200 may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores 1202 (e.g., 1 core), the microprocessor 1200 of this example is a multi-core semiconductor device including N cores. The cores 1202 of the microprocessor 1200 may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1202, or may be executed by multiple ones of the cores 1202 at the same time or at different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is broken into threads and executed in parallel by two or more of the cores 1202. The software program may correspond to a portion or all of the machine readable instructions and / or operations described by the flowcharts of FIGS. 6, 7, and / or 8.Cores 1202 may communicate through example bus 1204. In some examples, the bus 1204 may implement a communication bus to enable communication associated with one or more of the cores 1202. For example, the bus 1204 may implement an Inter-Integrated Circuit (I2C) bus and / or a Serial Peripheral Interface (SPI) bus and / or a PCI BUS and / or a PCIe bus. Additionally or alternatively, bus 1204 may implement any other type of data processing or electrical bus. Cores 1202 may receive data, instructions, and / or signals from one or more external devices through example interface circuitry 1206. The cores 1202 may output data, instructions, and / or signals to the one or more external devices through the interface circuit 1206. Although the cores 1202 of this example include example local memory 1220 (e.g., level 1 (L1) cache, which may be split into an L1 data cache and an L1 instruction cache), the microprocessor 1200 also includes example shared memory 1210 (e.g., level 2 (L2) cache) that may be shared by the cores for high speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) from shared memory 1210 by writing to and / or reading. The local memory 1220 of each of the cores 1202 and the shared memory 1210 may be part of a hierarchy of storage devices that include multiple levels of cache memory and main memory (e.g., main memory 914, 916 of FIG. 9, main memory 1014, 1016 of FIG. 10, main memory 1114, 1116 of FIG. 11). Typically, higher levels of memory in the hierarchy have a lower access time and have a smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.Each core 1202 may be referred to as a CPU, a DSP, a GPU, etc., or any other type of hardware circuit. Each core 1202 includes controller circuitry 1214, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 1216, multiple registers 1118, L1 cache 1220, and example bus 1222. Other structures may be present. For example, each core 1202 may include a vector unit circuit, a single instruction multiple data (SIMD) unit circuit, a load / store unit (LSU) circuit, a branch / jump unit circuit, a floating point unit (FPU) circuit, etc. The controller circuit 1214 includes semiconductor-based circuitry structured to control (e.g., coordinate) data movement within the corresponding core 1202. AL circuit 1216 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on the data within the corresponding core 1202. The AL circuit 1216 of some examples performs integer-based operations. In other examples, AL circuit 1216 also performs floating point operations. In still other examples, AL circuit 1216 may include a first AL circuit that performs integer-based operations and a second AL circuit that performs floating point operations. In some examples, AL circuit 1216 may be referred to as an arithmetic logic unit (ALU). The registers 1218 are semiconductor-based structures for storing data and / or instructions, such as results of one or more of the operations performed by the AL circuit 1216 of the corresponding core 1202. The registers 1218 may include, for example, one or more vector registers, one or more SIMD registers, one or more general purpose registers, one or more flag registers, one or more segment registers, one or more machine specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. The registers 1218 may be arranged in a bank as shown in Fig. 12. Alternatively, the registers 1218 may be organized in any other arrangement, format, or structure distributed across the core 1202 to reduce access time. The second bus 1222 may be implemented by an I2C bus and / or an SPI bus and / or a PCI bus and / or a PCIe bus.Each core 1202 and / or, more generally, microprocessor 1200 may include structures that are additional and / or alternative to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHA), one or more converged / common mesh stops (CMS), one or more shifters (e.g., barrel shifters), and / or other circuitry may be present. The microprocessor 1200 is a semiconductor device manufactured to include many transistors connected together to implement the structures described above in one or more integrated circuits (IC) included in one or more packages. The processor circuitry may include and / or cooperate with one or more accelerators. In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and / or efficiently than is possible with a general purpose processor. Examples of accelerators include ASIC and FPGA, such as those discussed herein. Also, a GPU or other programmable device may be an accelerator. Accelerators may be located on the processor circuit, in the same chip package as the processor circuit, and / or in one or more packages separate from the processor circuit.FIG. 13 is a block diagram 1300 of another example implementation of the processor circuit of FIGS. 9, 10, and / or 11. The FPGA circuit 1300 may be implemented by an FPGA, for example. For example, the FPGA circuit 1300 may be used to perform operations that could otherwise be performed by the example microprocessor 1200 of FIG. 12 executing corresponding machine readable instructions. However, after configuration, the FPGA circuit 1300 instantiates the machine readable instructions in hardware and thus may often perform the operations faster than would be possible with a general purpose microprocessor executing the appropriate software.In particular, unlike the microprocessor 1200 of FIG. 12 described above (which is a general purpose device that may be programmed to execute some or all of the machine readable instructions represented by the flowcharts of FIGS. 6, 7, and / or 8, but whose connections and logic circuitry are fixed after manufacture), the FPGA circuit 1300 of the example of FIG. 13 includes interconnects and logic circuitry that may be configured and / or interconnected in different ways after manufacture, for example, to instantiate some or all of the machine readable instructions represented by the flowcharts of FIGS. 6, 7, and / or 8. In particular, the FPGA 1300 may be considered an array of logic gates, interconnects, and switches. The switches may be programmed to change the manner in which the logic gates are interconnected by the interconnects, thereby effectively forming one or more dedicated logic circuits (if and as long as the FPGA circuit 1300 is not reprogrammed). The configured logic circuitry enables the logic gates to cooperate in different ways to perform different operations on the data received by input circuits. These operations may correspond to some or all of the software represented by the flowcharts of FIGS. 6, 7, and / or 8. As such, the FPGA circuit 1300 may be structured to effectively instantiate some or all of the machine readable instructions of the flowcharts of FIGS. 6, 7, and / or 8 as dedicated logic circuits to perform the operations corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuit 1300 may perform the operations corresponding to some or all of the machine readable instructions of FIGS. 6, 7, and / or 8 faster than the general purpose microprocessor may perform.In the example of FIG. 13, the FPGA circuit 1300 is structured to be programmed (and / or reprogrammed once or multiple times) by an end user through a hardware description language (HDL) such as Verilog. The FPGA circuit 1300 of FIG. 13 includes example input / output (I / O) circuitry 1302 to obtain and / or output data from / to example configuration circuitry 1304 and / or external hardware 1306. For example, the configuration circuit 1304 may implement an interface circuit that may receive machine readable instructions for configuring the FPGA circuit 1300 or one or more portions thereof. In some such examples, the configuration circuit 1304 may receive the machine readable instructions from a user, a machine (e.g., a hardware circuit (e.g., a programmed or dedicated circuit) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the instructions), etc. In some examples, external hardware 1306 may be implemented by an external hardware circuit. For example, the external hardware 1306 may be implemented by the microprocessor 1300 of FIG. 13. The FPGA circuit 1300 also includes an array of example logic gate circuits 1308, multiple example configurable interconnects 1310, and example storage circuit 1312. Logic gate circuit 1308 and configurable interconnects 1310 are configurable to instantiate one or more operations corresponding to at least a portion of the machine readable instructions of FIGS. 6, 7, and / or 8, and / or other desired operations. The logic gate circuit 1308 shown in FIG. 13 is made in groups or blocks. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic logic circuit building blocks. Electrically controllable switches (e.g., transistors) are provided within each of the logic gate circuits 1308 to enable configuration of the electrical structures and / or the logic gates to form circuits for performing desired operations. Logic gate circuit 1308 may include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.The configurable interconnects 1310 of the illustrated example are conductive paths, traces, vias, or the like, which may include electrically controllable switches (e.g., transistors), the state of which may be changed by programming (e.g., using an HDL instruction language) to enable or disable one or more interconnects between one or more of the logic gate circuits 1308 to program desired logic circuits.The storage circuit 1312 of the illustrated example is structured to store one or more results of the one or more operations performed by respective logic gates. The storage circuit 1312 may be implemented by registers or the like. In the illustrated example, the storage circuit 1312 is distributed across the logic gate circuit 1308 to facilitate access and increase an execution speed.The example FPGA circuit 1300 of FIG. 13 also includes example dedicated operation circuit 1314. In this example, dedicated operation circuit 1314 includes special purpose circuit 1316 that can be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry 1316 include memory (e.g., DRAM) control circuitry, PCIe control circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuits may be present. In some examples, the FPGA circuit 1300 may also include example programmable general purpose circuitry 1318 such as example CPU 1320 and / or example DSP 1322. Another programmable general purpose circuit 1318 may additionally or alternatively be present, such as a GPU, an XPU, etc., which may be programmed to perform other operations.Although FIGS. 12 and 13 illustrate two example implementations of the processor circuitry 912, 1012, 1112 of FIGS. 9, 10, and / or 11, many other approaches are contemplated. For example, as mentioned above, a modern FPGA circuit may include an internal CPU, such as one or more of the example CPU 1320 of FIG. 13. Therefore, the processor circuit 912, 1012, 1112 of FIGS. 9, 10, and / or 11 may be additionally implemented by combining the example microprocessor 1200 of FIG. 12 and the example FPGA circuit 1300 of FIG. 13. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts of FIGS. 6, 7, and / or 8 may be executed by one or more of the cores 1202 of FIG. 12, a second portion of the machine readable instructions represented by the flowcharts of FIGS. 6, 7, and / or 8 may be executed by the FPGA circuit 1300 of FIG. 13, and / or a third portion of the machine readable instructions represented by the flowcharts of FIGS. 6, 7, and / or 8 may be executed by an ASIC. It will be appreciated that some or all of the circuits of FIGS. 9, 10, 11 may thus be instantiated at the same time or at different times. For example, some or all of the circuits may be instantiated in one or more threads executing simultaneously and / or in series. Additionally, in some examples, some or all of the circuits of FIGS. 9, 10, 11 may be implemented by one or more virtual machines and / or containers executing on the microprocessor.In some examples, the processor circuitry 912, 1012, 1112 of FIGS. 9, 10, 11 may be located in one or more packages. For example, the processor circuit 1200 of FIG. 12 and / or the FPGA circuit 1300 of FIG. 13 may be located in one or more packages. In some examples, an XPU may be implemented by the processor circuitry 912, 1012, 1112 of FIGS. 9, 10, 11, which may be located in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in another package, and an FPGA in yet another package.A block diagram illustrating example software distribution platform 1405 for distributing software, such as example machine readable instructions 932, 1032, 1132 of FIGS. 9, 10, and / or 11, to and / or operated by third party owned hardware devices is illustrated in FIG. 14. The example software distribution platform 1405 may be implemented by any computer server, data plant, cloud service, etc., capable of storing and transferring software to other computing devices. The third party may be clients of the entity owned and / or operating the software distribution platform 1405. For example, the entity that owns and / or operates the software distribution platform 1405 may be a developer, a seller, and / or a licenseer of software such as the example machine readable instructions 932, 1032, 1132 of FIGS. 9, 10, and / or 11. The third party may be consumers, users, retailers, OEMs, etc., who buy and / or license the software for use and / or resale and / or underlend. In the illustrated example, the software distribution platform 1405 includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions 932, 1032, 1132 of FIGS. 9, 10, and / or 11, which may correspond to the example machine readable instructions 600, 615, and / or 800 of FIGS. 6, 7, and / or 8, as described above. The one or more servers of the example software distribution platform 1405 are in communication with network 1410, which may correspond to the Internet and / or any of the example networks described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or license of the software may be handled by the one or more servers of the software distribution platform and / or by a third party payment entity. The servers allow buyers and / or licensees to download the machine readable instructions 932, 1032, 1132 from the software distribution platform 1405. For example, software corresponding to the example machine readable instructions 600, 615, and / or 800 of FIGS. 6, 7, and / or 8 may be downloaded to the example processor platform 900, 1000, 1100 to execute the machine readable instructions 932, 1032, 1132 to implement the image segmentation circuit 110. In some examples, one or more servers of the software distribution platform 1405 periodically offer, transmit, and / or force updates for the software (e.g., the example machine readable instructions 932, 1032, 1132 of FIGS. 9, 10, 11) to ensure improvements, patches, updates, etc. are distributed and applied to the software at the end user devices.From the foregoing, it is understood that example systems, methods, apparatus, and articles of manufacture have been disclosed that enable image segmentation by using small data sets. In particular, methods and apparatus disclosed herein implement a two-stream network architecture by introducing gradient vector flow (GVF) as part of temporal features associated with an input image. Higher accuracy of image segmentation enables improved assessment of the one or more input images. Moreover, methods and apparatus disclosed herein enable a reduction in computational and / or storage requirements during image segmentation tasks, which also results in a reduction in the cost associated with image assessment compared to using existing image segmentation techniques.Example methods, apparatus, systems, and articles of manufacture for performing image segmentation on small data sets are disclosed herein. Further examples and combinations thereof include the following:Example 1 includes an apparatus comprising: at least one memory, machine readable instructions, and processor circuitry to instantiate or execute the machine readable instructions to identify a gradient vector flow associated with an input image and / or to generate a spatial feature map based on pixels of the input image by using a two-stream neural network architecture and / or to generate a field feature map based on the gradient vector flow by using the two-stream neural network architecture and / or to merge the spatial feature map and the field feature map and / or to output a segmented image of the input image based on the merged feature map.Example 2 includes the apparatus of example 1, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.Example 3 includes the apparatus of example 2, wherein the UNET architecture includes a spatial stream and a temporal stream.Example 4 includes the apparatus of example 1, wherein the processor circuitry is to train the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.Example 5 includes the apparatus of example 1, wherein the processor circuitry is to train the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.Example 6 includes the apparatus of example 1, wherein the processor circuitry is to fuse the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.Example 7 includes the apparatus of example 1, wherein the segmented image of the input image is a predicted mask, the predicted mask to identify a prediction accuracy of the two-stream neural network.Example 8 includes a method comprising: identifying a gradient vector flow associated with an input image; generating a spatial feature map based on pixels of the input image by using a two-stream neural network architecture; generating a field feature map based on the gradient vector flow by using the two-stream neural network architecture; merging the spatial feature map and the field feature map; and outputting a segmented image of the input image based on the merged feature map.Example 9 includes the method of example 8, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.Example 10 includes the method of example 9, wherein the UNET architecture includes a spatial stream and a temporal stream.Example 11 includes the method of example 8, further including training the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.Example 12 includes the method of example 8, further including training the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.Example 13 includes the method of example 8, further including fusing the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.Example 14 includes the method of example 8, wherein the segmented image of the input image is a predicted mask, the predicted mask to identify a prediction accuracy of the two-stream neural network.Example 15 includes a non-transitory machine readable storage medium comprising instructions that, when executed, cause the processor circuitry to at least: identify a gradient vector flow associated with an input image, generate a spatial feature map based on pixels of the input image by using a two-stream neural network architecture, generate a field feature map based on the gradient vector flow by using the two-stream neural network architecture, merge the spatial feature map and the field feature map, and output a segmented image of the input image based on the merged feature map.Example 16 includes the non-transitory machine readable storage medium of example 15, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.Example 17 includes the non-transitory machine readable storage medium of example 16, wherein the UNET architecture includes a spatial stream and a temporal stream.Example 18 includes the non-transitory machine readable storage medium of example 15, wherein the instructions, when executed, cause the processor circuitry to train the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.Example 19 includes the non-transitory machine readable storage medium of example 15, wherein the instructions, when executed, cause the processor circuitry to train the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.Example 20 includes the non-transitory machine readable storage medium of example 15, wherein the instructions, when executed, cause the processor circuitry to fuse the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.The following claims are hereby incorporated by reference into this detailed description. Although certain example systems, methods, devices, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. Rather, this patent covers all systems, methods, apparatus and articles of manufacture that reasonably fall within the scope of the claims of this patent.

Claims

An apparatus comprising: at least one memory; machine readable instructions; and processor circuitry to instantiate and / or execute the machine readable instructions to: identify a gradient vector flow associated with an input image; generate a spatial feature map based on pixels of the input image by using a two-stream neural network architecture; generate a field feature map based on the gradient vector flow by using the two-stream neural network architecture; merge the spatial feature map and the field feature map; and output a segmented image of the input image based on the merged feature map.The apparatus of claim 1, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.The apparatus of claim 2, wherein the UNET architecture includes a spatial stream and a temporal stream.The apparatus of claim 1, wherein the processor circuit is to train the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.The apparatus of claim 1, wherein the processor circuitry is to train the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.The apparatus of claim 1, wherein the processor circuitry is to fuse the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.The apparatus of claim 1, wherein the segmented image of the input image is a predicted mask, the predicted mask to identify a prediction accuracy of the two-stream neural network.A method comprising: identifying a gradient vector flow associated with an input image; generating a spatial feature map based on pixels of the input image by using a two-stream neural network architecture; generating a field feature map based on the gradient vector flow by using the two-stream neural network architecture; merging the spatial feature map and the field feature map; and outputting a segmented image of the input image based on the merged feature map.The method of claim 8, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.The method of claim 9, wherein the UNET architecture includes a spatial stream and a temporal stream.The method of claim 8, further comprising training the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.The method of claim 8, further comprising training the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.The method of claim 8, further comprising merging the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.The method of claim 8, wherein the segmented image of the input image is a predicted mask, the predicted mask to identify a prediction accuracy of the two-stream neural network.A non-transitory machine readable storage medium comprising instructions that, when executed, cause a processor circuit to at least: identify a gradient vector flow associated with an input image; generate a spatial feature map based on pixels of the input image by using a two-stream neural network architecture; generate a field feature map based on the gradient vector flow by using the two-stream neural network architecture; merge the spatial feature map and the field feature map; and output a segmented image of the input image based on the merged feature map.The non-transitory machine readable storage medium of claim 15, wherein the two-stream neural network architecture is a UNET architecture, wherein the UNET architecture is a convolutional neural network (CNN) model for encoding and decoding.The non-transitory machine readable storage medium of claim 16, wherein the UNET architecture includes a spatial stream and a temporal stream.The non-transitory machine readable storage medium of claim 15, wherein the instructions, when executed, cause the processor circuitry to train the neural network to determine weights associated with RGB values of the input image as part of generating the spatial feature map.The non-transitory machine readable storage medium of claim 15, wherein the instructions, when executed, cause the processor circuitry to train the neural network to determine weights associated with the gradient vector flow of the input image as part of generating the field feature map.The non-transitory machine readable storage medium of claim 15, wherein the instructions, when executed, cause the processor circuitry to fuse the spatial feature map and the field feature map by using a sum fusion and / or a matrix fusion and / or a concatenation fusion and / or a convolution fusion.

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