Array substrate, display panel and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a substrate (1), a plurality of gate line groups (2) on one side of the substrate (1), wherein a plurality of gate line groups (2) extend along a first direction (X), and a plurality of data lines (3) on the same side of the substrate (1) as the gate line groups.wherein the plurality of data lines (3) extend along a second direction (Y), a plurality of pixel electrodes (4) on the same side of the substrate (1) as the gate line groups and in a region formed by a crossing of the gate line group (2) and the data lines (3), and a plurality of pixel electrodes (4) comprising: a pixel electrode (41) of a first type and a pixel electrode (42) of a second type, a light-shielding section (5) is on the same side of the substrate (1) as the gate line group (2) and only in the region where the pixel electrode (41) of the first type is located, and the light-shielding section (5) comprising: a first section (51) extending in the first direction (X); an orthographic projection of the first section (51) on the substrate (1) passing through a central region of an orthographic projection of the pixel electrode (41) of the first type on the substrate (1).

Description

AREA OF TECHNOLOGY

[0001] The present disclosure relates to the field of semiconductor technology, in particular to an array substrate, a display panel and a display device. STATE OF THE ART

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) feature a variety of commonly used display modes, such as Twisted Nematic (TN), Vertically Alignment (VA), Fringe Field Switching (FFS), and In-Plane Switching (IPS). VA mode offers the advantages of better dark performance and contrast compared to other display modes. SUMMARY

[0003] Embodiments of the present disclosure provide an array substrate comprising: a substrate; a plurality of gate conduction groups on one side of the substrate, wherein the plurality of gate conduction groups extend along a first direction; a multitude of data lines on the same side of the substrate as the gate line groups; wherein the multitude of data lines extend along a second direction; a plurality of pixel electrodes on the same side of the substrate as the gate conductor groups and in an area formed by a crossing of the gate conductor groups and the data lines, wherein the plurality of pixel electrodes comprises: a pixel electrode of a first type and a pixel electrode of a second type; a light-shielding section on the same side of the substrate as the gate conduction groups and only in a region where the pixel electrode of the first type is located; wherein the light-shielding section comprises: a first section extending in the first direction; an orthographic projection of the first section on the substrate passing through a central region of an orthographic projection of the pixel electrode of the first type on the substrate.

[0004] In some embodiments, the light-shielding section further comprises: a second section located on one side of the first section and extending along the second direction; the second section is connected to one end of the first section, and an orthographic projection of the second section onto the substrate overlaps with an orthographic projection of a side region of the pixel electrode of the first type onto the substrate.

[0005] In some embodiments, the light-shielding section further comprises: a third section located on the other side of the first section and extending along the second direction; The third section is connected to the other end of the first section, and an orthographic projection of the third section onto the substrate overlaps with an orthographic projection of the other side area of ​​the pixel electrode of the first type onto the substrate.

[0006] In some embodiments, the pixel electrode of the first type is a pixel electrode corresponding to a blue color resistance, and the pixel electrode of the second type comprises a pixel electrode corresponding to a red color resistance, or a pixel electrode corresponding to a green color resistance.

[0007] In some embodiments, the array substrate further comprises: a first signal wiring layer, and the light-shielding section and the first signal wiring layer are on the same layer and made of the same material.

[0008] In some embodiments, the first signal wiring layer further comprises: a first common electrode wiring group extending along the second direction, and the first common electrode wiring group is separated at the gate wiring groups; The first common electrode wiring group comprises: two first common electrode wires extending along the second direction and located on opposite sides of each data line, and the light-shielding section and the first common electrode wire near the first-type pixel electrode in the first common electrode wiring group form an integrated interconnect structure.

[0009] In some embodiments, the width of the second section in the first direction is 1 to 3 times the width of the first common electrode wire in the first direction.

[0010] In some embodiments, the width of the third section in the first direction is essentially equal to the width of the second section in the first direction.

[0011] In some embodiments, the width of the first section in the second direction is essentially equal to the width of the second section in the first direction.

[0012] In some embodiments, the first signal wiring layer further comprises: a second common electrode wire extending along the first direction; a pixel electrode is provided between the second common electrode wire and the gate wiring group, and the second common electrode wire in the same direction of extension is an integrated interconnect structure; There is a gap between the second section and the second common electrode wire; and the first common electrode wire, the second common electrode wire and the second section form a first notch with an opening facing one side of the pixel electrode of the first type.

[0013] In some embodiments, each gate line group comprises: a primary gate line and a secondary gate line; the first signal wiring layer further comprises: a third common electrode wire arranged on a side of the secondary gate line furthest from the primary gate line and extending along the first direction; the pixel electrode is present between the third common electrode wire and the second common electrode wire, and the third common electrode wire is separated in the same direction of extension in an area where the data line is located; There is a gap between the third section and the third common electrode wire; and the first common electrode wire, the third common electrode wire and the third section form a second notch with an opening facing one side of the pixel electrode.

[0014] In some embodiments, the third common electrode wire comprises: a first subsection and a second subsection located on a side of the first subsection furthest from the second notch; a width of the first subsection in the second direction is greater than a width of the second subsection in the second direction.

[0015] In some embodiments, the first signal wiring layer further comprises: a fourth common electrode wire arranged on a side of the primary gate line furthest from the secondary gate line and extending along the first direction; the pixel electrode is present between the fourth common electrode wire and the second common electrode wire, and the fourth common electrode wire is separated in the same direction of extension in an area where the data line is located; The array substrate further comprises: a first transistor connected to the data line and located on one side of the data line; The fourth common electrode wire includes a notch group, the notch group comprising: a first notch located on one side of a data line, and a third notch located on the other side of the one data line and comprising an opening facing one side of the primary gate line, and the first notch and the first transistor are located on the same side of the one data line.

[0016] In some embodiments, the plurality of pixel electrodes comprises: a first row of pixel electrodes and a second row of pixel electrodes extending along the first direction and arranged alternately along the second direction; the first row of pixel electrodes is arranged on a side of the primary gate line furthest from the secondary gate line, and the second row of pixel electrodes is arranged on a side of the secondary gate line furthest from the primary gate line; The first pixel electrode array comprises a multitude of first pixel electrodes, and the second pixel electrode array comprises a multitude of second pixel electrodes.

[0017] In some embodiments, a layer in which the data line is located further comprises: a first electrode of the first transistor which is electrically connected to the data line, and a first electrode section which is arranged on one side of the first electrode of the first transistor; the first electrode section comprises: a second electrode of the first transistor, a first overlap section electrically connected to the second electrode of the first transistor, and a second overlap section extending along the first direction from one end of the first overlap section; An orthographic projection of the first overlap section on the substrate overlaps with an orthographic projection of the first pixel electrode on the substrate; the first overlap section is electrically connected to the first pixel electrode via a first through-hole; and an orthographic projection of the second overlap section on the substrate overlaps with an orthographic projection of the fourth common electrode wire on the substrate to form a first capacitance.

[0018] In some embodiments, the maximum width of the first overlap section in the second direction is greater than the maximum width of the second overlap section in the second direction.

[0019] In some embodiments, the layer containing the data line further comprises: a second electrode section located on the other side of the first electrode of the first transistor; the second electrode section comprises: a third electrode of the first transistor, a third overlap section, a first-transistor junction section connecting the third electrode of the first transistor and the third overlap section, and a fourth overlap section extending along the first direction from one end of the third overlap section; An orthographic projection of the third overlap section on the substrate overlaps with an orthographic projection of the second pixel electrode on the substrate; the third overlap section is electrically connected to the second pixel electrode via a second through-hole; an orthographic projection of the fourth overlap section on the substrate overlaps with an orthographic projection of the third common electrode wire on the substrate to form a second capacitance.

[0020] In some embodiments, the maximum width of the third overlap section in the second direction is greater than the maximum width of the fourth overlap section in the second direction.

[0021] In some embodiments, the layer in which the data line is located further comprises: a third electrode section arranged on a side of the second electrode section facing the gate conductor group; The third electrode section comprises: a second electrode of the second transistor and a fifth overlap section connected to the second electrode of the second transistor; an orthographic projection of the fifth overlap section on the substrate overlaps with the orthographic projection of the third common electrode wire on the substrate to form a third capacitance.

[0022] In some embodiments, the maximum width of the fifth overlap section in the second direction is greater than the maximum width of the second electrode of the second transistor in the second direction.

[0023] In some embodiments, the orthographic projection of the fifth overlap section on the substrate does not overlap with the orthographic projection of the fourth overlap section on the substrate.

[0024] In some embodiments, the first transistor comprises: a control electrode of the first transistor, an active layer of the first transistor, the first electrode of the first transistor, the second electrode of the first transistor, and the third electrode of the first transistor; wherein the control electrode of the first transistor is a section of the primary gate line.

[0025] In some embodiments, the array substrate further comprises: a second transistor; The second transistor comprises: a control electrode of the second transistor, an active layer of the second transistor, a first electrode of the second transistor, the second electrode of the second transistor; wherein the control electrode of the second transistor is a section of the secondary gate line, the first transistor interconnect section is multiplexed as the first electrode of the second transistor.

[0026] In some embodiments, the array substrate further comprises an active layer and a passivation layer covering a side of the active layer furthest from the substrate; the active layer comprises the active layer of the first transistor and the active layer of the second transistor; One material of the active layer comprises indium gallium zinc oxide, and one material of the passivation layer comprises silicon dioxide and silicon nitride.

[0027] In some embodiments, the array substrate further comprises: a first wiring, a second wiring, and an adapter section; A first insulating layer is present between the adapter section and the first wiring; the first insulating layer includes a third through-hole; the third through-hole exposes part of the first wiring and part of the substrate; A second insulating layer is present between the adapter section and the second wiring; the second insulating layer includes a fourth through-hole; the fourth through-hole exposes part of the second wiring and part of the substrate; One end of the adapter section covers the third through-hole and is in contact with the first wiring via the third through-hole; the other end of the adapter section covers the fourth through-hole and is in contact with the second wiring via the fourth through-hole; the adapter section overlaps the first wiring with the second wiring.

[0028] In some embodiments, the first wiring includes the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire, or the fourth common electrode wire; The second wiring includes: the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire, or the fourth common electrode wire.

[0029] In some embodiments, the adapter section and the pixel electrode are on the same layer and made of the same material.

[0030] In some embodiments, the first insulating layer comprises a gate insulating layer, a passivation layer and / or a planarization layer; the second insulating layer comprises an insulating layer, a passivation layer and / or a planarization layer.

[0031] Embodiments of the present disclosure provide an array substrate comprising: a substrate; a multitude of gate lines on one side of the substrate, extending in a first direction; a multitude of data lines on the same side of the substrate as the gate lines, extending along a second direction; a multitude of pixel electrodes on the same side of the substrate as the gate lines and in areas formed by a crossing of the gate lines and the data lines; wherein each data line comprises a first data segment extending in the second direction, a second data segment extending in the second direction, and a third data segment extending along the first direction and connecting the first data segment to the second data segment; an extension line of the first data segment does not overlap with an extension line of the second data segment; an orthographic projection of an extension line of the third data segment on the substrate passes through a central region of an orthographic projection of the pixel electrode on the substrate; an orthographic projection of the first data segment on the substrate overlaps with an orthographic projection of a first side region of the pixel electrode on the substrate;An orthographic projection of the second data section on the substrate overlaps with an orthographic projection of a second side region of the pixel electrode on the substrate.

[0032] In some embodiments, the length of the third data section in the first direction is 2 to 4 times the width of the first data section in the first direction.

[0033] In some embodiments, the array substrate further comprises: a second electrode of a transistor in the same layer as a layer containing the data lines, and a first electrode block connected to the second electrode of the transistor; The first electrode block is positioned between two adjacent third data sections; an orthographic projection of the first electrode block on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the first electrode block is electrically connected to the pixel electrode via a fifth through-hole.

[0034] In some embodiments, the array substrate further comprises: a fifth common electrode wiring group; the fifth common electrode group comprises: two fifth common electrode wires extending along the first direction; Between two fifth common electrode wires in an identical fifth common electrode wiring group, a second electrode block is provided, and an orthographic projection of the second electrode block on the substrate overlaps with an orthographic projection of the first common electrode block on the substrate to form a fourth capacitor.

[0035] Embodiments of the present disclosure further provide a display panel comprising the array substrate provided by embodiments of the present disclosure.

[0036] In some embodiments, the display panel further comprises: a counter-substrate opposite the array substrate, and the counter-substrate is provided with a common electrode layer.

[0037] In some embodiments, the display panel further comprises a liquid crystal layer arranged between the array substrate and the counter-substrate; the liquid crystal layer comprises four liquid crystal regions in a region where the pixel electrodes are located, and liquid crystal orientations in the liquid crystal regions are different.

[0038] Embodiments of the present disclosure further provide a display device comprising the display panel provided by embodiments of the present disclosure. BRIEF DESCRIPTION OF THE FIGURES Fig. Figure 1 is a schematic diagram of the principle of a pixel that creates a color shift. Fig. 2A is one of the schematic diagrams of the array substrate provided by an embodiment of the present disclosure. Fig. 2B is a schematic diagram of a single layer of a layer in which the gate line group is located in Fig. 2A is located. Fig. 2C is a schematic diagram of a single layer of an active layer in Fig. 2A. Fig. 2D is a schematic diagram of a single layer of a data line layer in Fig. 2A. Fig. 2E is a schematic diagram of a single layer of a pixel electrode layer in Fig. 2A. Fig. 2F is an enlarged schematic diagram of the middle left side of Fig. 2A. Fig. 2G is an enlarged schematic diagram of the middle right side in Fig. 2A. Fig. Figure 3 is a schematic diagram of a process of separating the data line and the second common electrode wire by cutting. Fig. Figure 4 is a schematic diagram of a circuit provided by an embodiment of the present disclosure. Fig. Figure 5A is a schematic diagram of a connection of different wires provided by an embodiment of the present disclosure. Fig. 5B is a cross-sectional diagram along the dashed line AA' in Fig. 5A. Fig. 5C is a cross-sectional diagram along the dashed line BB' in Fig. 5A. Fig. Figure 6 is an enlarged schematic diagram of the dashed circle S of Fig. 2A. Fig. Figure 7 is a schematic cross-sectional diagram of the display board provided by an embodiment of the present disclosure. Fig. Figure 8A is the second schematic diagram of the array substrate provided by an embodiment of the present disclosure. Fig. 8B is a schematic diagram of a single layer of a gate line 20 in Fig. 8A. Fig. 8C is a schematic diagram of a single layer of the data line in Fig. 8A. Fig. 8D is a schematic diagram of a single layer of the pixel electrode in Fig. 8A. Fig. Figure 9 is a schematic diagram of a liquid crystal with a plurality of orientation regions in the area where the same pixel electrode is located, as provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0039] To clarify the purpose, technical solution, and advantages of embodiments of this disclosure, the technical solutions of embodiments of this disclosure are described below in detail, in conjunction with the accompanying drawings of embodiments of this disclosure. Obviously, the described embodiments are some embodiments of this disclosure, not all embodiments. Based on the described embodiments of this disclosure, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of this disclosure.

[0040] Unless otherwise defined, technical or scientific terms used in this revelation shall have the ordinary meanings understood by persons with general knowledge in the field to which this revelation belongs. The terms “first,” “second,” and similar expressions used in this revelation do not indicate any order, number, or importance, but serve only to distinguish the different components. Words such as “include” or “comprehensive” mean that the element or object preceding the word includes the element or object listed after the word and its equivalents, and do not exclude other elements or objects. Similar terms such as “coupled” or “connected” are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc.are only used to specify the relative positional relationship, and if the absolute position of the described object changes, the relative positional relationship can also change accordingly.

[0041] As used herein, the words “approximately” or “essentially the same” encompass the stated values ​​and imply an acceptable deviation from the specific values ​​as determined by a person with ordinary technical knowledge, taking into account the measurements in question and the errors associated with the measurements of the specific quantities (i.e., the limitations of the measuring system). For example, “approximately the same” may mean that the difference from the stated value is within one or more standard deviations, or within the range of ±30%, 20%, 10%, or 5%.

[0042] In the drawings, the thickness of layers, films, sheets, areas, etc., is shown enlarged for clarity. This disclosure describes an exemplary embodiment with reference to a cross-sectional diagram, which is a schematic diagram of an idealized embodiment. In this way, deviations from the shape of the diagram are expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this article should not be interpreted as being limited to the specific shape of the area shown here, but rather as encompassing deviations in shape caused, for example, by the manufacturing process. For instance, an area shown or described as flat may typically exhibit rough and / or nonlinear properties. Furthermore, the sharp corners shown may be rounded.Therefore, the areas shown in the diagram are inherently schematic, and their shapes do not represent the exact shape of the areas depicted and are not intended to limit the scope of the claims.

[0043] In order to keep the following descriptions of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known parts are omitted.

[0044] VN-Display products, after ultraviolet-induced multi-domain vertical alignment (UV2A), as in Fig. 1 shown, for the liquid crystal molecules under the dark lines in the middle of the pixel and the dark lines on both branches (as in the black stripes in Fig. (1 shown), when the human eye views the liquid crystal molecules from a side angle, the liquid crystal molecules are viewed from the side of the longitudinal axis of the liquid crystal molecules, and due to the birefringence of the liquid crystal, light leakage occurs from the side angle of the UV2A orientation display mode, and for indium gallium zinc oxide (IGZO) type transistors, since SiO2 must be used in the gate insulating layer and passivation layer to protect IGZO, and the refractive index of SiO2 in the gate insulating layer and passivation layer is different from that of SiN, this leads to a violet color due to interference of the transmitted light from the side view, and the phenomenon of color shift occurs, and the side view image is blue.

[0045] In view of this, the embodiment of the present disclosure provides an array substrate as described in Fig. 2A to Fig. 2G shown. Fig. 2B is a schematic diagram of a single layer of a layer in which the gate line group is located in Fig. 2A is located. Fig. 2C is a schematic diagram of a single layer of an active layer in Fig. 2A. Fig. 2D is a schematic diagram of a single layer of a data line layer in Fig. 2A. Fig. 2E is a schematic diagram of a single layer of a pixel electrode layer in Fig. 2A. Fig. 2F is an enlarged schematic diagram of the middle left side of Fig. 2A. Fig. 2G is an enlarged schematic diagram of the middle right side in Fig. 2A. The array substrate comprises: a substrate 1; a plurality of gate conduction groups 2 on one side of the substrate 1, wherein the plurality of gate conduction groups 2 extend along a first direction X; a plurality of data lines 3 on the same side of the substrate 1 as the gate line groups 2; wherein the plurality of data lines 3 extend along a second direction Y; A plurality of pixel electrodes 4 on the same side of the substrate 1 as the gate conductor groups 2 and in a region formed by a crossing of the gate conductor groups 2 and the data lines 3, wherein the plurality of pixel electrodes 4 comprises: a pixel electrode 41 of a first type and a pixel electrode 42 of a second type; in some embodiments, the pixel electrodes 4, in addition to the pixel electrodes 41 of the first type, can be used as pixel electrodes 42 of the second type; the pixel electrodes 41 of the first type can be the pixel electrodes of blue pixels, and the pixel electrodes 42 of the second type can be pixel electrodes of red or green pixels; a light-shielding section 5 on the same side of the substrate 1 as the gate conduction groups 2 and only in a region where the pixel electrode 41 of the first type is located; wherein the light-shielding section 5 comprises: a first section 51 extending in the first direction X; an orthographic projection of the first section 51 on the substrate 1 passing through a central region of an orthographic projection of the pixel electrode 41 of the first type on the substrate 1.

[0046] In embodiments of the disclosure, the array substrate comprises a light-shielding section 5, the light-shielding section 5 comprises a first section 51 extending along the first direction X, the orthographic projection of the first section 51 onto the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 41 of the first type on the substrate, shading of the light leakage from the central part of the pixel electrode 41 of the first type can be realized, and in comparison to the case where the first section 51 is not arranged with all pixel electrodes 4 or where all pixel electrodes 4 are provided with a first section 51, the proportion of blue light in the color-mixed light cannot be reduced.The first section 51 is arranged only at the position of the pixel electrode 41 of the first type in the embodiments of the disclosure, so that the transmittance of the blue light of the liquid crystal at the side viewing angle can be reduced, thereby effectively suppressing the bluish tint of the side screen.

[0047] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the light-shielding section 5 further comprises: a second section 52, located on one side of the first section 51 and extending along the second direction Y. The second section 52 is connected to one end of the first section 51, and the orthographic projection of the second section 52 onto the substrate 1 overlaps with the orthographic projection of a side region of the first-type pixel electrode 41 onto the substrate 1. Specifically, as shown, for example, in Fig. As shown in Figure 2A, the second section 52 begins from the left end of the first section 51 and extends upwards to encompass the upper left side region of the first-type pixel electrode 41. Fig. 2A to shade. In embodiments of the disclosure, the array substrate comprises the second section 52, so that light leakage in a side region of the pixel electrode 41 of the first type can be avoided, thereby further reducing the transmittance of blue light from the liquid crystal from the side view angle of the side region, and effectively suppressing the blue bias of the image in the side view.

[0048] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the light-shielding section 5 further comprises: a third section 53, located on the other side of the first section 51 and extending along the second direction Y. The third section 53 is connected to the other end of the first section 51, and the orthographic projection of the third section 53 onto the substrate 1 overlaps with the orthographic projection of the other side region of the first-type pixel electrode 41 onto the substrate 1. For example, in conjunction with Fig. 2A the third section 53 from the right end of the first section 51 and extends downwards to encompass the lower right side region of the pixel electrode 41 of the first type in Fig. 2A to shade. In embodiments of the present disclosure, the array substrate comprises a third section 53, so that light leakage in the other side region of the pixel electrode 41 of the first type can be avoided, thereby further reducing the transmittance of blue light from the liquid crystal from the side view angle of the side region, and effectively suppressing the blue bias of the image in the side view.

[0049] As in Fig. As shown in Figure 1, in embodiments of the present disclosure only the position of the dashed circles in Fig. The dashed circles represent the color shift position when the human eye looks to the left and right of the array substrate during actual use; that is, the color shift position that exists under normal viewing conditions. For the dark lines other than those in the dashed circles, the color shift position is created when the human eye looks up and down the array substrate. Since the probability of the human eye viewing the scoreboard from the up and down direction of the array substrate is reduced, the dark lines at these positions cannot be shaded. This prevents a reduction in the scoreboard's aperture ratio and simplifies the array substrate manufacturing process, thus reducing the cost of manufacturing array substrates.

[0050] In some embodiments, the pixel electrode 41 of the first type can be a pixel electrode 4 corresponding to the blue color resistor, and the pixel electrode 42 of the second type can comprise a pixel electrode 4 corresponding to the red color resistor or a pixel electrode 4 corresponding to the green color resistor. In some embodiments, the blue color resistor, the red color resistor, and the green color resistor can be located on a counter-substrate opposite the array substrate, such that the display panel emits blue light at the position of the blue color resistor, red light at the position of the red color resistor, and green light at the position of the green color resistor.

[0051] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the array substrate further comprises a first signal wiring layer. The light-shielding section 5 and the first signal wiring layer are on the same layer and comprise the same material. In some embodiments, the first signal wiring layer may be the common signal wiring layer of the array substrate. In some embodiments, a common electrode layer may be arranged on the counter substrate opposite the array substrate, and the signals of the common signal wiring layer of the array substrate and the common electrode layer arranged on the counter substrate may be the same or different.

[0052] In some embodiments, the light-shielding section 5 and the first signal wiring layer are located on the same layer and comprise the same material, and the first signal wiring layer can be arranged on the same layer as a layer on which the gate line groups 2 are located. In this way, the light-shielding section 5 can be formed simultaneously with the formation of the gate line groups 2, and the color shift can be improved while the array substrate fabrication process can be reduced.

[0053] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the first signal wiring layer further comprises: a first common electrode wiring group 230 extending along the second direction Y. The first common electrode wiring group 230 is separated at the position of the gate line group 2. The first common electrode wiring group 230 comprises: two first common electrode wires 23 extending along the second direction Y on opposite sides of the data line 3. The light-shielding section 5 and the first common electrode wire 23 near the first-type pixel electrode 41 in the first common electrode wiring group 230 form an integrated interconnect structure.

[0054] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the width d2 of the second section 52 in the first direction X is 1 to 3 times the width d1 of the first common electrode wire 23 in the first direction X. In this way, it is avoided that if the second section 52 is made wider, this will have a greater impact on the opening rate of the array substrate, and it is also avoided that if the second section 52 is made narrower, light leakage cannot be effectively prevented and the color shift cannot be effectively improved.

[0055] In some embodiments, such as in Fig. 2A and Fig. As shown in 2B, the width d3 of the third section 53 in the first direction is approximately equal to the width d2 of the second section 52 in the first direction X.

[0056] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the width d4 of the first section 51 in the second direction Y is approximately equal to the width d2 of the second section 52 in the first direction X. In the same way, it can be avoided that if the first section 51 is made wider, this will have a greater impact on the aperture rate of the array substrate, and it can also be avoided that if the first section 51 is made narrower, light leakage cannot be effectively avoided and the color shift cannot be effectively improved.

[0057] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the first signal wiring layer further comprises: a second common electrode wire 24 extending along the first direction X. The pixel electrode 4 is provided between the second common electrode wire 24 and the gate conductor group 2. The second common electrode wires 24 in the same direction of extension form an integrated interconnect structure. A gap is located between the second section 52 and the second common electrode wire 24. The first common electrode wire 23, the second common electrode wire 24, and the second section 52 form a first notch 61 with an opening facing the side of the pixel electrode 41 of the first type. In some embodiments, as shown in Fig. As shown in Figure 3, if a short circuit occurs at the jumper of data line 3 and the second common electrode wire 24 due to foreign matter or a break in the gate insulating layer, the second common electrode wire 24 and the data line 3 below the jumper must be cut at both ends. The second common electrode wire 24 below the jumper is "floating" to prevent a short circuit that could occur from direct contact between the data line 3 and the second common electrode wire 24, and the two cut ends of the data line 3 are subsequently connected by a bridge. In embodiments of the present disclosure, the first common electrode wire 23, the second common electrode wire 24, and the second section 52 form the first notch 61, which opens toward one side of the pixel electrode 41 of the first type, such that the cut position (as shown by the thick black line in Figure 3) is... Fig. 3 shown) in the first direction X is narrower, and the problem that the cut cannot be achieved all at once during laser cutting and repair is avoided when the second section 52 is adjusted to improve the color shift.

[0058] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, each gate line group 2 comprises a primary gate line 21 and a secondary gate line 22. The first signal wiring layer further comprises a third common electrode wire 25 located on the side of the secondary gate line 22 furthest from the primary gate line 21 and extending along the first direction X. A pixel electrode 4 is present between the third common electrode wire 25 and the second common electrode wire 24. The third common electrode wire 25, extending in the same direction, is interrupted in the region where the data line 3 is located. A gap is present between the third section 53 and the third common electrode wire 25. The first common electrode wire 23, the third common electrode wire 25, and the third section 53 form a second notch 62 that opens toward one side of the pixel electrode 4.In the embodiment of the disclosure, a gap exists between the third section 53 and the third common electrode wire 25, the first common electrode wire 23, the third common electrode wire 25 and the third section 53 form a second notch 62 with an opening facing one side of the pixel electrode 4, so that the cutting position in the first direction X is narrower, and the problem that the cut cannot be achieved all at once during laser cutting and repair is avoided when the third section 53 is adjusted to improve the color shift.

[0059] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2B, the third common electrode wire 25 comprises a first subsection 251 and a second subsection 252, located on a side of the first subsection 251 furthest from the second notch 62. The width a1 of the first subsection 251 in the second direction X is greater than the width a2 of the second subsection 252 in the second direction X.

[0060] In some embodiments, such as in Fig. 2A, Fig. 2B and Fig. As shown in Figure 2F, the first signal wiring layer further comprises: a fourth common electrode wire 26, located on one side of the primary gate line 21 away from the secondary gate line 22 and extending along the first direction X. A pixel electrode 4 is present between the fourth common electrode wire 26 and the second common electrode wire 24. The fourth common electrode wire 26, extending in the same direction, is interrupted in the region where the data line 3 is located. The array substrate further comprises: a first transistor T1, connected to the data line 3 and located on one side of the data line 3. The fourth common electrode wire 26 has a notch group 60.The notch group 60 comprises: a first notch 64 located on one side of the data line 3, and a third notch 63 located on the other side of the same data line 3, comprising an opening facing one side of the primary gate line 21. The first notch 64 and the first transistor T1 are located on the same side of the data line 3. In some embodiments, the fourth common electrode wire 26 has the third notch 63, so that if a short circuit occurs at the jumper of the data line 3 and the fourth common electrode wire 26 due to foreign matter or a break in the gate insulating layer, the cut position in the second direction Y is narrower, and the problem of not being able to achieve the cut in one go during laser cutting and repair is avoided.In some embodiments, the length of the first notch 64 in the second direction Y can extend through the fourth common electrode wire 26; that is, the first notch is a through-hole. Since the first common electrode wire 23 and the second common electrode wire 24 form a connected structure at the periphery of the same pixel electrode 4 through which the communication signal can be conducted, and the first notch 64 is the through-hole, cutting in the event of a short circuit at the jumper of the data line 3 and the second common electrode wire 24 can be avoided.

[0061] In some embodiments, such as in Fig. 2A and Fig. As shown in Figure 2F, each pixel electrode 4 comprises: a first row of pixel electrodes 410 extending along the first direction X and arranged alternately along the second direction Y, and a second row of pixel electrodes 420. The first row of pixel electrodes 410 is located on the side of the primary gate line 21 furthest from the secondary gate line 22. The second row of pixel electrodes 420 is located on the side of the secondary gate line 22 furthest from the primary gate line 21. The first row of pixel electrodes 410 comprises a plurality of first pixel electrodes 4100, and a second row of pixel electrodes 420 comprises a plurality of second pixel electrodes 4200. In some embodiments, the plurality of first pixel electrodes 4100 (i.e., the first row of pixel electrodes 410) can include a pixel electrode of a first type 41 (e.g., a blue pixel with a light-shielding section 5) and a pixel electrode 42 of a second type. (e.g.The plurality of second pixel electrodes 4200 (i.e., the second row of pixel electrodes 420) may also include a pixel electrode 41 of a first type (e.g., a blue pixel with a light-shielding section 5) and a pixel electrode 42 of a second type (e.g., a red pixel or a green pixel without a light-shielding section 5). In some embodiments, the pattern shape of the first-type pixel electrode 41 in the first row of pixel electrodes 410 may differ from the pattern shape of the first-type pixel electrode in the second row of pixel electrodes 420. The pattern shape of the first-type pixel electrode 41 in the first row of pixel electrodes 410 may also differ from the pattern shape of the second-type pixel electrode 42 in the first row of pixel electrodes 410.The pattern shape of the first-type pixel electrode 41 in the second row of pixel electrodes 420 can differ from the pattern shape of the second-type pixel electrode 42 in the second row of pixel electrodes 420. In some embodiments, in the embodiment of the present disclosure, the colors of color resistors corresponding to the pixel electrodes 4 connected to the same data line 3 are the same on both sides of the same gate line group 2 in the first row of pixel electrodes 410 and the second row of pixel electrodes 420, that is, for example, as in . Fig. As shown in 2A, the colors of the color resistors corresponding to the two pixel electrodes 4, which face each other in the upward and downward directions, are the same.

[0062] In some embodiments, such as in Fig. 2A, Fig. 2D and Fig. As shown in Figure 2F, the layer in which the data line 3 is located further comprises: a first electrode T11 of a first transistor, which is electrically connected to the data line 3, and a first electrode section T12, which is located on one side of the first electrode T11 of the first transistor, as shown in Figure 2F. Fig. Figure 2A shows the first electrode section T12, which is located on the lower side of the first electrode T11 of the first transistor.

[0063] The first electrode section T12 comprises: a second electrode T121 of the first transistor, a first overlap section T122 which is electrically connected to the second electrode T121 of the first transistor, and a second overlap section T123 which extends along the first direction X from one end of the first overlap section T122.

[0064] The orthographic projection of the first overlap section T122 on substrate 1 overlaps with the orthographic projection of the first pixel electrode 4100 on substrate 1. The first overlap section T122 is electrically connected to the first pixel electrode 4100 via a first through-hole K1. The orthographic projection of the second overlap section T123 on substrate 1 overlaps with the orthographic projection of the fourth common electrode wire 26 on substrate 1 to form a first capacitor C1.

[0065] In some embodiments, such as in Fig. 2A and Fig. Shown in 2D, the maximum width b1 of the first overlap section T122 in the second direction Y is greater than the maximum width b2 of the second overlap section T123 in the second direction Y.

[0066] In some embodiments, such as in Fig. 2A, Fig. 2D and Fig. As shown in Figure 2F, the layer containing data line 3 further comprises: a second electrode section T13 located on the other side of the first electrode T11 of the first transistor, e.g., a second electrode section T13 located on the top side of the first electrode T11 of the first transistor in Fig. 2A is located.

[0067] The second electrode section T13 comprises: a third electrode T131 of the first transistor, a third overlap section T132, a first-transistor junction section T133 connecting the third electrode T131 of the first transistor and the third overlap section T132, and a fourth overlap section T134 extending along the first direction X from one end of the third overlap section T132.

[0068] The orthographic projection of the third overlap section T132 on substrate 1 overlaps with the orthographic projection of the second pixel electrode 4200 on substrate 1. The third overlap section T132 is electrically connected to the second pixel electrode 4200 via the second through-hole K2. The orthographic projection of the fourth overlap section T134 on substrate 1 overlaps with the orthographic projection of the third common electrode wire 25 on substrate 1 to form a second capacitor C2.

[0069] In some embodiments, such as in Fig. 2A, Fig. 2D and Fig. As shown in Figure 2F, the maximum width b3 of the third overlap section T132 in the second direction Y is greater than the maximum width b4 of the fourth overlap section T134 in the second direction Y.

[0070] In some embodiments, such as in Fig. 2A, Fig. 2D and Fig. As shown in Figure 2F, the layer in which the data line 3 is located further comprises: a third electrode section T14, which is located on one side of the second electrode section T13 facing the gate line group 2.

[0071] The third electrode section T14 comprises: a second electrode T141 of the second transistor and a fifth overlap section T142, which is connected to the second electrode T141 of the second transistor. The orthographic projection of the fifth overlap section T142 on substrate 1 overlaps with the orthographic projection of the third common electrode wire 25 on substrate 1 to form the third capacitor C3.

[0072] In some embodiments, such as in Fig. 2A and Fig. As shown in 2D, the maximum width b6 of the fifth overlap section T142 in the second direction Y is greater than the maximum width b5 of the second electrode T141 of the second transistor in the second direction Y.

[0073] In some embodiments, such as in Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D and Fig. As shown in Figure 2F, the orthographic projection of the fifth overlap section T142 on substrate 1 does not overlap with the orthographic projection of the fourth overlap section T134 on substrate 1.

[0074] In some embodiments, such as in Fig. 2A, Fig. 2B, Fig. 2C and Fig. Shown in 2D, the first transistor T1 comprises: a control electrode T10 of the first transistor, an active layer T15 of the first transistor, a first electrode T11 of the first transistor, a second electrode T121 of the first transistor, and a third electrode T131 of the first transistor. The control electrode of the first transistor T10 is part of the primary gate line 21.

[0075] In some embodiments, such as in Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D and Fig. As shown in 2F, the array substrate also includes a second transistor T2.

[0076] The second transistor T2 comprises: the control electrode T20 of the second transistor, the active layer T25 of the second transistor, the first electrode T21 of the second transistor, and the second electrode T141 of the second transistor. The control electrode T20 of the second transistor is part of the secondary gate line 22, and the first transistor interconnect T133 is multiplexed as the first electrode T21 of the second transistor.

[0077] In some embodiments, in combination with Fig. 2A, Fig. 2C and Fig. 7, the array substrate further comprises an active layer and a passivation layer 12, which covers one side of the active layer facing away from the substrate 1. The active layer comprises the active layer T15 of the first transistor and the active layer T25 of the second transistor. The material of the active layer comprises indium gallium zinc oxide, and the material of the passivation layer 12 comprises silicon dioxide and silicon nitride.

[0078] In some embodiments, such as in Fig. As shown in Figure 7, the active layer (comprising the first active layer T15) is located on the side of the primary gate line 21 furthest from substrate 1. The layer containing data line 3 (comprising the first electrode T11 of the first transistor) is located on the same side of the active layer (comprising the first active layer T15) as the primary gate line 21. The pixel electrode 4 is located on the same side of the layer (comprising the first electrode T11 of the first transistor) as the active layer, as the data line 3 is located.The array substrate further comprises a gate insulating layer 11 located between the active layer (which includes the first active layer T15) and the primary gate line 21, a planarization layer 13 located on a side of the passivation layer 12 away from the substrate 1, and a first alignment film layer 14 located on a side of the pixel electrode 4 away from the substrate 1.

[0079] In some embodiments, such as in Fig. 4 shown, can Fig. 4 the equivalent circuit diagram that represents the upper and lower pixel electrodes 4 in Fig. 2A corresponds to the circuit comprising: the first transistor T1, the second transistor T2, the first capacitor C1, the second capacitor C2, the third capacitor C3, the first liquid crystal capacitor Clc1, the second liquid crystal capacitor Clc2.

[0080] The control electrode T10 of the first transistor T1 is electrically connected to the primary gate line 21, the first electrode T11 of the first transistor T1 is electrically connected to the data line 3, the second electrode T121 of the first transistor T1 is electrically connected to one end of the first capacitor C1, and the third electrode T131 of the first transistor T1 is electrically connected to one end of the second capacitor C2.

[0081] The control electrode T20 of the second transistor T2 is electrically connected to the secondary gate line 22, the first electrode T21 of the second transistor T2 is electrically connected to the third electrode T131 of the first transistor T1, and the second electrode T141 of the second transistor is electrically connected to one end of the third capacitor C3.

[0082] The other end of the first capacitor C1 is electrically connected to the fourth common electrode wire 26. The other end of the second capacitor C2 is electrically connected to the third common electrode wire 25. The other end of the third capacitor C3 is electrically connected to the third common electrode wire 25. The first pixel electrode 4100 and the common electrode of the counter substrate form the first liquid crystal capacitance Clc1. The second pixel electrode 4200 and the common electrode of the counter substrate form the second liquid crystal capacitance Clc2.

[0083] In some embodiments, the array substrate can further comprise a plurality of cascaded gate driver units. The nth primary gate line 21 can be electrically connected to the gate driver unit of the nth level to transmit the gate signal output by the gate driver unit of the nth level. The secondary gate line 22 can be electrically connected to the gate driver unit of the (n+m)th level. That is, the gate driver unit of the (n+m)th level is electrically connected to the primary gate line 21 of the (n+m)th row and is also electrically connected to the secondary gate line 22 of the nth row to provide a gate signal to the primary gate line 21 of the (n+m)th row. Simultaneously, the gate signal is provided to the secondary gate line 22 of the nth row to turn on the (n+m)th row of the first transistor T1 while simultaneously turning on the nth row of the second transistor T2.so that the second pixel electrode 4200 in the nth row (in some embodiments, the pixel electrodes 4 on the upper and lower sides of a gate conductor group 2 can be used as one pixel electrode row, that is, one pixel electrode row can comprise: the first pixel electrode row 410 and the second pixel electrode row 420; the second pixel electrode 4200 of the nth row can be understood as the second pixel electrode 4200 of the second pixel electrode row 420 in the nth pixel electrode row.) achieves a voltage division through the third capacitor C3, which is passed through the second transistor T2, such that the electrode voltage of the second pixel electrode 4200 is lower than the electrode voltage of the first pixel electrode 4100, therefore the luminance of the second pixel electrode 4200 is lower than the luminance of the first pixel electrode 4100, so that the second pixel electrode row 420 is a dark pixel electrode row,and the first pixel electrode row 410 is a bright pixel electrode row, so that the pixels of the same luminance color have more luminance levels, and the problem of color shift of the liquid crystal display panel can be improved.

[0084] In some embodiments, m ≧ 1, m = 6, for example, when n = 1, m = 6, that is, the gate driver unit of the seventh level is electrically connected to the primary gate line 21 of the seventh row, and also electrically to the secondary gate line 22 of the first row, in order to provide a gate signal to the primary gate line 21 of the seventh row, and simultaneously to provide a gate signal to the secondary gate line 22 of the first row, so that when the seventh row of the first transistor T1 is switched on, the first row of the second transistor T2 is also switched on simultaneously, thus reducing the luminance of the second pixel electrode 4200 in the first row.

[0085] In some embodiments, see Fig. 5A, Fig. 5B, Fig. 5C, is Fig. 5B a schematic cross-sectional diagram along the dashed line AA' in Fig. 5A. Fig. 5C is a schematic cross-section along the dashed line BB' in Fig. 5A. The array substrate further comprises: a first wiring 71, a second wiring 72 and an adapter section 73.

[0086] A first insulating layer G1 is present between the adapter section 73 and the first wiring 71. The first insulating layer G1 is provided with a third through-hole K3. The third through-hole K3 exposes parts of the first wiring 71 and parts of the substrate 1.

[0087] A second insulating layer G2 is provided between the adapter section 73 and the second wiring 72. The second insulating layer G2 is provided with a fourth through-hole K4. The fourth through-hole K4 exposes parts of the second wiring 72 and parts of the substrate 1.

[0088] One end of the adapter section 73 covers the third hole K3 and contacts the first wiring 71 through the third hole K3, the other end covers the fourth through hole K4, contacts the second wiring 72 through the fourth through hole K4, and overlaps the first wiring 71 with the second wiring 72.

[0089] In the conventional design, when the first alignment film layer 14 is formed, the alignment fluid flow passes through a full hanging hole with a small through-hole size (e.g., less than or equal to 8 µm*8 µm) and a larger hole depth. Due to the fluid tension of the alignment fluid, its flowability is poor, and the alignment fluid cannot flow normally above the through-hole. The alignment fluid does not adhere, and a halo effect similar to that seen around the through-hole is formed. The macroscopic manifestation is a moiré pattern on the screen.In the embodiment of the disclosure, when the first wiring 71 and the second wiring 72 are overlapped and electrically connected, the original fully suspended hole is optimized to a half-suspended hole design, and the third hole K3 and the fourth through-hole K4 are designed as a half-through-hole design (i.e., for example, the third hole K3 exposes parts of the first wiring 71 and exposes parts of the substrate 1), such that the third hole K3 and the fourth through-hole K4 form an internal step structure, which has the technical effect of draining the alignment fluid, preventing non-adherence of the alignment fluid, and avoiding the moiré pattern phenomenon in the screen.

[0090] In some embodiments, the first wiring 71 may comprise: the primary gate line 21, the secondary gate line 22, the data line 3, the first common electrode wire 23, the second common electrode wire 24, the third common electrode wire 25 or the fourth common electrode wire 26.

[0091] The second wiring 72 can include: the primary gate line 21, the secondary gate line 22, the data line 3, the first common electrode wire 23, the second common electrode wire 24, the third common electrode wire 25 or the fourth common electrode wire 26.

[0092] In some embodiments, the adapter section 73 and the pixel electrode 4 are on the same layer and made of the same material.

[0093] In some embodiments, such as in Fig. As shown in Figure 7, the first insulating layer G1 can comprise: a gate insulating layer 11, a passivation layer 12 and / or a planarization layer 13. The second insulating layer G2 comprises: an insulating layer 11, a passivation layer 12 and / or a planarization layer 13.

[0094] In some embodiments, for example as in Fig. 6 shown, is Fig. 6 an enlarged schematic diagram at the dashed circle S in Fig. 2A, that is, the first wiring is a third common electrode wire 25 above the gate conductor group 2, the second wiring 72 is a fourth common electrode wire 26 below the gate conductor group 2. The third common electrode wire 25 on the upper side of the gate conductor group 2 is electrically connected via an adapter section 73. The third through-hole K3, which connects the adapter section 73 and the third common electrode wire 25 on the upper side of the gate conductor group 2, is a half-through hole. The fourth through-hole K4, which connects the adapter section 73 and the fourth common electrode wire 26 on the lower side of the gate conductor group 2, is a half-through hole design.

[0095] Based on the same inventive idea, embodiments of the present disclosure further provide an array substrate, as shown in Fig. 8A to Fig. 8D shown. Fig. 8B is a schematic diagram of a single layer of gate line 20 in Fig. 8A. Fig. 8C is a schematic diagram of a single layer of the data line in Fig. 8A. Fig. 8D is a schematic diagram of a single layer of the pixel electrode in Fig. 8A.

[0096] The array substrate includes: a substrate 1; a multitude of gate lines 20 located on one side of the substrate 1 and extending along the first direction X; a multitude of data lines 3, which are located on the same side of the substrate 1 as the gate line 20 and extend along the second direction; a multitude of pixel electrodes 4 located on the same side of the substrate 1 as the gate line 20 and situated in the areas formed by the intersection of the gate lines 20 and the data lines 3.

[0097] Each data line 3 comprises a first data segment 31 extending along the second direction Y, a second data segment 32 extending along the second direction Y, and a third data segment 33 extending along the first direction X and connecting the first data segment 31 to the second data segment 32. The extension line of the first data segment 31 does not overlap with the extension line of the second data segment 32. The orthographic projection of the extension line of the third data segment 33 passes through the central region of the orthographic projection of the pixel electrode 4 on the substrate 1. The orthographic projection of the first data segment 31 on the substrate 1 overlaps with the orthographic projection of the first side region 43 of the pixel electrode 4 on the substrate 1.The orthographic projection of the second data section 32 on the substrate 1 overlaps with the orthographic projection of the second side area 44 of the pixel electrode 4 on the substrate 1.

[0098] In embodiments of the disclosure, the data line 3 comprises a first data section 31 extending along the second direction Y, a second data section 32 extending along the second direction Y, and a third data section 33 extending along the first direction X and connecting the first data section 31 to the second data section 32, so that the first side region 43 and the second side region 44 of the pixel electrode 4 can be shielded from light leakage.

[0099] In some embodiments, such as in Fig. 8A and Fig. As shown in Figure 8C, the length e1 of the third data section 33 in the first direction X is 2 to 4 times the width e2 of the first data section 31 in the first direction X.

[0100] In some embodiments, such as in Fig. 8A and Fig. As shown in Figure 8C, the array substrate further comprises: a second electrode T32 of the transistor, which is located on the same layer as the layer containing the data line 3, and a first electrode block T33, which is connected to the second electrode T32 of the transistor.

[0101] The first electrode block T33 is located at a position between two adjacent third data sections 33. The orthographic projection of the first electrode block T33 onto the substrate 1 overlaps with the orthographic projection of the pixel electrode 4 onto the substrate 1. The first electrode block T33 is electrically connected to the pixel electrode 4 via the fifth through-hole K5.

[0102] In some embodiments, such as in Fig. 8A and Fig. As shown in Figure 8B, the array substrate further comprises: a fifth common electrode wiring group 270. The fifth common electrode wiring group 270 comprises two fifth common electrode wires 27 extending along the first direction X.

[0103] A second electrode block 271 is provided between two fifth common electrode wirings 27 in the same fifth common electrode wiring group 270. The orthographic projection of the second electrode block 271 on the substrate 1 overlaps with the orthographic projection of the first common electrode block T33 on the substrate 1 to form a fourth capacitor C4.

[0104] Based on the same inventive concept, embodiments of the disclosure further provide a display panel comprising the array substrate provided as embodiments of the present disclosure.

[0105] In some embodiments, such as in Fig. As shown in Figure 7, the display panel further comprises a counter-substrate opposite the array substrate. The counter-substrate is provided with a common electrode layer 93. In some embodiments, the counter-substrate may comprise a counter-base substrate 90, a black matrix layer 91 arranged between the counter-base substrate 90 and the common electrode layer 93, and a color resistance layer. The color resistance layer may comprise a blue color resistor 921, a red color resistor 922, and a green color resistor. A second alignment film layer 94 may also be arranged on a side of the common electrode layer 93 opposite the counter-base substrate 90. In some embodiments, as shown in Figure 7, the counter-base substrate 90 is provided with a common electrode layer 93. Fig. As shown in Figure 8A, the black matrix layer 91 can include a black matrix aperture 910.

[0106] In some embodiments, the display panel further comprises a liquid crystal layer arranged between the array substrate and the counter substrate. The liquid crystal layer has four liquid crystal regions in the area where the pixel electrodes 4 are located. The liquid crystal orientations in the liquid crystal regions are different. In some embodiments, as in Fig.As shown in Figure 9, the liquid crystal layer has, for example, four liquid crystal regions in the area where the pixel electrodes 4 are located, namely the first region, the second region, the third region, and the fourth region. The orientations of the liquid crystal corresponding to the first region, the second region, the third region, and the fourth region are different. In some embodiments, the orientations of the four liquid crystal regions corresponding to one pixel electrode are different, which can be achieved by irradiating the first alignment film layer and the second alignment film with ultraviolet light or by other methods to achieve different orientations.For example, the area of ​​the first alignment film corresponding to a pixel electrode is subdivided along the direction of the data line into a left and a right part. The alignment directions of the left and right parts are parallel and opposite to each other. The area of ​​the second alignment film corresponding to a pixel electrode is subdivided along the direction of the gate line into an upper and a lower part. The alignment directions of the upper and lower parts are parallel and opposite to each other. The alignment directions of the first and second alignment film layers are perpendicular to each other, ultimately forming four distinct alignment areas.

[0107] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising a display panel provided in embodiments of the present disclosure. The display device may be: mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigation devices, smartwatches, fitness trackers, personal digital assistants, and any other products or components with display functions. The other essential components of the display device are self-evident to those skilled in the art and are not repeated here, nor should they be used to limit the present invention.Furthermore, the embodiment of the display device can refer to the embodiment of the liquid crystal display board described above, since the principle of the display device for solving the problem is similar to the principle of the display board for solving the problem, and repetition is omitted.

[0108] Although preferred embodiments of the present invention have been described, these embodiments may be subject to further changes and modifications once the basic inventive concepts are known to those skilled in the art. Therefore, the appended claims are to be interpreted as encompassing the preferred embodiments and all changes and modifications that fall within the scope of the invention.

[0109] Obviously, a person skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, the present invention is to be understood as also encompassing such modifications and variations, provided that these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and its equivalents.

Claims

[1] Array substrate comprising: a substrate; a plurality of gate conduction groups on one side of the substrate, wherein the plurality of gate conduction groups extend along a first direction; a multitude of data lines on the same side of the substrate as the gate line groups; wherein the multitude of data lines extend along a second direction; a plurality of pixel electrodes on the same side of the substrate as the gate conductor groups and in an area formed by a crossing of the gate conductor groups and the data lines, wherein the plurality of pixel electrodes comprises: a pixel electrode of a first type and a pixel electrode of a second type; a light-shielding section on the same side of the substrate as the gate conduction groups and only in a region where the pixel electrode of the first type is located; wherein the light-shielding section comprises: a first section extending in the first direction; an orthographic projection of the first section on the substrate passing through a central region of an orthographic projection of the pixel electrode of the first type on the substrate. [2] Array substrate according to claim 1, wherein the light-shielding section further comprises: a second section located on one side of the first section and extending along the second direction; the second section being connected to an end of the first section, and an orthographic projection of the second section onto the substrate overlapping with an orthographic projection of a side region of the pixel electrode of the first type onto the substrate. [3] Array substrate according to claim 1 or 2, wherein the light-shielding section further comprises: a third section located on the other side of the first section and extending along the second direction; the third section being connected to the other end of the first section, and an orthographic projection of the third section onto the substrate overlapping with an orthographic projection of the other side region of the pixel electrode of the first type onto the substrate. [4] Array substrate according to any one of claims 1 to 3, wherein the pixel electrode of the first type is a pixel electrode corresponding to a blue color resistance, and the pixel electrode of the second type comprises a pixel electrode corresponding to a red color resistance, or a pixel electrode corresponding to a green color resistance. [5] Array substrate according to claim 3 or 4, further comprising: a first signal wiring layer, wherein the light-shielding section and the first signal wiring layer are on the same layer and made of the same material. [6] Array substrate according to claim 5, wherein the first signal wiring layer further comprises: a first common electrode wiring group extending along the second direction, wherein the first common electrode wiring group is separated at the gate line groups; the first common electrode wiring group comprises: two first common electrode wires extending along the second direction and located on opposite sides of each data line, and the light-shielding section and the first common electrode wire near the pixel electrode of the first type in the first common electrode wiring group form an integrated interconnect structure. [7] Array substrate according to claim 6, wherein the width of the second section in the first direction is 1 to 3 times the width of the first common electrode wire in the first direction. [8] Array substrate according to claim 6 or 7, wherein a width of the third section in the first direction is substantially equal to a width of the second section in the first direction. [9] Array substrate according to any one of claims 6 to 8, wherein a width of the first section in the second direction is substantially equal to a width of the second section in the first direction. [10] Array substrate according to any one of claims 6 to 9, wherein the first signal wiring layer further comprises: a second common electrode wire extending along the first direction; a pixel electrode being provided between the second common electrode wire and the gate wiring group, and the second common electrode wire being an integrated interconnect structure in the same direction of extension; a gap being provided between the second section and the second common electrode wire; and the first common electrode wire, the second common electrode wire and the second section forming a first notch with an opening facing one side of the pixel electrode of the first type. [11] Array substrate according to claim 10, wherein each gate line group comprises: a primary gate line and a secondary gate line; the first signal wiring layer further comprises: a third common electrode wire, which is located on a side of the secondary gate line furthest from the primary gate line and extends along the first direction; The pixel electrode is present between the third common electrode wire and the second common electrode wire, and the third common electrode wire is separated in the same direction of extension in an area where the data line is located; There is a gap between the third section and the third common electrode wire; and the first common electrode wire, the third common electrode wire and the third section form a second notch with an opening facing one side of the pixel electrode. [12] Array substrate according to claim 11, wherein the third common electrode wire comprises: a first subsection and a second subsection located on a side of the first subsection away from the second notch; a width of the first subsection in the second direction is greater than a width of the second subsection in the second direction. [13] Array substrate according to claim 11, wherein the first signal wiring layer further comprises: a fourth common electrode wire arranged on a side of the primary gate line away from the secondary gate line and extending along the first direction; The pixel electrode is present between the fourth common electrode wire and the second common electrode wire, and the fourth common electrode wire is separated in the same direction of extension in an area where the data line is located; The array substrate further comprises: a first transistor connected to the data line and located on one side of the data line; the fourth common electrode wire comprises a notch group, the notch group comprising: a first notch located on one side of a data line, and a third notch located on the other side of the one data line, and comprising an opening facing one side of the primary gate line, and the first notch and the first transistor being located on the same side of the one data line. [14] Array substrate according to claim 13, wherein the plurality of pixel electrodes comprise: a first row of pixel electrodes and a second row of pixel electrodes extending along the first direction and arranged alternately along the second direction; the first row of pixel electrodes is arranged on a side of the primary gate line furthest from the secondary gate line, and the second row of pixel electrodes is arranged on a side of the secondary gate line furthest from the primary gate line; The first pixel electrode row comprises a multitude of first pixel electrodes, and the second pixel electrode row comprises a multitude of second pixel electrodes. [15] Array substrate according to claim 14, wherein a layer in which the data line is located further comprises: a first electrode of the first transistor which is electrically connected to the data line, and a first electrode section which is arranged on one side of the first electrode of the first transistor; the first electrode section comprises: a second electrode of the first transistor, a first overlap section electrically connected to the second electrode of the first transistor, and a second overlap section extending along the first direction from one end of the first overlap section; an orthographic projection of the first overlap section on the substrate overlaps with an orthographic projection of the first pixel electrode on the substrate, the first overlap section is electrically connected to the first pixel electrode via a first through-hole, and an orthographic projection of the second overlap section on the substrate overlaps with an orthographic projection of the fourth common electrode wire on the substrate to form a first capacitance. [16] Array substrate according to claim 14 or 15, wherein a maximum width of the first overlap section in the second direction is greater than a maximum width of the second overlap section in the second direction. [17] Array substrate according to one of claims 14 to 16, wherein the layer in which the data line is located further comprises: a second electrode section arranged on the other side of the first electrode of the first transistor; the second electrode section comprises: a third electrode of the first transistor, a third overlap section, a first-transistor junction section connecting the third electrode of the first transistor and the third overlap section, and a fourth overlap section extending along the first direction from one end of the third overlap section; an orthographic projection of the third overlap section on the substrate overlaps with an orthographic projection of the second pixel electrode on the substrate, the third overlap section being electrically connected to the second pixel electrode via a second through-hole; an orthographic projection of the fourth overlap section on the substrate overlaps with an orthographic projection of the third common electrode wire on the substrate to form a second capacitance. [18] Array substrate according to claim 17, wherein a maximum width of the third overlap section in the second direction is greater than a maximum width of the fourth overlap section in the second direction. [19] Array substrate according to claim 17 or 18, wherein the layer in which the data line is located further comprises: a third electrode section arranged on a side of the second electrode section facing the gate conductor group; the third electrode section comprises: a second electrode of the second transistor and a fifth overlap section connected to the second electrode of the second transistor; an orthographic projection of the fifth overlap section on the substrate overlapping with the orthographic projection of the third common electrode wire on the substrate to form a third capacitance. [20] Array substrate according to claim 19, wherein a maximum width of the fifth overlap section in the second direction is greater than a maximum width of the second electrode of the second transistor in the second direction. [21] Array substrate according to claim 19 or 20, wherein the orthographic projection of the fifth overlap section on the substrate does not overlap with the orthographic projection of the fourth overlap section on the substrate. [22] Array substrate according to any one of claims 19 to 21, wherein the first transistor comprises: a control electrode of the first transistor, an active layer of the first transistor, the first electrode of the first transistor, the second electrode of the first transistor and the third electrode of the first transistor; wherein the control electrode of the first transistor is a section of the primary gate line. [23] Array substrate according to claim 22, further comprising: a second transistor; the second transistor comprising: a control electrode of the second transistor, an active layer of the second transistor, a first electrode of the second transistor, the second electrode of the second transistor; wherein the control electrode of the second transistor is a section of the secondary gate line, the first transistor interconnect section is multiplexed as the first electrode of the second transistor. [24] Array substrate according to any one of claims 1 to 23, further comprising an active layer and a passivation layer covering a side of the active layer away from the substrate; the active layer comprising the active layer of the first transistor and the active layer of the second transistor; a material of the active layer comprising indium gallium zinc oxide, and a material of the passivation layer comprising silicon dioxide and silicon nitride. [25] Array substrate according to any one of claims 13 to 24, further comprising: a first wiring, a second wiring and an adapter section; a first insulating layer is present between the adapter section and the first wiring; the first insulating layer includes a third through-hole; the third through-hole exposes part of the first wiring and part of the substrate; a second insulating layer is present between the adapter section and the second wiring; the second insulating layer includes a fourth through-hole; the fourth through-hole exposes part of the second wiring and part of the substrate; one end of the adapter section covers the third through-hole and is in contact with the first wiring via the third through-hole; the other end of the adapter section covers the fourth through-hole and is in contact with the second wiring via the fourth through-hole; the adapter section overlaps the first wiring with the second wiring. [26] Array substrate according to claim 25, wherein the first wiring comprises the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire or the fourth common electrode wire; the second wiring comprises: the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire or the fourth common electrode wire. [27] Array substrate according to claim 25 or 26, wherein the adapter section and the pixel electrode are on the same layer and made of the same material. [28] Array substrate according to any one of claims 25 to 27, wherein the first insulating layer comprises a gate insulating layer, a passivation layer and / or a planarization layer; the second insulating layer comprises an insulating layer, a passivation layer and / or a planarization layer. [29] Array substrate, comprising: a substrate; a multitude of gate lines on one side of the substrate, extending in a first direction; a multitude of data lines on the same side of the substrate as the gate lines, extending along a second direction; a multitude of pixel electrodes on the same side of the substrate as the gate lines and in areas formed by a crossing of the gate lines and the data lines; wherein each data line comprises a first data segment extending in the second direction, a second data segment extending in the second direction, and a third data segment extending along the first direction and connecting the first data segment to the second data segment; an extension line of the first data segment does not overlap with an extension line of the second data segment; an orthographic projection of an extension line of the third data segment on the substrate passes through a central area of ​​an orthographic projection of the pixel electrode on the substrate; an orthographic projection of the first data section on the substrate overlaps with an orthographic projection of a first side region of the pixel electrode on the substrate; an orthographic projection of the second data section on the substrate overlaps with an orthographic projection of a second side region of the pixel electrode on the substrate. [30] Array substrate according to claim 29, wherein the length of the third data section in the first direction is 2 to 4 times the width of the first data section in the first direction. [31] Array substrate according to claim 29 or 30, further comprising: a second electrode of a transistor in the same layer as a layer in which the data lines are located, and a first electrode block connected to the second electrode of the transistor; the first electrode block being arranged at a position between two adjacent third data sections; an orthographic projection of the first electrode block on the substrate overlapping with the orthographic projection of the pixel electrode on the substrate, and the first electrode block being electrically connected to the pixel electrode via a fifth through-hole. [32] Array substrate according to claim 31, further comprising: a fifth common electrode wiring group; the fifth common electrode group comprises: two fifth common electrode wires extending along the first direction; a second electrode block is provided between two fifth common electrode wires in an identical fifth common electrode wiring group, and an orthographic projection of the second electrode block on the substrate overlaps with an orthographic projection of the first common electrode block on the substrate to form a fourth capacitor. [33] Display panel comprising the array substrate according to any one of claims 1 to 28 or the array substrate according to any one of claims 29 to 32. [34] Display panel according to claim 33, further comprising: a counter-substrate opposite the array substrate, wherein the counter-substrate is provided with a common electrode layer. [35] Display panel according to claim 33, further comprising a liquid crystal layer arranged between the array substrate and the counter substrate; wherein the liquid crystal layer comprises four liquid crystal regions in a region in which the pixel electrodes are located, and liquid crystal orientations are different in the liquid crystal regions. [36] Display device comprising the display panel according to any one of claims 33 to 35.

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