ARRAY SUBSTRATE, DISPLAY FIELD AND DISPLAY DEVICE

Abstract

An array substrate, a display array, and a display device. The array substrate comprises a plurality of pixel driver circuits and a base substrate, wherein the plurality of pixel driver circuits are arranged in a plurality of rows and a plurality of columns, each of the plurality of pixel driver circuits comprising a plurality of transistors, and wherein the array substrate further comprises a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is arranged on one side of the base substrate and comprises a plurality of first-type light-shielding wires. The semiconductor layer is arranged on a side of the light-shielding layer facing away from the base substrate and comprises active layer patterns of the plurality of transistors.The first gate layer is arranged on a side of the semiconductor layer facing away from the base substrate and comprises a plurality of sampling signal lines, each of which crosses an active layer pattern of at least one transistor, and the plurality of sampling signal lines transmit sampling signals. Each of the plurality of first-type optical shielding wires crosses an active layer pattern of at least one transistor, and the first-type optical shielding wires transmit sampling signals.

Description

[0001] The present application claims priority over the Chinese patent application with file number 202310996423.2, which was filed on August 8, 2023, and the entire contents of which are hereby incorporated by reference. TECHNICAL AREA

[0002] The present disclosure relates to the field of display technologies, in particular an array substrate, a display field and a display device. STATE OF THE ART

[0003] Organic light-emitting diode (OLED) display panels have gradually become one of the mainstream products in the display sector due to their excellent properties such as low power consumption, high color saturation, wide viewing angle, low thickness and flexibility. REVELATION OF THE INVENTION

[0004] According to one aspect, an array substrate is provided. The array substrate comprises a plurality of pixel driver circuits, the plurality of pixel driver circuits being arranged in a plurality of rows and a plurality of columns, and each of the plurality of pixel driver circuits comprising a plurality of transistors. The array substrate includes: a base substrate, a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is arranged on one side of the base substrate and comprises a plurality of first light-shielding wires. The semiconductor layer is arranged on the side of the light-shielding layer facing away from the base substrate, the semiconductor layer comprising active layer patterns of the plurality of transistors.The first gate layer is arranged on a side of the semiconductor layer facing away from the base substrate, wherein the first gate layer comprises a plurality of sampling signal lines and each of the sampling signal lines crosses an active layer pattern of at least one transistor; and the plurality of sampling signal lines transmit sampling signals, wherein each of the plurality of light shielding wires of the first type crosses an active layer pattern of at least one transistor; wherein a light shielding wire of the first type and a sampling signal line crossing an active layer pattern of the same transistor transmit the same sampling signal.

[0005] In some embodiments, the transistors of each pixel driver circuit comprise a compensation transistor and a data write transistor, and the plurality of sampling signal lines comprises first sampling signal lines, wherein orthographic projections of the active layer patterns of the compensation transistors and the data write transistors in a series of pixel driver circuits on the base substrate overlap with an orthographic projection of a first sampling signal line on the base substrate; wherein the plurality of light shielding wires of the first type comprise first light shielding wires, wherein the orthographic projections of the active layer patterns of the compensation transistors and the data write transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of a first light shielding wire on the base substrate;and wherein the first light shielding wire and the first scanning signal line transmit a first scanning signal.

[0006] In some embodiments, the transistors of each pixel driver circuit further comprise a first reset transistor, and the plurality of sampling signal lines comprise second sampling signal lines, wherein orthographic projections of the active layer patterns of the first reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of a second sampling signal line on the base substrate; wherein the plurality of light-shielding wires of the first type comprise second light-shielding wires, wherein the orthographic projections of the active layer patterns of the first reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of a second light-shielding wire on the base substrate; and wherein the second light-shielding wire and the second sampling signal line carry a second sampling signal.

[0007] In some embodiments, the first scanning signal line and the second scanning signal line, which overlap with the same series of pixel driver circuits, transmit the same signal; wherein the array substrate comprises a display area and a perimeter area, the plurality of light-shielding wires of the first type extending along a line direction to the perimeter area, wherein areas of the perimeter area located on both sides of the display area along the line direction are each a first area and a second area; and wherein the first light-shielding wire and the second light-shielding wire, which overlap with the same series of pixel driver circuits, are electrically connected in the first area and / or in the second area.

[0008] In some embodiments, the array substrate further comprises at least one gate driver circuit located in the periphery, wherein the gate driver circuit comprises a plurality of shift registers, each shift register being configured to transmit a sampling signal to an array of pixel driver circuits; wherein each shift register comprises an output terminal electrically connected to the first sampling signal line and the second sampling signal line associated with the array of pixel driver circuits;and wherein the array substrate further comprises a source-drain metal layer located on a side of the first gate layer facing away from the light-shielding layer, the source-drain metal layer comprising a plurality of first interconnecting lines, each first interconnecting line being electrically connected at one end to an output terminal and at the other end to a first light-shielding wire or a second light-shielding wire.

[0009] In some embodiments, the first light shielding wire is electrically connected to the first scanning signal line and the second light shielding wire is electrically connected to the second scanning signal line.

[0010] In some embodiments, the array substrate comprises a display area and a perimeter area, wherein the plurality of light-shielding wires of the first type extends along a line direction to the perimeter area, wherein areas of the perimeter area located on both sides of the display area along the line direction are each a first area and a second area; and wherein the first light-shielding wire is electrically connected to the first scanning signal line in the first area and / or in the second area, and the second light-shielding wire is electrically connected to the second scanning signal line in the first area and / or in the second area.

[0011] In some embodiments, the transistors of each pixel driver circuit further comprise a second reset transistor, and the plurality of sampling signal lines comprise third sampling signal lines; wherein orthographic projections of the active layer patterns of the second reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of the third sampling signal line on the base substrate; wherein the plurality of light-shielding wires of the first type comprise third light-shielding wires, wherein the orthographic projections of the active layer patterns of the second reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of the third light-shielding wire on the base substrate; and wherein the third light-shielding wire and the third sampling signal line carry a third sampling signal.

[0012] In some embodiments, a third sampling signal line associated with an nth row of pixel driver circuits and a second sampling signal line associated with an (n-1)th row of pixel driver circuits are the same signal line.

[0013] In some embodiments, the transistors of each pixel driver circuit further comprise a driver transistor and the light-shielding layer comprises a plurality of second-type light-shielding wires; wherein orthographic projections of the active layer patterns of the driver transistors in a series of pixel driver circuits on the base substrate overlap with an orthographic projection of a second-type light-shielding wire on the base substrate; and wherein the second-type light-shielding wire carries a first voltage signal.

[0014] In some embodiments, a source-drain metal layer is provided which is arranged on a side of the first gate layer facing away from the light-shielding layer, wherein the source-drain metal layer comprises first voltage signal lines and a first voltage signal line is electrically connected to the second type of light-shielding wire.

[0015] In some embodiments, each second-type light shielding wire overlaps with the driver transistors in a series of pixel driver circuits, and each column of pixel driver circuits is connected to a corresponding first voltage signal line; and wherein at least three adjacent pixel driver circuits in each series of pixel driver circuits form a pixel driver circuit group, and a first voltage signal line connected to at least one pixel driver circuit in the pixel driver circuit group is connected to the second-type light shielding wire.

[0016] In some embodiments, the array substrate comprises a display area and a perimeter area, and the first voltage signal lines are electrically connected to each other in the perimeter area.

[0017] In some embodiments, the second type of light-shielding wire comprises a plurality of light-shielding patterns and a plurality of interconnection patterns arranged alternately, each interconnection pattern being connected to two adjacent light-shielding patterns, wherein an orthographic projection of each light-shielding pattern on the base substrate surrounds an orthographic projection of a driver transistor of a pixel driver circuit on the base substrate.

[0018] According to another aspect, a display field is provided which includes the array substrate described in one of the embodiments mentioned above.

[0019] According to another aspect, a display device is provided which includes the display field described in one of the embodiments mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly describe the technical solutions in the present disclosure, the drawings used in some embodiments of the present disclosure are briefly presented. It is understood that the drawings described below are merely drawings of some embodiments of the present disclosure and that a person skilled in the art in the relevant technical field can derive other drawings from these drawings. Furthermore, the drawings in the following description may be considered schematic representations. They do not represent any limitations regarding the actual sizes of the products, the actual processes of the procedures, the actual timing of signals, etc., contained in the embodiments of the present disclosure. Fig. 1 is a top view showing a structure of a display device according to some embodiments; Fig. Figure 2 is a sectional view showing the structure of an array substrate according to some embodiments; Fig. 3 is a structural diagram of an equivalent circuit of a pixel driver circuit according to some embodiments; Fig. 4A is a structural diagram of a pixel driver circuit according to some embodiments; Fig. Figure 4B is a top view showing the structure of a light-shielding layer of an array substrate according to some embodiments; Fig. 4C is a structural diagram of a semiconductor layer of an array substrate according to some embodiments; Fig. 4D is a structural diagram of a first gate layer of an array substrate according to some embodiments; Fig. Figure 4E is a structural diagram of a second gate layer of an array substrate according to some embodiments; Fig. Figure 5A is a structural diagram showing a connection between a light shielding wire and a shift register of an array substrate according to some embodiments; Fig. Figure 5B is a structural diagram showing a further connection between a light shielding wire and a shift register of an array substrate according to some embodiments; Fig. Figure 5C is a structural diagram showing a further connection between a light shielding wire and a shift register of an array substrate according to some embodiments; Fig. Figure 6A is a structural diagram showing a connection between a light shielding wire and a scanning signal line of an array substrate according to some embodiments; Fig. Figure 6B is a structural diagram showing a further connection between a light shielding wire and a scanning signal line of an array substrate according to some embodiments; Fig. Figure 6C is a structural diagram showing a further connection between a light shielding wire and a scanning signal line of an array substrate according to some embodiments; Fig. Figure 7 is a sectional view showing another structure of an array substrate according to some embodiments; Fig. Figure 8A is a structural diagram showing a connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 8B is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 8C is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 9A is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 9B is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 9C is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 9D is a structural diagram showing a further connection between a first voltage signal line and a second type of light shielding wire of an array substrate according to some embodiments; Fig. Figure 10 is a structural diagram of first voltage signal lines of an array substrate according to some embodiments; and Fig. Figure 11 is a sectional view showing the structure of a display field according to some embodiments. SPECIFIC EXECUTION FORMS

[0021] The technical solutions in some embodiments of the present disclosure are clearly and completely described below with reference to the drawings, whereby the described embodiments naturally represent only some, but not all, embodiments of the present disclosure. All other embodiments that a person skilled in the art in the relevant technical field obtains on the basis of the embodiments provided in the present disclosure fall within the scope of protection of the present disclosure.

[0022] Unless the context otherwise requires, the term "comprise" and other forms thereof, such as the third-person singular form "comprises" and the present participle form "comprising," are to be interpreted throughout the description and claims as having an open and inclusive meaning, i.e., "including but not limited to." In the presentation of the description, terms such as "an embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are to indicate that certain features, structures, materials, or properties relating to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure.

[0023] Schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or properties may be incorporated in one or more embodiments or examples in any suitable manner.

[0024] In the following, terms such as "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or suggesting the relative importance or implicitly the number of the specified technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of embodiments of this disclosure, the term "one / the plurality of" means two or more, unless otherwise specified.

[0025] In describing some embodiments, the terms "coupled," "connected," and their derivatives may be used. The term "connected" is to be understood in a broader sense. For example, the term "connected" may denote a fixed connection, a detachable connection, or a one-piece connection; alternatively, the term "connected" may denote a direct connection or an indirect connection via an intermediate medium. The term "coupled" means, for example, that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other but nevertheless work together or interact with each other. The embodiments disclosed herein are not necessarily limited to the content described herein.

[0026] The expression “at least one of A, B and C” has the same meaning as the expression “at least one of A, B or C”, and both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C and a combination of A, B and C.

[0027] The expression “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0028] The expression “applicable to” or “trained for” used here is an open and comprehensive expression that does not exclude devices that are applicable or trained to perform additional tasks or steps.

[0029] Furthermore, the expression “based on” is to be understood as open and comprehensive, since a process, step, calculation or other action based on one or more of the specified conditions or values ​​may in practice be based on additional conditions or values ​​beyond those specified.

[0030] As used here, the term “about”, “essentially” or “approximately” includes a given value and an average value within an acceptable range of deviation of a given value, the acceptable range of deviation being determined by an average person skilled in the relevant technical field, taking into account the measurement in question and the errors associated with measuring a given quantity (i.e., the limits of a measuring system).

[0031] The terms used here, such as "parallel," "perpendicular," or "equal," encompass a specified case and cases similar to the specified case within an acceptable range of deviation. The acceptable range of deviation is determined by a person skilled in the relevant technical field, taking into account the measurement in question and the errors associated with measuring a given quantity (i.e., the limitations of a measuring system). For example, the term "parallel" encompasses absolute parallelism and approximate parallelism, and an acceptable range of deviation for approximate parallelism might be, for instance, a deviation within 5°. The term "perpendicular" encompasses absolute perpendicularism and approximate perpendicularism, and an acceptable range of deviation for approximate perpendicularism might also be, for instance, a deviation within 5°.The term "equal" encompasses absolute equality and approximate equality, and an acceptable range of deviation for approximate equality may be a difference between two equal values ​​that is less than or equal to 5% of either value.

[0032] It is understood that when a layer or element is described as being located on another layer or substrate, that layer or element may either be lying directly on top of the other layer or substrate, or there may be one or more intermediate layers between the layer or element and the other layer or substrate.

[0033] Exemplary embodiments are described here with reference to sectional and / or top views as idealized example drawings. For clarity, the layer thicknesses and area sizes are shown enlarged in the drawings. Deviations in shape from the drawings, for example due to manufacturing technologies and / or tolerances, are conceivable. Therefore, the exemplary embodiments should not be considered limited to the shapes of the areas shown here, but should also include shape deviations, for example due to manufacturing. For instance, an etched area shown as rectangular generally has a curved shape.Therefore, the areas shown in the drawings are schematic, and their shapes are not intended to represent the actual shapes of areas in devices or to limit the scope of exemplary embodiments.

[0034] As in Fig. As shown in Figure 1, some embodiments of the present disclosure provide a display device 1000. The display device 1000 provided in the embodiments of the present disclosure can be any device that displays images, whether moving images (e.g., videos) or still images (e.g., static images), and whether text or graphics. More specifically, it is expected that the embodiments can be implemented in or connected to a variety of electronic devices. The variety of electronic devices can include, for example (but are not limited to), mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigation devices, cameras, MP4 video players, video cameras, game consoles, wristwatches, wall clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g.,The invention includes odometer displays, navigation devices, cockpit controls and / or displays, camera display devices (e.g., reversing camera display devices in vehicles), electronic photographs, electronic billboards or displays, projectors, building structures, packaging, and aesthetic structures (e.g., displays for presenting a piece of jewelry), etc. The specific shape of the display device 1000 is not specifically limited in the embodiments described in this disclosure.

[0035] As in Fig. Figure 1 shows an embodiment of the present disclosure described by way of an example in which the display device 1000 is a mobile phone.

[0036] As in Fig. As shown in Figure 2, the display device 1000 comprises a display field 100. The display device 1000 further comprises: a frame, a circuit board, a driver chip, and other electronic components. The display field 100 is arranged in the frame. The driver chip serves to control the display field 100 in order to perform a display.

[0037] As in Fig. As shown in Figure 2, the display field 100 is, for example, an OLED (Organic Light-Emitting Diode) display field. The display field 100 comprises an array substrate 1. The array substrate 1 comprises a base substrate 101 and a pixel circuit layer 40, which is arranged on the base substrate 101.

[0038] For example, one material of the base substrate 101 includes glass, metal, or a flexible material.

[0039] The pixel circuit layer 40 comprises a variety of pixel driver circuits 10. For example, the pixel circuit layer 40 comprises: a light shielding layer 11, a buffer layer 12, a semiconductor layer 13, a first gate insulating layer 14, a first gate layer 15, a second gate insulating layer 16, a second gate layer 17, a dielectric intermediate layer 18, a source-drain metal layer 19, and a planarization layer 21, which are stacked sequentially.

[0040] For example, a material of the semiconductor layer 13 comprises one of the following materials: low-temperature polysilicon, indium gallium zinc oxide, or low-temperature polycrystalline oxide.

[0041] For example, one material of the planarization layer 21 comprises polyimide. Materials of the buffer layer 12, the first gate insulating layer 14 and the second gate insulating layer 16 each comprise silicon nitride and silicon oxide to achieve an effect of blocking moisture, oxygen and alkaline ions.

[0042] In some embodiments, the pixel driver circuit 10 can be a circuit of 7T1C, 8T1C, or 9T1C, where T represents a transistor and the number before T indicates the number of transistors; and C represents a capacitor and the number before C indicates the number of capacitors. For example, 7T1C denotes seven transistors and one capacitor.

[0043] In some embodiments, a structure of the in Fig. Figure 3 shows the pixel driver circuit 10, which is a 7T1C type pixel driver circuit. The pixel driver circuit 10 comprises: a second reset transistor T1, a compensation transistor T2, a driver transistor T3, a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a first reset transistor T7.

[0044] As in Fig. As shown in Figure 3, the second reset transistor T1 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the second reset transistor T1 is electrically connected to a third sampling line, Gate3. The first electrode of the second reset transistor T1 is electrically connected to a first initialization signal line, Vinit1. The second electrode of the second reset transistor T1 is electrically connected to a first node, N1. The second reset transistor T1 is configured to reset a gate of the driver transistor T3 (the first node, N1) in response to a reset signal received at the third sampling line, Gate3.

[0045] As in Fig. As shown in Figure 3, the compensation transistor T2 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the compensation transistor T2 is electrically connected to a first sampling signal line, Gate1. The first electrode of the compensation transistor T2 is electrically connected to the first node, N1. The second electrode of the compensation transistor T2 is electrically connected to a third node, N3. The compensation transistor T2 is configured to perform a reset or threshold compensation of the driver transistor T3 in response to a sampling signal received at the first sampling signal line, Gate1.

[0046] As in Fig. As shown in Figure 3, the driver transistor T3 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the driver transistor T3 is electrically connected to the first node N1. The first electrode of the driver transistor T3 is electrically connected to a second node N2. The second electrode of the driver transistor T3 is electrically connected to the third node N3. The driver transistor T3 is configured to generate a driver current signal.

[0047] As in Fig. As shown in Figure 3, the data write transistor T4 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the data write transistor T4 is electrically connected to the first sampling signal line, Gate1. The first electrode of the data write transistor T4 is electrically connected to a data signal line, Data. The second electrode of the data write transistor T4 is electrically connected to the second node, N2. The data write transistor T4 is configured to transmit a data signal received at the Data signal line to the driver transistor T3 in response to the sampling signal received at the first sampling signal line, Gate1.

[0048] As in Fig. As shown in Figure 3, the first light emission control transistor T5 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the first light emission control transistor T5 is electrically connected to a light emission control signal line EM. The first electrode of the first light emission control transistor T5 is electrically connected to a power supply signal line ELVDD. The second electrode of the first light emission control transistor T5 is electrically connected to the second node N2. The first light emission control transistor T5 is configured to transmit a power supply signal received at the power supply signal line ELVDD to the driver transistor T3 in response to a light emission control signal received at the light emission control signal line EM.

[0049] As in Fig. As shown in Figure 3, the second light emission control transistor T6 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM. The first electrode of the second light emission control transistor T6 is electrically connected to the third node N3. The second electrode of the second light emission control transistor T6 is electrically connected to a fourth node N4. The second light emission control transistor T6 is configured to transmit the control current signal to a light-emitting device L in response to the light emission control signal received at the light emission control signal line EM, in order to control the light-emitting device L to emit light.

[0050] As in Fig. As shown in Figure 3, the first reset transistor T7 comprises, for example, a gate, a first electrode, and a second electrode. The gate of the first reset transistor T7 is electrically connected to a second sampling signal line, Gate2. The first electrode of the first reset transistor T7 is electrically connected to a second initialization signal line, Vinit2. The second electrode of the first reset transistor T7 is electrically connected to the fourth node, N4. The first reset transistor T7 is configured to transmit an initialization signal received at the second initialization signal line, Vinit2, to the light-emitting device L in response to a reset signal received at the second sampling signal line, Gate2, in order to reset the light-emitting device L.

[0051] For example, an anode of the light-emitting device L is electrically connected to the fourth node N4, and a cathode of the light-emitting device L is electrically connected to a reference voltage line ELVSS.

[0052] It should be noted that in the present disclosure, the first electrode of the transistor is either the source or the drain of the transistor, and the second electrode of the transistor is the other of the two. Since the source and drain of the transistor can be symmetrically constructed, they are structurally indistinguishable from one another. That is to say, there can be no difference in construction between the first electrode and the second electrode of the transistor in the embodiments of the present disclosure. For example, if the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode of the transistor is the drain. If the transistor is, for example, an N-type transistor, the first electrode of the transistor is the drain and the second electrode of the transistor is the source.

[0053] In the circuit provided in the embodiments of the present disclosure, nodes do not represent actual components, but rather connection points of relevant electrical connections in the circuit diagram. That is, these nodes are nodes that correspond to the connection points of the relevant electrical connections in the circuit diagram.

[0054] As in Fig. As shown in Figure 3, the pixel driver circuit further includes, for example, a capacitor Cst. The capacitor Cst comprises a first electrode plate Cst1 and a second electrode plate Cst2. The first electrode plate Cst1 of the capacitor Cst is electrically connected to the first node N1. The second electrode plate Cst2 of the capacitor Cst is electrically connected to the power supply signal line ELVDD.

[0055] In some embodiments, an LTPO (low-temperature polycrystalline oxide) circuit is used as the pixel driver circuit 10. That is, a single pixel driver circuit 10 comprises both an LTPS (low-temperature polysilicon) thin-film transistor and an oxide thin-film transistor. The low-temperature polysilicon thin-film transistor has a high power handling capability. The oxide thin-film transistor has a low turn-off current and a higher charge storage capacity than the low-temperature polysilicon thin-film transistor. Thus, high charge mobility and good stability of the pixel driver circuit 10 can be achieved.

[0056] For example, in Fig. As shown in Figure 3, an oxide thin-film transistor can be used as the compensation transistor T2. The compensation transistor T2 is an N-type transistor that turns on at a high level. The second reset transistor T1, the driver transistor T3, the data write transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the first reset transistor T7 are all low-temperature P-type polysilicon thin-film transistors that turn on at a low level. By designing the compensation transistor T2 as an oxide thin-film transistor, current leakage from the first node N1 can be effectively prevented.

[0057] In some embodiments, illumination in a method where the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor are used in the pixel driver circuit 10 leads to characteristic displacements of the thin-film transistors. For example, in the 7T1C type pixel driver circuit 10, the second reset transistor T1 and the compensation transistor T2 are connected to the first node N1, and the data write transistor T4 is connected to the second node N2, and the second reset transistor is connected to the fourth node N4. If illumination leads to characteristic displacements of the second reset transistor T1, the compensation transistor T2, the data write transistor T4, and the first reset transistor T7, current leakage can occur, which changes the voltages of the first node N1, the second node N2, and the third node N3.The driver transistor T3 is designed to generate a control current signal. The characteristic shift due to the illumination directly affects the control current of the pixel driver circuit 10 and ultimately leads to uneven brightness of the display field.

[0058] Due to the aforementioned problems, some embodiments of the present disclosure, as in Fig. Figures 2 and 4A to 4E show an array substrate 1, wherein the array substrate 1 comprises a plurality of pixel driver circuits 10 and a base substrate 101. The plurality of pixel driver circuits 10 is arranged in a plurality of rows and columns, each of the plurality of pixel driver circuits 10 comprising a plurality of transistors.

[0059] For example, the pixel driver circuits 10 are arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect and both the first direction X and the second direction Y are parallel to a surface of the base substrate 101. For example, the first direction X is perpendicular to the second direction Y. The first direction X is a row direction in which the plurality of pixel driver circuits 10 are arranged. The second direction Y is a column direction in which the plurality of pixel driver circuits 10 are arranged.

[0060] For example, the transistors included in each pixel driver circuit 10 are a second reset transistor T1, a compensation transistor T2, a driver transistor T3, a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a first reset transistor T7. For connections between the transistors, refer to the diagram above.

[0061] As in Fig. As shown in Figures 2 and 4A to 4E, the array substrate 1 provided in the embodiments of the present disclosure comprises: a light-shielding layer 11 arranged on one side of the base substrate 101, a semiconductor layer 13 arranged on a side of the light-shielding layer 11 facing away from the base substrate 101, and a first gate layer 15 arranged on a side of the semiconductor layer 13 facing away from the base substrate 101. The light-shielding layer 11 comprises a plurality of light-shielding wires 110 of the first type. The semiconductor layer 13 comprises active layer patterns of the plurality of transistors. The first gate layer 15 comprises a plurality of sample signal lines. Each of the sample signal lines traverses an active layer pattern of at least one transistor. The plurality of sample signal lines transmits sample signals.Each of the multiple light-shielding wires 110 of the first type crosses an active layer pattern of at least one transistor. A light-shielding wire 110 of the first type and a gate scanning signal line that cross the active layer pattern of the same transistor transmit the same scanning signal.

[0062] For example, each sampling signal line crosses the gate with reference to Fig. 2 and 4A to 4E represent an active layer pattern of at least one transistor. That is, an orthographic projection of a single sampling signal line (gate) on the base substrate 101 overlaps with an orthographic projection of an active layer pattern of at least one transistor on the base substrate 101. For example, a section of a single sampling signal line that crosses an active layer pattern of a transistor serves as the gate of the transistor, as described in Fig. 3, which is equivalent to the fact that the sampling signal line is electrically connected to the gate of the transistor. Each first-type light-shielding wire 110 crosses an active layer pattern of at least one transistor. That is, an orthographic projection of a single first-type light-shielding wire 110 on the base substrate 101 overlaps with an orthographic projection of an active layer pattern of at least one transistor on the base substrate 101. The first-type light-shielding wire can shield the active layer pattern of the transistor and prevent external light from penetrating the semiconductor from the side of the base substrate. The illumination causes a shift in the properties of the transistor's active layer pattern, which affects the stability of the drive current generated by the pixel driver circuit and ultimately leads to an uneven display on the display panel.

[0063] A first-type light shield wire and a scanning signal line crossing the active layer pattern of the same transistor transmit the same scanning signal. That is, the first-type light shield wire and the scanning signal line that overlap with the active layer pattern of the same transistor transmit the same scanning signal. It is understandable that the first-type light shield wire and the scanning signal line overlap and are located above and below the active layer pattern of the transistor, respectively.

[0064] In the array substrate provided in some embodiments of the present disclosure, the light shielding wire of the first type receives a sampling signal, and the sampling signal line Gate and the light shielding wire 110 of the first type, which overlap with the active layer pattern of the same transistor, transmit the same sampling signal, so that the signals received by the upper and lower layers of the active layer pattern of the same transistor can be synchronized.This improves signal transmission capability, avoids the formation of excessive parasitic capacitance due to overlap between the scanning line and the light-shielding wire carrying different signals, and prevents interference between the signals. This improves the stability of the scanning signal transmitted by the scanning line, makes the scanning signal received by the transistor gate more stable, and ensures normal transistor switching on and off. Furthermore, the light-shielding metal layer blocks external light, preventing shifts in the transistor's active layer pattern caused by external light. This ensures the normal operation of the pixel driver circuit and improves the uniformity of the display on the screen.

[0065] The following uses a series of pixel driver circuits as an example to illustrate the positional relationships between the transistors of the pixel driver circuits, a sampling signal line, and a light shielding wire.

[0066] In some embodiments, such as in Fig. 4A and Fig. As shown in Figure 4C, the transistors of each pixel driver circuit 10 comprise a compensation transistor T2 and a data write transistor T4. The multiple sampling signal lines Gate includes the first sampling signal lines Gate1. The orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits 10 on the base substrate 101 overlap with the orthographic projection of the first sampling signal line Gate1 on the base substrate 101. The plurality of first-type light shielding wires 110 includes first light shielding wires 110a, wherein the orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits on the base substrate 101 overlap with the orthographic projection of the first light shielding wire 110a on the base substrate 101.The first light shielding wire 110a and the first scanning signal line Gate1 both transmit a first scanning signal.

[0067] It is understandable that in the pixel driver circuits 10 arranged along the first direction X, the orthographic projections of the active layer patterns of the compensation transistor T2 and the data write transistor T4 in each pixel driver circuit 10 on the base substrate 101 overlap with the orthographic projection of the first sampling signal line Gate1 on the base substrate 101. The term "overlap" here means that the orthographic projections of the active layer patterns of the compensation transistor T2 and the data write transistor T4 on the base substrate 101 each partially overlap with the orthographic projection of the first sampling signal line Gate1 on the base substrate 101, and the overlapping parts of the first sampling signal line Gate1 each serve as the gate pattern of the compensation transistor T2 and the data write transistor T4. That is to say,The gates of the compensation transistor T2 and the data write transistor T4 receive the same first sampling signal.

[0068] The wording “the orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits on the base substrate 101 each overlap with the orthographic projection of the first light shielding wire 110a on the base substrate 101” may imply that the orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits 10 on the base substrate 101 each partially overlap with the orthographic projection of the first light shielding wire 110a on the base substrate 101, or may imply thatthat the orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits on the base substrate 101 all lie within the orthographic projection of the first light shielding wire 110a on the base substrate 101, or may include that the boundaries of the orthographic projections of the active layer patterns of the compensation transistors T2 and the data write transistors T4 in the series of pixel driver circuits on the base substrate 101 completely coincide with the boundary of the orthographic projection of the first light shielding wire 110a on the base substrate 101.

[0069] It is understandable that the first light shielding wire 110a overlaps with the first sampling signal line Gate1 and that the width of the first light shielding wire 110a is greater than that of the first sampling signal line Gate1, thus ensuring that the first light shielding wire 110a shields the active layer patterns of the compensation transistor T2 and the data write transistor T4.

[0070] As in Fig. As shown in Figure 4C, the compensation transistor T2 is a dual-gate transistor. The active layer pattern of the compensation transistor T2 has the shape of an "L" and features two channel regions G1 and G2, as well as a connecting region N1 between the two channel regions. The first sampling signal line, Gate1, overlaps with the two channel regions but does not overlap with the connecting region. By designing the compensation transistor T2 as a dual-gate transistor, current leakage can be reduced. The first light-shielding wire 110a overlaps with the two channel regions and the connecting region of the active layer pattern of the compensation transistor T2. That is, the first light-shielding wire 110a completely shields the active layer pattern of the compensation transistor T2, further ensuring the light-shielding effect on the compensation transistor T2.

[0071] In the array substrate provided in some embodiments of the present disclosure, the first light shielding wire 110a receives the first sampling signal, and both the first light shielding wire 110a and the first sampling signal line Gate1, which overlap with the active layer patterns of the compensation transistor T2 and the data write transistor T4, transmit the first sampling signal, thereby ensuring that the signals received by the upper and lower layers of the active layer patterns of the compensation transistor T2 and the data write transistor T4, whose orthographic projections on the base substrate 101 each overlap with the orthographic projections of the first light shielding wire 110a and the first sampling signal line Gate1 on the base substrate 101, can be synchronized.This improves signal transmission efficiency, avoids the formation of excessive parasitic capacitance due to overlap between the sampling line and the light-shielding wire carrying different signals, and prevents interference between the signals. This improves the stability of the sampling signal transmitted by the sampling line, makes the sampling signal received by the transistor gate more stable, and ensures normal transistor switching on and off. Furthermore, the light-shielding metal layer blocks external light, preventing shifts in the transistor's active layer pattern caused by external light. This ensures the normal operation of the pixel driver circuit and improves the uniformity of the display on the screen.

[0072] In some embodiments, with further reference to Fig. 4A and Fig. In 4C, the transistors of each pixel driver circuit 10 further comprise a first reset transistor T7. The plurality of sample signal lines Gate includes second sample signal lines Gate2. The orthographic projections of the active layer patterns of the first reset transistors T7 in the series of pixel driver circuits 10 on the base substrate 101 overlap with the orthographic projection of the second sample signal line Gate2 on the base substrate 101. The plurality of first-type light shielding wires 110 comprises second light shielding wires 110b, wherein the orthographic projections of the active layer patterns of the first reset transistors T7 in the series of pixel driver circuits 10 on the base substrate 101 overlap with the orthographic projection of the second light shielding wire 110b on the base substrate 101. The second light shielding wire 110b and the second scanning signal line Gate2 both transmit a second scanning signal.

[0073] It is understandable that in the pixel driver circuits 10 arranged along the first direction X, the orthographic projection of the active layer pattern of the first reset transistor T7 in each pixel driver circuit 10 on the base substrate 101 overlaps with the orthographic projection of the second sampling signal line Gate2 on the base substrate 101. The term "overlap" here means that the orthographic projection of the active layer pattern of the first reset transistor T7 on the base substrate 101 partially overlaps with the orthographic projection of the second sampling signal line Gate2 on the base substrate 101, and the overlapping part of the second sampling signal line Gate2 serves as the gate pattern of the first reset transistor T7. That is, the gate of the first reset transistor T7 receives the second sampling signal.

[0074] The wording “the orthographic projection of the active layer pattern of the first reset transistor T7 in the series of pixel driver circuits 10 on the base substrate 101 overlaps with the orthographic projection of the second light-shielding wire 110b on the base substrate 101” can imply that the orthographic projection of the active layer pattern of the first reset transistor T7 in the series of pixel driver circuits 10 on the base substrate 101 partially overlaps with the orthographic projection of the second light-shielding wire 110b on the base substrate 101, or can imply that the orthographic projection of the active layer pattern of the first reset transistor T7 in the series of pixel driver circuits 10 on the base substrate 101 lies within the orthographic projection of the second light-shielding wire 110b on the base substrate 101, or can includethat the boundary of the orthographic projection of the active layer pattern of the first reset transistor T7 in the series of pixel driver circuits 10 on the base substrate 101 completely coincides with the boundary of the orthographic projection of the second light shielding wire 110b on the base substrate 101.

[0075] It is understandable that the second light shielding wire 110b overlaps with the second sampling signal line Gate2 and that the width of the second light shielding wire 110b is greater than that of the second sampling signal line Gate2, thus ensuring that the second light shielding wire 110b shields the active layer pattern of the first reset transistor T7.

[0076] In the array substrate provided in some embodiments of the present disclosure, the second light shielding wire 110b receives the second sampling signal, and both the second light shielding wire 110b and the second sampling signal line Gate2, which overlap with the active layer pattern of the first reset transistor T7, transmit the second sampling signal, thereby ensuring that the signals received by the upper and lower layers of the active layer pattern of the first reset transistor T7, whose orthographic projection on the base substrate 101 overlaps with the orthographic projections of the second light shielding wire 110b and the second sampling signal line Gate2 on the base substrate 101, can be synchronized.This improves signal transmission efficiency, avoids the formation of excessive parasitic capacitance due to overlap between the sampling line and the light-shielding wire carrying different signals, and prevents interference between the signals. This improves the stability of the sampling signal transmitted by the sampling line, makes the sampling signal received by the transistor gate more stable, and ensures normal transistor switching on and off. Furthermore, the light-shielding metal layer blocks external light, preventing shifts in the transistor's active layer pattern caused by external light. This ensures the normal operation of the pixel driver circuit and improves the uniformity of the display on the screen.

[0077] In some embodiments, with reference to Fig. 4A, 4C, and 5A through 5C transmit the same signal to the first sampling signal line (Gate 1) and the second sampling signal line (Gate 2), which overlap with the same series of pixel driver circuits 10. That is, the compensation transistor T2, the data write transistor T4, and the first reset transistor T7 in a single pixel driver circuit all receive the same sampling signal. Similarly, the first light shield wire 110a and the second light shield wire 110b, which overlap with the same series of pixel driver circuits 10, also transmit the same signal.

[0078] The array substrate 1 comprises a display area AA and a border area BB, wherein the border areas BB located on both sides of the display area BB along the line direction are each a first area B1 and a second area B2. The plurality of light-shielding wires 110 of the first type extends along the line direction (first direction X) to the border area BB. The first light-shielding wire 110a and the second light-shielding wire 110b, which overlap with the same row of pixel driver circuits 10, are electrically connected in the first area B1 and / or in the second area B2.

[0079] For example, as in Fig. Figure 5A shows the two ends of the first light-shielding wire 110a and the second light-shielding wire 110b extending in the line direction to the first area B1 and the second area B2, respectively. The first ends of the first light-shielding wire 110a and the second light-shielding wire 110b, which overlap with the same row of pixel driver circuits 10, are electrically connected in the first area B1.

[0080] For example, as in Fig. Figure 5B shows the two ends of the first light-shielding wire 110a and the second light-shielding wire 110b extending in the line direction to the first area B1 and the second area B2, respectively. The second ends of the first light-shielding wire 110a and the second light-shielding wire 110b, which overlap with the same row of pixel driver circuits 10, are electrically connected in the second area B2.

[0081] For example, as in Fig. Figure 5C shows the two ends of the first light-shielding wire 110a and the second light-shielding wire 110b extending in the line direction to the first region B1 and the second region B2, respectively. The first ends of the first light-shielding wire 110a and the second light-shielding wire 110b, which overlap with the same row of pixel driver circuits 10, are electrically connected in the first region B1. The second ends of the first light-shielding wire 110a and the second light-shielding wire 110b are electrically connected in the second region B2.

[0082] For example, the first sampling signal lines Gate1 and the second sampling signal lines Gate2 extend along the row direction (first direction X) to the edge region BB. The first sampling signal lines Gate1 and the second sampling signal lines Gate2, which overlap with the same row of pixel driver circuits 10, are electrically connected in the first region B1 and / or in the second region B2.

[0083] Details can be found in the description above for the first light shielding wire 110a and the second light shielding wire 110b.

[0084] The following describes an embodiment for feeding a scanning signal into the first type of light shielding wire.

[0085] In some embodiments, such as in Fig. As shown in Figures 5A to 5C, the array substrate 1 further comprises at least one gate driver circuit 20 located in the boundary region BB. The gate driver circuit 20 comprises a plurality of shift registers 201, each shift register 201 configured to transmit a sampling signal to an array of pixel driver circuits 10. Each shift register 201 includes an output terminal 201a electrically connected to the first sampling signal line Gate1 and the second sampling signal line Gate2 associated with the array of pixel driver circuits 10. The array substrate 1 further comprises a source-drain metal layer 19 located on a side of the first gate layer 15 facing away from the light-shielding layer 11. The source-drain metal layer 19 comprises a plurality of first interconnect lines 191.Each first connecting line 191 is electrically connected at one end to an output terminal 201a and at the other end to a first light shielding wire 110a or a second light shielding wire 110b. A1 represents the area in which the pixel driver circuit is located. The mapping relationship between the area A1, in which the pixel driver circuit is located, and the signal line is used to represent the mapping relationship between the pixel driver circuit and the signal line.

[0086] It should be noted that with reference to Fig. 2 and Fig. 5A The output terminal 201a of the shift register 201 is electrically connected to the first sampling signal line Gate1 and the second sampling signal line Gate2, which are assigned to the series of pixel driver circuits 10. That is, the output terminal 201a of the shift register 201 is located in the source-drain metal layer 19 and is electrically connected to the first sampling signal line Gate1 and the second sampling signal line Gate2 via a first through-hole K1, which penetrates the second gate insulating layer 16 and the dielectric intermediate layer 18.

[0087] Here, the through-hole can be connected to the first sampling signal line Gate1 by passing through it, or to the second sampling signal line Gate2 by passing through it.

[0088] For example, with reference to Fig. 2 and 5A to 5C each of the plurality of first connecting lines 191 located in the source-drain metal layer 19, electrically connected at one end to an output terminal 201a and at the other end, via a second through-hole K2 penetrating the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16 and the dielectric intermediate layer 18, electrically connected to the first light shielding wire 110a or the second light shielding wire 110b.

[0089] It is understandable that the second through-hole K2 can be connected by penetration to the first light-shielding wire 110a or by penetration to the second light-shielding wire 110b.

[0090] In some embodiments, the position of the first through-hole for connecting the output terminal of the shift register to the first sampling signal line Gate1 or the second sampling signal line Gate2 is on a side away from the display area of ​​the position of the second through-hole for connecting the output terminal of the shift register to the first light shielding wire 110a or the second light shielding wire 110b via the first connecting line.

[0091] In some examples, there may be an electrical connection or no electrical connection between the first light shielding wire 110a and the first scanning signal line Gate1, and there may be an electrical connection or no electrical connection between the second light shielding wire 110b and the second scanning signal line Gate2.

[0092] By arranging the first connecting line in the source-drain metal layer, the first light shielding wire 110a and the second light shielding wire 110b are directly connected to the output terminal of the corresponding shift register via the first connecting line, so that the sampling signal output by the shift register is directly input into the first light shielding wire 110a and the second light shielding wire 110b.In this way, a stable sampling signal can be transmitted in the first light shielding wire 110a and the second light shielding wire 110b, and the connection position between the first light shielding wire 110a and the second light shielding wire 110b on the one hand and the shift register on the other hand does not conflict with the connection position between the first sampling signal line Gate1 or the second sampling signal line Gate2 and the shift register and does not impair the transmission of the sampling signal in the first sampling signal line Gate1 and the second sampling signal line Gate2.

[0093] The following describes another embodiment for feeding a scanning signal into the light shielding wire of the first type.

[0094] In some embodiments, with reference to Fig. 6A to 6C, the first light shielding wire 110a is electrically connected to the first scanning signal line Gate1, and the second light shielding wire 110b is electrically connected to the second scanning signal line Gate2.

[0095] For example, the first light shielding wire 110a is electrically connected to the first sampling signal line Gate1, so that the first light shielding wire 110a and the first sampling signal line Gate1 can transmit the same signal to a corresponding transistor, thus avoiding the generation of excessive parasitic capacitance due to signal asynchrony and preventing interference between signals. Similarly, the second light shielding wire 110b is electrically connected to the second sampling signal line Gate2, so that the second light shielding wire 110b and the second sampling signal line Gate2 can transmit the same signal to a corresponding transistor, thus avoiding the generation of excessive parasitic capacitance due to signal asynchrony and preventing interference between signals.

[0096] In some embodiments, with reference to Fig. In components 6A to 6C, the array substrate 1 comprises a display area AA and a border area BB. A plurality of first-type light-shielding wires 110 extend along the line direction to the border area BB. The border area BB, located along the line direction on both sides of the display area AA, is defined as a first area B1 and a second area B2. The first light-shielding wire 110a is electrically connected to the first scanning signal line Gate1 in the first area B1 and / or in the second area B2. The second light-shielding wire 110b is electrically connected to the second scanning signal line Gate2 in the first area B1 and / or in the second area B2. A1 represents the area containing the pixel driver circuitry.The mapping relationship between area A1, where the pixel driver circuit is located, and the signal line is used to represent the mapping relationship between the pixel driver circuit and the signal line.

[0097] For example, with reference to Fig. 6A the first light shielding wire 110a and the first scanning signal line Gate1 are electrically connected to each other via a third through hole K3 in the first area B1, and the second light shielding wire 110b and the second scanning signal line Gate2 are electrically connected to each other via a fourth through hole K4 in the first area B1.

[0098] For example, with reference to Fig. 6B the first light shielding wire 110a and the first scanning signal line Gate1 are electrically connected to each other via a fifth through hole K5 in the second area B2, and the second light shielding wire 110b and the second scanning signal line Gate2 are electrically connected to each other via a sixth through hole K6 in the second area B2.

[0099] For example, with reference to Fig. 6C The first light shielding wire 110a and the first scanning signal line Gate1 are electrically connected to each other via the third through-hole K3 in the first area B1 and electrically connected to each other via the fifth through-hole K5 in the second area B2. The second light shielding wire 110b and the second scanning signal line Gate2 are electrically connected to each other via the fourth through-hole K4 in the first area B1 and are simultaneously electrically connected to each other via the sixth through-hole K6 in the second area B2.

[0100] For example, the first light shielding wire 110a and the first scanning signal line Gate1 are electrically connected to each other via through holes in the first area B1 / second area B2, and the second light shielding wire 110b and the second scanning signal line Gate2 are electrically connected to each other via through holes in the second area B2 / first area B1.

[0101] It should be noted that the third through hole K3, the fourth through hole K4, the fifth through hole K5 and the sixth through hole K6 all penetrate the buffer layer 12, the semiconductor layer 13, the first gate insulating layer 14, the first gate layer 15, the second gate insulating layer 16, the second gate layer 17 and the dielectric intermediate layer 18, which are in Fig. 2 are shown.

[0102] In the embodiment described above, the first sampling signal line, Gate1, and the second sampling signal line, Gate2, are electrically connected to the output terminal of the corresponding shift register to receive the sampling signal output by the shift register. The first optical shielding wire, 110a, is electrically connected to the first sampling signal line, Gate1. The second optical shielding wire, 110b, is electrically connected to the second sampling signal line, Gate2. The sampling signal is transmitted via the first sampling signal line, Gate1, and the second sampling signal line, Gate2, to the first optical shielding wire, 110a, and the second optical shielding wire, 110b. Therefore, it is not necessary to connect the first optical shielding wire, 110a, and the second optical shielding wire, 110b, to the shift register, which simplifies the wiring and the manufacturing process.

[0103] In some embodiments, with reference to Fig. 4A and Fig. 4C, the transistors of each pixel driver circuit 10 further comprise a second reset transistor T1. The plurality of sampling signal lines Gate includes third sampling signal lines Gate3. The orthographic projections of the active layer patterns of the second reset transistors T1 in a series of pixel driver circuits 10 on the base substrate 101 overlap with an orthographic projection of a third sampling signal line Gate3 on the base substrate 101. The plurality of light shielding wires 110 of the first type includes third light shielding wires 110c. The orthographic projections of the active layer patterns of the second reset transistors T1 in the series of pixel driver circuits 10 on the base substrate 101 overlap with an orthographic projection of a third light shielding wire 110c on the base substrate 101. The third light shielding wire 110c and the third sampling signal line Gate3 both transmit a third sampling signal.

[0104] It is understandable that in the pixel driver circuits 10 arranged along the first direction X, the orthographic projection of the active layer pattern of the second reset transistor T1 in each pixel driver circuit 10 on the base substrate 101 overlaps with the orthographic projection of the third sampling signal line Gate3 on the base substrate 101. The term "overlap" here means that the orthographic projection of the active layer pattern of the second reset transistor T1 on the base substrate 101 partially overlaps with the orthographic projection of the third sampling signal line Gate3 on the base substrate 101, and the overlapping part serves as the gate pattern of the second reset transistor T1. That is, the gate of the second reset transistor T1 receives the third sampling signal.

[0105] The wording “the orthographic projection of the active layer pattern of the second reset transistor T1 in the series of pixel driver circuits 10 on the base substrate 101 overlaps with the orthographic projection of the third light-shielding wire 110c on the base substrate 101” can imply that the orthographic projection of the active layer pattern of the second reset transistor T1 in the series of pixel driver circuits 10 on the base substrate 101 partially overlaps with the orthographic projection of the third light-shielding wire 110c on the base substrate 101, or can imply that the orthographic projection of the active layer pattern of the second reset transistor T1 in the series of pixel driver circuits 10 on the base substrate 101 lies within the orthographic projection of the third light-shielding wire 110c on the base substrate 101, or can includethat the boundary of the orthographic projection of the active layer pattern of the second reset transistor T1 in the series of pixel driver circuits 10 on the base substrate 101 completely coincides with the boundary of the orthographic projection of the third light shielding wire 110c on the base substrate 101.

[0106] In the array substrate provided in some embodiments of the present disclosure, the third light shielding wire 110c receives the third sampling signal, and both the third light shielding wire 110c and the third sampling signal line Gate3, which overlap with the active layer pattern of the second reset transistor T1, transmit the third sampling signal, thereby ensuring that the signals received by the upper and lower layers of the active layer pattern of the second reset transistor T1, whose orthographic projection on the base substrate 101 overlaps with the orthographic projections of the third light shielding wire 110c and the third sampling signal line Gate3 on the base substrate 101, can be synchronized.This improves signal transmission efficiency, avoids the formation of excessive parasitic capacitance due to overlap between the sampling line and the light-shielding wire carrying different signals, and prevents interference between the signals. This improves the stability of the sampling signal transmitted by the sampling line, makes the sampling signal received by the transistor gate more stable, and ensures normal transistor switching on and off. Furthermore, the light-shielding metal layer blocks external light, preventing shifts in the transistor's active layer pattern caused by external light. This ensures the normal operation of the pixel driver circuit and improves the uniformity of the display on the screen.

[0107] It should be noted that the plurality of pixel driver circuits 10 are arranged in an array on the array substrate in a plurality of rows and columns. For example, the plurality of pixel driver circuits 10 are arranged in a plurality of rows along the second direction. The active layer pattern of the second reset transistor T1 of the current row of pixel driver circuits is located on one side of the active layer pattern of the first reset transistor T7 of the previous row of pixel driver circuits in the row direction. A sampling signal line crosses both the second reset transistor of the current row and the first reset transistor of the previous row. That is to say,The third sampling signal line Gate3, which is connected to the gate of the second reset transistor T1 of the current row, and the second sampling signal line Gate2, which is connected to the gate of the first reset transistor T7 of the previous row, can be the same sampling signal line Gate (as in . Fig. 4A shown). That is, when a sampling signal line Gate is switched on, the sampling signal line Gate transmits the sampling signal simultaneously to the second reset transistor T1 of the current row and the first reset transistor T7 of the previous row.

[0108] In some embodiments, with reference to Fig. 4A, the third sampling signal line Gate3, which is assigned to an nth row of pixel driver circuits, and the second sampling signal line Gate2, which is assigned to an (n-1)th row of pixel driver circuits, are the same signal line.

[0109] It is understandable that, as in Fig. Figure 4A shows that the third sample signal line, Gate3, which is connected to the gates of the second reset transistors T1 assigned to the nth row of pixel driver circuits, and the second sample signal line, Gate2, which is connected to the gates of the first reset transistors T7 assigned to the (n-1)th row of pixel driver circuits, can act as the same sample signal line, Gate. That is, when a sample signal line, Gate, is turned on, it transmits the sample signal simultaneously to the second reset transistor T1 of the current row and the first reset transistor T7 of the previous row.

[0110] In some embodiments, with reference to Fig. 4A to 4C, the transistors of each pixel driver circuit 10 further comprise a driver transistor T3. The light-shielding layer 11 comprises a plurality of second-type light-shielding wires 120. The orthographic projections of the active layer patterns of the driver transistors T3 in a series of pixel driver circuits 10 on the base substrate 101 overlap with an orthographic projection of a second-type light-shielding wire 120 on the base substrate 101. The second-type light-shielding wire 120 transmits a first voltage signal.

[0111] Referring to Fig. In 4A to 4C, the second type of light-shielding wire 120 comprises a plurality of light-shielding patterns 121 and a plurality of connection patterns 122 arranged alternately, each connection pattern 122 being connected to two adjacent light-shielding patterns 121. An orthographic projection of each light-shielding pattern 121 on the base substrate 101 surrounds an orthographic projection of a driver transistor T3 of a pixel driver circuit 10 on the base substrate 101.

[0112] For example, the one in Fig. Figures 4A to 4C show a second-type light-shielding wire 120 in a pixel driver circuit 10. The second-type light-shielding wire 120 comprises a light-shielding pattern 121 and a connection pattern 122, which are connected together. An orthographic projection of the light-shielding pattern 121 on the base substrate 101 is larger than an orthographic projection of the connection pattern 122 on the base substrate 101. With reference to Fig. 4A to 4C surrounds the orthographic projection of the light shielding pattern 121 on the base substrate 101 and the orthographic projection of the active layer pattern of the driver transistor T3 in the corresponding pixel driver circuit 10 on the base substrate 101. That is, the orthographic projection of the active layer pattern of the driver transistor T3 on the base substrate 101 lies within the orthographic projection of the light shielding pattern 121 on the base substrate 101.

[0113] It is understandable that the wording “the orthographic projections of the active layer patterns of the driver transistors T3 in a series of pixel driver circuits 10 on the base substrate 101 overlap with an orthographic projection of a second-type light shielding wire 120 on the base substrate 101” may imply that the orthographic projections of the active layer patterns of the driver transistors T3 in the series of pixel driver circuits 10 on the base substrate 101 partially overlap with the orthographic projection of the second-type light shielding wire 120 on the base substrate 101, or may imply that the orthographic projections of the active layer patterns of the driver transistors T3 in the series of pixel driver circuits 10 on the base substrate 101 lie within the orthographic projection of the second-type light shielding wire 120 on the base substrate 101. or may includethat the boundaries of the orthographic projections of the active layer patterns of the driver transistors T3 in the series of pixel driver circuits 10 on the base substrate 101 completely coincide with the boundary of the orthographic projection of the second type of light shielding wire 120 on the base substrate 101.

[0114] The second type of light shielding wire 120 overlaps the driver transistor, preventing external light from reaching it. This avoids any shift in the driver transistor's characteristics caused by illumination and ensures the stability of the drive current generated by the driver transistor. The first voltage signal is a constant voltage signal. This first voltage signal is carried in the second type of light shielding wire 120, preventing interference from signals carried in other signal lines and avoiding any influence on the gate voltage of the driver transistor T3. This further ensures the stability of the drive current generated by the driver transistor and improves the uniformity of the display.

[0115] In some embodiments, with reference to Fig. 2, Fig. 6C and Fig. 7, the array substrate 1 further comprises a source-drain metal layer 19, which is arranged on a side of the first gate layer 15 facing away from the light-shielding layer 11. The source-drain metal layer 19 comprises first voltage signal lines 192. The first voltage signal line 192 is electrically connected to the second-type light-shielding wire 120.

[0116] For example, with reference to Fig. 2, Fig. 6C and Fig. 7 the first voltage signal line 192 is arranged in the source-drain metal layer 19. The first voltage signal line 192 is electrically connected to the second type light shielding wire 120 via a through hole that penetrates the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16 and the dielectric intermediate layer 18.

[0117] In some embodiments, with continued reference to Fig. In the 5A to 5C, 6A to 6C, and 8A to 8C series, each type 2 light shield wire 120 overlaps with the driver transistors T3 in a series of pixel driver circuits 10. Each column of pixel driver circuits 10 is connected to a corresponding first voltage signal line 192. At least three adjacent pixel driver circuits 10 in each series of pixel driver circuits 10 form a pixel driver circuit group 30. The first voltage signal line 192 connected to at least one pixel driver circuit 10 in a pixel driver circuit group 30 is connected to the type 2 light shield wire 120. A1 represents the area in which the pixel driver circuit is located. The mapping relationship between the area A1, in which the pixel driver circuit is located, and the signal line is used to represent the mapping relationship between the pixel driver circuit and the signal line.

[0118] For example, with reference to Fig. Figures 8A to 8C show the pixel driver circuits 10 arranged in a row and three columns as an example. Each column of pixel driver circuits 10 is connected to a corresponding first voltage signal line 192. The first light emission control transistor T5 and the storage capacitor in each column of pixel driver circuits are electrically connected to a first voltage signal line. Each column of pixel driver circuits 10 transmits a first voltage signal. Three adjacent pixel driver circuits 10 in a row of pixel driver circuits 10 form a pixel driver circuit group 30.The first voltage signal line 192, which is connected to a pixel driver circuit 10 in each pixel driver circuit group 30, is electrically connected to the second-type light shielding wire 120 via a seventh through-hole K7 that penetrates the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16, and the dielectric intermediate layer 18. It should be noted that the three adjacent pixel driver circuits 10 in the pixel driver circuit group 30 can, for example, each drive a red subpixel, a green subpixel, and a blue subpixel.

[0119] For example, with reference to Fig. Figures 9A to 9D show the pixel driver circuits 10 arranged in a row and four columns as an example. Each column of pixel driver circuits 10 is connected to a corresponding first voltage signal line 192. Each column of pixel driver circuits 10 transmits a first voltage signal. Four adjacent pixel driver circuits 10 in a row of pixel driver circuits 10 form a pixel driver circuit group 30. The first voltage signal line 192, connected to any pixel driver circuit 10 in each pixel driver circuit group 30, is electrically connected to the second-type light shielding wire 120 via a seventh through-hole K7 that penetrates the buffer layer 12, the first gate insulating layer 14, the second gate insulating layer 16, and the dielectric intermediate layer 18.It should be noted that the four adjacent pixel driver circuits 10 in the pixel driver circuit group 30 can, for example, each control a red subpixel, a green subpixel, a blue subpixel and a green subpixel.

[0120] It is understandable that the first voltage signal lines 192, each connected to two, three or all pixel driver circuits 10 in a pixel driver circuit group 30, are each electrically connected to the light shielding wire 120 of the second type, which is not specifically restricted here.

[0121] Since the second-type metal wire extends along the row direction and overlaps with the driver transistors T3 of the pixel driver circuits 10 in a row of pixel driver circuits, and the first voltage signal is fed into the second-type metal wire, it is assumed that three / four adjacent pixel driver circuits are grouped together. In each pixel driver circuit group 30, only the first voltage signal line 192, which is connected to at least one pixel driver circuit 10, needs to be connected to the second-type metal wire via a through-hole, and it is not necessary to connect the first voltage signal lines, which are connected to all pixel driver circuits, to the second-type metal wire via through-holes.In this way, based on ensuring that the first voltage signal is fed into the second type of metal wire, the layout space design is optimized, space is saved and the manufacturing process is simplified.

[0122] In some embodiments, the array substrate 1 comprises, with reference to Fig. Figure 10 defines a display area AA and a border area BB. A plurality of first voltage signal lines 192 are electrically connected to each other in the border area BB. A1 represents the area in which the pixel driver circuit is located. The mapping relationship between the area A1, in which the pixel driver circuit is located, and the signal line is used to represent the mapping relationship between the pixel driver circuit and the signal line.

[0123] For example, each column of in Fig. The 10 pixel driver circuits 10 shown are connected to a first voltage signal line 192. The plurality of first voltage signal lines 192 are electrically connected to each other on the same side of the first voltage signal lines 192, which extend along the column direction. For example, the plurality of first voltage signal lines 192 in the edge region BB are electrically connected via a voltage signal link line 193. That is, each column of pixel driver circuits 10 transmits the first voltage signal to ensure transmission efficiency.

[0124] Embodiments of the present disclosure further provide a display field 100, wherein the display field 100 comprises the array substrate 1 provided in one of the above-mentioned embodiments. Therefore, the display field 100 provided in the present disclosure has all the advantageous effects of the array substrate 1 provided in one of the above-mentioned embodiments, which are not repeated here.

[0125] In some embodiments, the display field comprises 100 with reference to Fig. 11 furthermore, a layer 50 of light-emitting devices and an encapsulation layer 60, which are arranged on the array substrate 1. The array substrate 1 comprises a base substrate 101 and a layer stack 40 of pixel driver circuits. The layer stack 40 of pixel driver circuits comprises a plurality of TFT transistors. The layer 50 of light-emitting devices and the encapsulation layer 60 are stacked sequentially on the layer stack 40 of pixel driver circuits.

[0126] Layer 50 of the light-emitting device comprises an anode layer 22, a pixel definition layer 23, a light-emitting layer 24 and a cathode layer 25, which are arranged on the planarization layer 21.

[0127] The anode layer 22 comprises a plurality of anodes 221. The plurality of anodes 221 is electrically connected to the source-drain metal layer 19 via through-holes. The light-emitting layer 24 comprises a plurality of light-emitting sections. Each light-emitting section overlaps with an anode 221. The pixel definition layer 23 is provided with a plurality of pixel openings. Each pixel opening exposes a portion of an anode. The light-emitting sections in the light-emitting layer 24 are arranged in a one-to-one correspondence within the pixel openings, such that one edge of the light-emitting section coincides with an edge of the pixel opening.

[0128] The cathode layer is located on a side of the pixel definition layer 23 and the light-emitting layer 24 facing away from the array substrate 1.

[0129] The in Fig. Figure 11 shows a light-emitting device L comprising an anode, a cathode, and a light-emitting layer positioned between the anode and the cathode. A voltage is applied to both the anode and the cathode to generate an electric field between them, causing holes in the anode and electrons in the cathode to recombine in the light-emitting layer, thus enabling the light-emitting layer to emit light. The anode is positioned on the array substrate 1 and can be electrically connected to the pixel driver circuit 10.

[0130] The encapsulation layer 60 is located on the side of the cathode layer 25 facing away from the array substrate 1. For example, the encapsulation layer 60 comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 60 serves to encapsulate the light-emitting devices in order to protect the light-emitting devices L and thereby prevent corrosion by external water and oxygen.

[0131] Some embodiments of the present disclosure provide a display device 1000, wherein the display device may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle computer, or a portable display device. The embodiments of the present disclosure do not specifically restrict a particular form of the display device. As in Fig.As shown in Figure 1, the display device 1000 comprises the display field 100 provided in one of the embodiments mentioned above. Therefore, the display device 1000 provided in the present disclosure has all the advantageous effects of the display field 100 provided in one of the embodiments mentioned above, which are not repeated here.

[0132] The foregoing descriptions are only specific embodiments of the present disclosure. However, the scope of protection of the present disclosure is not limited thereto, and any person skilled in the art in the relevant technical field can conceive variations or substitutions within the technical scope of the present disclosure that fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of protection of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 202310996423.2

[0001]

Claims

[1] Array substrate, comprising: a plurality of pixel driver circuits, wherein the plurality of pixel driver circuits is arranged in a plurality of rows and a plurality of columns, and each of the plurality of pixel driver circuits comprises a plurality of transistors; a base substrate; a light-shielding layer arranged on one side of the base substrate, wherein the light-shielding layer comprises a plurality of light-shielding wires of the first type; a semiconductor layer arranged on a side of the light-shielding layer facing away from the base substrate, wherein the semiconductor layer comprises active layer patterns of the plurality of transistors; and a first gate layer located on a side of the semiconductor layer facing away from the base substrate, wherein the first gate layer comprises a plurality of sampling signal lines and Each of the sampling signal lines crosses an active layer pattern of at least one transistor; and the plurality of sampling signal lines transmits sampling signals, wherein each of the plurality of light-shielding wires of the first type crosses an active layer pattern of at least one transistor; and wherein a light shielding wire of the first type and a scanning signal line crossing an active layer pattern of the same transistor transmit the same scanning signal. [2] Array substrate according to claim 1, wherein the transistors of each pixel driver circuit comprise a compensation transistor and a data write transistor and the plurality of sampling signal lines comprise first sampling signal lines, wherein orthographic projections of the active layer patterns of the compensation transistors and the data write transistors in a series of pixel driver circuits on the base substrate overlap with an orthographic projection of a first sampling signal line on the base substrate; wherein the plurality of first-type light-shielding wires comprise first light-shielding wires, wherein the orthographic projections of the active layer patterns of the compensation transistors and the data-write transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of a first light-shielding wire on the base substrate; and wherein the first light shielding wire and the first scanning signal line transmit a first scanning signal. [3] Array substrate according to claim 2, wherein the transistors of each pixel driver circuit further comprise a first reset transistor and the plurality of sampling signal lines comprise second sampling signal lines, wherein orthographic projections of the active layer patterns of the first reset transistors in the array of pixel driver circuits overlap with an orthographic projection of a second sampling signal line on the base substrate; wherein the plurality of light-shielding wires of the first type comprise second light-shielding wires, wherein the orthographic projections of the active layer patterns of the first reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of a second light-shielding wire on the base substrate; and where the second light shielding wire and the second scanning signal line transmit a second scanning signal. [4] Array substrate according to claim 3, wherein the first sampling signal line and the second sampling signal line, which overlap with the same series of pixel driver circuits, transmit the same signal; wherein the array substrate comprises a display area and a border area, wherein the plurality of light-shielding wires of the first type extends along a line direction to the border area, wherein areas of the border area located on both sides of the display area along the line direction are each a first area and a second area; and wherein the first light-shielding wire and the second light-shielding wire, which overlap with the same series of pixel driver circuits, are electrically connected in the first area and / or in the second area. [5] Array substrate according to claim 4, wherein the array substrate further comprises at least one gate driver circuit located in the edge region, the gate driver circuit comprising a plurality of shift registers and each shift register being configured to transmit a sampling signal to a series of pixel driver circuits; wherein each shift register includes an output terminal that is electrically connected to the first sampling signal line and the second sampling signal line that are assigned to the series of pixel driver circuits; and wherein the array substrate further comprises a source-drain metal layer located on a side of the first gate layer facing away from the light-shielding layer, wherein the source-drain metal layer comprises a plurality of first interconnecting lines, each first interconnecting line being electrically connected at one end to an output terminal and electrically connected at the other end to a first light-shielding wire or a second light-shielding wire. [6] Array substrate according to one of claims 3 to 5, wherein the first light shielding wire is electrically connected to the first scanning signal line and the second light shielding wire is electrically connected to the second scanning signal line. [7] Array substrate according to claim 6, wherein the array substrate comprises a display area and a border area, wherein the plurality of light-shielding wires of the first type extends along a line direction to the border area, wherein areas of the border area located on both sides of the display area along the line direction are each a first area and a second area; and wherein the first light shielding wire is electrically connected to the first scanning signal line in the first area and / or in the second area and the second light shielding wire is electrically connected to the second scanning signal line in the first area and / or in the second area. [8] Array substrate according to claim 3, wherein the transistors of each pixel driver circuit further comprise a second reset transistor and the plurality of sampling signal lines comprise third sampling signal lines; wherein orthographic projections of the active layer patterns of the second reset transistors in the array of pixel driver circuits overlap with an orthographic projection of the third sampling signal line on the base substrate; wherein the plurality of light-shielding wires of the first type comprise third light-shielding wires, wherein the orthographic projections of the active layer patterns of the second reset transistors in the series of pixel driver circuits on the base substrate overlap with an orthographic projection of the third light-shielding wire on the base substrate; and where the third light shielding wire and the third scanning signal line transmit a third scanning signal. [9] Array substrate according to claim 8, wherein a third sampling signal line associated with an nth row of pixel driver circuits and a second sampling signal line associated with an (n-1)th row of pixel driver circuits are the same signal line. [10] Array substrate according to any one of claims 1 to 9, wherein the transistors of each pixel driver circuit further comprise a driver transistor and the light-shielding layer comprises a plurality of second-type light-shielding wires; wherein orthographic projections of the active layer patterns of the driver transistors in a series of pixel driver circuits on the base substrate overlap with an orthographic projection of a second-type light-shielding wire on the base substrate; and where the second type of light shielding wire transmits a first voltage signal. [11] Array substrate according to claim 10, further comprising: a source-drain metal layer arranged on a side of the first gate layer facing away from the light-shielding layer, wherein the source-drain metal layer includes first voltage signal lines and a first voltage signal line is electrically connected to the second type of light-shielding wire. [12] Array substrate according to claim 11, wherein each second-type light shielding wire overlaps with the driver transistors in a series of pixel driver circuits and each column of pixel driver circuits is connected to a corresponding first voltage signal line; and wherein at least three adjacent pixel driver circuits in each row of pixel driver circuits form a pixel driver circuit group and a first voltage signal line connected to at least one pixel driver circuit in the pixel driver circuit group is connected to the second type of light shielding wire. [13] Array substrate according to claim 12, wherein the array substrate comprises a display area and a perimeter area and the first voltage signal lines in the perimeter area are electrically connected to each other. [14] Array substrate according to any one of claims 10 to 13, wherein the second type of light-shielding wire comprises a plurality of light-shielding patterns and a plurality of connection patterns arranged alternately, each connection pattern being connected to two adjacent light-shielding patterns, wherein an orthographic projection of each light-shielding pattern on the base substrate surrounds an orthographic projection of a driver transistor of a pixel driver circuit on the base substrate. [15] Display field comprising the array substrate according to any one of claims 1 to 14. [16] Display device comprising the display field according to claim 15.

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