Multimodal power amplifier module, chip and communication terminal

Description

BACKGROUND Technical Field

[0001] The present invention relates to a multimode power amplifier module, a method for controlling the multimode power amplifier module, and a chip and a communication terminal that include the multimode power amplifier module, and belongs to the field of wireless communication technologies.Related Art

[0002] Currently, 4GLTE has entered a phase of large-scale promotion. However, it is quite a long process to implement full coverage of VoLTE, that is, mobile wideband audio application, and make traditional circuit switching quit the historical stage. Reasons are that on one hand, VoLTE relates to relatively many new technologies and requires necessary tests and experiments, and on the other hand, deployment and integration of an IMS (IP multimedia subsystem) takes some time, and a device of an existing network also needs to be upgraded and improved step by step.

[0003] Within quite a long period of time, an LTE network cannot provide an audio service. An audio part needs to use a 3G / 2G network. Because 3GWCDMA / CDMA relates to a problem of patent fees of Qualcomm, a platform manufacturer, for example, Media Tek, Spreadtrum, and Leadcore Technology all launch a solution of applying 2G to an audio part. Therefore, 2GGSM is indispensable within quite a long time in 4G communication. For this, mobile operators are making great efforts to promote three-mode and five-mode solutions. Three modes are mainly GSM / TD_SCDMA / TDD_LTE. Five modes are mainly GSM / TD_SCDMA / TDD _LTE / WCDMA / FDD _LTE. It is not hard to see that three modes and five modes are both inseparable from several modes: GSM / EDGE / TD_SCDMA / TDD_LTE.

[0004] In the foregoing several modes, two time-division multiplexing modes, TD-SCDMA and TDD-LTE, are mainly used for data transmission. Therefore, power consumption is a relatively serious problem. Power consumption of a multimode power amplifier module mainly focuses on a power amplifier. If performance and power consumption optimization of a power amplification chip can be performed in the two time-division multiplexing modes, performance and power consumption of the multimode power amplifier module can be optimized.

[0005] US 2006 / 214729 A1 relates to the technology effectively applied to a high-frequency power amplifier circuit that amplifies and outputs high-frequency signals. US 2015 / 222234 A1 relates to a power amplifier module, wherein the consumption current can be reduced in which the power supply voltage supplied to the power amplification transistor is controlled according to the level of output power.SUMMARY

[0006] The invention is set out in the appended set of claims.

[0007] Compared with the prior art, in the multimode power amplifier module, the chip, and the communication terminal provided in the present invention, according to frequency band features in different modes in a communication protocol, a power amplifier channel is fully multiplexed, so that different working modes of high and low frequency bands can share the power amplifier channel through adjustment of the control circuit, and in a time-division multiplexing mode, a bias voltage or bias current is made to implement a plurality of values as the baseband signal varies, so as to simplify design complexity of the power amplifier module and reduce costs of implementation of a related design.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a structural block diagram of a multimode power amplifier module according to an embodiment; FIG. 2 is a circuit diagram of a multimode power amplifier module according to an embodiment; FIG. 3 is a schematic diagram of controlling a power amplifier gain circuit according to a logic signal according to an embodiment; FIG. 4 is a schematic diagram of a collector voltage generation circuit according to an embodiment; FIG. 5 is a schematic diagram of a reference voltage generation circuit according to an embodiment; FIG. 6 is a schematic diagram of a bias signal generation circuit according to an embodiment; FIG. 7 is a schematic diagram of controlling a one-stage current adjustment circuit in a power amplifier by a bias signal according to an embodiment; FIG. 8 is a schematic diagram of a first embodiment of controlling a power amplifier bias signal according to a baseband signal; FIG. 9 is a schematic diagram of a relationship between a bias signal Reg_HB and a baseband signal Vramp according to the first embodiment; FIG. 10 is a schematic diagram of a second embodiment of controlling a power amplifier bias signal according to a baseband signal; FIG. 11 is a schematic diagram of a relationship between a bias signal Reg_HB and a baseband signal Vramp according to the second embodiment; FIG. 12 is a schematic diagram of a third embodiment of controlling a power amplifier bias signal according to a baseband signal; and FIG. 13 is a schematic diagram of a relationship between a bias signal Reg_HB and a baseband signal Vramp according to the third embodiment. DETAILED DESCRIPTION

[0009] The technical content of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0010] It should be noted first that in the embodiments of the present invention, the involved communication terminal refers to a computer device that may be used in a mobile environment and supports a plurality of communication systems such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE. The communication terminal includes but is not limited to a mobile phone, a notebook computer, a tablet computer, and an on-board computer. In addition, the multimode power amplifier module is also applicable to scenarios to which other multi-mode technologies are applied, for example, a communication base station compatible with multiple communication systems.

[0011] As stated in Related Art of the present invention, whether a three-mode solution or a five-mode solution includes three modes GSM / TD_SCDMA / TDD_LTE. Due to limitation of LTE network coverage, in a current three-mode / five-mode solution, it is still required to be compatible with an EDGE mode. A frequency of a PCS band in high-frequency GSM is 1850 MHz to 1910 MHz, a frequency band of TD_SCDMA is 1880 MHz to 1920 MHz and 2010 MHz to 2025 MHz, and a B39 frequency band of TD_LTE is 1880 MHz to 1920 MHz. Frequencies in the three modes are relatively close. In addition, frequency bands of GSM and EDGE completely overlap. These provide a possibility for circuit multiplexing. A power amplifier module has different requirements on an output power, a gain, linearity, and a working current when working in different modes. The foregoing indexes of the power amplifier module are determined by a power amplifier in the module. Therefore, the output power, gain, current, and linearity can be optimized by optimizing a gain network, a collector voltage, and a bias voltage (current) of the power amplifier in different modes.

[0012] FIG. 1 is a structural block diagram of a multimode power amplifier module according to an embodiment. As shown in FIG. 1, the multimode powder amplifier module includes: a low-frequency power amplifier channel, a high-frequency power amplifier channel, a control circuit, and a transmit-receive switch. The low-frequency power amplifier channel has at least a one-stage amplification circuit, and the high-frequency power amplifier channel also has at least a one-stage amplification circuit.

[0013] The low-frequency power amplifier channel includes a low-frequency input matching network, a low-frequency power amplifier, and a low-frequency output matching network that are connected in series and in sequence. The low-frequency input matching network is provided with a low-frequency input end and is used to access a low-frequency radio frequency signal, to implement impedance matching. The low-frequency power amplifier accesses the low-frequency radio frequency signal output by the low-frequency input matching network and is used to amplify the low-frequency radio frequency signal. The low-frequency output matching network is used to implement low-frequency impedance conversion, to output a low-frequency output power according to the amplified low-frequency radio frequency signal.

[0014] The high-frequency power amplifier channel includes a high-frequency input matching network, a high-frequency power amplifier, and a high-frequency output matching network that are connected in series and in sequence. The high-frequency input matching network is provided with a high-frequency input end and is used to access a high-frequency radio frequency signal, to implement impedance matching. The high-frequency power amplifier accesses the high-frequency radio frequency signal output by the high-frequency input matching network and is used to amplify the high-frequency radio frequency signal. The high-frequency output matching network is used to implement high-frequency impedance conversion, to output a high-frequency output power according to the amplified high-frequency radio frequency signal.

[0015] The control circuit is a core control component of the multimode power amplifier module. The control circuit is provided with at least three input ends, which are respectively used to access a control power supply Vbat, a baseband signal Vramp, and a working mode selection signal. The control circuit is connected to the low-frequency power amplifier and the high-frequency power amplifier and sends an amplifier control signal to the low-frequency power amplifier or the high-frequency power amplifier according to the baseband signal Vramp and the working mode selection signal. By using the control signal, the low-frequency power amplifier or the high-frequency power amplifier is controlled to amplify and optimize the accessed low-frequency radio frequency signal or high-frequency radio frequency signal.

[0016] The transmit-receive switch is connected to the control circuit, the low-frequency output matching network, and the high-frequency output matching network. The transmit-receive switch is used to select, according to the working mode selection signal, a corresponding working mode for transmission or receiving.

[0017] In the multimode power amplifier module, according to frequency band features in different modes in a communication protocol, a power amplifier channel is fully multiplexed, so that different working modes of high and low frequency bands can share the power amplifier channel through adjustment of the control circuit, so as to simplify design complexity of the power amplifier module, reduce costs of implementation of a related design, and provide advantages of being simple and flexible and being easy to implement.

[0018] FIG. 2 is a circuit diagram of a multimode power amplifier module according to an embodiment. As shown in FIG. 2, the multimode power amplifier module shown in this embodiment is designed to work in GMS (Global System for Mobile Communication), EDGE (Enhanced Data Rate for GSM Evolution), TD_SCDMA (Time Division-Synchronous Code Division Multiple Access), and TDD_LTE (Time Division Long Term Evolution) modes. Based on the foregoing analysis, the GSM mode and the EDGE mode further include a high-frequency mode and a low-frequency mode. Therefore, the two modes are divided into a low-frequency GSM mode, a high-frequency GSM mode, a low-frequency EDGE mode, and a high-frequency EDGE mode.

[0019] As shown in FIG. 2, in this embodiment, an external pin of the multimode power amplifier module includes: 109 is a low-frequency input end of a low-frequency power amplifier channel and is used to access a low-frequency GSM / EDGE radio frequency signal. 110 is a power supply access end of a control power supply of a control circuit 104 and is used to access a control power supply Vbat. 111 is a TX_enble interface and is used to access an enable signal of TX to the control circuit. 113 / 114 / 115 are interfaces of logic signals B0 / B1 / B2 and are used to access the logic signals B0 / B1 / B2 to the control circuit. The three logic signals B0 / B1 / B2 and the enable signal of TX together constitute a working mode selection signal of the control circuit and together control the multimode power amplifier module to select the working modes. 112 is a baseband signal interface of the control circuit and is used to access a baseband signal Vramp. The baseband signal Vramp may be any value from 0 to 1.8 V. When the GSM mode starts to operate, an output power of the multimode power amplifier module may be adjusted by setting different baseband signals Vramp. 116 is a high-frequency input end of the low-frequency power amplifier channel and is used to access GSM / EDGE / TD_SCDMA / TDD_LTE radio frequency signals. 117 is an antenna end. 118 / 119 / 120 / 121 / 122 / 123 respectively corresponding to TRX1, TRX2, TRX3, TRX4, TRX5, and TRX6, are six transmit-receive ports, and may be used as transmission ports or output ports.

[0020] As shown in FIG. 2, in this embodiment, the multimode power amplifier module includes: a low-frequency input matching network 101, used to access a low-frequency GSM / EDGE radio frequency signal, to implement matching of an impedance to 50 Ohm. The low-frequency power amplifier 102 is used to amplify the accessed low-frequency GSM / EDGE radio frequency signals (824 MHz to 849 MHz; 880 MHz to 915 MHz). The low-frequency output matching network 103 is used to implement low-frequency impedance conversion, to output a desired output power. The control circuit 104 may be implemented by using a CMOS. This is considered mainly from flexibility of design and costs. The control circuit 104 provides the amplifier control signal to the low-frequency power amplifier 102 and the high-frequency power amplifier 106 mainly according to the baseband signal Vramp and the working mode selection signal. The amplifier control signal includes: a logic signal Vmode, a bias signal Reg, and / or a collector voltage Vcc. In addition, the control circuit 104 also provides a power voltage and a logic voltage to the transmit-receive switch 108. The high-frequency input matching network 105 is used to access a high-frequency GSM / EDGE signal, a TD_SCDMA signal, and a TDD_LTE signal, to implement matching to 50 Ohm. The high-frequency power amplifier 106 amplifies the accessed high-frequency GSM / EDGE radio frequency signal, TD_SCDMA signal, and TDD_LTE signal (1710 MHz to 2025 MHz). The high-frequency output network 107 is used to implement high-frequency impedance conversion, to output a desired output power. The transmit-receive switch 108 is located at an antenna end and is connected to a transmit output and a receive input. The transmit-receive switch 108 in the embodiment shown in FIG. 2 is SP8T. the transmit-receive switch may be expanded to any SPXT according to needs, and is generally applied in a mobile phone antenna end. X is not less than 4. For example, three-mode five-frequency needs SP8T, five-mode 12-frequency needs SP16T, and SP10T, SP12T, or SP14T is applied in some cases.

[0021] The control circuit in the multimode power amplifier module provides an amplifier control signal to the power amplifier according to the baseband signal Vramp and the working mode selection signal, to perform amplification adjustment by controlling the power amplifier. The multimode power amplifier module fully multiplexes the power amplifier channel in this manner, so that different working modes of high and low frequency bands can share the power amplifier channel through adjustment of the control circuit. The amplifier control signal herein includes: the logic signal Vmode, the bias signal Reg, and / or the collector voltage Vcc.

[0022] How the control circuit performs amplification adjustment on the power amplifier by using the amplifier control signal is described in detail below by using several embodiments.

[0023] FIG. 3 is a schematic diagram of controlling a power amplifier gain circuit according to a logic signal. The power amplifier shown in FIG. 3 may be a low-frequency power amplifier or may be a high-frequency power amplifier. As shown in FIG. 3, a collector of the power amplifier is powered by the collector voltage Vcc output by the control circuit. A feedback circuit is disposed in the power amplifier. In FIG. 3, the feedback circuit of the power amplifier is composed of capacitors C30 and C31 and R30 that are mutually connected in series. The logic signal Vmode (for example, 0 or Vbat) output by the control circuit is used to control a feedback switch on the feedback circuit to be opened or closed.

[0024] When the logic signal Vmode controls the feedback switch to be opened, the feedback circuit is in a disconnected working state. In this case, because the feedback circuit does not function, the power amplifier is in a high gain mode. Generally, in a GSM working mode, a system requires the highest output power of the power amplifier module. Therefore, when the control circuit is in that working mode, the logic signal Vmode may be output to control the power amplifier to work in the high gain mode.

[0025] When the logic signal Vmode controls the feedback switch to be closed, the feedback circuit is in a connected working state. In this case, because the feedback circuit functions, the power amplifier is in a low gain mode. Generally, in EDGE / TD_SCDMA / TDD_LTE modes, a system requires a relatively low output power of the power amplifier module. Therefore, when the control circuit is in that working mode, the logic signal Vmode may be output to control the power amplifier to work in the low gain mode.

[0026] It can be learned that in this embodiment, the control circuit may determine, according to the working mode selection signal, a working mode in which the control circuit is, to determine whether the power amplifier should be located in the high gain mode or the low gain mode, to output a corresponding logic signal Vmode to the power amplifier.

[0027] As stated above, the collector voltage Vcc output by the control circuit is used to power the corresponding power amplifier as a collector voltage, to adjust an output power of the power amplifier. Therefore, the control circuit outputs different collector voltages Vcc according to current different working modes and may have a function of adjusting output of the power amplifier.

[0028] FIG. 4 is a schematic diagram of a collector voltage generation circuit. The collector voltage generation circuit is located in the control circuit. The control circuit determines, according to the working mode selection signal, a working mode in which the control circuit is. A corresponding basis voltage is selected according to the working mode in which the control circuit is, to generate the collector voltage Vcc based on the basis voltage.

[0029] As shown in FIG. 4, an operational amplifier is disposed in the collector voltage generation circuit. An output end of the operational amplifier is connected to a gate of an insulated gate bipolar transistor. An emitter of the insulated gate bipolar transistor accesses the control power supply Vbat. A collector of the insulated gate bipolar transistor is an output end of the collector voltage Vcc and is used to output the collector voltage Vcc. A resistor R41 is provided between a positive input end of the operational amplifier and the output end of the collector voltage Vcc. A resistor R42 is provided between the positive input end of the operational amplifier and the ground. A negative input end of the operational amplifier is a basis voltage input end and is used to input a basis voltage selected by the control circuit. As shown in FIG. 4, the basis voltage input end selects, by using different switches, to access different basis voltages.

[0030] When the working mode selection signal is in the GSM mode, a GSM_enble switch in FIG. 4 is closed, and the control circuit selects the baseband signal Vramp as the basis voltage, to generate the collector voltage Vcc. Vcc = 1 + R 41 R 42 × Vramp. Different Vcc values are obtained from different baseband Vramp values. Vcc is a power supply voltage of the power amplifier collector, and the output power P and Vcc have the following correspondence: P ≅ Vcc 2 2 R L , where RL is a load of the power amplifier and is determined by the output matching network. Therefore, the control circuit may adjust the output power of the power amplifier by using different baseband signals Vramp.

[0031] When the working mode selection signal is in the EDGE, TD_SCDMA, or TDD_LTE mode, EDGE / TD_SCDMA / TDD_LTE_enble switches in FIG. 4 are closed, and the control circuit selects the reference voltage Vref4 as the basis voltage, to generate the collector voltage Vcc. In this case, the power amplifier module is in a linear working mode, and change of the output power is implemented by changing change of the input signal. Vcc = 1 + R 41 R 42 × Vref 4. A proper reference voltage Vref4 is selected, so that the collector voltage Vcc = Vbat - V DS , where V DS is a saturated voltage difference of an M41 source / drain, and is generally 0.15 V to 0.2 V.

[0032] Vref4 is generated by a circuit principle diagram in FIG. 5. In FIG. 5, Vref4 = V BEQ 53 + R 52 R 51 × V T × lnn. V BE53 is a voltage difference from a base to an emitter of a bipolar transistor Q53, and is generally 0.7 V in a silicon process, n is a ratio of Q52 and Q51 emitter areas, and V T is a thermal voltage and is 0.026 V.

[0033] The bias signal Reg is used to adjust a current of the power amplifier. The control circuit controls, according to the working mode selection signal, to close a corresponding switch in the bias signal switch group, to generate a bias signal Reg corresponding to the working mode. Switches corresponding to the working modes are disposed in the bias signal switch group. The bias signal may be a voltage signal or may be a current signal.

[0034] FIG. 6 is a schematic diagram of a bias signal generation circuit. The bias signal generation circuit is located in the control circuit. The control circuit determines, according to the working mode selection signal, a working mode in which the control circuit is. The control circuit controls, according to the working mode in which the control circuit is, to close a corresponding switch in the bias signal switch group, to generate a bias signal Reg corresponding to the working mode.

[0035] As shown in FIG. 6, the bias signal generation circuit includes: an operational amplifier, a PMOS transistor, and the bias signal switch group.

[0036] A negative input end of the operational amplifier accesses the reference voltage Vref6, and the bias signal Reg is determined according to the reference voltage Vref6. Different bias signals Reg are needed in different modes. Reg and Vref6 conform to certain formulas. An output end of the operational amplifier is connected to a gate of the PMOS transistor. A source of the PMOS accesses the control power supply Vbat. A drain of the PMOS is an output end of the bias signal generation circuit and is used to output the bias signal Reg. The reference voltage Vref6 is generated based on the circuit shown in FIG. 5 and is not described in detail herein.

[0037] The bias signal switch group is connected between a positive input end of the operational amplifier and a collector of the PMOS transistor. Resistors are connected in series between the switches in the bias signal switch group.

[0038] As shown in FIG. 6, a TDD_SCDMA_enble switch, a TDD_LTE enble switch, an EDGE_enble switch, and a GSM_enble switch are disposed in the bias signal switch group. As shown in FIG. 6, resistors R61, R62, R63, R64, and R65 are respectively connected in series between the switches. The control circuit determines, according to the working mode selection signal, a working mode in which the control circuit is. The control circuit selects, according to the working mode in which the control circuit is, to control closing a corresponding switch in the bias signal switch group. For example, when in the TDD_LTE mode, the control circuit selects to close the TDD_LTE_enble switch, and other switches remain in a disconnected state. The bias signal Reg is generated based on this.

[0039] Generally, in the GSM mode, the bias signal Reg is higher, and in the EDGE / TD_SCDMA modes, the bias signals Reg are sequentially reduced. However, the bias voltage in the TDD_LTE mode is between that in the GSM mode and those in the EDGE / TD_SCDMA modes and mainly balances power consumption and linearity. Based on the bias signal generation circuit provided in FIG. 6, in the GSM mode, Reg = 1 + R 61 + R 62 + R 63 + R 64 R 65 × Vref 6; in the EDGE mode, Reg = 1 + R 61 + R 62 + R 63 R 64 + R 65 × Vref 6 ; in the TDD_SCDMA mode, R eg = 1 + R 61 + R 62 R 63 + R 64 + R 65 × Vref 6 ; in the TD_LTE mode, Reg = 1 + R 61 R 62 + R 63 + R 64 + R 65 × Vref 6. It can be learned that bias signals Reg corresponding to the GSM, EDGE, TD_SCDMA, and TDD_LTE working modes are sequentially reduced. The general design herein also includes that TD_SDMA and TDD_LTE share the same Reg or the bias signal of TDD_LTE is greater than that of TD_SCDMA.

[0040] Certainly, setting of specific switches in the bias signal switch group may be correspondingly adjusted according to specific working mode types supported by the multimode power amplifier module. However, a basic design principle is the same. Any adjustment performed by a person skilled in the art on the bias signal switch group based on the technical teaching provided in this embodiment should be considered to fall within the protection scope of the present invention.

[0041] The bias signal adjusts a power amplifier current by using a circuit shown in FIG. 7. FIG. 7 is a principle diagram of controlling a one-stage circuit in a power amplifier by a bias signal. In an actual design, the power amplifier may be two-stage or three-stage, and each stage may be controlled by using a bias circuit part in FIG. 7. In FIG. 7, V 71 ≅ R D 1 + R D 2 R D 1 + R D 2 + R 71 × Reg , where R D1 and R D2 are conduction resistors of diodes D1 and D2, and after the diodes D1 and D2 are selected, R D1 and R D2 are fixed values.

[0042] V 72 = V 71 - V BEQ71 , V 73 = V BEQ72 , I BQ 72 = V 72 − V 73 R 72 , I CQ 72 = β × I BQ 72 ≅ β × R D 1 + R D 2 R D 1 + R D 2 + R 71 × Reg − V BEQ 71 − V BEQ 72 R 72 , , where V BEQ71 and V BEQ72 are voltage differences between bases and emitters of heterojunction bipolar transistors (HBT) Q71 and Q72. Using a gallium arsenide HBT as an example, V be =1.3 V. I BQ72 is a base current of the heterojunction bipolar transistor Q72, β is an amplification multiple, generally ranges from 60 to 160, and is mainly determined by a process of the heterojunction bipolar transistor.

[0043] As stated above, the bias signal Reg accesses the bias circuit of the power amplifier. The bias circuit includes R71, D1, D2, and a collector of a bipolar transistor Q71. The diodes D1 and D2 and R71 generate V71 through voltage division. V71 generates V72 through voltage drop of one V BE . A voltage difference between V72 and V73 determines a current passing through R72, that is, a base current of the bipolar transistor Q72, to implement current control over Q72. Q72 herein is the power amplifier transistor of the power amplifier. The collector of Q71 may also be directly connected to Vbat.

[0044] On the other hand, in two time-division multiplexing modes, TD_SCDMA and TDD_LTE, the power amplifier should be in a linear power amplification state all the time. When an output power of the multimode power amplifier module is relatively high, to ensure certain linearity, the power amplifier needs a relatively large bias current. In this case, the control circuit needs to provide a relatively large bias signal Reg. In this way, performance of the multimode power amplifier module is optimized. When the output power of the multimode power amplifier module is relatively low, in this case, the power amplifier needs only a relatively low bias current to implement enough linearity. In this case, if the control circuit provides a relatively small bias signal Reg, the bias current needed by the power amplifier can be reduced, to reduce power consumption of the multimode power amplifier module.

[0045] As stated above, the control circuit in the multimode power amplifier module provides the amplifier control signal to the power amplifier according to the baseband signal and the working mode selection signal, to perform amplification adjustment by controlling the power amplifier. The amplifier control signal herein includes but is not limited to: the logic signal Vmode, the bias signal Reg, and / or the collector voltage Vcc. In the existing two time-division multiplexing modes, TD_SCDMA and TDD_LTE, the baseband signal Vramp participate in selection of the two time-division multiplexing modes as a logic level, and may be a high level or a low level. Therefore, the bias voltage or bias current in the two time-division multiplexing modes has only one value and cannot be adjusted according to the output power of the multimode power amplifier module.

[0046] Other embodiments provided in the present invention breaks through the foregoing technical limitation, and creatively propose making the bias voltage or bias current implement a plurality of values in the time-division multiplexing mode as the baseband signal Vramp varies. For unity of descriptions, the foregoing bias voltage and bias current are collectively referred to as bias signals Reg. that is, in a scenario in which a voltage signal needs to be used as a bias signal, the bias signal Reg is the bias voltage; in a scenario in which a current signal needs to be used as a bias signal, the bias signal Reg is the bias current. Change of the bias voltage or bias current causes an output current of the power amplifier to change, to optimize performance and power consumption of the entire multimode power amplifier module.

[0047] How the control circuit adjusts the bias signal Reg of the power amplifier by using the baseband signal Vramp is specifically described below by using several other embodiments.

[0048] FIG. 8 is a schematic diagram of a first embodiment of controlling a power amplifier bias signal according to a baseband signal. In this embodiment, the baseband signal Vramp is input into the negative input end (also referred to as a reverse-phase input end) of the operational amplifier. The output end of the operational amplifier is connected to a gate of an insulated gate bipolar transistor. A source of the insulated gate bipolar transistor accesses the control power supply Vbat. A drain of the insulated gate bipolar transistor is an output end of the bias signal Reg_HB and is used to output a bias signal. The drain of the insulated gate bipolar transistor is grounded by using resistors R21 and R22. A connection point of the resistors R21 and R22 is directly connected to a positive input end (also referred to as an in-phase input end) of the operational amplifier.

[0049] As shown in FIG. 9, in the two time-division multiplexing modes, TD_SCDMA and TDD_LTE, by using the baseband signal Vramp, the bias signal Reg_HB and the baseband signal Vramp are made to satisfy a linear function relationship. For example, Reg_HB=G*Vramp or Reg _HB=G*(Vramp+Vbias), where a parameter G is a fixed value. The bias signal Reg_HB herein may be a voltage signal or may be a current signal. According to a value of the baseband signal Vramp and a value of the bias voltage or bias current that is needed for design of optimization, the corresponding parameter G can be obtained. In the first embodiment shown in FIG. 8, the following formula: Reg_HB = 1 + R 21 R 22 × Vramp can be obtained. In other words, the parameter G needed by a user can be obtained by selecting proper resistances of the resistors R21 and R22.

[0050] FIG. 10 is a schematic diagram of a second embodiment of controlling a power amplifier bias signal according to a baseband signal. In the second embodiment, connection manners of most of circuits are basically the same as those in the first embodiment, and a difference mainly lies in a drain output part of the insulated gate bipolar transistor. In the second embodiment, the collector of the insulated gate bipolar transistor is connected to the ground by using the resistors R31, R32, R33, and R34. A gating switch is disposed between a connection point of the resistors R31 and R32 and the positive input end of the operational amplifier. The gating switch is conducted when Vramp<A and is open in other cases. A gating switch is disposed between a connection point of the resistors R32 and R33 and the positive input end of the operational amplifier. The gating switch is conducted when A<Vramp<B and is open in other cases. A gating switch is disposed between a connection point of the resistors R33 and R34 and the positive input end of the operational amplifier. The gating switch is conducted when Vramp>B and is open in other cases. Herein, A and B are particular threshold voltages.

[0051] Based on the circuit diagram of the second embodiment shown in FIG. 10, the bias signal Reg_HB and the baseband signal Vramp may be made to in the stair step linear relationship shown in FIG. 11. In the embodiment shown in FIG. 11, using an example in which a stair step shape is divided into three segments, the bias signal Reg_HB may be set to several fixed values according to different baseband signal Vramp values. That is, when Vramp<A, Reg_HB=V1; when A<Vramp<B, Reg_HB=V2. When Vramp>B, Reg_HB=V3. Further, when Vramp<A, Reg_HB = V 1 = 1 + R 31 R 32 + R 33 + R 34 × V ref ; when A<Vramp<B, Reg HB = V 2 = 1 + R 31 + R 32 R 33 + R 34 × V ref ; when Vramp>B, Reg_HB = V 3 = 1 + R 31 + R 32 + R 33 R 34 × V ref . Herein, V1<V2<V3. In an actual implementation process, a value of a relationship between V1, V2, and V3 is determined by the designed performance requirement. In some cases, one of the values V1, V2, or V3 can be 0.

[0052] FIG. 12 is a schematic diagram of a third embodiment of controlling a power amplifier bias signal according to a baseband signal. In the third embodiment, connection manners of most of circuits are basically the same as those in the second embodiment, and a difference mainly lies in that the baseband signal Vramp and the reference voltage Vref41 respectively access a positive input end and a negative input end of a multi-channel analog switch (MUX). An output end signal Vref42 of the multi-channel analog switch, in replacement of an original baseband signal Vramp, accesses the negative input end of the operational amplifier. The multi-channel analog switch has at least two channels, and opening or closing of the channels are determined by the baseband signal and the working mode. In the third embodiment, the collector of the insulated gate bipolar transistor is connected to the ground by using the resistors R41, R42, R43, and R44. A gating switch is disposed between a connection point of the resistors R41 and R42 and the positive input end of the operational amplifier. The gating switch is conducted when Vramp<A and is open in other cases. A gating switch is disposed between a connection point of the resistors R42 and R43 and the positive input end of the operational amplifier. The gating switch is conducted when A<Vramp<B and is open in other cases. A gating switch is disposed between a connection point of the resistors R43 and R44 and the positive input end of the operational amplifier. The gating switch is conducted when Vramp>B and is open in other cases. Herein, A and B are particular threshold voltages.

[0053] Based on the circuit diagram of the third embodiment shown in FIG. 12, the bias signal Reg_HB and the baseband signal Vramp may be made to in the step linear relationship shown in FIG. 13. In the embodiment shown in FIG. 13, using an example in which a step shape is divided into three segments, the bias signal Reg_HB may be set to several fixed values according to different baseband signal Vramp values. That is, when the baseband signal Vramp<A, the bias signal Reg_HB is a fixed voltage value V4; when A<Vramp<B, the bias signal Reg _HB=V5=G*Vramp; when the baseband signal Vramp>B, the bias signal Reg_HB is also a fixed voltage value, and Reg_HB=V6. Further, when the baseband signal Vramp<A, the multi-channel analog switch changes an output thereof to Vref42=Vref41, and Reg HB = V 4 = 1 + R 41 R 42 + R 43 + R 44 × V ref 41 . When A<Vramp<B, the multi-channel analog switch changes the output thereof to Vref42=Vramp, and Reg_HB = V 5 = 1 + R 41 + R 42 R 43 + R 44 × Vramp. When the baseband signal Vramp>B, the multi-channel analog switch changes the output thereof to Vref42=Vref41, and Reg_HB = V 6 = 1 + R 41 + R 42 + R 43 R 44 × Vref 41.

[0054] It should be noted that if more resistors are disposed between the drain of the transistor and the ground, and more gating switches are disposed, the stair step linear relationship between the baseband signal Vramp and the bias signal Reg can be made to become more complex and various, to satisfy actual needs of different application scenarios. The transistor herein includes but is not limited to the insulated gate biopolar transistor, the field-effect transistor, or a triode. Corresponding circuit adjustment is a conventional technical means that can be mastered by a person skilled in the art and does not go beyond the technical teaching provided in the present invention, and is not described in detail herein.

[0055] On the other hand, although TD_SCDMA and TDD_LTE are both time-division multiplexing working modes, they have different requirements on the bias signal Reg. therefore, in the TD_SCDMA and TDD_LTE modes, working performance can be further optimized by setting different baseband signals Vramp.

[0056] Based on different embodiments of the foregoing multimode power amplifier module, a multimode power amplifier module output control method provided in the present invention may be further summarized. The method includes the following steps: providing a bias signal to a low-frequency power amplifier channel, where a magnitude of the bias signal is determined by a magnitude of a baseband signal and a working mode; and providing a bias signal to a high-frequency power amplifier channel, where a magnitude of the bias signal is determined by the magnitude of the baseband signal and the working mode. The bias signal is controlled by the baseband signal and the working mode and linearly or very nearly linearly changes with the baseband signal. Alternatively, the bias signal is controlled by the baseband signal and the working mode and changes with the baseband signal in a stair step manner. Alternatively, the bias signal is controlled by the baseband signal and the working mode and linearly changes with the baseband signal in a step manner.

[0057] The multimode power amplifier module shown in the foregoing embodiment may be used in a chip. The structure of the multimode power amplifier module in the chip is not described in detail herein.

[0058] In addition, the multimode power amplifier module may also be used in a communication terminal as an important component of a radio frequency circuit. The communication terminal herein refers to a computer device that may be used in a mobile environment and supports a plurality of communication modes such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE. The communication terminal includes but is not limited to a mobile phone, a notebook computer, a tablet computer, and an on-board computer. In addition, the multimode power amplifier module is also applicable to scenarios to which other multi-mode technologies are applied, for example, a communication base station compatible with multiple communication systems. Details are not provided herein.

[0059] The multimode power amplifier module, the chip, and the communication terminal provided in the present invention are described in detail above.

Claims

1. A multimode power amplifier module, comprising a low-frequency power amplifier channel, a high-frequency power amplifier channel, a control circuit (104), and a transmit-receive switch (108), wherein the low-frequency power amplifier channel comprises a low-frequency input matching network (101), a low-frequency power amplifier (102), and a low-frequency output matching network (103) that are connected in series and in sequence; the low-frequency input matching network (101) is configured to access a low-frequency radio frequency signal, to implement impedance matching; the low-frequency power amplifier (102) is configured to amplify the low-frequency radio frequency signal; the low-frequency output matching network (103) is configured to implement low-frequency impedance conversion, to output a low-frequency output power according to the amplified low-frequency radio frequency signal; the high-frequency power amplifier channel comprises a high-frequency input matching network (105), a high-frequency power amplifier (106), and a high-frequency output matching network (107) that are connected in series and in sequence; the high-frequency input matching network (105) is configured to access a high-frequency radio frequency signal, to implement impedance matching; the high-frequency power amplifier (106) is configured to amplify the high-frequency radio frequency signal; the high-frequency output matching network (107) is configured to implement high-frequency impedance conversion, to output a high-frequency output power according to the amplified high-frequency radio frequency signal; the control circuit (104) is configured to access a control power supply (Vbat), a baseband signal (Vramp), and a working mode selection signal; the control circuit (104) is configured to send an amplifier control signal to the low-frequency power amplifier or the high-frequency power amplifier in accordance with the baseband signal (Vramp) and the working mode selection signal; the amplifier control signal includes: a logic signal, a bias signal, and / or a collector voltage (Vcc_LB, Vcc_HB); the transmit-receive switch (108) is connected to the control circuit (104), the low-frequency output matching network, and the high-frequency output matching network and is configured to select a corresponding working mode for transmitting or receiving according to the working mode selection signal; characterized in that: in the control circuit (104), the baseband signal (Vramp) and a reference voltage (Vref41) are connected to the positive input and the negative input of a multi-channel analog switch, respectively, the output of the multi-channel analog switch is connected to the negative input of an operational amplifier, and the output of the operational amplifier is connected to the gate of a transistor, the source of the transistor is connected to the control power supply (Vbat), wherein in a time-division multiplexing working mode the control circuit is configured to generate the bias signal (Reg_HB) at the drain of the transistor, wherein the drain of the transistor is connected to the ground by a plurality of resistors (R41, R42, R43, R44) connected in series, a first gating switch is disposed between a first connection point between a first resistor (R41) of the plurality of resistors and a second resistor (R42) of the plurality of resistors, and the positive input end of the operational amplifier, the first gating switch is only conducting when a magnitude of the baseband signal is smaller than or equal to A; a second gating switch is disposed between a second connection point between the second resistor (R42) of the plurality of resistors and a third resistor (R43) of the plurality of resistors, and the positive input end of the operational amplifier, the second gating switch is only conducting when the magnitude of the baseband signal is larger than A and smaller than B; a third gating switch is disposed between a third connection point between the third resistor (R43) of the plurality of resistors and a fourth resistor (R44) of the plurality of resistors, and the positive input end of the operational amplifier, the third gating switch is only conducting when the magnitude of the baseband signal is larger than or equal to B; wherein A and B are threshold voltages and A is smaller than B; wherein the output of the multi-channel analog switch is configured to provide the baseband signal when the magnitude of the baseband signal is larger than A and smaller than B, and to provide the reference voltage when the magnitude of the baseband signal is smaller than or equal to A or greater than or equal to B; and wherein the control circuit is configured to provide the bias signal to the high-frequency power amplifier.

2. A multimode power amplifier module, comprising a low-frequency power amplifier channel, a high-frequency power amplifier channel, a control circuit (104), and a transmit-receive switch (108), wherein the low-frequency power amplifier channel comprises a low-frequency input matching network (101), a low-frequency power amplifier (102), and a low-frequency output matching network (103) that are connected in series and in sequence; the low-frequency input matching network (101) is configured to access a low-frequency radio frequency signal, to implement impedance matching; the low-frequency power amplifier (102) is configured to amplify the low-frequency radio frequency signal; the low-frequency output matching network (103) is configured to implement low-frequency impedance conversion, to output a low-frequency output power according to the amplified low-frequency radio frequency signal; the high-frequency power amplifier channel comprises a high-frequency input matching network (105), a high-frequency power amplifier (106), and a high-frequency output matching network (107) that are connected in series and in sequence; the high-frequency input matching network (105) is configured to access a high-frequency radio frequency signal, to implement impedance matching; the high-frequency power amplifier (106) is configured to amplify the high-frequency radio frequency signal; the high-frequency output matching network (107) is configured to implement high-frequency impedance conversion, to output a high-frequency output power according to the amplified high-frequency radio frequency signal; the control circuit (104) is configured to access a control power supply (Vbat), a baseband signal (Vramp), and a working mode selection signal; the control circuit (104) is configured to send an amplifier control signal to the low-frequency power amplifier or the high-frequency power amplifier in accordance with the baseband signal (Vramp) and the working mode selection signal; the amplifier control signal includes: a logic signal, a bias signal, and / or a collector voltage (Vcc_LB, Vcc_HB); the transmit-receive switch (108) is connected to the control circuit (104), the low-frequency output matching network, and the high-frequency output matching network and is configured to select a corresponding working mode for transmitting or receiving according to the working mode selection signal; characterized in that: in the control circuit (104), a reference signal (Vref) is input to the negative input of an operational amplifier, the output of the operational amplifier is connected to the gate of a transistor; the source of the transistor is connected to the control power supply (Vbat), wherein in a time-division multiplexing working mode the control circuit is configured to generate the bias signal (Reg_HB) at the drain of the transistor, wherein the drain of the transistor is connected to the ground by a plurality of resistors (R31, R32, R33, R34) connected in series, a first gating switch is disposed between a first connection point between a first resistor (R31) of the plurality of resistors and a second resistor (R32) of the plurality of resistors, and the positive input end of the operational amplifier, the first gating switch is only conducting when a magnitude of the baseband signal is smaller than or equal to A; a second gating switch is disposed between a second connection point between the second resistor (R32) of the plurality of resistors and a third resistor (R33) of the plurality of resistors, and the positive input end of the operational amplifier, the second gating switch is only conducting when the magnitude of the baseband signal is larger than A and smaller than B; a third gating switch is disposed between a third connection point between the third resistor (R33) of the plurality of resistors and a fourth resistor (R34) of the plurality of resistors, and the positive input end of the operational amplifier, the third gating switch is only conducting when the magnitude of the baseband signal is larger than or equal to B; wherein A and B are threshold voltages and A is smaller than B; and wherein the control circuit is configured to provide the bias signal to the high-frequency power amplifier.

3. The multimode power amplifier module according to claims 1 or 2, wherein the time-division multiplexing working mode is a TD_SCDMA or TDD_LTE working mode.

4. A chip having a multimode power amplifier module, wherein the chip comprises the multimode power amplifier module according to any one of claims 1 to 3.

5. A communication terminal having a multimode power amplifier module, wherein the communication terminal comprises the multimode power amplifier module according to any one of claims 1 to 3.