METHOD FOR DETECTING A DOWNLINK CONTROL CHANNEL AND DEVICE AND METHOD FOR DETECTION

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, in particular to a method for detecting a downlink control channel, a method for transmitting a downlink control channel, and relevant devices.BACKGROUND

[0002] In a satellite communication system, a Synchronization Signal Block (SSB) is transmitted periodically in a fixed pattern. Each SSB occupies 4 consecutive Orthogonal Frequency Division Multiplexing (OFDM) symbols in a time domain, and within a slot for transmitting the SSBs, a first SSB occupies the 4 th< to 7 th< OFDM symbols. Considering the requirement on a Peak-to-Average Power Ratio (PAPR), a downlink control channel and the SSB are multiplexed in a Time Division Multiplexing (TDM) manner on first N symbols within each slot. A first symbol within the slot is used to transmit a Common Reference Signal (CRS) rather than the other channel(s). However, a Direct Fourier Transformer Spread Orthogonal Frequency Division Multiplexing (DFT-s-OFDM) waveform is used in the satellite communication system, and in order to ensure a single-carrier characteristic, it is impossible to transmit different channels on a time-domain symbol on a transmission bandwidth. When there is a collision between a Control Resource Set (CORESET) and a symbol for transmitting the SSB, all Physical Downlink Control Channels (PDCCHs) in the CORESET are incapable of being transmitted normally, resulting in a scheduling failure.

[0003] A 3GPP contribution titled "Summary of open issues related to rate-matching in NR" (R1-1805518) discloses certain issues regarding rate-matching for PDSCH in NR.

[0004] A 3GPP contribution titled "Remaining details of RMSI" (R1-1800080) discusses certain issues regarding RMSI PDCCH search space indication in NR-PBCH.SUMMARY

[0005] An object of the present disclosure is to provide a method for detecting a downlink control channel, a method for transmitting a downlink control channel, and relevant devices, so as to solve the problem in the related art where the PDCCHs in the CORESET are incapable of being transmitted normally and thereby the scheduling failure occurs when there is a collision between the CORESET and the symbol for transmitting the SSB.

[0006] The present invention is set out in the appended set of claims.

[0007] The present disclosure has the following beneficial effects.

[0008] According to the embodiments of the present disclosure, the downlink control channel is detected within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in a downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a flow chart of a method for detecting a downlink control channel according to one embodiment of the present disclosure; FIG. 2 is a schematic view showing the application of the methods according to some embodiments of the present disclosure; FIG. 3 is another schematic view showing the application of the methods according to some embodiments of the present disclosure; FIG. 4 is a flow chart of a method for transmitting a downlink control channel according to one embodiment of the present disclosure; FIG. 5 is a schematic view showing a UE according to one embodiment of the present disclosure; and FIG. 6 is a schematic view showing a network device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments.

[0011] As shown in FIG. 1, the present disclosure provides in some embodiments a method for detecting a downlink control channel for a UE, which includes Step 101 of detecting the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot. According to the embodiments of the present disclosure, the downlink control channel is detected within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in a downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.

[0012] Of course, the downlink control channel is transmitted by a corresponding network device within the current slot using the PDCCH resource pattern in accordance with whether there is the SSB within the current slot, so that the UE detects and receives the downlink control information.

[0013] In some possible embodiments of the present disclosure, Step 101 includes detecting the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

[0014] Here, the first PDCCH resource pattern is a PDCCH resource pattern suitable for detecting the downlink control channel within the slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in the time domain, and occupies B1 RBs in the frequency domain. In this regard, the UE detects and receives the downlink control channel using the first PDCCH resource pattern within the slot where there is the SSB.

[0015] Correspondingly, the network device transmits the downlink control channel using the first PDCCH resource pattern within the slot where the SSB is transmitted.

[0016] In the embodiments of the present disclosure, in order to ensure that a PDCCH transmission resource does not overlap the SSB in the time domain. In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0017] Here, for the first PDCCH resource pattern predefined in a protocol or determined in accordance with the resource position of the SSB, the consecutive N1 symbols occupied in the time domain do not overlap the SSB in the time domain.

[0018] In addition, in the embodiments of the present disclosure, Step 101 further includes detecting the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0019] Here, the second PDCCH resource pattern is a PDCCH resource pattern suitable for detecting the downlink control channel within the slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in the time domain, and occupies B2 RBs in the frequency domain. In this regard, the UE detects and receives the downlink control channel using the second PDCCH resource pattern within the slot where there is no SSB.

[0020] Correspondingly, the network device transmits the downlink control channel using the second PDCCH resource pattern within the slot where no SSB is transmitted.

[0021] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by the network device through high layer signaling.

[0022] The application of the method in the embodiments of the present disclosure will be described hereinafter in conjunction with specific scenarios.

[0023] In a first scenario, the network device, e.g., a base station, needs to transmit two SSBs (SSB#1 and SSB#2) within a period of 20ms, and the SSBs are transmitted within 5ms. Within a slot (slot#0) where the SSBs are transmitted, SSB#1 occupies symbols {#2 #3 #4 #5}, and SSB#2 occupies symbols {#8 #9 #10 #11}. A downlink control channel transmission region configured by the base station for the UE is symbols {#1 #2 #3} within the slot, and it occupies an entire transmission bandwidth B3 in the frequency domain. The symbol #0 is used for transmitting a CRS. The downlink control channel transmission region is called as a PDCCH resource pattern 1. Meanwhile, a PDCCH resource pattern 2 is defined as occupying the symbol {#1} within the slot in the time domain and occupying the entire transmission bandwidth B3 in the frequency domain. As shown in FIG. 2, within the slot (slot#1) where no SSB is transmitted, the base station transmits the downlink control channel using the PDCCH resource pattern 1, and the UE detects and receives the downlink control channel using the PDCCH resource pattern 1. Within the slot (slot#0) where the SSB is transmitted, the base station transmits the downlink control channel using the PDCCH resource pattern 2, and the UE detects and receives the downlink control channel using the PDCCH pattern 2. In other words, the base station and the UE adaptively and flexibly adjust a transmission region and a reception region for the downlink control channel in accordance with a transmission position of the SSB.

[0024] In this regard, the base station does not need to transmit the downlink control channel using a single PDCCH resource pattern, so it is able to prevent a decrease in a control channel capacity within the slot where the SSB is transmitted, and enable the UE to detect and receive the PDCCH within the slot where the SSB is transmitted.

[0025] In a second scenario, the network device, e.g., a base station, needs to transmit two SSBs (SSB#1 and SSB#2) within a period of 20ms, and the SSBs are transmitted within 5ms. Within a slot (slot#0) where the SSBs are transmitted, SSB#1 occupies symbols {#2 #3 #4 #5}, and SSB#2 occupies symbols {#8 #9 #10 #11}. A downlink control channel transmission region configured by the base station for the UE is symbols {#1 #2 #3} within the slot, and it occupies a bandwidth B4 in the frequency domain. The bandwidth B4 is determined implicitly in accordance with a size of a frequency domain of CORESET#0, e.g., it occupies a same number of RBs in the frequency domain as CORESET#0. The symbol #0 is used for transmitting a Cell Reference Signal (CRS).

[0026] The downlink control channel transmission region is called as a PDCCH resource pattern 3. Meanwhile, a PDCCH resource pattern 4 is defined as occupying the symbol {#1} within the slot in the time domain and occupying an entire transmission bandwidth B5 in the frequency domain, where B5>B4.

[0027] As shown in FIG. 3, within the slot (slot#1) where no SSB is transmitted, the base station transmits the downlink control channel using the PDCCH resource pattern 4, and the UE detects and receives the downlink control channel using the PDCCH resource pattern 4. Within the slot (slot#0) where the SSB is transmitted, the base station transmits the downlink control channel using the PDCCH resource pattern 3, and the UE detects and receives the downlink control channel using the PDCCH pattern 3. In other words, the base station and the UE adaptively and flexibly adjust a transmission region and a reception region for the downlink control channel in accordance with a transmission position of the SSB.

[0028] In this regard, the base station does not need to transmit the downlink control channel using a single PDCCH resource pattern, so it is able to prevent a decrease in a control channel capacity within the slot where the SSB is transmitted, and enable the UE to detect and receive the PDCCH within the slot where the SSB is transmitted.

[0029] According to the method for detecting the downlink control channel in the embodiments of the present disclosure, the downlink control channel is detected within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in the downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.

[0030] As shown in FIG. 4, the present disclosure provides in some embodiments a method for transmitting a downlink control channel for a network device, which includes Step 401 of transmitting the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot.

[0031] Through this step, the network device transmits the downlink control channel within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in a downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.

[0032] In some possible embodiments of the present disclosure, Step 401 includes transmitting the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

[0033] Here, the first PDCCH resource pattern is a PDCCH resource pattern suitable for detecting the downlink control channel within the slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in the time domain, and occupies B1 RBs in the frequency domain.

[0034] In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0035] Here, for the first PDCCH resource pattern predefined in a protocol or determined in accordance with the resource position of the SSB, the consecutive N1 symbols occupied in the time domain do not overlap the SSB in the time domain.

[0036] In some possible embodiments of the present disclosure, Step 401 includes transmitting the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0037] Here, the second PDCCH resource pattern is a PDCCH resource pattern suitable for detecting the downlink control channel within the slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in the time domain, and occupies B2 RBs in the frequency domain. In this regard, the network device transmits the downlink control channel using the second PDCCH resource pattern within the slot where there is no SSB.

[0038] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by a network device through high layer signaling.

[0039] It should be appreciated that, the method is applied to the network device, and cooperates with the above-mentioned method for detecting the downlink control channel for UE to transmit and receive the downlink control channel. The implementation of the method may refer to that of the method for the UE mentioned hereinabove, with a same technical effect.

[0040] As shown in FIG. 5, the present disclosure provides in some embodiments a UE, which includes a transceiver 520, a memory 540, a processor 510, and a program stored in the memory 540 and executed by the processor 510. The processor 510 is configured to execute the program, so as to detect the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot.

[0041] In some possible embodiments of the present disclosure, the processor 510 is further configured to detect the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1. In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0042] In some possible embodiments of the present disclosure, the processor 510 is further configured to detect the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0043] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by a network device through high layer signaling.

[0044] In FIG. 5, bus architecture may include a number of buses and bridges connected to each other, so as to connect various circuits for one or more processors 510 and one or more memories 540. In addition, as is known in the art, the bus architecture may be used to connect any other circuits, such as a circuit for a peripheral device, a circuit for a voltage stabilizer and a power management circuit. A bus interface may be provided, and the transceiver 520 may consist of a plurality of elements, i.e., a transmitter and a receiver for communication with any other devices over a transmission medium. For example, the transceiver 520 receives external data from the other device, and transmits data processed by the processor 510 to the other device. Depending on properties of a computing system, a user interface 530, e.g., a keypad, a display, a speaker, a microphone or a joystick, may also be provided.

[0045] The processor 510 may take charge of managing a bus 500 as well as general processings. The memory 540 may store therein data for the operation of the processor 510.

[0046] In some possible embodiments of the present disclosure, the processor 510 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

[0047] As shown in FIG. 6, the present disclosure provides in some embodiments a network device, which includes a transceiver 620, a memory 630, a processor 610, and a program stored in the memory 630 and executed by the processor 610. The processor 610 is configured to execute the program so as to transmit the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot.

[0048] In some possible embodiments of the present disclosure, the transceiver 620 is configured to transmit the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

[0049] In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0050] In some possible embodiments of the present disclosure, the transceiver 620 is further configured to transmit the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0051] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by a network device through high layer signaling.

[0052] The transceiver 620 is configured to receive and transmit data under the control of the processor 610. In FIG. 6, bus architecture may include a number of buses and bridges connected to each other, so as to connect various circuits for one or more processors 610 and one or more memories 630. In addition, as is known in the art, the bus architecture may be used to connect any other circuits, such as a circuit for a peripheral device, a circuit for a voltage stabilizer and a power management circuit. A bus interface may be provided, and the transceiver 620 may consist of a plurality of elements, i.e., a transmitter and a receiver for communication with any other devices over a transmission medium. The processor 610 may take charge of managing the bus architecture as well as general processings. The memory 630 may store therein data for the operation of the processor 610.

[0053] The present disclosure further provides in some embodiments a device for detecting a downlink control channel for a UE, which includes a processing module configured to detect the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot.

[0054] In some possible embodiments of the present disclosure, the processing module includes a first processing sub-module configured to detect the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

[0055] In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0056] In some possible embodiments of the present disclosure, the processing module includes a second processing sub-module configured to detect the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0057] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by a network device through high layer signaling.

[0058] According to the device in the embodiments of the present disclosure, the downlink control channel is detected within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in a downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.

[0059] It should be appreciated that, the device is configured to implement the above-mentioned method for the UE, and the implementation of the device may refer to that of the method for the UE with a same technical effect.

[0060] The present disclosure further provides in some embodiments a device for transmitting a downlink control channel for a network device, which includes a transmission module configured to transmit the downlink control channel within a current slot using a corresponding PDCCH resource pattern in accordance with whether there is an SSB within the current slot.

[0061] In some possible embodiments of the present disclosure, the transmission module includes a first transmission sub-module configured to transmit the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted. The first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 RBs in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

[0062] In some possible embodiments of the present disclosure, the first PDCCH resource pattern is pre-defined in a protocol or determined in accordance with a resource position of the SSB.

[0063] In some possible embodiments of the present disclosure, the transmission module includes a second transmission sub-module configured to transmit the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted. The second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

[0064] In some possible embodiments of the present disclosure, the second PDCCH resource pattern is configured by a network device through high layer signaling.

[0065] According to the device in the embodiments of the present disclosure, the downlink control channel is transmitted within the current slot using an appropriate PDCCH resource pattern in accordance with whether there is the SSB within the current slot. As a result, it is able to prevent a decrease in a downlink control channel capacity, thereby to prevent the occurrence of such a circumstance where it is impossible to transmit the downlink control channel within the slot where the SSB is transmitted.

[0066] It should be appreciated that, the device is configured to implement the above-mentioned method for the network device, and the implementation of the device may refer to that of the method for the network device with a same technical effect.

[0067] The present disclosure further provides in some embodiments a computer-readable storage medium storing therein a program. The program is executed by a processor so as to implement the steps in the above-mentioned method for detecting the downlink control channel for the UE, or the steps in the above-mentioned method for transmitting the downlink control channel.

[0068] The computer-readable storage medium may include volatile or nonvolitle, mobile or immobile storage medium capable of storing therein information using any method or technique. The information may be a computer-readable instruction, a data structure, a program or any other data. The computer-readable storage medium may include, but not limited to, a Random Access Memory (e.g., Phase Change Random Access Memory (PRAM), Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM)), a Read Only Memory (ROM) (e.g., an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, a Compact Disc Read Only Memory (CD-ROM) or a Digital Video Disk (DVD)), a magnetic storage device (e.g., a cassette magnetic tape or a magnetic disk), or any other non-transmission medium capable of storing therein information which can be accessed by a computing device. As defined in the present disclosure, the computer-readable storage medium may not include any transitory media, e.g., modulated data signal or carrier.

[0069] It should be further appreciated that, the UE described in the specification includes, but not limited to, smart phone or tablet computer. The functional members described in the specification are referred to as modules, so as to emphasize the independence of the implementation in a more particular manner.

[0070] In the embodiments of the present disclosure, the modules are implemented by software, so as to be executed by various processors. For example, an identified, executable code module includes one or more physical or logical blocks including computer instructions, and the module is constructed as an image, a process or a function. Even so, the executable codes of the identified modules are unnecessary to be physically located together, but include different instructions stored in different locations. When these instructions are logically combined together, they form the modules and achieve the prescribed purposes of the modules.

[0071] Actually, the executable code module is a single instruction or a plurality of instructions, and even it is distributed at different code segments, in different programs, or across a plurality of memory devices. Also, operational data is identified in the modules, implemented in any appropriate form, and organized in any data structure of an appropriate type. The operational data is collected as a single data set, or distributed at different locations (including different memory devices), and it is at least partially present in a system or network merely as an electronic signal.

[0072] When the modules can be implemented by software, considering the current hardware level, a person skilled in the art can build a corresponding hardware circuit to achieve the corresponding function if taking no account of the cost. The hardware circuit includes a conventional very-large-scale integration (VLSI) circuit, a gate array, an existing semiconductor such as a logic chip and a transistor, or other discrete components. The modules are further implemented by a programmable hardware device, such as a field-programmable gate array, a programmable array logic device and a programmable logic device.

[0073] It should be appreciated that, the embodiments of the present disclosure are implemented by hardware, software, firmware, middleware, microcode or a combination thereof. For the hardware implementation, the processor includes one or more of an Application Specific Integrated Circuits (ASIC), a Digital Signal Processor (DSP), a DSP device (DSPD), a Programmable Logic Device (PLD), a Field-Programmable Gate Array (FPGA), a general-purpose processor, a controller, a microcontroller, a microprocessor, any other electronic unit capable of achieving the functions in the present disclosure, or a combination thereof.

[0074] The scope of protection of the invention is limited by the appended claims.

Claims

1. A method for detecting a downlink control channel performed by a User Equipment, UE, the method comprising: detecting (101) the downlink control channel within a current slot using a corresponding Physical Downlink Control Channel, PDCCH, resource pattern in accordance with whether there is a Synchronization Signal Block, SSB, within the current slot, the method being characterized by the detecting (101) the downlink control channel within the current slot using the corresponding PDCCH resource pattern in accordance with whether there is the SSB within the current slot comprises: detecting (101) the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted; or detecting (101) the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted.

2. The method according to claim 1, wherein the first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 Resource Blocks, RBs, in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

3. The method according to claim 2, wherein the first PDCCH resource pattern is pre-defined or determined in accordance with a resource position of the SSB.

4. The method according to claim 1, wherein the second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

5. The method according to claim 4, wherein the second PDCCH resource pattern is configured by a network device through high layer signaling.

6. A method for transmitting a downlink control channel performed by a network device, the method comprising: transmitting (401) the downlink control channel within a current slot using a corresponding Physical Downlink Control Channel, PDCCH, resource pattern in accordance with whether there is a Synchronization Signal Block, SSB, within the current slot, the method being characterized by the transmitting (401) the downlink control channel within the current slot using the corresponding PDCCH resource pattern in accordance with whether there is the SSB within the current slot comprises: transmitting (401) the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted; or transmitting (401) the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted.

7. The method according to claim 6, wherein the first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 Resource Blocks, RBs, in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1.

8. The method according to claim 7, wherein the first PDCCH resource pattern is pre-defined or determined in accordance with a resource position of the SSB.

9. The method according to claim 6, wherein the second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1.

10. The method according to claim 9, wherein the second PDCCH resource pattern is configured by a network device through high layer signaling.

11. A User Equipment, UE, comprising a transceiver (520), a memory (540), a processor (510), and a program stored in the memory (540) and executed by the processor (510), wherein the processor (510) is configured to execute the program, so as to detect (101) the downlink control channel within a current slot using a corresponding Physical Downlink Control Channel, PDCCH, resource pattern in accordance with whether there is a Synchronization Signal Block, SSB, within the current slot, the UE being characterized by the processor (510) is further configured to detect the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted; or the processor (510) is further configured to detect the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted.

12. The UE according to claim 11, wherein the first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 Resource Blocks, RBs, in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1, wherein the first PDCCH resource pattern is pre-defined or determined in accordance with a resource position of the SSB.

13. The UE according to claim 11, wherein the second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1, wherein the second PDCCH resource pattern is configured by a network device through high layer signaling.

14. A network device, comprising a transceiver (620), a memory (630), a processor (610), and a program stored in the memory (630) and executed by the processor (610), wherein the transceiver (620) is configured to execute the program, so as to transmit (401) the downlink control channel within a current slot using a corresponding Physical Downlink Control Channel, PDCCH, resource pattern in accordance with whether there is a Synchronization Signal Block, SSB, within the current slot, the network device being characterized by wherein the transceiver (620) is further configured to transmit the downlink control channel using a first PDCCH resource pattern within a slot where the SSB is transmitted; or wherein the transceiver (620) is further configured to transmit the downlink control channel using a second PDCCH resource pattern within a slot where no SSB is transmitted.

15. The network device according to claim 14, wherein the first PDCCH resource pattern occupies consecutive N1 symbols in a time domain and B1 Resource Blocks, RBs, in a frequency domain, and the N1 symbols do not overlap symbols for transmitting the SSB, where N1 is a positive integer greater than or equal to 1, and B1 is a positive integer greater than or equal to 1, wherein the first PDCCH resource pattern is pre-defined or determined in accordance with a resource position of the SSB; or wherein the second PDCCH resource pattern occupies consecutive N2 symbols in a time domain and B2 RBs in a frequency domain, where N2 and B2 are each a positive integer greater than or equal to 1, wherein the second PDCCH resource pattern is configured by a network device through high layer signaling.