COMMUNICATION METHOD FOR ELECTRONIC CIRCUITS OF AN ELECTRIC ACCUMULATOR BATTERY

Description

[0001] This patent application claims priority from French patent application FR19 / 15090 which will be considered as an integral part of this description. Technical field

[0002] This description generally relates to a method of exchanging data between electronic circuits, in particular electronic circuits of an electric accumulator battery, also called a battery pack. Prior art

[0003] It is known to produce a battery comprising several stages or modules in each of which electric accumulators, also called cells, can be connected in series or in parallel by controllable switches. Such a battery is adapted to provide a voltage whose waveform varies over time by varying the connection of the cells over time via the closing or opening of the switches.

[0004] The battery may include a control circuit, called a master control circuit, which can transmit data to each module. The master control circuit may, in particular, transmit commands to each module to close and / or open the module's switches. Each module may transmit data to the master control circuit, in particular data from sensors, for example the voltage across each cell in the module or the temperature of each cell in the module.

[0005] The master control circuit can receive an instruction, for example a voltage and / or current and / or connection instruction for a given number of cells, and select the cells to be connected or disconnected for each module so as to obtain the desired voltage and / or current. The transmission of commands from the master control circuit to the modules is generally considered to have priority, in particular compared to other signals exchanged between the master control circuit and the modules.

[0006] For some applications, it may be desirable to provide a single bidirectional communication bus between the master control circuit and the modules, in particular to reduce the manufacturing costs of the battery pack. However, it may be difficult to ensure proper exchange of signals between the master control circuit and the modules with different priorities assigned to the exchanged signals, in particular when the frequency of transmission of switch opening and closing commands from the master control circuit to the modules is high. Documents US 2008 / 059682, US 2018 / 357199, US 6,452,946, and FR 3,076,108 describe methods for exchanging data between electronic circuits. Summary of the invention

[0007] Thus, an object of an embodiment is to provide a data exchange method, in particular for a battery, which overcomes at least some of the drawbacks of the data exchange methods described previously.

[0008] Another object of an embodiment is that the transmission of commands from the master control circuit of the battery to the modules is not disturbed by the transmission of data other than the commands between the modules and the master control circuit.

[0009] Another object of an embodiment is to prevent conflicts between the modules for transmitting signals to the master control circuit.

[0010] An embodiment provides a method of communication between a first electronic circuit and second electronic circuits via a bidirectional bus allowing full duplex communication, each second electronic circuit having a unique identifier, the method comprising the transmission by the first electronic circuit of first frames on the bus to the second electronic circuits, each first frame comprising the same number of bits, the bits of each first frame being distributed into successive groups of bits, the positions of the groups being the same in each first frame, a first group of bits among the groups of bits corresponding to a first identifier among the identifiers,a second group of bits among the groups of bits corresponding to commands to be executed by the second electronic circuit corresponding to the first identifier and a third group of bits among the groups of bits corresponding to a second identifier among the identifiers, only the second electronic circuit corresponding to the second identifier being authorized to transmit a second frame to the first electronic circuit on the bus.,

[0011] According to one embodiment, the first electronic circuit modifies the third group of bits of the first frames to cyclically scan all of the identifiers according to a given order.

[0012] According to one embodiment, the first electronic circuit transmits a succession of first frames with the third group of words corresponding to the same second identifier if it has not received a second frame transmitted by the second electronic circuit corresponding to the second identifier.

[0013] According to one embodiment, the first electronic circuit successively emits several first frames with the third group of words corresponding to a given value not corresponding to one of the identifiers if, after the emission of said succession of first frames, it has still not received a second frame emitted by the second electronic circuit corresponding to the second identifier.

[0014] According to one embodiment, the first electronic circuit and the second electronic circuits are part of a battery of electric accumulators, the electric accumulators being distributed into sets of electric accumulators, each second electronic circuit corresponding to the first identifier controlling the connection or disconnection of each electric accumulator from one of the sets from said commands.

[0015] According to one embodiment, the commands are commands for closing or opening switches connecting the electrical accumulators.

[0016] According to one embodiment, when the first identifier is identical to the second identifier, the second electronic circuit corresponding to the first identifier executes the commands before sending the second frame.

[0017] According to one embodiment, each second electronic circuit is connected to at least one voltage and / or current sensor, and the second frame comprises data representative of at least one value measured by the sensor connected to the second electronic circuit corresponding to the second identifier.

[0018] According to one embodiment, the transmission by the first electronic circuit of the first frames on the bus to the second electronic circuits is carried out periodically.

[0019] An embodiment also provides an electronic system comprising a first electronic circuit and second electronic circuits connected to the first electronic circuit by a bidirectional bus configured to allow full duplex communication, each second electronic circuit having a unique identifier, the first electronic circuit being configured to transmit first frames on the bus to the second electronic circuits, each first frame comprising the same number of bits, the bits of each first frame being distributed into successive groups of bits, the positions of the groups being the same in each first frame, a first group of bits among the groups of bits corresponding to a first identifier among the identifiers,a second group of bits among the groups of bits corresponding to commands to be executed by the second electronic circuit corresponding to the first identifier and a third group of bits among the groups of bits corresponding to a second identifier among the identifiers, only the second electronic circuit corresponding to the second identifier being authorized to transmit a second frame to the first electronic circuit on the bus.,

[0020] According to one embodiment, the system corresponds to a battery of electric accumulators, the electric accumulators being distributed into sets of electric accumulators, each second electronic circuit being configured to control the connection and disconnection of each electric accumulator from one of the sets from said commands. Brief description of the drawings

[0021] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there Figure 1 represents, in a partial and schematic manner, an embodiment of an accumulator battery; the Figure 2 is a block diagram illustrating an embodiment of a method of communication in the battery of the Figure 1 seen from the master control circuit side; the Figure 3 is a block diagram illustrating an embodiment of a method of communication in the battery of the Figure 1 seen from the side of one of the slave control circuits; and the Figure 4 represents, in a partial and schematic way, an example of a battery module of the Figure 1 . Description of the embodiments

[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the conventional functions performed by a master control circuit of a storage battery such as cell balancing are well known to those skilled in the art and are not described in more detail below. In addition, a "binary signal" is a signal that alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example a high state, denoted "1".The high and low states of different binary signals in the same electronic circuit can be different. In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

[0023] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures. Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%.

[0024] There Figure 1represents an embodiment of a battery 5. The battery 5 comprises N modules E 1 to EN . The number N is an integer which can be between 1 and 50. Each module comprises a positive terminal B+ and a negative terminal B- and several cells, not shown, which can be connected together, in series and / or in parallel, by means of switches, not shown, between the terminals B+ and B-. The modules E 1 to EN can be connected in series between a first Neutral terminal of the battery 5 and a second Phase terminal of the battery 5. An example of such a battery is described in patent application WO 2012 / 117110.

[0025] The battery 5 comprises a BMS circuit for controlling the modules E 1 to EN , hereinafter called the master control circuit. The BMS master control circuit may correspond to a dedicated circuit or may comprise a processor, for example a microprocessor or a microcontroller, adapted to execute instructions of a computer program stored in a memory. The BMS master control circuit may exchange data with each module E 1 to EN via a data transmission bus BUS, also called a communication bus. The data transmission bus BUS is a bidirectional bus. Each module E i , i varying from 1 to N, comprises a circuit SC i , hereinafter called the slave control circuit, configured to control the switches of the module E i from commands supplied by the BMS master control circuit.Each module E i further comprises sensors, not shown, for example sensors of the voltage at the terminals of each cell of the module, sensors of the current supplied by each cell of the module and / or sensors of the temperature of each cell of the module. The slave control circuit SC i of each module E 1 to EN is adapted to transmit data to the master control circuit BMS via the data transmission bus BUS, for example data representative of the measurements of voltages, currents, temperatures, the state of the cells, etc.

[0026] The master control circuit BMS is configured to receive a setpoint C, for example a voltage and / or current and / or connection setpoint of a given number of electrical accumulators between the Phase and Neutral terminals, and to select the cells to be connected or disconnected for each module so as to obtain the desired voltage and / or current between the Phase and Neutral terminals of the battery 5. The master control circuit BMS then provides commands to the slave control circuits of the modules via the data transmission bus BUS from which the slave control circuit SC i of each module E i connects or disconnects the cells of the module E i according to the desired configuration.

[0027] The data transmission bus BUS is a bidirectional bus. According to one embodiment, the battery 5 does not comprise any other data transmission bus from the master control circuit BMS to the modules E 1 to EN , nor any other data transmission bus from the modules E 1 to EN to the master control circuit BMS. According to one embodiment, the data transmission bus BUS is a fast bus, i.e. a bus on which data is transmitted with a rate greater than 3 megabits per second, preferably between 5 megabits per second and 7 megabits per second. For example, the data transmission bus BUS is a bus conforming to the RS485 standard.

[0028] According to one embodiment, the data transmission bus BUS is a bidirectional bus which allows full duplex communication, i.e. the simultaneous transmission of signals in both directions. The data transmission bus BUS may comprise at least a first line BUS1 for transmitting data from the master control circuit BMS to each slave control circuit SC i and a second line BUS2 for transmitting data from each slave control circuit SC i to the master control circuit BMS.

[0029] There Figure 2 is a block diagram illustrating an embodiment of a method for transmitting data from the master control circuit BMS to the slave control circuits SC 1 to SC N .

[0030] In step 10 (Send frame), the BMS master control circuit transmits a data frame on the data transmission bus BUS. A data frame comprises a series of bits.

[0031] According to one embodiment, the master control circuit BMS transmits frames on the data transmission bus BUS in a substantially periodic manner. The frequency of transmission of successive frames by the master control circuit BMS on the data transmission bus BUS may be between 1 kHz and 50 kHz, for example equal to approximately 20 kHz.

[0032] According to one embodiment, the frames transmitted by the master control circuit BMS on the data transmission bus BUS have the same size, that is to say they each comprise the same number of bits. According to one embodiment, each frame transmitted by the master control circuit BMS on the data transmission bus BUS may have a number of bits between 50 bits and 100 bits, for example approximately 70 bits.

[0033] According to one embodiment, the frames transmitted by the master control circuit BMS on the data transmission bus BUS have the same structure. This means that the bits of the frame are divided into successive groups of bits, each group of bits corresponding to a particular data item, and the position of each group of bits in the frame is the same from one frame to another, that is to say that for each group, the position of the first bit of the group is the same for each frame and the position of the last bit of the group is the same for each frame.

[0034] The fact that the frames transmitted by the master control circuit BMS on the data transmission bus BUS have the same size and the same structure advantageously makes it easier for the slave control circuits to process the frames.

[0035] According to one embodiment, each slave control circuit is associated with a different identifier. A first group of bits among the groups of bits of the frame corresponds to an identifier of one of the modules E 1 to EN to which commands for connecting / disconnecting the cells of the module are sent with the same frame. A second group of bits among the groups of bits of the frame corresponds to commands for connecting / disconnecting the cells, i.e. commands for opening / closing the switches of the module whose identifier is that of the first group. According to one embodiment, each frame transmitted by the master control circuit BMS only includes the commands for connecting / disconnecting cells, in whole or in part, for only one of the modules E 1 to EN .According to one embodiment, for a particular value of the first group of bits, the commands of the second group of bits of the frame can be treated by each slave control circuit as being intended for it. This advantageously makes it possible to send the same commands simultaneously to all the slave control circuits.

[0036] According to one embodiment, the BMS master control circuit performs cell balancing, i.e. the selection of the cells is carried out in such a way that the differences between the charge states of the cells are permanently as small as possible. According to one embodiment, the BMS master control circuit takes into account, for the selection of the cells, a possible failure of a cell so as, for example, to exclude this cell from the selection. According to one embodiment, the BMS master control circuit selects cells to be connected / disconnected by ensuring that each cell operates within its optimal operating range based on the voltage, current and temperature measurements provided by the modules.

[0037] A third bit group among the bit groups corresponds to an identifier of one of the modules E 1 to EN which is authorized to transmit data on the data transmission bus BUS. The module corresponding to the identifier of the third bit group may be identical to or different from the module corresponding to the identifier of the first bit group. The identifier of the third bit group is called a token hereinafter to distinguish it from the identifier of the first bit group.

[0038] A fourth group of bits among the groups of bits in the frame corresponds to data other than cell connection / disconnection commands, hereinafter referred to as slow data, and which are intended for all the slave control circuits. The slow data may comprise an operating mode of the battery pack modules, between, for example, a normal operating mode, in which the cells can be connected / disconnected, and a maintenance operating mode, in which, for example, a program is transmitted to the slave control circuits. The slow data may comprise programming data, in particular a program executed by the slave control circuits.

[0039] Generally speaking, the reading of the bits of the frame by each slave control circuit, from the first bit of the frame to the last bit of the frame, is not done in one go, but set of bits after set of bits, each set of bits comprising the same number of bits. A group of bits as defined above can correspond to several successive sets of bits. Each set of bits corresponds, for example, to a byte.

[0040] According to one embodiment, one of the bits of each set of bits at a fixed position in the set of bits, for example the most significant bit of the set of bits or the least significant bit of the set of bits, is in a first state, for example at "1", for the first set of bits read from a frame, and is in a second state, for example at "0", for all the other sets of bits of the frame. This makes it easier for the slave control circuits to detect the reception of a new frame.

[0041] According to one embodiment, one of the bits of each set of bits at a fixed position in the set of bits, for example the most significant bit of the set of bits or the least significant bit of the set of bits, is in a first state, for example at "1", for the last set of bits read from a frame, and is in a second state, for example at "0", for all the other sets of bits of the frame. This makes it easier for the slave control circuits to detect the end of reception of the current frame.

[0042] In a step 11 (Receive response?), the BMS master control circuit determines whether it has received a response from the slave control circuit corresponding to the token of the frame transmitted in step 10. If, in step 11, the BMS master control circuit has not received a response (N), the method continues to a step 12 (Threshold?). If, in step 11, the BMS master control circuit determines that it has received a response from the slave control circuit corresponding to the token of the last frame transmitted (O), the method continues to a step 13 (Change identifier).

[0043] In step 12, the BMS master control circuit determines whether enough frames including the same token have been transmitted. If not (N), the method continues to step 10 in which the BMS master control circuit transmits a new frame with the same token as the previous frame. However, for this new frame, the first, second and fourth data groups described above may be different from those of the previous frame transmitted by the BMS master control circuit. If, in step 12, the BMS master control circuit determines that enough frames including the same token have been transmitted (O), the method continues to a step 14 (Wait).The BMS master control circuit determines that enough frames including the same token have been transmitted, for example when the number of frames successively transmitted by the BMS master control circuit with the same token exceeds a number or when frames are successively transmitted by the master control circuit with the same token for a determined duration, for example 1 ms.

[0044] In step 14, the master control circuit BMS transmits on the communication bus BUS, for a determined duration, frames whose token does not correspond to any of the identifiers of the slave control circuits (or the previous token), which indicates that no slave control circuit is authorized to transmit on the communication bus BUS. This determined duration may be between 100 µs and 5 ms, for example equal to approximately 500 µs. This makes it possible to take into account the case where the slave control circuit, corresponding to the token of the last frame transmitted in step 10 by the master control circuit BMS, only begins to respond to the master control circuit BMS shortly after the transmission of this frame. The method continues, after the determined duration, in step 13.

[0045] In step 13, the master control circuit BMS modifies the token to be used in the next frame to be transmitted in step 10 to designate another slave control circuit. The method continues in step 10 in which the master control circuit BMS transmits a frame containing the new token on the communication bus BUS.

[0046] According to one embodiment, each slave control circuit SC i can only transmit a frame on the communication bus BUS after receiving a frame, transmitted by the master control circuit BMS, comprising the token that corresponds to it. This makes it possible to prevent two slave control circuits from simultaneously transmitting frames on the communication bus BUS. The master control circuit BMS changes the token in the next frame to be transmitted only when it has received a satisfactory response from the slave control circuit to which the token currently in use corresponds or when a threshold is reached as described previously. When the master control circuit BMS has not received a response from the slave control circuit corresponding to the last token used at the end of step 14, the master control circuit BMS can then consider that the slave control circuit to which the token corresponds is faulty.

[0047] According to one embodiment, the master control circuit BMS uses, in the transmitted frames, the tokens corresponding to all the slave control circuits according to a given order, for example from the token corresponding to the slave control circuit SC 1 to the token corresponding to the slave control circuit SC N . When all the identifiers have been used, the master control circuit BMS starts using the tokens again from the beginning according to the given order. As a result, the slave control circuits are authorized to transmit data to the master control circuit BMS in turn. Advantageously, this allows each slave control circuit to be polled regularly.

[0048] According to one embodiment, as soon as a slave control circuit receives a frame transmitted by the master control circuit BMS comprising the token associated with it, it seeks to transmit a frame in response on the communication bus BUS as quickly as possible. However, according to one embodiment, when the slave control circuit receives a frame transmitted by the master control circuit BMS comprising both the token associated with it and the identifier of the first group of bits associated with it, the slave control circuit executes the commands indicated in the frame before attempting to transmit a frame in response on the communication bus BUS.

[0049] There Figure 3is a block diagram illustrating an embodiment of a method for transmitting data from one of the slave control circuits SC i on the communication bus BUS to the master control circuit BMS. This method can be implemented by each slave control circuit.

[0050] At a step 20 (Frame reception), the slave control circuit SC i detects a frame on the communication bus BUS transmitted by the master control circuit BMS. The process continues at a step 21 (Command to be executed?).

[0051] In step 21, the slave control circuit determines whether the first group of bits of the frame, corresponding to the identifier of one of the modules E 1 to EN to which commands for connecting / disconnecting the cells of the module are sent with the same frame, corresponds to its identifier. If the first group actually corresponds to the identifier of the control circuit SC i (O), the method continues to a step 22 (Execution of the commands). If the first group does not correspond to the identifier of the control circuit SC i (N), the method continues to a step 23 (Token?).

[0052] In step 22, the slave control circuit controls the connection and / or disconnection of electrical accumulators from the module according to the commands present in the frame. The method continues in step 23.

[0053] In step 23, the slave control circuit determines whether the token present in the received frame is the one that corresponds to it. If the token actually corresponds to that of the slave control circuit SC i (O), the method continues to a step 24 (Sending frame). If the token does not correspond to that of the slave control circuit SC i (N), the method continues to a step 25 (Additional tasks).

[0054] In step 24, the slave control circuit SC i prepares a response frame, which it transmits on the communication bus BUS. For example, the response frame may contain the voltage values of the cells of the module, the temperature values of the cells of the module, the operating states of the cells of the module, other operating faults of the module and / or information relating to the programs executed by the slave control circuit SC i .

[0055] In step 25, the slave control circuit performs secondary tasks other than those performed in step 22 and step 24. This may involve the collection of measured values of voltage, current, temperature, etc., and the processing of the collected data. Step 25 is interrupted upon receipt of a new frame transmitted by the master control circuit BMS on the communication bus BUS. The method then continues in step 20. Step 24 may also be interrupted upon receipt of a new frame transmitted by the master control circuit BMS on the communication bus BUS, the method then continuing in step 20.

[0056] The transmission frequency of frames from the slave control circuits to the master control circuit may be lower than the transmission frequency of frames from the master control circuit to the slave control circuits. The maximum transmission frequency of frames from the slave control circuits to the master control circuit may be of the order of 100 Hz.

[0057] There Figure 4 represents an embodiment of the module E i , where i varies from 1 to N.

[0058] According to the present embodiment, the module E i is adapted to provide a voltage U i between the positive terminal B+ and the negative terminal B-. The module E i comprises cells C 1 to CM where M is an integer between 2 and 10, preferably between 2 and 5, four cells C 1 , C 2 , C 3 and C 4 being represented as an example in Figure 4. The cells C 1 to CM are connected to each other and to the terminals B+ and B- by switches. In the present embodiment, for each cell C k , k being an integer varying from 1 to M, the module E i comprises a first switch SW 1,k in series with the cell C k and a second switch SW 2,k in parallel with the assembly comprising the cell C k and the switch SW 1,k . The M assemblies comprising the cell C k and the first switch SW 1,k are arranged in series between a node A and a node B. The control of the switches SW 1,k and SW 2,k , k varying from 1 to M, makes it possible to put in series between the nodes A and B, 1 to M cells among the M cells C 1 to CM . In the present embodiment, the module E i further comprises an inverter bridge, also called an H-bridge, between the nodes A and B and the terminals B+ and B- which makes it possible to apply the voltage present between the nodes A and B between the terminals B+ and B- in both directions.According to one embodiment, the inverter bridge comprises a switch SW 3 connecting node A to terminal B+, a switch SW 4 connecting node A to terminal B-, a switch SW 5 connecting node B to terminal B+ and a switch SW 6 connecting node B to terminal B-. For example, each switch SW 1,k and SW 2,k, k varying from 1 to M, SW 3 , SW 4 , SW 5 and SW 6 may correspond to an insulated gate field effect transistor, also called a MOS (Metal Oxide Semiconductor) transistor, in particular a power MOS transistor, for example an N-channel MOS transistor.

[0059] Each module E i further comprises the slave control circuit SC i (µC) adapted to exchange data transmitted by the master control circuit BMS on the data transmission bus BUS. The slave control circuit SC i may correspond to a dedicated circuit or may comprise a processor, for example a microprocessor or a microcontroller, adapted to execute instructions of a computer program stored in a memory.

[0060] Each module E i further comprises a control circuit 32 (Inverter bridge driver) connected to the switches SW 3 , SW 4 , SW 5 and SW 6 of the inverter bridge and a control circuit 34 (Transistors driver) connected to the switches SW 1,k and SW 2,k , k varying from 1 to M. Each control circuit 32, 34 is adapted to convert the control signals supplied by the slave control circuit SC i into signals adapted to the control of the switches.

[0061] Each module E i further comprises sensors 36 (U, I, T° sensor) connected to the slave control circuit SC i . The module E i may comprise, for each cell C k , a temperature sensor adapted to measure the temperature of the cell C k . The module E i may further comprise, for each cell C k , a voltage sensor adapted to measure the voltage across the cell C k . The module E i may further comprise a current sensor adapted to measure the current flowing at node A or at node B. The slave control circuit SC i of each module E i is adapted to transmit third data to the master control circuit BMS on the data transmission bus BUS representative of the measurements made by the sensors SC i of the module E i . The number and type of sensors depends in particular on the arrangement of the cells of the module E i . In the arrangement of cells shown in Figure 4, only one sensor of the current flowing at node A or node B can be provided.

[0062] In the embodiment of battery module E i shown in Figure 4, a connection order of cell C k of module E i means that cell C k must be connected in series between nodes A and B of module E i , which is achieved by closing switch SW 1,k and opening switch SW 2,k , and a disconnection order of cell C k of module E i means that cell C k must not be connected in series between nodes A and B of module E i , which is achieved by opening switch SW 1,k and closing switch SW 2,k . However, for a different arrangement of cells C k of module E i in which cells C k may be arranged in series and / or in parallel with each other between nodes A and B, a connection order of a cell C k further specifies in which configuration, series or parallel, cell C k is in relation to the other cells of module E i .

[0063] According to one embodiment, the second group defined previously of each frame can, for the architecture of the modules E i represented in Figure 4 , to understand : an open / close command for switches SW 1,1 and SW 2,1; an open / close command for switches SW 1,2 and SW 2,2; an open / close command for switches SW 1,3 and SW 2,3; an open / close command for switches SW 1,4 and SW 2,4; and the H-bridge command.

[0064] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to those skilled in the art. In particular, although, in the embodiments described above, the master control circuit BMS transmits frames on the data transmission bus BUS in a substantially periodic manner, the master control circuit BMS transmits frames on the data transmission bus BUS in an irregular manner, for example randomly. Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Method of communication between a first electronic circuit (BMS) and second electronic circuits (SCi) via a bidirectional bus (BUS) allowing the full duplex communication, each second electronic circuit having a single identifier corresponding thereto, the method comprising the transmission by the first electronic circuit of first frames over the bus to the second electronic circuits, characterized in that each first frame comprising the same number of bits, the bits of each first frame being distributed in successive groups of bits, the positions of the groups being the same in each first frame, the first frames being such that, in each first frame, a first group of bits among the groups of bits indicates a corresponding first identifier among the identifiers, a second group of bits among the groups of bits indicates corresponding orders to be executed by the second electronic circuit corresponding to the first identifier of the first frame, and a third group of bits among the groups of bits indicates a corresponding second identifier among the identifiers, the method being such that, as a response to the first frame of the plurality of first frames, only the second electronic circuit indicated by the corresponding second identifier is authorized to transmit a second frame to the first electronic circuit over the bus.

2. Method according to claim 1, wherein the first electronic circuit (BMS) modifies the third group of bits of the first frames to cyclically scan all the identifiers according to a given order.

3. Method according to claim 1 or 2, wherein the first electronic circuit (BMS) transmits a succession of first frames with the third group of words corresponding to the same second identifier if it has not received a second frame transmitted by the second electronic circuit (SCi) corresponding to the second identifier.

4. Method according to claim 3, wherein the first electronic circuit (BMS) successively transmits a plurality of first frames with the third group of words corresponding to a given value which does not correspond to one of the identifiers if, after the transmission of said succession of first frames, it still has not received a second frame transmitted by the second electronic circuit (SCi) corresponding to the second identifier.

5. Method according to any of claims 1 to 4, wherein the first electronic circuit (BMS) and the second electronic circuits (SCi) form part of a battery (5) of electrical accumulators (C1, C2, C3, C4), the electrical accumulators being distributed in assemblies of electrical accumulators, and wherein, for each first frame of said first frames, the second electronic circuit designated by the corresponding first identifier controls the connection or the disconnection of each electrical accumulator of one of the corresponding assemblies based on said corresponding orders.

6. Method according to claim 5, wherein the orders are orders to turn on or off switches (SW1,1, SW1,2, SW1,3, SW1,4, SW2,1, SW2,2, SW2,3, SW2,4, SW3, SW4, SW5, SW6) coupling the electrical accumulators (C1, C2, C3, C4).

7. Method according to any of claims 1 to 6, wherein, when the first identifier is identical to the second identifier, the second electronic circuit (SCi) corresponding to the first identifier executes the orders before the sending of the second frame.

8. Method according to any of claims 1 to 7, wherein each second electronic circuit (SCi) is coupled to at least one voltage and / or current sensor (36) and wherein the second frame comprises data representative of at least one value measured by the sensor coupled to the second electronic circuit corresponding to the second identifier.

9. Method according to any of claims 1 to 8, wherein the transmission by the first electronic circuit (BMS) of the first frames over the bus (BUS) to the second electronic circuits (SCi) is performed periodically.

10. Electronic system (5) comprising a first electronic circuit (BMS) and second electronic circuits (SCi) coupled to the first electronic circuit by a bidirectional bus (BUS) configured to allow the full duplex communication, each second electronic circuit having a single identifier corresponding thereto, the first electronic circuit being configured to transmit first frames over the bus to the second electronic circuits, characterized in that each first frame comprising the same number of bits, the bits of each first frame being distributed in successive groups of bits, the positions of the groups being the same in each first frame, the first frames being such that, in each first frame, a first group of bits among the groups of bits indicates a corresponding first identifier among the identifiers, a second group of bits among the groups of bits to indicates corresponding orders to be executed by the second electronic circuit corresponding to the first identifier, and a third group of bits among the groups of bits indicates a corresponding second identifier among the identifiers, only the second electronic circuit indicated by the corresponding second identifier being authorized, as a response to each first frame of the plurality of first frames, to transmit a corresponding second frame to the first electronic circuit over the bus.

11. System according to claim 10, further comprising a battery (5) of electrical accumulators (C1, C2, C3, C4), the electrical accumulators being distributed in assemblies of electrical accumulators, each second electronic circuit (SCi) being configured to control the connection and the disconnection of each electrical accumulator of one of the assemblies based on said orders.