DATA DRIVER CIRCUIT AND DISPLAY DEVICE

Description

BACKGROUND Field

[0001] The present disclosure relates to a data driving circuit and a display device.Description of Related Art

[0002] EP 3 040 971 A1 describes an OLED display device includes an OLED display panel on which subpixels are disposed, a gamma reference voltage supply circuit supplying gamma reference voltages that are variable during driving and when sensing a threshold voltage, and a data driver supplying data voltages based on the gamma reference voltages to data lines.

[0003] KR 2015 0017287 A describes an organic light emitting display device, and more particularly, an organic light emitting display device including a configuration for compensating for a threshold voltage and electron mobility of a driving thin film transistor constituting each pixel.

[0004] The growth of the information society leads to increased demand for display devices to display images and use of various types of display devices, such as liquid crystal display devices, organic light emitting display devices, etc.

[0005] Among such display devices, the organic light emitting display device utilizes an organic light emitting diode emitting light by itself, so that there may have advantages in the rapid response speed, excellent contrast ratio and high color reproduction.

[0006] The organic light emitting display device may include, for example, an organic light emitting diode disposed in each subpixel, and a driving transistor for supplying a driving current to the organic light emitting diode.

[0007] As the driving time of the organic light emitting display device increases, circuit elements such as organic light emitting diodes and driving transistors disposed in subpixels may deteriorate. Further, a characteristic value of the driving transistor may change due to deterioration of the driving transistor.

[0008] As the characteristic values of the driving transistors change, there may occur deviations in characteristic values between the driving transistors disposed in the subpixels, so that the driving current supplied to the organic light emitting diode by the driving transistor may not be accurately controlled.

[0009] Accordingly, there is a need for a method for preventing image quality abnormality of the organic light emitting display device due to deterioration of the driving transistor.SUMMARY

[0010] Embodiments of the present disclosure may provide a manner capable of compensating the change in characteristic value due to deterioration of a driving transistor supplying a driving current to a light emitting device disposed in a subpixel by a circuit structure and driving method of the subpixel.

[0011] Embodiments of the present disclosure may provide a manner capable of improving an accuracy of compensation in compensating for changes in characteristic values due to deterioration of the driving transistor by the circuit structure and driving method of the subpixel.

[0012] The above identified object is solved by the feature of independent claim 1. Advantagous embodiments thereof are described in the respective dependent claims.

[0013] According to embodiments of the present disclosure, in compensating for the change value of the characteristic value of the driving transistor disposed in the subpixel by an internal compensation method, by supplying a voltage including a loss compensation voltage calculated based on the change value of the characteristic value of the driving transistor to the subpixel, it is possible to prevent the compensation value reflected by the internal compensation from being lost in a boosting period after an internal compensation period and to improve the accuracy of the internal compensation.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 schematically illustrates a configuration of a display device according to embodiments of the present disclosure. FIG. 2 illustrates an example of a circuit structure of a subpixel included in a display device according to embodiments of the present disclosure. FIG. 3 illustrates an example of a driving method of a subpixel included in a display device according to embodiments of the present disclosure. FIG. 4 illustrates another example of a driving method of a subpixel included in a display device according to embodiments of the present disclosure. FIGS. 5 to 9 specifically illustrate a driving method of the subpixel shown in FIG. 4. FIGS. 10 and 11 illustrate examples of a method of obtaining a change value of a threshold voltage of a driving transistor included in a subpixel when driving a subpixel according to the driving method of the subpixel shown in FIG. 4. DETAILED DESCRIPTION

[0015] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which it is shown by way of illustration specific examples or embodiments that can be implemented, and in which the same reference numerals and signs can be used to designate the same or like components even when they are shown in different accompanying drawings from one another. Further, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure rather unclear. The terms such as "including", "having", "containing", and "constituting" used herein are generally intended to allow other components to be added unless the terms are used with the term "only". As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0016] Terms, such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define essence, order, sequence, or number of elements etc., but is used merely to distinguish the corresponding element from other elements.

[0017] When it is mentioned that a first element "is connected or coupled to", "overlaps" etc. a second element, it should be interpreted that, not only can the first element "be directly connected or coupled to" or "directly contact or overlap" the second element, but a third element can also be "interposed" between the first and second elements, or the first and second elements can "be connected or coupled to", "overlap", etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that "are connected or coupled to", "contact or overlap", etc. each other.

[0018] When time relative terms, such as "after," "subsequent to," "next," "before," and the like, are used to describe processes or operations of elements or configurations, or flows or steps in operating, processing, manufacturing methods, these terms may be used to describe non-consecutive or non-sequential processes or operations unless the term "directly" or "immediately" is used together.

[0019] In addition, when any dimensions, relative sizes etc. are mentioned, it should be considered that numerical values for an elements or features, or corresponding information (e.g., level, range, etc.) include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.) even when a relevant description is not specified. Further, the term "may" fully encompasses all the meanings of the term "can".

[0020] FIG. 1 schematically illustrates a configuration included in a display device 100 according to embodiments of the present disclosure.

[0021] Referring to FIG. 1, the display device 100 includes a display panel 110, a gate driving circuit 120 and a data driving circuit 130 for driving the display panel 110, a controller 140, or the like.

[0022] In the display panel 110, a plurality of subpixels SP is disposed. The display panel 110 may include an active area AA in which the plurality of subpixels SP are disposed, and a non-active area NA positioned outside the active area AA.

[0023] A plurality of gate lines GL and a plurality of data lines DL are disposed on the display panel 110. The subpixel SP are positioned in a region where the gate line GL and the data line DL intersect.

[0024] The gate driving circuit 120 is controlled by the controller 140. The gate driving circuit 120 can sequentially output scan signals to the plurality of gate lines GL arranged on the display panel 110, thereby controlling the driving timing of the plurality of subpixels SP.

[0025] The gate driving circuit 120 may include one or more gate driver integrated circuits GDIC. The gate driving circuit 120 may be located only at one side of the display panel 110, or can be located at both sides thereof according to a driving method.

[0026] Each gate driver integrated circuit GDIC may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method. Alternatively, each gate driver integrated circuit GDIC may be implemented as a gate-in-panel (GIP) type and disposed directly on the display panel 110. Alternatively, each gate driver integrated circuit GDIC may be integrated and disposed on the display panel 110 in some cases. Alternatively, each gate driver integrated circuit GDIC may be implemented in a chip-on-film (COF) method mounted on a film connected to the display panel 110.

[0027] The data driving circuit 130 may receive data signal DATA from the controller 140 and converts the data signal into an analog data voltage Vdata. The data driving circuit 130 outputs (supplies) the data voltage Vdata (independently) to each data line DL of the plurality of data lines DL, preferably according to the timing at which the scan signal is applied through the respective gate line GL of the plurality of gate lines GL so that each of the plurality of subpixels SP emits light having brightness according to the supplied data voltage Vdata, which in turn corresponds to the received data signal DATA.

[0028] The data driving circuit 130 may include one or more source driver integrated circuits SDIC.

[0029] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0030] Each source driver integrated circuit SDIC may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method. Alternatively, each source driver integrated circuit SDIC may be disposed directly on the display panel 110. Alternatively, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110 in some cases. Alternatively, each source driver integrated circuit SDIC may be implemented in a chip-on-film (COF) manner. In this case, each source driver integrated circuit SDIC may be mounted on a film connected to the display panel 110, and may be electrically connected to the display panel 110 through lines on the film.

[0031] The controller 140 may supply various control signals to the gate driving circuit 120 and the data driving circuit 130, and control the operation of the gate driving circuit 120 and the data driving circuit 130.

[0032] The controller 140 may be mounted on a printed circuit board or a flexible printed circuit. The controller 140 may be electrically connected to the gate driving circuit 120 and the data driving circuit 130 through a printed circuit board or a flexible printed circuit.

[0033] The controller 140 may control the gate driving circuit 120 to output a scan signal according to timing implemented in each frame. The controller 140 may convert externally received image data to match a signal format used by the data driving circuit 130, and output the converted data signal to the data driving circuit 130.

[0034] The controller 140 may receive various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK from the outside (e.g., host system).

[0035] The controller 140 may generate various control signals by using various timing signals received from the outside, and may output the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0036] For example, in order to control the gate driving circuit 120, the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE.

[0037] The gate start pulse GSP controls operation start timing of one or more gate driver integrated circuits GDIC constituting the gate driving circuit 120. The gate shift clock GSC, which is a clock signal commonly input to one or more gate driver integrated circuits GDIC, controls the shift timing of a scan signal. The gate output enable signal GOE specifies timing information on one or more gate driver integrated circuits GDIC.

[0038] In addition, in order to control the data driving circuit 130, the controller 140 may output various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, or the like.

[0039] The source start pulse SSP controls a data sampling start timing of one or more source driver integrated circuits SDIC constituting the data driving circuit 130. The source sampling clock SSC is a clock signal for controlling the timing of sampling data in the respective source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0040] The display device 100 may further include a power management integrated circuit for supplying various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, and the like or controlling various voltages or currents to be supplied thereto.

[0041] Each subpixel SP may be a region defined by the intersection of the gate line GL and the data line DL, in which at least one circuit element including a light emitting device may be disposed.

[0042] For example, in the case that the display device 100 is an organic light emitting display device, an organic light emitting diode OLED and various circuit elements may be disposed in the plurality of subpixels SP. The display device 100 controls the electrical current supplied to the organic light emitting diode OLED disposed in the subpixel SP by driving several circuit elements, so that each subpixel SP may be controlled to display brightness corresponding to image data. To control the electrical current, the data driving circuit 130 outputs (supplies) the data voltage Vdata (independently) to each data line DL of the plurality of data lines DL, preferably according to the timing at which the scan signal is applied through the respective gate line GL of the plurality of gate lines GL, to the several circuit elements in a particular subpixel SP. In conclusion, each of the plurality of subpixels SP emits light having brightness according to the supplied data voltage Vdata, which in turn corresponds to the received data signal DATA.

[0043] FIG. 2 illustrates an example of a circuit structure of the subpixel SP included in the display device 100 according to embodiments of the present disclosure. The term "circuit structure" can be used interchangably with the term "subpixel circuit". Each subpixel circuit may comprise the several circuit elements. The term "several circuit elements" refers to a minimum of two different circuit elements of the subpixel circuit, namely one driving transistor DRT and one capacitor Cstg.

[0044] Referring to FIG. 2, each of the plurality of subpixels SP disposed on the display panel 110 includes a light emitting device ED and a driving transistor DRT for driving the light emitting device ED.

[0045] The subpixel circuit includes further circuit elements, such as one or more transistors in addition to the driving transistor DRT. The subpixel circuit includes further circuit elements, such as more than one capacitor. The number of circuit elements in the subpixel circuit is dependent on the actual application of the display device. The following examplary embodiments of the structure of a subpixel circuit are not complete. Besides the concrete examples provided hereinafter, other structures such as 3TC1, 5TC1, 6TC1, 7TC1, 8TC1, 3TC2, 4TC2, 5TC2, 6TC2, 7TC2 or 8TC2 are known in the field and may be used instead for the inventive concept.

[0046] FIG. 2 illustrates an example in which three transistors T1, T2 and T3 are disposed in the subpixel SP in addition to the driving transistor DRT, and one storage capacitor Cstg is disposed. FIG. 2 illustrates an example of a 4T1C structure, however, embodiments of the present disclosure are not limited thereto.

[0047] The driving transistor DRT may be electrically connected between a driving voltage line DVL and a light emitting device ED. A first driving voltage EVDD may be supplied through the driving voltage line DVL, and the first driving voltage EVDD may be a high potential driving voltage.

[0048] The driving transistor DRT may control the driving current supplied to the light emitting device ED.

[0049] One electrode of the light emitting device ED may be electrically connected to the driving transistor DRT. The other electrode of the light emitting device ED may be electrically connected to a second driving voltage EVSS. The second driving voltage EVSS may be a low potential driving voltage.

[0050] The light emitting device ED may emit light according to the driving current supplied from the driving transistor DRT, and may express the luminance corresponding to image data.

[0051] The first transistor T1 is electrically connected between the data line DL and a first node N1. The first node N1 is a gate node of the driving transistor DRT.

[0052] The first transistor T1 may be controlled by a scan signal supplied through the gate line GL.

[0053] The first transistor T1 may be controlled so that a data voltage Vdata supplied through the data line DL is applied to the first node N1 which is the gate node of the driving transistor DRT.

[0054] The second transistor T2 is electrically connected between the reference voltage line RVL and a second node N2. The second node N2 is a source node or a drain node of the driving transistor DRT. A third node N3 to which the driving transistor DRT is electrically connected to the driving voltage line DVL may be a drain node or a source node.

[0055] The second transistor T2 may be controlled by a scan signal supplied through the gate line GL.

[0056] The second transistor T2 may be controlled so that a reference voltage Vref supplied through the reference voltage line RVL is applied to the second node N2.

[0057] The third transistor T3 is electrically connected between an initialization voltage line IVL and the first node N1.

[0058] The third transistor T3 may be controlled by a scan signal supplied through the gate line GL.

[0059] The third transistor T3 may control the application of an initialization voltage Vinit to the first node N1 which is the gate node of the driving transistor DRT.

[0060] The storage capacitor Cstg is electrically connected between the first node N1 and the second node N2. The storage capacitor Cstg may maintain the data voltage Vdata for one frame period.

[0061] The driving transistor DRT or the light emitting device ED disposed in the subpixel SP may be deteriorated as the driving time of the display device 100 increases. The deterioration of the driving transistor DRT may cause a change in a characteristic value such as a threshold voltage or mobility of the driving transistor DRT.

[0062] The display device 100 according to embodiments of the present disclosure may provide a method for compensating for deterioration of the driving transistor DRT disposed in the subpixel SP.

[0063] As an example, the characteristic value of the driving transistor DRT disposed in the subpixel SP may be detected during a preset period.

[0064] The data voltage Vdata may be supplied by adding a compensation value calculated based on the detected characteristic value, so that it is possible to compensate a change in the characteristic value of the driving transistor DRT. This compensation method may be referred to as an external compensation method.

[0065] Alternatively, the compensation for the characteristic value of the driving transistor DRT may be preformed during the driving process of the subpixel SP. Since the data voltage Vdata is supplied after compensation is performed, the display driving may be performed without being affected by a change in the characteristic value of the driving transistor DRT. This compensation method may be referred to as an internal compensation method.

[0066] The circuit structure of the subpixel SP shown in FIG. 2 is a structure in which both the above-described external compensation and internal compensation can be performed. The change in the characteristic value of the driving transistor DRT may be compensated by the external compensation method or the internal compensation method according to circumstances.

[0067] In the case that the compensation for a change in the characteristic value of the driving transistor DRT is performed by the internal compensation, the change in the characteristic value of the driving transistor DRT may be compensated for simultaneously with driving the display without performing driving for detecting the characteristic value of the driving transistor DRT.

[0068] FIG. 3 illustrates an example of a driving method of a subpixel included in a display device 100 according to embodiments of the present disclosure.

[0069] FIG. 3 illustrates an example of a internal compensation method for compensating for a change in the characteristic value of the driving transistor DRT disposed in the subpixel SP during the driving process of the subpixel SP.

[0070] For example, one frame period for driving the subpixel SP may include a compensation period CP and a display period DP. The frame period is a time period. The frame period is also referred to the frame rate (expressed in frames per second or FPS) which is the frequency (rate) at which images (frames) are displayed on the display device 100. The frame period can be 1 / (the frame rate). The frame period can include an active period and a blank period. The active period can be a time period that the data voltage Vdata is supplied to the subpixel SP. And the blank period can be a time period between the two adjacent active periods.

[0071] The compensation period CP may include a first compensation period CP1 corresponding to an initialization period and a second compensation period CP2 corresponding to a sensing period. Here, the sensing period is a sensing period for internal compensation and may be referred to as an internal sensing period.

[0072] The display period DP may include a first display period DP1 corresponding to a data writing period, a second display period DP2 corresponding to a boosting period, and a third display period DP3 corresponding to a light emission period.

[0073] In the initialization period of the compensation period CP, the first transistor T1 may be in a turn-off state. In the initialization period of the compensation period CP, the second transistor T2 may be turned on and the third transistor T3 may be turned on.

[0074] Since the third transistor T3 is turned on, an initialization voltage Vinit may be applied to the first node N1. Since the second transistor T2 is turned on, a reference voltage Vref may be applied to the second node N2.

[0075] The difference between the initialization voltage Vinit and the reference voltage Vref may be, for example, greater than the threshold voltage Vth of the driving transistor DRT.

[0076] In the sensing period of the compensation period CP, the second transistor T2 may be turned off, and the third transistor T3 may maintain a turn-on state.

[0077] Since the second transistor T2 is turned off, the second node N2 may be in a floating state.

[0078] Since the second node N2 is in the floating state and the initialization voltage Vinit is applied to the first node N1, a voltage of the second node N2 forming a capacitance with the first node N1 may increase. So, the voltage of the second node N2 increases. The first node N1 and the second node N2 form a capacitance.

[0079] If a certain time elapses, the voltage of the second node N2 may be in a saturation state.

[0080] In the saturation state, a difference between the voltage of the first node N1 and the voltage of the second node N2 may correspond to the threshold voltage Vth of the driving transistor DRT. In addition, if the driving transistor DRT is deteriorated, the difference between the voltage of the first node N1 and the voltage of the second node N2 in the saturation state may correspond to (Vth + ΔVth) which is the changed threshold voltage of the driving transistor DRT.

[0081] By driving in the compensation period CP, a voltage difference corresponding to the changed threshold voltage Vth of the driving transistor DRT may be formed between the first node N1 as the gate node of the driving transistor DRT and the second node N2 as the source node of the driving transistor DRT.

[0082] Accordingly, it is possible to compensate for the change value ΔVth of the threshold voltage Vth of the driving transistor DRT. In an embodiment, the change value ΔVth of the threshold voltage Vth of the driving transistor DRT included in a first subpixel among the plurality of subpixels SP may be 0, and the change value ΔVth of the threshold voltage Vth of the driving transistor DRT included in a second subpixel may be not zero. Further, in a light emission period of the display period DP, a voltage of the second node N2 of the driving transistor DRT included in the first subpixel may be the same as a voltage of the second node N2 of the driving transistor DRT included in the second subpixel.

[0083] In the display period DP after the compensation period CP, the first transistor T1 may be turned on during the data writing period DP1.

[0084] Since the first transistor T1 is turned on, the data voltage Vdata supplied through the data line DL may be applied to the first node N1.

[0085] The data voltage Vdata may be a voltage corresponding to the luminance of the light emitting device ED disposed in the subpixel SP. That is, it may be a voltage for expressing a grayscale according to image data.

[0086] The first transistor T1 may be turned off during the boosting period DP2 of the display period DP.

[0087] Since the second transistor T2 is also turned off during the boosting period DP2 of the display period DP, both the first node N1 and the second node N2 may be in a floating state.

[0088] Since both, the first node N1 and the second node N2 are in the floating state, the voltage of the first node N1 and the voltage of the second node N2 may increase. A degree that the voltage of the second node N2 increase may be ΔVs, and the degree may be configured based on the voltage applied to the first node N1 and the voltage applied to the second node N2.

[0089] If the voltage of the second node N2 increases to match an operating point of the light emitting device ED, a driving current corresponding to the difference between the voltage of the gate node of the driving transistor DRT and the voltage of the source node of the driving transistor DRT may be supplied to the light emitting device ED.

[0090] During the light emission period DP3 of the display period DP, the voltage of the first node N1 and the voltage of the second node N2 are constantly maintained, and the light emitting device ED may display a luminance corresponding to the data voltage Vdata.

[0091] As described above, according to the embodiments of the present disclosure, the change in the characteristic value of the driving transistor DRT disposed in the subpixel SP may be compensated for in real time by the driving of the internal compensation method, and the display device may be driven.

[0092] Meanwhile, in the above-described example, information about the characteristic value of the driving transistor DRT may be applied to the second node N2 which is the source node of the driving transistor DRT.

[0093] Accordingly, in the boosting period DP2 of the display period DP, information on the characteristic value of the driving transistor DRT stored in the second node N2 may be transmitted to the first node N1 serving as the gate node.

[0094] In this case, the first node N1 forms a capacitance by the second node N2 and the storage capacitor Cstg, but may also form a parasitic capacitance with other signal lines in the subpixel SP.

[0095] For example, the first node N1 may form a parasitic capacitance with a voltage line such as the gate line GL or the driving voltage line DVL in the subpixel SP. In addition, there may occur a loss in a process in which information on the characteristic value of the driving transistor DRT stored in the second node N2 is transmitted to the first node N1 due to the parasitic capacitance.

[0096] Referring to FIG. 3, in the case that the threshold voltage of the driving transistor DRT is Vth since deterioration of the driving transistor DRT does not proceed, the difference Vgs1 between the voltage of the first node N1 and the voltage of the second node N2 during the data writing period of the display period DP may be (Vdata + Vth).

[0097] When a boosting remain ratio excluding the loss due to parasitic capacitance in the boosting process is refer as B_Remain, the boosting remain ratio B_Remain is a value less than 1 (e.g., 0.5, 0.6, etc.). A boosting loss ratio is a value obtained by subtrating the boosting remain ratio from 1.

[0098] The difference between the voltage of the first node N1 and the voltage of the second node N2 during the light emission period of the display period DP may be Vgs1'.

[0099] Vgs1' may be different from Vgs1 which is a difference between the voltage of the first node N1 and the voltage of the second node N2 in the data writing period DP1. For example, Vgs1' may be smaller than Vgs1. Vgs1' may be a value obtained by subtracting a loss value of ΔVs from Vgs1. In other words, Vgs1' may be a value obtained by substracting the lost value of ΔVs configured based on Vgs1 in a boosting process from Vgs1.

[0100] Alternatively, in some cases, Vgs1' may be (Vgs1 × B_Remain). Vgs1 may be lost to be remained as the boosting remain ratio in the boosting process. Alternatively, in some cases, Vgs1' may be (Vgs1 × B_Remain'). B Remain' may be greater than B_Remain. Since a loss is occurred on the second node N2 in the boosting process, a loss value of Vgs1 may be smaller than a loss value of the voltage of the second node N2.

[0101] In the case that the deterioration of the driving transistor DRT progresses and the change value of the threshold voltage Vth of the driving transistor DRT becomes ΔVth, the difference Vgs2 between the voltage of the first node N1 and the voltage of the second node N2 in the data writing period DP1 of the display period DP may be (Vgs1 + ΔVth).

[0102] During the light emission period DP3 of the display period DP, Vgs1 may become Vgs1'. ΔVth may become (ΔVth X B_Remain) in the light emission period DP3 by a loss in the boosting process. Vgs2' may become {Vgs1' + (ΔVth X B_Remain)}.

[0103] Such as above-mentioned, since a loss of ΔVth compensated for in the compensation period CP occurs, the position of the operating point of the light emitting device ED may be changed during the light emission period due to inaccurate compensation of ΔVth.

[0104] Accordingly, as the light emission period DP3 of the display period DP shown in FIG. 3, there may exist a difference ΔD between the voltage of the second node N2 before the deterioration of the driving transistor DRT and the voltage of the second node N2 after the deterioration of the driving transistor DRT. As a result, there may generate a non-uniform driving between the subpixels SP due to this difference.

[0105] Embodiments of the present disclosure may provide a method capable of preventing loss of compensation values during the boosting period DP2 and improving the accuracy of compensation in the process of compensating for changes in the characteristic values of the driving transistors DRT using the internal compensation method.

[0106] FIG. 4 illustrates another example of a driving method of a subpixel included in a display device 100 according to embodiments of the present disclosure.

[0107] Referring to FIG. 4, one frame period in which the subpixel SP is driven may include a compensation period CP and a display period DP.

[0108] In an initialization period CP1 of the compensation period CP, an initialization voltage Vinit may be applied to a first node N1 and a reference voltage Vref may be applied to a second node N2. In a sensing period CP2 of the compensation period CP, the second node N2 may be in a floating state, and the voltage of the second node N2 may increase.

[0109] The difference between the voltage of the first node N1 and the voltage of the second node N2 through the compensation period CP may correspond to (Vth + ΔVth), which is the changed threshold voltage of the driving transistor DRT. In addition, the example shown in FIG. 4 illustrates an example in which ΔVth is positively shifted, but in some cases, ΔVth may be negatively shifted.

[0110] The voltage applied to the first node N1 in a data writing period of the display period DP may be the sum of the data voltage Vdata and the loss compensation voltage Vc.

[0111] Here, the data voltage Vdata may be a voltage corresponding to the luminance displayed by the light emitting device ED disposed in the subpixel SP. In addition, the loss compensation voltage Vc may be a voltage for compensating for loss in a boosting process of the change value ΔVth of the threshold voltage Vth of the driving transistor DRT compensated for in the compensation period CP.

[0112] As an example, the loss compensation voltage Vc is a value obtained by multiplying the change value ΔVth of the threshold voltage Vth of the driving transistor DRT by a boosting loss ratio.

[0113] The boosting loss ratio may be referred as B_Loss, and the boosting loss ratio B_Loss is expressed as (1 - B_Remain). That is, the sum of the boosting loss ratio and the boosting remain ratio is 1.

[0114] Accordingly, the loss compensation voltage Vc may be expressed as (ΔVth * (1 - B_Remain)).

[0115] The boosting remain ratio may be a ratio of the voltage excluding the voltage lost by the parasitic capacitance in the boosting process.

[0116] The boosting remain ratio may be, for example, a ratio of a change value of a voltage of the second node N2 in a light emission period of the display period DP with respect to the change value ΔVs of the voltage of the second node N2 configured based on a difference between a voltage of the first node N1 and a voltage of the second node N2 in a data writing period DP1 of the display period DP . Alternatively, in some cases, the boosting remain ratio may be, in a state in which the change value ΔVth of the threshold voltage of the driving transistor DRT is 0, a ratio of a difference between a voltage of the first node N1 and a voltage of the second node N2 in a light emission period of the display period DP with respect to a difference between a voltage of the first node N1 and a voltage of the second node N2 in the data writing period of the display period DP.

[0117] The boosting remain ratio according to the invention is a ratio of a capacitance by the storage capacitor Cstg to a sum of a parasitic capacitance Cpara formed by the first node N1 and the capacitance by the storage capacitor Cstg (i.e., B_Remain = Cstg / (Cpara + Cstg)).

[0118] Since the boosting remain ratio is less than 1, the loss compensation voltage Vc is smaller than the change value ΔVth of the threshold voltage of the driving transistor DRT.

[0119] The loss compensation voltage Vc set in consideration of the boosting remain ratio may be supplied to the first node N1 in addition to the data voltage Vdata during the data writing period DP1 of the display period DP.

[0120] When the data voltage Vdata is applied to the first node N1 of the driving transistor DRT, there may be added (ΔVth × ( 1 - B_Remain)), which is a value at which the change value ΔVth of the threshold voltage of the driving transistor can be lost in the boosting process, so that it is possible to compensate for the loss of ΔVth in the boosting period and to improve the accuracy of the compensation.

[0121] For example, as the internal compensation is performed in the compensation period CP before the display period DP, the difference between the voltage of the first node N1 and the voltage of the second node N2 may be a voltage corresponding to (Vth + ΔVth) which is a changed threshold voltage Vth of the driving transistor DRT. A compensation for ΔVth which is a changed value of the threshold voltage may be performed.

[0122] The data voltage Vdata and the loss compensation voltage Vc may be applied to the first node N1 in the data writing period DP1 of the display period DP.

[0123] The data voltage Vdata may be a voltage corresponding to a luminance that the light emitting device ED represents. The loss compensation voltage Vc may be a voltage for compensating that ΔVth compensated in the compensation period CP is lost in the boosting process.

[0124] It may mean that the data voltage Vdata which is sum of a first voltage corrpesonding to a luminance the light emitting device ED represents and a second voltage for compensating a loss of ΔVth is applied to the first node N1.

[0125] As ΔVth is applied to the second node N2 in the compensation period CP, ΔVth is lost in the boosting process. A loss of ΔVth is compensated by the loss compensation voltage Vc which is applied to the first node N1 with the data voltage Vdata.

[0126] As (Vdata + Vc) is applied to the first node N1 in the data writing period of the display period DP, Vgs2 which is a difference between the voltage of the first node N1 and the voltage of the second node N2 is (Vgs1 + ΔVth + Vc).

[0127] A loss by a parasitic capacitance formed by the first node N1 may be occurred in the boosting period DP2 of the display period DP. Vgs2 of the data writing period of the display period DP may be changed to Vgs2' in the light emission period of the display period DP. Vgs2' may be expressed as follows. Vgs2 ′ = Vgs1 ′ + Δ Vth X B_Remain + Vc = Vgs1 ′ + Δ Vth X B_Remain + Δ Vth X 1 − B_Remain = Vgs1 ′ + Δ Vth X B_Remain + Δ Vth − Δ Vth X B_Remain = Vgs1 ′ + Δ Vth

[0128] As the loss compensation voltage Vc is applied to the first node N1 with the data voltage Vdata, the loss compensation voltage Vc may not be lost unlike the voltage of the second node N2 is lost in the boosting period. The loss compensation voltage Vc may be maintained on the first node N1 in the light emission period after the boosting period of the display period DP. A lost value of ΔVth may be compensated by the loss compensation voltage Vc.

[0129] A changed value ΔVth of the threshold voltage Vth compensated in the compensation period CP before the display period DP may be maintained in the light emission period DP3 of the display period DP. The changed value ΔVth of the threshold voltage Vth according to the degeneration of the driving transistor DRT may be compensated accurately. As the changed value ΔVth of the threshold voltage Vth is compensated accurately, a luminance that the subpixel SP represents may be controlled accurately. It may be prevented that a display quality is dropped.

[0130] Alternatively, the loss compensation voltage Vc may be a value obtained by multiplying the change value ΔVth of the threshold voltage Vth of the driving transistor DRT by the boosting loss ratio. Alternatively, the loss compensation voltage Vc may be a value obtained by dividing a value obtained by multiplying the change value ΔVth of the threshold voltage Vth of the driving transistor DRT by the boosting loss ratio by a value which is greater than the boosting remain ratio and smaller than 1.

[0131] As the loss compensation voltage Vc is applied to the first node N1 in the data writing period DP1 of the dislay period DP, the loss compensation voltage Vc may not be lost when the voltage of the second node N2 increases. But, in some cases, the loss compensation voltage Vc may be lost as smaller ratio than a ratio that the voltage of the second node N2 is lost.

[0132] Alternatively, in some cases, the loss compensation voltage Vc may be lost as same ratio with the ratio that the voltage of the second node N2 is lost.

[0133] For example, in a case that the loss compensation voltage Vc is lost as same ratio with the ratio that the voltage of the second node N2 is lost, the loss compensation voltage Vc may be expressed as (ΔVth * B_Loss / B_Remain) or as (ΔVth * (1 - B_Remain) / B_Remain).

[0134] If the boosting remain ratio is 0.5 or more, ((1 - B_Remain) / B_Remain) may be less than 1. Accordingly, the loss compensation voltage Vc may be smaller than the change value ΔVth of the threshold voltage Vth of the driving transistor DRT.

[0135] In some cases, if the boosting remain ratio is less than 0.5, the loss compensation voltage Vc may be greater than the change value ΔVth of the threshold voltage Vth of the driving transistor DRT.

[0136] The loss compensation voltage Vc may be set in consideration of the fact that the loss compensation voltage Vc may be lost during the boosting process, thereby preventing the loss of change value ΔVth of the threshold voltage Vth of the driving transistor DRT during the boosting process and accurately performing the compensation of ΔVth by the internal compensation.

[0137] For example, as the internal compensation is performed in the compensation period CP before the display period DP, the difference between the voltage of the first node N1 and the voltage of the second node N2 may be a voltage corresponding to the changed threshold voltage (Vth + ΔVth) of the driving transistor DRT.

[0138] In a data writing period of the display period DP, a voltage obtained by summing the data voltage Vdata and the loss compensation voltage Vc may be applied to the first node N1.

[0139] The data voltage Vdata may be a voltage corresponding to the luminance of the light emitting device ED, and the loss compensation voltage Vc may be a voltage for compensating for a loss of the compensated ΔVth in the boosting process.

[0140] There may be considered that the data voltage Vdata obtained by adding a first voltage corresponding to the luminance of the light emitting device ED and a second voltage which may be smaller than the change value ΔVth of the threshold voltage of the driving transistor DRT for compensating for the loss of ΔVth (i.e., the loss compensation voltage) is supplied to the first node N1. In an embodiment, in the light emission period of the display period, a value obtained by subtracting the change value of the threshold voltage of the driving transistor DRT from a difference between a voltage of the first node N1 and a voltage of the second node N2 of the driving transistor DRT may be less than the sum of the first voltage and the threshold voltage of the driving transistor DRT.

[0141] Since (Vdata + Vc) is supplied to the first node N1 in the data writing period of the display period DP, the difference Vgs2 between the voltage of the first node N1 and the voltage of the second node N2 may be (Vgs1 + ΔVth + Vc).

[0142] Since loss due to the parasitic capacitance formed by the first node N1 occurs during the boosting period of the display period DP, the difference Vgs2' between the voltage of the first node N1 and the voltage of the second node N2 in the light emission period of the display period DP may be (Vgs2 * B_Remain). Further, Vgs2' may be expressed as follows. Vgs2 ′ = Vgs2*B_Remain = Vgs1 + Δ Vth + Vc *B_Remain = Vgs1*B_Remain + Δ Vth*B_Remain + Vc * B _ Remain = Vgs1*B_Remain + Δ Vth*B_Remain + Δ Vth* 1 − B_Remain / B_Remain *B_Remain = Vgs1*B_Remain + Δ Vth*B_Remain + Δ Vth − Δ Vth*B_Remain =Vgs1*B_Remain + Δ Vth

[0143] Accordingly, the difference Vgs2' between the voltage of the first node N1 and the voltage of the second node N2 in the light emission period DP3 of the display period DP may be a value obtained by adding ΔVth to (Vgs1 * B_Remain) which is Vgs2 before deterioration of the driving transistor DRT, so that accurate compensation of the change value ΔVth of the threshold voltage Vth of the driving transistor DRT can be performed.

[0144] In addition, since accurate compensation for the change value ΔVth of the threshold voltage Vth of the driving transistor DRT is performed, the operating point of the light emitting device ED may be constantly maintained.

[0145] In the light emission period of the display period DP, the voltage of the second node N2 before the deterioration of the driving transistor DRT and the voltage of the second node N2 after the deterioration of the driving transistor DRT may be maintained to be the same (i.e., ΔD' = 0). Accordingly, it is possible to prevent non-uniform driving due to a deviation between subpixels SP having different degrees of deterioration of the driving transistor DRT.

[0146] FIGS. 5 to 9 specifically illustrate a driving method of the subpixel SP shown in FIG. 4. FIGS. 5 to 9 exemplary illustrate a driving method of the subpixel SP in a case that the loss compensation voltage Vc is {ΔVth X (1 - B_Remain)}.

[0147] Referring to FIG. 5, there may exist a compensation period CP for internal compensation before a display period DP.

[0148] In an initialization period CP1 of the compensation period CP, a first transistor T1 may be turned off, a second transistor T2 may be turned on, and a third transistor T3 may be turned on.

[0149] As the third transistor T3 is turned on, an initialization voltage Vinit may be applied to a first node N1. As the second transistor T2 is turned on, a reference voltage Vref may be applied to a second node N2.

[0150] Referring to FIG. 6, the second transistor T2 may be turned off in a sensing period CP2 of the compensation period CP. In the sensing period CP2 of the compensation period CP, the third transistor T3 may maintain a turn-on state.

[0151] Since the second node N2 is in a floating state while the initialization voltage Vinit is applied to the first node N1, the voltage of the second node N2 may increase.

[0152] If the voltage of the second node N2 becomes a saturation state, the difference between the voltage of the first node N1 and the voltage of the second node N2 may correspond to the threshold voltage Vth of the driving transistor DRT, or may correspond to the changed threshold voltage (Vth + ΔVth) of the driving transistor DRT.

[0153] Accordingly, in the compensation period CP, a change value ΔVth in the threshold voltage Vth of the driving transistor DRT may be compensated for by the internal compensation method.

[0154] Referring to FIG. 7, in a data writing period DP1 of the display period DP, the first transistor T1 may be turned on. The second transistor T2 and the third transistor T3 may maintain a turn-off state during the display period DP.

[0155] Since the first transistor T1 is turned on, a voltage supplied through the data line DL may be applied to the first node N1.

[0156] The voltage supplied through the data line DL may be a voltage in which a loss compensation voltage Vc for compensating for a loss of a change value ΔVth of the threshold voltage Vth of the driving transistor DRT is added to the data voltage Vdata corresponding to the image data.

[0157] The data voltage output from the data driving circuit 130 to the data line DL may be considered as a voltage obtained by adding a first voltage corresponding to image data and a second voltage for loss compensation.

[0158] Since (Vdata + Vc) is applied to the first node N1 in a state in which the difference between the voltage of the first node N1 and the voltage of the second node N2 is (Vth + ΔVth), the difference between the voltage of the first node N1 and the voltage of the second node N2 may be (Vth + ΔVth + Vdata + Vc).

[0159] Here, since (Vdata + Vth) is equal to Vgs1, the difference between the voltage of the first node N1 and the voltage of the second node N2 may be (Vgs1 + ΔVth + Vc).

[0160] In the data writing period DP1 of the display period DP, the difference Vgs2 between the voltage of the first node N1 and the voltage of the second node N2 may be a voltage obtained by adding Vgs1 before deterioration of the driving transistor DRT to the change value ΔVth of the threshold voltage Vth due to deterioration of the driving transistor DRT and Vc for compensating for a loss of ΔVth during the boosting process.

[0161] Referring to FIG. 8, in a boosting period DP2 of the display period DP, the first transistor T1 may be turned off.

[0162] Since the first transistor T1 is turned off, the first node N1 may be in a floating state. Since the first node N1 and the second node N2 are in a floating state, the voltage of the first node N1 and the voltage of the second node N2 may increase.

[0163] When the voltage of the second node N2 coincides with the operating point of the light emitting device ED, the increase of the voltage of the first node N1 and the increase of the voltage of the second node N2 may be stopped.

[0164] Referring to FIG. 9, a driving current corresponding to a difference between the voltage of the first node N1 and the voltage of the second node N2 may be supplied to the light emitting device ED in a light emission period DP3 of the display period DP.

[0165] The light emitting device ED emits light according to the driving current supplied by the driving transistor DRT, and may display luminance corresponding to image data.

[0166] The difference Vgs2' between the voltage of the first node N1 and the voltage of the second node N2 in the light emission period of the display period DP may be {Vgsl' + (ΔVth × B_Remain) + Vc}.

[0167] As described above, Vc is {ΔVth × (1 - B_Remain)}, which means a value obtained by adding ΔVth to Vgs1' before deterioration of the driving transistor DRT.

[0168] That is, in the boosting period DP2, the loss of Vgs1 is maintained the same as before the deterioration of the driving transistor DRT, so that the loss of ΔVth can be compensated to increase the accuracy of compensation of ΔVth by internal compensation.

[0169] Therefore, according to the embodiments of the present disclosure, there may perform in real time the compensation due to the deterioration of the driving transistor DRT disposed in the subpixel through internal compensation. In addition, by additionally supplying a loss compensation voltage Vc for compensating for the loss of the compensation value during the boosting period to the subpixel SP, it is possible to accurately compensate the deterioration of the driving transistor DRT.

[0170] The loss compensation value Vc, such as above-mentioned, may be applied to the first node N1 that a loss by a parasitic capacitance is not occurred in the boosting process, and may be a voltage corresponding to a loss value of ΔVth in the boosting process.

[0171] Furthermore, in some cases, considering to a case that a loss of at least a part of the loss compensation voltage Vc is occurred, the loss compensation value Vc may be calculated by dividing the voltage corresponding to the loss value of ΔVth by a value which is greater or equal to the boosting remain ratio and smaller than 1.

[0172] In addition, in order to calculate the loss compensation voltage Vc, it is required to obtain a change value ΔVth of the threshold voltage Vth of the driving transistor DRT.

[0173] FIGS. 10 and 11 illustrate examples of a method of obtaining a change value ΔVth of a threshold voltage Vth of a driving transistor DRT included in a subpixel SP when driving a subpixel SP according to the driving method of the subpixel shown in FIG. 4.

[0174] Referring to FIG. 10, the data driving circuit 130 of the display device 100 is configured to detect a change value ΔVth of a threshold voltage Vth of the driving transistor DRT by, for example, a method of detecting a change value ΔVth of a characteristic value (e.g. the threshold voltage Vth) of the driving transistor DRT according to an external compensation method.

[0175] The display device 100 may detect the change value ΔVth of the threshold voltage Vth of the driving transistor DRT during the detection period SP.

[0176] The change value ΔVth of the threshold voltage Vth of the driving transistor DRT is detected by a data driving circuit 130 included in the display device 100.

[0177] Alternatively, in some cases not covered by the scope of the claims, the change value ΔVth of the threshold voltage Vth of the driving transistor DRT may be detected by a configuration separately disposed from the data driving circuit 130.

[0178] The detection period SP may be a period other than the frame period during which display driving is performed. For example, the detection period SP may be a specific period after driving of the display device 100 is started. Alternatively, the detection period SP may be a predetermined period after the driving of the display device 100 is terminated. In some cases, the detection period SP may be at least a partial period of a blank period included in the frame period. The detection period (external sensing period) may be a period other than the frame period before or after driving the display. Or, the detection period (external sensing period) may be a period included in the frame period.

[0179] The detection period SP may be referred to as an external sensing period.

[0180] The data driving circuit 130 may include a sensing unit 131 and a data voltage output unit 132.

[0181] The detection period SP may include a first detection period SP1 corresponding to an initialization period, a second detection period SP2 corresponding to a sensing period, and a third detection period SP3 corresponding to a sampling period.

[0182] In the initialization period of the detection period SP, a first transistor T1 may be turned on and a second transistor T2 may be turned on. In the detection period SP, a third transistor T3 may maintain a turn-off state.

[0183] In the initialization period of the detection period SP, a first switch SW1 electrically connected to a reference voltage line RVL may be turned on, and a second switch SW2 may be turned off.

[0184] As the first transistor T1 is turned on, a sensing data voltage Vsen output by the data voltage output unit 132 may be applied to the first node N1. As the second transistor T2 and the first switch SW1 are turned on, a reference voltage Vref may be applied to the second node N2.

[0185] The first switch SW1 may be turned off during the sensing period of the detection period SP.

[0186] Accordingly, a voltage of the second node N2 may increase during the sensing period of the detection period SP. In addition, when a predetermined period elapses, the voltage of the second node N2 may become a saturation state.

[0187] If the voltage of the second node N2 becomes the saturation state, the difference between the voltage of the first node N1 and the voltage of the second node N2 may correspond to a changed threshold voltage Vth' (= Vth + ΔVth) of the driving transistor DRT.

[0188] In the sampling period of the detection period SP, the second switch SW2 electrically connected between the reference voltage line RVL and an analog-to-digital converter ADC may be turned on.

[0189] Accordingly, the voltage of the second node N2 may be sampled.

[0190] Through the above-described process, the change value ΔVth of the threshold voltage Vth of the driving transistor DRT is detected.

[0191] A loss compensation voltage Vc may be calculated using the detected ΔVth.

[0192] When outputting the data voltage Vdata in the display period DP, the data voltage output unit 132 of the data driving circuit 130 may output a voltage to which the loss compensation voltage Vc is reflected, thereby accurately compensating the ΔVth by the internal compensation.

[0193] Alternatively, the loss compensation voltage Vc may be calculated using the change value ΔVth of the threshold voltage set according to the accumulated stress of the driving transistor DRT, without using the detection method according to the external compensation method.

[0194] Referring to FIG. 11, the display device 100 may include a look-up table in which a stress value Vstr of the driving transistor DRT and a change value ΔVth corresponding to the stress value Vstr are set.

[0195] Such a look-up table, for example, may be stored in a memory located inside or outside the controller 140.

[0196] The stress value Vstr of the driving transistor DRT may be, for example, a value calculated by accumulating the data voltage Vdata supplied to a gate node of the driving transistor DRT as the display device 100 is driven.

[0197] As the driving time of the driving transistor DRT increases, the stress value Vstr may increase. The change value ΔVth of the threshold voltage of the driving transistor DRT corresponding to the increased stress value Vstr may be identified through the look-up table.

[0198] As an example, a change value corresponding to a first stress value Vstr1 may be ΔVth1, and a change value corresponding to a second stress value Vstr2 may be ΔVth2.

[0199] Since the change value ΔVth of the threshold voltage of the driving transistor DRT can be identified through the look-up table, the loss compensation voltage Vc can be calculated using the identified ΔVth.

[0200] The ΔVth predicted according to the driving of the driving transistor DRT may be used without performing a separate driving for detecting the change value ΔVth of the threshold voltage of the driving transistor DRT, thereby easily calculating the loss compensation voltage Vc for improving the accuracy of internal compensation.

[0201] According to the above-described embodiments of the present dislosure, the change in the characteristic value of the driving transistor DRT disposed in the subpixel SP may be compensated by using the internal compensation method, so that the deterioration of the driving transistor DRT may be easily compensated for in the driving process of the subpixel SP.

[0202] In addition, the loss compensation voltage Vc calculated based on a change value of a characteristic value of the driving transistor DRT may be added to the voltage supplied to the subpixel SP. Accordingly, it is possible to prevent the change value ΔVth of the threshold voltage of the driving transistor DRT reflected by the internal compensation from being lost in a boosting period and to improve the accuracy of the internal compensation.

Claims

1. A display device (100) comprising: a display panel (110) on which a plurality of subpixels (SP), a plurality of gate lines (GL) and a plurality of data lines (DL) are disposed, wherein each subpixel (SP) is positioned in a region, where one of the plurality of gate lines (GL) intersects with one of the plurality of data lines (DL); and a data driving circuit (130) configured to supply a data voltage (Vdata) to each of the data lines (DL), wherein each of the plurality of subpixels (SP) is configured to emit light having a brightness according to the supplied data voltage (Vdata), wherein each of the plurality of subpixels (SP) comprises: a light emitting device (ED); a subpixel circuit comprising: a driving transistor (DRT) configured to drive the light emitting device (ED) and a storage capacitor (Cstg) electrically connected between a first node (N1) and a second node (N2) of the driving transistor (DRT), wherein the first node is a gate node of the driving transistor (DRT), and the second node is a source node or a drain node of the driving transistor (DRT) and is connected to the light emitting device; wherein each of the plurality of subpixels (SP) further comprises: a first transistor (Tl) electrically connected between the first node (N1) of the driving transistor (DRT) and one data line of the plurality of data lines (DL); a second transistor (T2) electrically connected between the second node (N2) of the driving transistor (DRT) and a reference voltage line (RVL); and a third transistor (T3) electrically connected between the first node (N1) of the driving transistor (DRT) and an initialization voltage line (IVL); wherein the data driving circuit (130) is configured: to detect, in an external sensing period, a change value (ΔVth) of a threshold voltage (Vth) of the driving transistor (DRT) included in one of the plurality of subpixels (SP), to obtain, in a display period (DP), the data voltage (Vdata) by adding a first voltage corresponding to received image data for said one of the plurality of subpixels (SP) and a second voltage (Vc) smaller than the change value (ΔVth) of the threshold voltage (Vth) of the driving transistor (DRT), and to supply the data voltage (Vdata) to said one subpixel of the plurality of subpixels (SP), wherein the data driving circuit is configured to obtain the second voltage (Vc) by multiplying the change value (ΔVth) of the threshold voltage (Vth) of the driving transistor (DRT) by a boosting loss ratio (B_Loss), the boosting loss ratio (B_Loss) being a value obtained by subtrating a boosting remain ratio (B_Remain) from 1, and the boosting remain ratio (B_Remain) being a ratio of a capacitance by the storage capacitor (Cstg) to a sum of a parasitic capacitance (Cpara) formed by the first node (N1) of the driving transistor (DRT) and the capacitance by the storage capacitor (Cstg).

2. The display device of claim 1, further configured, in a compensation period (CP) prior to the display period (DP) in a frame period, to turn off the first transistor (T1).

3. The display device of claim 2, further configured to turn on the second transistor (T2) and the third transistor (T3) in an initialization period (CP1) of the compensation period (CP) prior to the display period (DP), and, in an internal sensing period (CP2) of the compensation period (CP), to turn off the second transistor (T2) and to maintain the third transistor (T3) in a turn-on state.

4. The display device of claim 3, further configured to control, in the initialization period (CP1), a difference between an initialization voltage supplied through the initialization voltage line (IVL) and a reference voltage supplied through the reference voltage line (RVL) to be greater than the threshold voltage (Vth) of the driving transistor (DRT).

5. The display device of one of the claims 2 to 4, further configured to turn on the first transistor (T1) in a data writing period (DP1) of the display period (DP), and to turn off the first transistor (T1) in a boosting period (DP2) and a light emission period (DP3) of the display period (DP).

6. The display device of one of the claims 2 to 5, further configured to turn off the second transistor (T2) and the third transistor (T3) in the display period (DP).

7. The display device of one of the preceding claims, wherein the change value (ΔVth) of the threshold voltage (Vth) of the driving transistor (DRT) is a value set in response to a stress value (Vstr) of said one of the plurality of subpixels (SP).