METHOD AND DEVICE FOR DETERMINING THE NEGATIVE CURRENT OUT OF VOLTAGE OF A SWITCHING TRANSISTOR, INVERTER, COMPUTER-READABLE STORAGE MEDIUM AND SWITCHING TRANSISTOR CONTROL CIRCUIT

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Chinese Patent Application No. 202210360280.1, titled "METHOD AND APPARATUS FOR DETERMINING TURN-OFF VOLTAGE OF SWITCHING TRANSISTOR, AND SWITCHING TRANSISTOR DRIVE CONTROL CIRCUIT", and filed on April 06, 2022.FIELD

[0002] The present disclosure relates to the field of inverter technologies, and more particularly, to a method and an apparatus for determining a turn-off negative voltage of a switching transistor, and a switching transistor drive control circuit.BACKGROUND

[0003] With the gradual improvement of the living standard of people, more and more vehicles enter thousands of households to provide convenience for t raveling. In the related art, a silicon-carbide Metal Oxide Semiconductor (MOS) transistor is used in vehicle compressor inverter system of a high input voltage to reduce loss and improve efficiency of the inverter. However, the silicon-carbide MOS transistor has the problem of being easily turned on mistakenly. CN 109 831 197 A provides a gate turn-off control method and device for a silicon carbide field effect transistor and a driving circuit of the silicon carbide field effect transistor, so as to adopt a scientific and reasonable gate turn-off voltage to the silicon carbide field effect transistor.SUMMARY

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent. To this end, the present invention is to provide a processor-implemented method for determining a turn-off negative voltage of a switching transistor, which can accurately determining a turn-off negative voltage interval of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0005] The present invention is further to provide an apparatus for determining a turn-off negative voltage of a switching transistor.

[0006] The present invention is further to provide an inverter.

[0007] The present invention is further to provide a computer-readable storage medium.

[0008] The present invention is further to provide a switching transistor drive control circuit.

[0009] The present invention is further to provide a motor control system.

[0010] The present invention is further to provide a compressor.

[0011] The present invention is further to provide a vehicle.

[0012] The present invention provides a processor-implemented method for determining a turn-off negative voltage of a switching transistor. The method comprises: determining a first turn-off negative voltage model and a second turn-off negative voltage model; acquiring a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor; inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor, and inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor; and determining a turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0013] In the method for determining the turn-off negative voltage of the switching transistor according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0014] In some embodiments of the present disclosure, the first turn-off negative voltage model is expressed as V SS_min =λ 1 *f 1 (R G_on , R G_off , V DC )-V th , where V SS_min represents the turn-off negative voltage upper limit absolute value, λ 1 represents a first derating parameter, f 1 (R G_on , R G-off , V DC ) represents a function expression corresponding to the first turn-off negative voltage model, R G_on represents the turn-on gate resistance, R G_off represents the turn-off gate resistance, V DC represents the bus voltage, and V th represents the minimum turn-on voltage.

[0015] In some embodiments of the present disclosure, the second turn-off negative voltage model is expressed as V SS_max =V GS_max -λ 2 *f 2 (R G_on , R G_off , V DC ), where V SS_max represents the turn-off negative voltage lower limit absolute value, λ 2 represents a second derating parameter, f 2 (R G_on , R G_off , V DC ) represents a function expression corresponding to the second turn-off negative voltage model, R G_on represents the turn-on gate resistance, R G_off represents the turn-off gate resistance, V DC represents the bus voltage, and V GS_max represents the maximum bearable negative voltage absolute value.

[0016] In some embodiments of the present disclosure, the determining the turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value comprises: setting a negative value of the turn-off negative voltage upper limit absolute value as a turn-off negative voltage upper limit voltage, and setting a negative value of the turn-off negative voltage lower limit absolute value as a lower limit voltage of the turn-off negative voltage; and determining the turn-off negative voltage interval based on the upper limit voltage of the turn-off negative voltage and the lower limit voltage of the turn-off negative voltage.

[0017] In some embodiments of the present disclosure, the switching transistor is a silicon-carbide Metal Oxide Semiconductor (MOS) transistor.

[0018] The present invention further provides an apparatus for determining a turn-off negative voltage of a switching transistor. The apparatus comprises: a first determining module configured to determine a first turn-off negative voltage model and a second turn-off negative voltage model; an acquiring module configured to acquire a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor; and a second determining module configured to: input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor; input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor; and determine a turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0019] In the apparatus for determining the turn-off negative voltage of the switching transistor according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0020] The present invention further provides an inverter. The inverter comprises a memory, a processor, and a program for determining a turn-off negative voltage of a switching transistor stored on the memory and executable on the processor. The processor is configured to implement, when executing the program for determining the turn-off negative voltage of the switching transistor, the method for determining the turn-off negative voltage of the switching transistor according to any one of the above-mentioned embodiments.

[0021] In the inverter of the embodiments according to the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0022] The present invention further provides a computer-readable storage medium, having a program for determining a turn-off negative voltage of a switching transistor stored thereon. The program for determining the turn-off negative voltage of the switching transistor, when executed by a processor, implements the method for determining the turn-off negative voltage of the switching transistor according to any one of the above-mentioned embodiments.

[0023] In the computer-readable storage medium according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0024] The present invention further provides a switching transistor drive control circuit. The switching transistor drive control circuit comprises a drive power supply, a drive unit, and a control unit. The control unit is configured to acquire a turn-off negative voltage interval of a switching transistor by implementing the method for determining the turn-off negative voltage of the switching transistor according to any one of the above-mentioned embodiments, and control the drive power supply based on the turn-off negative voltage interval to provide a negative turn-off voltage to the drive unit. The drive unit is configured to drive, in response to receiving a turn-off control signal, the switching transistor to be turned off based on the negative turn-off voltage.

[0025] In the switching transistor drive control circuit according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0026] In some embodiments of the present disclosure, the drive unit comprises a drive chip and a first gate resistor. The drive chip has a positive power pin connected to a positive turn-on voltage supply terminal of the drive power supply, a negative power pin connected to a negative turn-off voltage supply terminal of the drive power supply, and an input pin connected to the control unit to receive the turn-off control signal sent by the control unit. The first gate resistor has a terminal connected to an output pin of the drive chip and another terminal connected to a gate of the switching transistor.

[0027] In some embodiments of the present disclosure, the drive unit further comprises a first diode and a second gate resistor. The first diode has a cathode connected to a terminal of the first gate resistor. The second gate resistor has a terminal connected to an anode of the first diode and another terminal connected to the other terminal of the first gate resistor.

[0028] In some embodiments of the present disclosure, the drive unit further comprises a second diode. The second diode has a cathode connected to the terminal of the first gate resistor and an anode connected to the cathode of the first diode.

[0029] In some embodiments of the present disclosure, the drive unit further comprises a first diode and a second gate resistor. The first diode has a cathode connected to the terminal of the first gate resistor and an anode connected to the other terminal of the first gate resistor. The second gate resistor has a terminal connected to an anode of the first diode, and another terminal connected to the gate of the switching transistor.

[0030] In some embodiments of the present disclosure, the drive unit further comprises a first coupling capacitor and a second coupling capacitor. The first coupling capacitor has a terminal connected to a positive turn-on voltage supply terminal of the drive power supply. The second coupling capacitor has a terminal connected to another terminal of the first coupling capacitor, and another terminal connected to a negative turn-off voltage supply terminal of the drive power supply.

[0031] In some embodiments of the present disclosure, when the switching transistor is an upper bridge switching transistor, a node between the first coupling capacitor and the second coupling capacitor is connected to a midpoint of a bridge arm at which the upper bridge switching transistor is located. When the switching transistor is a lower bridge switching transistor, the node between the first coupling capacitor and the second coupling capacitor is grounded.

[0032] The present invention further provides a motor control system. The motor control system comprises the switching transistor drive control circuit according to any one of the above-mentioned embodiments.

[0033] In the motor control system according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0034] The present invention further provides a compressor. The compressor comprises the motor control system according to any one of the above-mentioned embodiments.

[0035] In the compressor according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0036] The present invention further provides a vehicle. The vehicle comprises the compressor according to any one of the above-mentioned embodiments.

[0037] In the vehicle according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0038] Additional aspects and advantages of the embodiments of the present disclosure will be given at least in part in the following description, or become apparent at least in part from the following description, or can be learned from practicing of the embodiments of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present disclosure will become more apparent and more understandable from the following description of embodiments taken in conjunction with the accompanying drawings. FIG. 1 is a schematic flowchart showing a method for determining a turn-off negative voltage of a switching transistor according to an embodiment of the present disclosure. FIG. 2 is a schematic scene graph showing a method for determining a turn-off negative voltage of a switching transistor according to an embodiment of the present disclosure. FIG. 3 is a schematic scene graph showing a method for determining a turn-off negative voltage of a switching transistor according to another embodiment of the present disclosure. FIG. 4 is a schematic flowchart showing a method for determining a turn-off negative voltage of a switching transistor according to another embodiment of the present disclosure. FIG. 5 is a structural block diagram showing an apparatus for determining a turn-off negative voltage of a switching transistor according to an embodiment of the present disclosure. FIG. 6 is a structural block diagram showing an inverter according to an embodiment of the present disclosure. FIG. 7 is a structural block diagram showing a switching transistor drive control circuit according to an embodiment of the present disclosure. FIG. 8 is a schematic circuit view showing a switching transistor drive control circuit according to an embodiment of the present disclosure. FIG. 9 is a schematic circuit view showing a switching transistor drive control circuit according to another embodiment of the present disclosure. FIG. 10 is a schematic circuit view showing a switching transistor drive control circuit according to another embodiment of the present disclosure. FIG. 11 is a schematic circuit view showing a switching transistor drive control circuit according to another embodiment of the present disclosure. FIG. 12 is a structural block diagram showing a motor control system according to an embodiment of the present disclosure. FIG. 13 is a structural block diagram showing a compressor according to an embodiment of the present disclosure. FIG. 14 is a structural block diagram showing a vehicle according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] Embodiments of the present disclosure will be described in detail below with reference to examples thereof as illustrated in the accompanying drawings, throughout which same or similar elements, or elements having same or similar functions, are denoted by same or similar reference numerals. The embodiments described below with reference to the drawings are illustrative only, and are intended to explain, rather than limiting, the present disclosure.

[0041] In order to clearly explain a method and apparatus for determining a turn-off negative voltage of a switching transistor, and a switching transistor drive control circuit according to the embodiments of the present disclosure, a description will be made in conjunction with a schematic flowchart of a method for determining a turn-off negative voltage of a switching transistor shown in FIG. 1. As shown in FIG. 1, the method for determining the turn-off negative voltage of the switching transistor according to the embodiments of the present disclosure comprises operations at blocks S11 to S17.

[0042] At block S11, a first turn-off negative voltage model and a second turn-off negative voltage model are determined.

[0043] At block S13, a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor are acquired.

[0044] At block S15, the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage are inputted into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor, and the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value are inputted into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor.

[0045] At block S17, a turn-off negative voltage interval of the switching transistor is determined based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0046] In the method for determining the turn-off negative voltage of the switching transistor according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0047] It may be understood that although the method of applying the turn-off negative voltage to the gate can prevent the switching transistor from being turned on mistakenly, in a case where the turn-off negative voltage upper limit absolute value is set too low, the switching transistor may still be turned on mistakenly in some cases, and in a case where the turn-off negative voltage lower limit absolute value is set too high, a negative voltage spike value may exceed an allowable driving negative voltage lower limit absolute value of the switching transistor, reducing life of the switching transistor and even causing damage to the switch. Therefore, the turn-off negative voltage interval of the switching transistor needs to be accurately determined.

[0048] In an exemplary embodiment of the present disclosure, the first turn-off negative voltage model can determine the turn-off negative voltage upper limit absolute value of the switching transistor. An expression form of the first turn-off negative voltage model comprises, but is not limited to, a neural network model, a data mapping graph / table, a mathematical relational expression, and the like. When the first turn-off negative voltage model is the neural network model, inputs of the neural network model may comprise the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage of the switching transistor, and outputs of the neural network model may comprise the turn-off negative voltage upper limit absolute value of the switching transistor. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage of the switching transistor are acquired, the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage are inputted into the neural network model, to quickly obtain corresponding relatively accurate turn-off negative voltage upper limit absolute value of the switching transistor. When the first turn-off negative voltage model is the data mapping graph / table, the data mapping graph / table may comprise predetermined turn-off gate resistances, turn-on gate resistances, and bus voltages of different switching transistors, and turn-off negative voltage upper limit absolute values corresponding to minimum turn-on voltages of the different transistors. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage of the switching transistor are acquired, corresponding relatively accurate turn-off negative voltage upper limit absolute value of the switching transistor can be quickly obtained by finding the data mapping map / table. When the first turn-off negative voltage model is the mathematical relational expression, the mathematical relational expression can reflect a relationship between the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage of the switching transistor and the turn-off negative voltage upper limit absolute value of the switching transistor. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage of the switching transistor are acquired, the corresponding turn-off negative voltage upper limit absolute value of the switching transistor can be obtained from the mathematical relationship expression.

[0049] The second turn-off negative voltage model can determine the turn-off negative voltage lower limit absolute value of the switching transistor. An expression form of the second turn-off negative voltage model comprises, but is not limited to, a neural network model, a data mapping graph / table, a mathematical relational expression, and the like. When the second turn-off negative voltage model is the neural network model, inputs of the neural network model may comprise the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor, and outputs of the neural network model may comprise the turn-off negative voltage lower limit absolute value of the switching transistor. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor are acquired, the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value are inputted into the neural network model, to quickly obtain corresponding relatively accurate turn-off negative voltage lower limit absolute value of the switching transistor. When the second turn-off negative voltage model is the data mapping graph / table, the data mapping graph / table may comprise predetermined turn-off gate resistances, turn-on gate resistances, and bus voltages of different switching transistors, and turn-off negative voltage lower limit absolute values corresponding to maximum bearable negative voltage absolute values of the different switching transistors. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor are acquired, corresponding relatively accurate turn-off negative voltage lower limit absolute value of the switching transistor can be quickly obtained by finding the data mapping map / table. When the second turn-off negative voltage model is the mathematical relational expression, the mathematical relational expression can reflect a relationship between the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. As a result, after the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor are acquired, the corresponding turn-off negative voltage lower limit absolute value of the switching transistor can be obtained from the mathematical relationship expression.

[0050] In some embodiments, the first turn-off negative voltage model and the corresponding second turn-off negative voltage model may be determined based on a model of the switching transistor, respectively. The first turn-off negative voltage model of the switching transistors of indifferent models may have the same or different expression forms, and the second turn-off negative voltage model of the switching transistors of different models may have the same or different expression forms, which are not limited herein. In some embodiments, the first turn-off negative voltage model and the second turn-off negative voltage model of the switching transistor of a same model have a same form.

[0051] It should be noted that the turn-off negative voltage is negative, and the turn-off negative voltage interval may be understood as a value interval of the turn-off negative voltage. That is, all of numerical values in the turn-off negative voltage interval are negative.

[0052] In some embodiments of the present disclosure, the first turn-off negative voltage model is expressed as: V SS_min =λ 1 *f 1 (R G_on , R G_off , V DC )-V th , i.e. equation (1), where V SS_min represents the turn-off negative voltage upper limit absolute value, λ 1 represents a first derating parameter, f 1 (R G_on , R G_off , V DC ) represents a function expression corresponding to the first turn-off negative voltage model, R G_on represents the turn-on gate resistance, R G_off represents the turn-off gate resistance, V DC represents the bus voltage, and V th represents the minimum turn-on voltage.

[0053] In this way, a relationship between the turn-on gate resistance and the turn-on gate resistance of the switching transistor, the bus voltage, and the minimum turn-on voltage of the switching transistor and the turn-off negative voltage upper limit absolute value of the switching transistor can be clearly expressed by the above equation (1).

[0054] In an exemplary embodiment of the present disclosure, the turn-off gate resistance may be understood as a total resistance of a turn-off circuit when the switching transistor is turned off, and the turn-on gate resistance may be understood as a total resistance of a turn-on circuit when the switching transistor is turned on. In some embodiments, the minimum turn-on voltage may be obtained by querying corresponding data based on a specific model of the switching transistor. In some embodiments, the first derating parameter may be obtained by querying corresponding derating criteria based on a specific model of the resistor. In some embodiments, the bus voltage may be obtained by a bus voltage measurement device.

[0055] In some embodiments, a relationship between the turn-off negative voltage upper limit absolute value and the turn-on gate resistance, the turn-off gate resistance, and the bus voltage is shown in FIG. 2. It should be understood that when the turn-on gate resistance, the turn-off gate resistance, and the bus voltage input into the first turn-off negative voltage model change, the turn-off negative voltage upper limit absolute value output from the first turn-off negative voltage model will also change accordingly. Further, different turn-on gate resistances, different turn-off gate resistances, different bus voltages, and corresponding turn-off negative voltage upper limit absolute values, which are obtained through extensive simulation experiments, are substituted into the above equation (1) to obtain multiple different polynomials. After polynomial fitting, a specific expression of the first turn-off negative voltage model can be expressed as V SS_min =b 2 *R G_on +b 3 *R G_off +b 4 *V DC +b 5 *R G_on 2< +b 6 *R G_off 2< +b 7 *V DC 2< +b 8 *R G_on *R G_off +b 9 *R G_off *V DC +b 10 *R G_off *V DC - V th, , i.e. equation (2), where b 2 =-24.41, b 3 =63.47, b 4 =222.4, b 5 =0.555, b 6 =1.033, b 7 =-8.683, b 8 =-1.096, b 9 =6.276, and b 10 =-2.759.

[0056] In an example, the minimum turn-on voltage of the switching transistor is 1.5 V, and the bus voltage is 900 V. The selected turn-on gate resistance is 40 Ω, and the selected turn-off gate resistance is 20 Ω. By using the equation (2), it is obtained that the turn-off negative voltage upper limit absolute value is 2.44 V. That is, the turn-off negative voltage of the switching transistor should be smaller than -2.44 V.

[0057] In some embodiments of the present disclosure, the second turn-off negative voltage model is expressed as V SS_max =V GS_max -λ 2 *f 2 (R G_on , R G_off , V DC ), i.e. equation (3), where V SS_max is the turn-off negative voltage lower limit absolute value, λ 2 is a second derating parameter, f 2 (R G_on , R G_off , V DC ) is a function expression corresponding to the second turn-off negative voltage model, R G_on is the turn-on gate resistance, R G_off is the turn-off gate resistance, V DC is the bus voltage, and V GS_max is the maximum bearable negative voltage absolute value.

[0058] Thus, a relationship between the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor can be clearly expressed by the above equation (3).

[0059] In an exemplary embodiment of the present disclosure, the turn-off gate resistance may be understood as the total resistance of the turn-off circuit when the switching transistor is turned off, and the turn-on gate resistance may be understood as the total resistance of the turn-on circuit when the switching transistor is turned on. In some embodiments, the maximum bearable negative voltage absolute value may be obtained by querying corresponding data based on a specific model of the switching transistor. In some embodiments, the second derating parameter may be obtained by querying corresponding derating criteria based on a specific model of the resistor. In some embodiments, the bus voltage may be obtained by the bus voltage measurement device.

[0060] In some embodiments, a relationship between the turn-off negative voltage lower limit absolute value and the turn-on gate resistance, the turn-off gate resistance, and the bus voltage is shown in FIG. 3. It should be understood that when the turn-on gate resistance, the turn-off gate resistance, and the bus voltage input by the second turn-off negative voltage model change, the turn-off negative voltage lower limit absolute value output from the second turn-off negative voltage model will also change accordingly. Further, different turn-on gate resistances, different turn-off gate resistances, different bus voltages, and corresponding turn-off negative voltage upper lower absolute values are substituted into the above equation (3) to obtain multiple different polynomials. After polynomial fitting, a specific expression of the second turn-off negative voltage model may be expressed as V SS_max =V GS_max +d 2 *R G_on +d 3 *R G_off +d 4 *V DC +d 5 *R G_on 2< +d 6 *R G_off 2< +d 7 *V DC 2< +d 8 *R G_on * R G_off + d 9 *R G_off *V DC + d 10 *R G_off *V DC , i.e. equation (4), where d 2 =-122.9, d 3 =1454.0, d 4 =-488.3, d 5 =2.069, d 6 =-47.87, d 7 =15.43, d 8 =-0.805, d 9 =3.800, and d 10 =-5.223.

[0061] In an example, the maximum bearable negative voltage of the switching transistor is -9V. That is, the switching transistor maximum bearable negative voltage absolute value is 9V. The bus voltage is 900 V, the selected turn-on gate resistance is 40 Ω, and the selected turn-off gate resistance is 20 Ω. By using the equation (4), it is obtained that the turn-off negative voltage lower limit absolute value is 4.96 V. That is, the turn-off negative voltage of the switching transistor should be greater than -4.96 V.

[0062] Referring to FIG. 4, in some embodiments of the present disclosure, the operation at block S17 further comprises operations at blocks S171 and S173.

[0063] At block S171, a negative value of the turn-off negative voltage upper limit absolute value is set as a turn-off negative voltage upper limit voltage, and a negative value of the turn-off negative voltage lower limit absolute value is set as a lower limit voltage of the turn-off negative voltage.

[0064] At block S173, the turn-off negative voltage interval is determined based on the upper limit voltage of the turn-off negative voltage and the lower limit voltage of the turn-off negative voltage.

[0065] In this way, the turn-off negative voltage interval of the switching transistor can be accurately obtained. When a voltage of the gate of the switching transistor is within the turn-off negative voltage interval, the switching transistor can be turned off, effectively preventing the switching transistor from being turned on mistakenly.

[0066] In an exemplary embodiment of the present disclosure, the turn-off negative voltage upper limit absolute value may be understood as an upper limit of an absolute value of the turn-off negative voltage, and the turn-off negative voltage lower limit absolute value may be understood as a lower limit of an absolute value of the turn-off negative voltage. That is, both the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value are positive, and the turn-off negative voltage of the switching transistor is negative. Therefore, a negative value of the turn-off negative voltage upper limit absolute value is set as the upper limit voltage of the turn-off negative voltage, and a negative value of the turn-off negative voltage lower limit absolute value is set as the lower limit voltage of the turn-off negative voltage, and then the turn-off negative voltage interval is determined based on the lower limit voltage of the turn-off negative voltage and the upper limit voltage of the turn-off negative voltage. In this way, it can be ensured that the turn-off negative voltage of the selected switching transistor is greater than or equal to the lower limit voltage of the turn-off negative voltage, and the turn-off negative voltage of the switching transistor is smaller than or equal to the upper limit voltage of the turn-off negative voltage.

[0067] In an example, the minimum turn-on voltage of the switching transistor may be 1.5 V, and the maximum bearable negative voltage of the switching transistor is -9 V. That is, the maximum bearable negative voltage absolute value of the switching transistor is 9 V. The bus voltage may be 900 V. The selected turn-on gate resistance is 40 Ω, and the selected turn-off gate resistance is 20 Ω. By using the equation (2), it is obtained that the turn-off negative voltage upper limit absolute value is 2.44 V. That is, the upper limit voltage of the turn-off negative voltage of the switching transistor is -2.44 V. By using the equation (4), it is obtained that the turn-off negative voltage lower limit absolute value of the switching transistor is 4.96 V. That is, the lower limit voltage of the turn-off negative voltage of the switching transistor is -4.96 V. Thus, the turn-off negative voltage interval of the switching transistor can be determined as [-4.96 V, -2.44V].

[0068] In some embodiments of the present disclosure, the switching transistor is a silicon-carbide Metal Oxide Semiconductor (MOS) transistor.

[0069] Therefore, the turn-off negative voltage interval can be accurately determined based on the above method, thereby effectively preventing the silicon carbide MOS transistor from being turned on mistakenly, protecting the silicon carbide MOS transistor, and prolonging the service life of the silicon carbide MOS transistor. It should be understood that the silicon carbide MOS transistor is more likely to be turned on mistakenly due to its fast speed and a low minimum turn-on voltage.

[0070] It should be noted that the specific numerical values mentioned above are only for the purpose of illustrating the embodiments of the present disclosure in detail by way of example, and should not be construed as limitations on the present disclosure. In other examples or embodiments, other numerical values may be selected in accordance with the present disclosure, and the present disclosure is not limited in this regard.

[0071] In order to implement the above embodiments, embodiments of the present disclosure further provide an apparatus for determining a turn-off negative voltage of a switching transistor. The apparatus can implement the method for determining the turn-off negative voltage of the switching transistor according to any of the above embodiments. FIG. 5 is a block diagram of an apparatus for determining a turn-off negative voltage of a switching transistor according to an embodiment of the present disclosure. As shown in FIG. 5, an apparatus 10 for determining a turn-off negative voltage of a switching transistor according to an embodiment of the present disclosure comprises a first determining module 12, an acquiring module 14, and a second determining module 16. The first determining module 12 is configured to determine a first turn-off negative voltage model and a second turn-off negative voltage model. The acquiring module 14 is configured to acquire a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor. The second determining module 16 is configured to: input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor; input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor; and determine a turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0072] In the apparatus 10 for determining the turn-off negative voltage of the switching transistor according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0073] In some embodiments of the present disclosure, the first turn-off negative voltage model is expressed as V SS_min =λ 1 *f 1 (R G_on , R G_off , V DC )-V th , i.e. equation (1), where V SS_min represents the turn-off negative voltage upper limit absolute value, λ 1 represents a first derating parameter, f 1 (R G_on , R G_off , V DC ) represents a function expression corresponding to the first turn-off negative voltage model, R G_on represents the turn-on gate resistance, R G_off represents the turn-off gate resistance, V DC represents the bus voltage, and V th is the minimum turn-on voltage.

[0074] In some embodiments of the present disclosure, the second turn-off negative voltage model is expressed as V SS_max =V GS_max -λ 2 *f 2 (R G_on , R G_off , V DC ), i.e. equation (3), where V SS_max represents the turn-off negative voltage lower limit absolute value, λ 2 represents a second derating parameter, f 2 (R G_on , R G_off , V DC ) represents a function expression corresponding to the second turn-off negative voltage model, R G_on represents the turn-on gate resistance, R G_off represents the turn-off gate resistance, V DC represents the bus voltage, and V GS_max represents the maximum bearable negative voltage absolute value.

[0075] In some embodiments of the present disclosure, the second determination module 16 comprises a first determination unit and a second determination unit. The first determination unit is configured to set a negative value of the turn-off negative voltage upper limit absolute value as a turn-off negative voltage upper limit voltage, and set a negative value of the turn-off negative voltage lower limit absolute value as a lower limit voltage of the turn-off negative voltage. The second determination unit is configured to determine the turn-off negative voltage interval based on the lower limit voltage of the turn-off negative voltage and the upper limit voltage of the turn-off negative voltage.

[0076] In some embodiments of the present disclosure, the switching transistor is the silicon-carbide MOS transistor.

[0077] It should be noted that the explanatory description of the embodiments and beneficial effects of the method for determining the turn-off negative voltage of the switching transistor is also adapted to the apparatus 10 for determining the turn-off negative voltage of the switching transistor of the present disclosure, and thus the detailed description thereof will be omitted herein to avoid redundancy.

[0078] In order to implement the above embodiments, embodiments of the present disclosure further provide an inverter, which can implement the method for determining the turn-off negative voltage of the switching transistor according to any one of the above embodiments. FIG. 6 is a block diagram of an inverter according to an embodiment of the present disclosure. As shown in FIG. 6, an inverter 30 comprises a memory 32, a processor 34, and a program 36 for determining a turn-off negative voltage of a switching transistor stored in the memory 32 and executable on the processor 34. The processor 34 is configured to implement, when executing the program 36 for determining the turn-off negative voltage of the switching transistor, the method for determining the turn-off negative voltage of the switching transistor according to any one of the embodiments described above.

[0079] In the inverter 30 according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0080] For example, the processor 34 is configured to implement, when the program 36 for determining the turn-off negative voltage of the switching transistor is executed by processor 34, operations at blocks at S11 to S17 of the method for determining the turn-off negative voltage of the switching transistor.

[0081] At block S11, a first turn-off negative voltage model and a second turn-off negative voltage model are determined.

[0082] At block S13, a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor are acquired.

[0083] At block S15, the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage are inputted into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor, and the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value are inputted into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor.

[0084] At block S17, a turn-off negative voltage interval of the switching transistor is determined based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0085] It should be noted that the explanatory description of the embodiments and beneficial effects of the method for determining the turn-off negative voltage of the switching transistor is also adapted to the inverter 30 of the present disclosure, and thus the detailed description thereof will be omitted herein to avoid redundancy.

[0086] In order to implement the above embodiments, embodiments of the present disclosure further provide a computer-readable storage medium having a program for determining a turn-off negative voltage of a switching transistor stored thereon. The program for determining the turn-off negative voltage of the switching transistor, when executed by a processor, implements the method for determining the turn-off negative voltage of the switching transistor according to any one of the above embodiments.

[0087] In the computer-readable storage medium of the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when a negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0088] In order to implement the above embodiments, embodiments of the present disclosure further provide a switching transistor drive control circuit. FIG. 7 is a schematic circuit diagram of a switching transistor drive control circuit according to an embodiment of the present disclosure. As shown in FIG. 7, a switching transistor drive control circuit 50 comprises a drive power supply 52, a drive unit 54, and a control unit 56. The control unit 56 is configured to acquire a turn-off negative voltage interval of a switching transistor 70 by implementing the method for determining the turn-off negative voltage of the switching transistor 70 according to any one of the embodiments described above, and control the drive power supply 52 to provide a negative turn-off voltage to the drive unit 54 based on the turn-off negative voltage interval. The drive unit 54 is configured to drive, in response to receiving a turn-off control signal, the switching transistor 70 to be turned off based on the negative turn-off voltage.

[0089] In the switching transistor drive control circuit 50 according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor 70 is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor 70 into the first turn-off negative voltage model, and the turn-off negative voltage lower limit absolute value of the switching transistor 70 is obtained by inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum bearable negative voltage absolute value of the switching transistor 70 into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor 70 is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor 70 and the turn-off negative voltage lower limit absolute value of the switching transistor 70. Therefore, when a negative voltage turn-off control is performed on the switching transistor 70 by using the turn-off negative voltage interval, the switching transistor 70 can be effectively prevented from being turned on mistakenly, and the switching transistor 70 can be protected, which can prolong service life of the switching transistor 70.

[0090] In some embodiments, the control unit 56 may be a Micro Control Unit (MCU).

[0091] In some embodiments of the present disclosure, the drive unit 54 comprises a first coupling capacitor and a second coupling capacitor. The first coupling capacitor has a terminal connected to a positive turn-on voltage supply terminal of the drive power supply. The second coupling capacitor has a terminal connected to another terminal of the first coupling capacitor, and another terminal connected to a negative turn-off voltage supply terminal of the drive power supply.

[0092] Thus, the positive turn-on voltage supply terminal and the negative turn-off voltage supply terminal of the drive power supply are isolated by the first coupling capacitor and the second coupling capacitor.

[0093] In an example, referring to FIG. 8, the first coupling capacitor comprises a capacitor C 1P and a capacitor C 2P . The second coupling capacitor comprises a capacitor C 1N and a capacitor C 2N . The drive power supply 52 comprises a first drive power supply 522 and a second drive power supply 524. The capacitor C 1P has a terminal connected to a positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. Another terminal of the capacitor C 1P is connected to a terminal of the capacitor C 1N , and the capacitor C 1P has a first node P1. The capacitor C 1N has another terminal connected to a negative turn-off voltage supply terminal VSS1 of the first drive power supply 522. The capacitor C 2P has a terminal connected to a positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. Another terminal of is connected to a terminal of the capacitor C 2N , and the capacitor C 2P has a second node P2. The capacitor C 2N has another terminal connected to a negative turn-off voltage supply terminal VSS2 of the second drive power supply 524.

[0094] In some embodiments of the present disclosure, when the switching transistor 70 is an upper bridge switching transistor, a node between the first coupling capacitor and the second coupling capacitor is connected to a midpoint of a bridge arm at which the upper bridge switching transistor is located. When the switching transistor 70 is a lower bridge switching transistor, a node between the first coupling capacitor and the second coupling capacitor is grounded.

[0095] In this way, in a bridge inverter circuit, by using the switching transistor drive control circuit 50, the switching transistor can be accurately turned off, thereby effectively preventing the switching transistor 70 from being turned on mistakenly, protecting the switching transistor 70, and prolonging service life of the switching transistor 70. It should be understood that the bridge inverter circuit may comprise a single-phase full-bridge inverter circuit, a three-phase bridge inverter circuit, or bridge inverter circuits of other topologies.

[0096] In an example, referring to FIG. 8, the switching transistor 70 comprises an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2. A source of the upper bridge switching transistor Q1 is connected to a drain of the lower bridge switching transistor Q2, and the upper bridge switching transistor Q1 has a third node P3. When the switching transistor 70 is the upper bridge switching transistor Q1, a first node P1 between the first coupling capacitor C 1P and the second coupling capacitor C 1N is connected to a midpoint (i.e. a third node P3) of the bridge arm at which the upper bridge switching transistor Q1 is located. When the switching transistor 70 is the lower bridge switching transistor Q2, a second node P2 between the first coupling capacitor C 2P and the second coupling capacitor C 2N is grounded.

[0097] In some embodiments of the present disclosure, the drive unit 54 comprises a drive chip and a first gate resistor. The drive chip has a positive power pin connected to the positive turn-on voltage supply terminal of the drive power supply, a negative power pin connected to the negative turn-off voltage supply terminal of the drive power supply, and an input pin connected to the control unit to receive a turn-off control signal sent by the control unit. The first gate resistor has a terminal connected to the output pin of the drive chip, and another terminal connected to a gate of the switching transistor.

[0098] In this way, the drive chip can drive the switching transistor to be turned on or off by the first gate resistor.

[0099] In an example, referring to FIG. 8, the drive chip comprises a chip U1 and a chip U2. The first gate resistor comprises a resistor R on 1 and a resistor R on 2. The drive power supply 52 comprises a first drive power supply 522 and a second drive power supply 524. The switching transistor 70 comprises an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2. The first coupling capacitor comprises a capacitor C 1P and a capacitor C 2P . The second coupling capacitor comprises a capacitor C 1N and a capacitor C 2N .

[0100] The drive chip U1 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. The drive chip U1 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS1 of the first drive power supply 522. The drive chip U1 has an input pin IN connected to a first terminal of the control unit 56 to receive a turn-off control signal sent by the control unit 56. The drive chip U1 has an output pin OUT connected to a terminal of the resistor R on 1. The resistor R on 1 has another terminal connected to a gate of the upper bridge switching transistor Q1. A source of the upper bridge switching transistor Q1 is connected to a drain of the lower bridge switching transistor Q2, and the upper bridge switching transistor Q1 has a third node P3. The capacitor C 1P has a terminal connected to the positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. Another terminal of the capacitor C 1P is connected to a terminal of the capacitor C 1N , and the capacitor C 1P has a first node P1. The first node P1 is connected to the third node P3. The capacitor C 1N has another terminal connected to the negative turn-off voltage supply terminal VSS1 of the first drive power supply 522.

[0101] The drive chip U2 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. The drive chip U2 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS2 of the second drive power supply 524. The drive chip U2 has an input pin IN connected to a second terminal of the control unit 56 to receive the turn-off control signal sent by the control unit 56. The drive chip U2 has an output pin OUT connected to a terminal of the resistor R on 2. The resistor R on 2 has another terminal connected to a gate of the lower bridge switching transistor Q2. A drain of the lower bridge switching transistor Q2 is connected to the source of the upper bridge switching transistor Q1, and a source of the lower bridge switching transistor Q2 is grounded. The capacitor C 2P has a terminal connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. Another terminal of the capacitor C 2P is connected to a terminal of the capacitor C 2N , and the capacitor C 2P has a second node P2. The second node P2 is grounded. The capacitor C 2N has another terminal connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524.

[0102] When the control unit 56 sends the turn-on control signal through the first terminal, the positive power pin VDD of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a positive voltage to the positive power pin VDD of the drive chip U1, and the OUT pin of the drive chip U1 outputs the positive voltage. After voltage division by the resistor R on 1, a positive turn-on voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned on. It should be understood that the turn-on gate resistance is the resistor R on 1 in this case. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power pin VSS of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a negative voltage to the negative power pin VSS of the drive chip U1, and the OUT pin of the drive chip U1 outputs the negative voltage. After voltage division by the resistor R on 1, a negative turn-off voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned off. It should be understood that the turn-off gate resistance is a resistance value of the resistor R on 1 in this case.

[0103] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power pin VDD of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a positive voltage to the positive power pin VDD of the drive chip U2, and the OUT pin of the drive chip U2 outputs the positive voltage. After voltage division by the resistor R on 2, a positive turn-on voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned on. It should be understood that the turn-on gate resistance is the resistor R on 2 in this case. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power pin VSS of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a negative voltage to the drive chip U2, and the OUT pin of the drive chip U2 outputs the negative voltage. After voltage division by the resistor R on 2, a negative turn-off voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned off. It should be understood that the turn-off gate resistance is a resistance value of the resistor R on 2 in this case.

[0104] In some embodiments of the present disclosure, the drive unit 54 further comprises a first diode and a second gate resistor. The first diode has a cathode connected to a terminal of the first gate resistor. The second gate resistor has a terminal connected to an anode of the first diode, and another terminal connected to the other terminal of the first gate resistor.

[0105] In an example, referring to FIG. 9, the drive chip comprises a chip U1 and a chip U2. The first gate resistor comprises a resistor R on 1 and a resistor R on 2. The second gate resistor comprises a resistor R off 1 and a resistor R off 2. The drive power supply 52 comprises a first drive power supply 522 and a second drive power supply 524. The switching transistor 70 comprises an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2. The first coupling capacitor comprises a capacitor C 1P and a capacitor C 2P . The second coupling capacitor comprises a capacitor C 1N and a capacitor C 2N . The first diode comprises a diode D1 and a diode D2.

[0106] The drive chip U1 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. The drive chip U1 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS1 of the first drive power supply 522. The drive chip U1 has an input pin IN connected to a first terminal of the control unit 56 to receive a turn-off control signal sent by the control unit 56. The drive chip U1 has an output pin OUT connected to a terminal of the resistor R on 1. The resistor R on 1 has another terminal connected to a gate of the upper bridge switching transistor Q1. A source of the upper bridge switching transistor Q1 is connected to a drain of the lower bridge switching transistor Q2, and the upper bridge switching transistor Q1 has a third node P3. A cathode of the diode D1 is connected to a terminal of the resistor R on 1, and an anode of the diode D1 is connected to a terminal of the resistor R off 1. The resistor R off 1 has another terminal connected to another terminal of the resistor R on 1. The capacitor C 1P has a terminal connected to the positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. Another terminal of the capacitor C 1P is connected to a terminal of the capacitor C 1N , and the capacitor C 1P has a first node P1. The first node P1 is connected to a third node P3. The capacitor C 1N has another terminal connected to the negative turn-off voltage supply terminal VSS1 of the first drive power supply 522.

[0107] The drive chip U2 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. The drive chip U2 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS2 of the second drive power supply 524. The drive chip U2 has an input pin IN connected to a second terminal of the control unit 56 to receive a turn-off control signal sent by the control unit 56. The drive chip U2 has an output pin OUT connected to a terminal of the resistor R on 2. The resistor R on 2 has another terminal connected to a gate of the lower bridge switching transistor Q2. A drain of the lower bridge switching transistor Q2 is connected to a source of the upper bridge switching transistor Q1, and a source of the lower bridge switching transistor Q2 is grounded. A cathode of the diode D2 is connected to a terminal of the resistor R on 2, and an anode of the diode D2 is connected to a terminal of the resistor R off 2. The resistor R off 2 has another terminal connected to another terminal of the resistor R on 2. The capacitor C 2P has a terminal connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. Another terminal of the capacitor C 2P is connected to a terminal of the capacitor C 2N , and the capacitor C 2P has a second node P2. The second node P2 is grounded. The capacitor C 2N has another terminal connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524.

[0108] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power pin VDD of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a positive voltage to the positive power pin VDD of the drive chip U1, the OUT pin of the drive chip U1 outputs the positive voltage, and the diode D1 is turned off. After voltage division by the resistor R on 1, a positive turn-on voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned on. It should be understood that the turn-on gate resistance is the resistor R on 1 in this case. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power pin VSS of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a negative voltage to the negative power pin VSS of the drive chip U1, the OUT pin of the drive chip U1 outputs the negative voltage, and the diode D1 is turned on. After the resistor R on 1 and the resistor R off 1 are connected in parallel, a negative turn-off voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned off. It should be understood that the turn-off gate resistance may be a resistance value of the connected resistor R on 1 and resistor R off 1 in parallel.

[0109] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power pin VDD of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a positive voltage to the positive power pin VDD of the drive chip U2, the OUT pin of the drive chip U2 outputs the positive voltage, and the diode D2 is turned off. After voltage division by the resistor R on 2, a positive turn-on voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned on. It should be understood that the turn-on gate resistance is the resistor R on 2 in this case. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power pin VSS of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a negative voltage to the drive chip U2, the OUT pin of the drive chip U2 outputs the negative voltage, and the diode D2 is turned on. After the resistor R on 2 and the resistor R off 2 are connected in parallel, a negative turn-off voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned off. It should be understood that the turn-off gate resistance may be a resistance value of the connected resistor R on 2 and resistor R off 2 in parallel.

[0110] It should be noted that the diode has a turn-on resistance when being turned on. In some embodiments, the turn-on resistance of the diode may be considered when calculating the turn-on gate resistance and the turn-off gate resistance.

[0111] In some embodiments of the present disclosure, the drive unit 54 further comprises a second diode. The second diode has a cathode connected to the terminal of the first gate resistor and an anode connected to the cathode of the first diode.

[0112] In an example, referring to FIG. 10, the drive chip comprises a chip U1 and a chip U2. The first gate resistor comprises a resistor R on 1 and a resistor R on 2. The second gate resistor comprises a resistor R off 1 and a resistor R off 2. The drive power supply 52 comprises a first drive power supply 522 and a second drive power supply 524. The switching transistor 70 comprises an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2. The first coupling capacitor comprises a capacitor C 1P and a capacitor C 2P . The second coupling capacitor comprises a capacitor C 1N and a capacitor C 2N . The first diode comprises a diode D1 and a diode D3. The second diode comprises a diode D2 and a diode D4.

[0113] The drive chip U1 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. The drive chip U1 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS1 of the first drive power supply 522. The drive chip U1 has an input pin IN connected to a first terminal of the control unit 56 to receive a turn-off control signal sent by the control unit 56. The drive chip U1 has an output pin OUT connected to an anode of the diode D2. A cathode of the diode D2 is connected to a terminal of the resistor R on 1. The resistor R on 1 has another terminal connected to a gate of the upper bridge switching transistor Q1. A source of the upper bridge switching transistor Q1 is connected to a drain of the lower bridge switching transistor Q2, and the upper bridge switching transistor Q1 has a third node P3. A cathode of the diode D1 is connected to an anode of the diode D2. An anode of the diode D1 is connected to a terminal of the resistor R off 1. The resistor R off 1 has another terminal connected to another terminal of the resistor R on 1. The capacitor C 1P has a terminal connected to the positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. Another terminal of the capacitor C 1P is connected to a terminal of the capacitor C 1N , and the capacitor C 1P has a first node P1. The first node P1 is connected to the third node P3. The capacitor C 1N has another terminal connected to the negative turn-off voltage supply terminal VSS1 of the first drive power supply 522.

[0114] The drive chip U2 has a positive power pin VDD connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. The drive chip U2 has a negative power pin VSS connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524. The drive chip U2 has an input pin IN connected to a second terminal of the control unit 56 to receive the turn-off control signal sent by the control unit 56. The drive chip U2 has an output pin OUT connected to an anode of the diode D4. A cathode of diode D4 is connected to a terminal of resistor R on 2. The resistor R on 2 has another terminal connected to a gate of the lower bridge switching transistor Q2. A cathode of the diode D3 is connected to the anode of the diode D4. An anode of the diode D3 is connected to a terminal of the resistor R off 2. The resistor R off 2 has another terminal connected to another terminal of the resistor R on 2. The drain of the lower bridge switching transistor Q2 is connected to the source of the upper bridge switching transistor Q1, and the source of the lower bridge switching transistor Q2 is grounded. The capacitor C 2P has a terminal connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. Another terminal of the capacitor C 2P is connected to a terminal of the capacitor C 2N , and the capacitor C 2P has a second node P2. The second node P2 is grounded. The capacitor C 2N has another terminal connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524.

[0115] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power pin VDD of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a positive voltage to the positive power pin VDD of the drive chip U1, and the OUT pin of the drive chip U1 outputs the positive voltage. The diode D2 is turned on, and the diode D1 is turned off. After voltage division by the resistor R on 1, a positive turn-on voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned on. It should be understood that the turn-on gate resistance is the resistor R on 1 in this case. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power pin VSS of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a negative voltage to the negative power pin VSS of the drive chip U1, and the OUT pin of the drive chip U1 outputs the negative voltage. The diode D1 is turned on, and the diode D2 is turned off. After voltage division by the resistor R off 1, a negative turn-off voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned off. It should be understood that the turn-off gate resistance is a resistance value of the resistor R off 1 in this case.

[0116] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power pin VDD of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a positive voltage to the positive power pin VDD of the drive chip U2, and the OUT pin of the drive chip U2 outputs the positive voltage. The diode D4 is turned on, and the diode D3 is turned off. After voltage division by the resistor R on 2, a positive turn-on voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned on. It should be understood that at this time, the turn-on gate resistance is the resistor R on 2 in this case. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power pin VSS of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a negative voltage to the drive chip U2, and the OUT pin of the drive chip U2 outputs the negative voltage. The diode D3 is turned on, and the diode D4 is turned off. After voltage division by the resistor R off 2, a negative turn-off voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned off. It should be understood that the turn-off gate resistance is a resistance value of the resistor R off 2 in this case.

[0117] It should be noted that the diode has a turn-on resistance when being turned on. In some embodiments, the turn-on resistance of the diode may be considered when calculating the turn-on gate resistance and the turn-off gate resistance.

[0118] In some embodiments of the present disclosure, the drive unit 54 further comprises a first diode and a second gate resistor. The first diode has a cathode connected to the terminal of the first gate resistor and an anode connected to another terminal of the first gate resistor. The second gate resistor has a terminal connected to the anode of the first diode, and another terminal connected to the gate of the switching transistor.

[0119] In an example, referring to FIG. 11, the drive chip comprises a chip U1 and a chip U2. The first gate resistor comprises a resistor R on 1 and a resistor R on 2. The second gate resistor comprises a resistor R off 1 and the resistor R off 2. The drive power supply 52 comprises a first drive power supply 522 and a second drive power supply 524. The switching transistor 70 comprises an upper bridge switching transistor Q1 and a lower bridge switching transistor Q2. The first coupling capacitor comprises a capacitor C 1P and a capacitor C 2P . The second coupling capacitor comprises a capacitor C 1N and a capacitor C 2N . The first diode comprises a diode D1 and a diode D2.

[0120] The drive chip U1 has a positive power pin VDD connected to a positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. The drive chip U1 has a negative power pin VSS connected to a negative turn-off voltage supply terminal VSS1 of the first drive power supply 522. The drive chip U1 has an input pin IN connected to a first terminal of the control unit 56 to receive a turn-off control signal sent by the control unit 56. The drive chip U1 has an output pin OUT connected to a terminal of the resistor R on 1. The resistor R on 1 has another terminal connected to a terminal of the resistor R off 1. The resistor R off 1 has another terminal connected to a gate of the upper bridge switching transistor Q1. A source of the upper bridge switching transistor Q1 is connected to a drain of the lower bridge switching transistor Q2, and the upper bridge switching transistor Q1 has a third node P3. A cathode of the diode D1 is connected to a terminal of the resistor R on 1, and an anode of the diode D1 is connected to another terminal of the resistor R on 1. The capacitor C 1P has a terminal connected to the positive turn-on voltage supply terminal VDD1 of the first drive power supply 522. Another terminal of the capacitor C 1P is connected to a terminal of the capacitor C 1N , and the capacitor C 1P has a first node P1. The first node P1 is connected to the third node P3. The capacitor C 1N has another terminal connected to the negative turn-off voltage supply terminal VSS1 of the first drive power supply 522.

[0121] The drive chip U2 has a positive power pin VDD connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. The drive chip U2 has a negative power pin VSS connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524. The drive chip U2 has an input pin IN connected to a second terminal of the control unit 56 to receive the turn-off control signal sent by the control unit 56. The drive chip U2 has an output pin OUT connected to a terminal of the resistor R on 2. The resistor R on 2 has another terminal connected to a terminal of the resistor R off 2. The resistor R off 2 has another terminal connected to the gate of the lower bridge switching transistor Q2. The drain of the lower bridge switching transistor Q2 is connected to the source of the upper bridge switching transistor Q1, and the source of the lower bridge switching transistor Q2 is grounded. A cathode of the diode D2 is connected to a terminal of the resistor R on 2, and an anode of the diode D2 is connected to a terminal of the resistor R on 2. The capacitor C 2P has a terminal connected to the positive turn-on voltage supply terminal VDD2 of the second drive power supply 524. Another terminal of the capacitor C 2P is connected to a terminal of the capacitor C 2N , the capacitor C 2P has a second node P2. The second node P2 is grounded. The capacitor C 2N has another terminal connected to the negative turn-off voltage supply terminal VSS2 of the second drive power supply 524.

[0122] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power pin VDD of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a positive voltage to the positive power pin VDD of the drive chip U1, and the OUT pin of the drive chip U1 outputs the positive voltage. The diode D1 is turned off. After voltage division through the resistor R on 1 and the resistor R off 1 connected in series, a positive turn-on voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned on. It should be understood that, in this case, the turn-on gate resistance is a resistance value of the connected resistor R on 1 and resistor R off 1 in series. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power pin VSS of the drive chip U1 is in communication with the output pin OUT of the drive chip U1. The first drive power supply 522 provides a negative voltage to the negative power pin VSS of the drive chip U1, and the OUT pin of the drive chip U1 outputs the negative voltage. The diode D1 is turned on, and the resistor R on 1 is short-circuited. After voltage division by the resistor R off 1, a negative turn-off voltage is provided for the gate of the upper bridge switching transistor Q1, and the upper bridge switching transistor Q1 is turned off. It should be understood that the turn-off gate resistance may be a resistance value of the resistor R off 1 in this case.

[0123] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power pin VDD of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a positive voltage to the positive power pin VDD of the drive chip U2, and the OUT pin of the drive chip U2 outputs a positive voltage. The diode D2 is turned off. After voltage division through the connected resistor R on 1 and resistor R off 1 in series, a positive turn-on voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned on. It should be understood that, in this case, the turn-on gate resistance is a resistance value of the connected resistor R on 1 and resistor R off 1 in series. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power pin VSS of the drive chip U2 is in communication with the output pin OUT of the drive chip U2. The second drive power supply 524 provides a negative voltage to the negative power pin VSS of the drive chip U2, and the OUT pin of the drive chip U2 outputs the negative voltage. The diode D2 is turned on, and the resistor R on 2 is short-circuited. After voltage division by the resistor R off 2, a negative turn-off voltage is provided for the gate of the lower bridge switching transistor Q2, and the lower bridge switching transistor Q2 is turned off. It should be understood that the turn-off gate resistance may be a resistance value of the resistor R off 2 in this case.

[0124] It should be noted that the diode has a turn-on resistance when being turned on. In some embodiments, the turn-on resistance of the diode may be considered when calculating the turn-on gate resistance and the turn-off gate resistance.

[0125] In order to implement the above embodiments, embodiments of the present disclosure further provide a motor control system. FIG. 12 is a structural block diagram of a motor control system according to an embodiment of the present disclosure. As shown in FIG. 12, the motor control system100 comprises the switching transistor drive control circuit 50 according to any one of the above embodiments.

[0126] In order to implement the above embodiments, embodiments of the present disclosure further provide a compressor. FIG. 13 is a structural block diagram of a compressor according to an embodiment of the present disclosure. As shown in FIG. 13, the compressor 200 comprises the motor control system 100 according to the above embodiments.

[0127] In order to implement the above embodiments, embodiments of the present disclosure further provide a vehicle. FIG. 14 is a structural block diagram of a vehicle according to an embodiment of the present disclosure. As shown in FIG. 14, the vehicle 300 comprises the compressor 200 according to the above embodiments.

[0128] The vehicle 300 may be a new energy vehicle. In some embodiments, the new energy vehicle may be a pure electric vehicle using an electric motor as a main driving force. In other embodiments, the new energy vehicle may also be a hybrid vehicle using an internal combustion engine and an electric motor as main driving forces. With regard to the internal combustion engine and the electric motor for providing driving power for the new energy vehicle mentioned in the above embodiments, the internal combustion engine may employ gasoline, diesel oil, hydrogen, or the like as fuel, and the electric motor may employ a power battery, hydrogen fuel cell, or the like to providing electric energy, and the present disclosure is not limited in this regards. It should be noted that the embodiments are only an exemplary description of a structure of the new energy vehicle, and is not intended to limit the scope of the present disclosure.

[0129] In addition, in some embodiments, the compressor applicable to the new energy vehicle according to the embodiments of the present disclosure may be an electric compressor comprising a driving portion and a compression portion. The driving portion in the electric compressor is configured to drive the compression portion to perform a compression operation. For example, the driving portion may be a driving motor comprising a rotor and a stator. In addition, in some embodiments, the electric compressor may be a low back pressure compressor. The drive portion may be disposed at a low pressure chamber in communication with an intake port of the compressor. The compression portion may be disposed at a high pressure chamber in communication with an exhaust port of the compressor. Further, in some embodiments, the electric compressor may be a horizontal compressor, and the drive portion and the compression portion may be arranged transversely.

[0130] In the motor control system 100, the compressor 200, and the vehicle 300 according to the embodiments of the present disclosure, the turn-off negative voltage upper limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance and turn-on gate resistance of the switching transitory, the acquired bus voltage, and the acquired minimum turn-on voltage of the switching transistor into the first turn-off negative voltage model, and a turn-off negative voltage lower limit absolute value of the switching transistor is obtained by inputting the acquired turn-off gate resistance and turn-on gate resistance, the acquired bus voltage, and the maximum bearable negative voltage absolute value of the switching transistor into the second turn-off negative voltage model. Then, the turn-off negative voltage interval of the switching transistor is accurately determined based on the turn-off negative voltage upper limit absolute value of the switching transistor and the turn-off negative voltage lower limit absolute value of the switching transistor. Therefore, when the negative voltage turn-off control is performed on the switching transistor by using the turn-off negative voltage interval, the switching transistor can be effectively prevented from being turned on mistakenly, and the switching transistor can be protected, which can prolong service life of the switching transistor.

[0131] It should be noted that the explanatory description of the embodiments and beneficial effects of the switching transistor drive control circuit is also adapted to the motor control system 100, the compressor 200, and the vehicle 300 of the present disclosure, and thus the detailed description thereof will be omitted herein to avoid redundancy.

[0132] Those skilled in the art should understand that the embodiments of the present disclosure can be provided as a method, a system, or a computer program product. Therefore, the present disclosure may adopt a form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. In addition, the present disclosure may employ a form of a computer program product implemented on one or more computer-usable storage media (comprising but being not limited to disk storage, Compact Disc Read-Only Memory (CD-ROM), optical storage, etc.) containing computer-usable program codes.

[0133] The present disclosure is described with reference to flowcharts and / or block diagrams of the method, the device (system), and the computer program product according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and a combination of processes and / or blocks in the flowcharts and / or block diagrams may be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that instructions executed by the processor of the computer or other programmable data processing devices generate an apparatus for implementing functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0134] These computer program instructions may further be stored in a computer-readable memory that can guide a computer or other programmable data processing devices to work in a specific manner, such that instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device. The instruction device implements functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0135] These computer program instructions can further be loaded on a computer or other programmable data processing devices to enable a series of operation steps to be executed on the computer or other programmable devices for producing computer-implemented processing, such that instructions executed on the computer or other programmable devices provide actions for implementing functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0136] In the description of this specification, description with reference to the terms "an embodiment", "some embodiments", "exemplary embodiments", "examples" "specific examples", or "some examples" etc., mean that specific features, structure, materials or characteristics described in conjunction with the embodiment or example are comprised in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0137] In addition, terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features associated with "first" and "second" may explicitly or implicitly comprise at least one of the features. In the description of the present disclosure, "plurality" means at least two, e.g., two, three, four, etc., unless otherwise specifically defined.

[0138] In the present disclosure, unless otherwise clearly specified and limited, terms such as "install", "connect", "connect to", "fix" and the like should be understood in a broad sense. For example, it may be a fixed connection or a detachable connection or connection as one piece; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate; internal communication of two components or the interaction relationship between two components, unless otherwise clearly limited. For those skilled in the art, the specific meaning of the above-mentioned terms in the present disclosure should be understood according to specific circumstances.

[0139] It should be noted that, in order to make the description simple, all possible combinations of the technical features in the foregoing embodiments are not described. However, as long as there is no conflict between the technical features in the embodiments, any combination of technical features in the above-described embodiments may be adopted, which should be considered in the scope of this specification.

[0140] Although embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are merely exemplary, and cannot be construed as limitations of the present disclosure. For those skilled in the art, changes, alternatives, and modifications can be made to the above embodiments without departing from the scope of the present invention as defined in the appended claims.

Claims

1. A processor-implemented method for determining a turn-off negative voltage of a switching transistor (70), comprising: (S11) determining a first turn-off negative voltage model and a second turn-off negative voltage model; (S13) acquiring a turn-off gate resistance and a turn-on gate resistance of the switching transistor (70), a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor (70); (S15) inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor (70), and inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor (70); and (S17) determining a turn-off negative voltage interval of the switching transistor (70) based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

2. The method according to claim 1, wherein the first turn-off negative voltage model is expressed as: V SS_min = λ 1 * f 1 R G_on , R G_off , V DC − V th , where: VSS_min represents the turn-off negative voltage upper limit absolute value; λ1 represents a first derating parameter; f1(RG_on, RG_off, VDC) represents a function expression corresponding to the first turn-off negative voltage model; RG_on represents the turn-on gate resistance; RG_off represents the turn-off gate resistance; VDC represents the bus voltage; and Vth represents the minimum turn-on voltage; and / or the second turn-off negative voltage model is expressed as: V SS_max = V GS_max − λ 2 * f 2 R G_on , R G_off , V DC , where: VSS_max represents the turn-off negative voltage lower limit absolute value; λ2 represents a second derating parameter; f2(RG_on, RG_off, VDC) represents a function expression corresponding to the second turn-off negative voltage model; RG_on represents the turn-on gate resistance; RG_off represents the turn-off gate resistance; VDC represents the bus voltage; and VGS_max represents the maximum bearable negative voltage absolute value; and / or wherein said (S17) determining the turn-off negative voltage interval of the switching transistor (70) based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value comprises: (S171) setting a negative value of the turn-off negative voltage upper limit absolute value as an upper limit voltage of the turn-off negative voltage, and setting a negative value of the turn-off negative voltage lower limit absolute value as a lower limit voltage of the turn-off negative voltage; and (S173) determining the turn-off negative voltage interval based on the upper limit voltage of the turn-off negative voltage and the lower limit voltage of the turn-off negative voltage; and / or wherein the switching transistor (70) is a silicon-carbide Metal Oxide Semiconductor (MOS) transistor.

3. An apparatus (10) for determining a turn-off negative voltage of a switching transistor (70), comprising: a first determining module (12) configured to determine a first turn-off negative voltage model and a second turn-off negative voltage model; an acquiring module (14) configured to acquire a turn-off gate resistance and a turn-on gate resistance of the switching transistor (70), a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor (70); and a second determining module (16) configured to: input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor (70); input the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor (70); and determine a turn-off negative voltage interval of the switching transistor (70) based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

4. An inverter (30), comprising: a memory (32); a processor (34); and a program (36) determining a turn-off negative voltage of a switching transistor (70) stored in the memory (32) and executable on the processor (34), wherein the processor (34) is configured to implement, when executing the program (36) for determining the turn-off negative voltage of the switching transistor (70), a method according to claim 1 or 2.

5. A computer-readable storage medium, having a program (36) for determining a turn-off negative voltage of a switching transistor (70) stored thereon, wherein the program (36) for determining the turn-off negative voltage of the switching transistor (70), when executed by a processor (34), implements a method according to claim 1 or 2.

6. A switching transistor drive control circuit (50), comprising: a drive power supply (52); a drive unit (54); and a control unit (56), wherein: the control unit (56) is configured to acquire a turn-off negative voltage interval of a switching transistor (70) by implementing a method according to claim 1 or 2, and control the drive power supply (52) to provide a negative turn-off voltage to the drive unit (54) based on the turn-off negative voltage interval; and the drive unit (54) is configured to drive, in response to receiving a turn-off control signal, the switching transistor (70) to be turned off based on the negative turn-off voltage.

7. The switching transistor drive control circuit (50) according to claim 6, wherein the drive unit (54) comprises: a drive chip (U1, U2) having a positive power pin (VDD) connected to a positive turn-on voltage supply terminal (VDD1, VDD2) of the drive power supply (52), and having a negative power pin (VSS) connected to a negative turn-off voltage supply terminal (VSS1, VSS2) of the drive power supply (52), and an input pin (IN) of the drive chip connected to the control unit (56) to receive the turn-off control signal sent by the control unit (56); and a first gate resistor having a terminal connected to an output pin (OUT) of the drive chip (U1, U2), and having an other terminal connected to a gate of the switching transistor (70).

8. The switching transistor drive control circuit (50) according to claim 7, wherein the drive unit (54) further comprises: a first diode having a cathode connected to the terminal of the first gate resistor; and a second gate resistor having a terminal connected to an anode of the first diode, and having another terminal connected to the other terminal of the first gate resistor.

9. The switching transistor drive control circuit (50) according to claim 8, wherein the drive unit (54) further comprises: a second diode having a cathode connected to the terminal of the first gate resistor and having an anode connected to a cathode of the first diode.

10. The switching transistor drive control circuit (50) according to any one of claims 7 to 9, wherein the drive unit (54) further comprises: the first diode having the cathode connected to the terminal of the first gate resistor and the anode connected to the other terminal of the first gate resistor; and the second gate resistor having the terminal connected to the anode of the first diode, and the other terminal connected to the gate of the switching transistor (70).

11. The switching transistor drive control circuit (50) according to any one of claims 7 to 10, wherein the drive unit (54) further comprises: a first coupling capacitor having a terminal connected to the positive turn-on voltage supply terminal (VDD1, VDD2) of the drive power supply (52); and a second coupling capacitor having a terminal connected to another terminal of the first coupling capacitor, and another terminal connected to the negative turn-off voltage supply terminal (VSS1, VSS2) of the drive power supply (52).

12. The switching transistor drive control circuit (50) according to claim 11, wherein: when the switching transistor (70) is an upper bridge switching transistor (Q1), a node between the first coupling capacitor and the second coupling capacitor is connected to a midpoint of a bridge arm at which the upper bridge switching transistor (Q1) is located; and when the switching transistor (70) is a lower bridge switching transistor (Q2), a node between the first coupling capacitor and the second coupling capacitor is grounded.

13. A motor control system (100), comprising a switching transistor drive control circuit (50) according to any one of claims 6 to 12.

14. A compressor (200), comprising a motor control system (100) according to claim 13.

15. A vehicle (300), comprising a compressor (200) according to claim 14.