NON-VOID STORAGE STRUCTURE WITH A STACK ARRANGED IN A VIA AND A CONDITION OVER IT, AS WELL AS THEIR MANUFACTURING METHOD.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of non-volatile memories formed from a stack of layers and comprising at least one layer of active material between two electrodes. It relates more particularly to ferroelectric memories (FeRAM), resistive memories (OxRAM), and ferroelectric tunnel junction (FTJ) memories.

[0002] The present invention provides a microelectronic device with a non-volatile memory structure, the arrangement of which is improved, as well as an improved method for manufacturing such a device. EARLIER ART

[0003] Ferroelectric memories, or FeRAM, are characterized by their non-volatility, meaning they retain stored information even when their power supply is interrupted; their low energy consumption; fast read and write times; the ability to be massively integrated onto chips with low operating voltages; low access latency; and good radiation immunity. Furthermore, this type of memory exhibits very high write endurance. These memories operate based on the ferroelectric properties of their active material, which is sandwiched between two electrodes.By applying a potential difference between the two electrodes, creating an electric field greater than the positive coercive field, the ferroelectric memory is placed in a high remanent polarization state. By applying a potential difference, creating an electric field less than the negative coercive field, the ferroelectric memory is placed in a low remanent polarization state. The high remanent polarization state then corresponds to a given first logic state, for example '0', and the low remanent polarization state to a complementary logic state, for example '1', thus enabling information storage.

[0004] Another type of memory, called resistive memory, such as OxRAM (Oxide Resistive RAM), relies on an active material between two electrodes exhibiting at least two resistive states: a high resistance state (HRS) and a low resistance state (LRS), under the application of a voltage. OxRAM's main advantages are its non-volatility, fast read and write times, ability to be integrated onto chips in large quantities, low access latency, and good immunity to radiation and temperature. OxRAM typically has a MIM (Metal-Insulator-Metal) structure comprising an active material with variable electrical resistance, generally a transition metal oxide, placed between two metallic electrodes.The transition from the "HRS" state to the "LRS" state is governed by the formation and breaking of at least one conductive filament between the two electrodes. This conductive filament is created by the presence of oxygen vacancies in the active layer of the memory. By changing the potentials applied to the electrodes, it is possible to modify the filament's distribution and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken or reformed to vary the resistance level of the memory cell during write and reset cycles (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations, resulting in the HRS state, when the filament is broken again by applying a SET voltage, VSET, or RESET voltage, VRESET, to the electrode terminals, respectively).

[0005] Ferroelectric Tunnel Junction (FTJ) memories are memories that use the change in electrical resistance of a ferroelectric-type active material arranged between two electrodes to store information, with low volatility and high information density.

[0006] The aforementioned memories have in common that they are formed from a stack of layers containing at least one active material arranged between two electrodes.

[0007] Nowadays, this type of memory stacking is mainly carried out in a final metallic interconnect layer.

[0008] An example of implementation in a final metallic interconnect layer is given in the document entitled "16kbit HfO2:Si-based 1T-1C FeRAM Arrays Demonstrating High Performance Operation and Solder Reflow Compatibility", François, 2021 IEDM. This document specifically describes a "2D" (i.e., planar) arrangement of such a stack.

[0009] To increase the developed area of ​​the stack and improve performance, so-called "3D" arrangements have emerged. The paper "Ferroelectric deep trench capacitors based on Al:HfO2 for 3D non-volatile memory applications," Polakowski, 2014, IEEE International Memory Workshop (IMW), presents, for example, such an arrangement, in which the arrangement extends into a particular region where a plurality of juxtaposed trenches have been formed. Non-volatile memory devices according to the preamble of independent claim 1 are known, for example, from US patents 9,553,265 B1 and WO 2015 / 147801 A1.

[0010] Implementing such an arrangement may require dedicating a specific area of ​​a microelectronic device to the memory structure and additional, specific photolithography steps. It also presents challenges in terms of contact with the lower or upper electrode.

[0011] Therefore, there is a need to address one or more of the disadvantages mentioned above. DESCRIPTION OF THE INVENTION

[0012] According to one aspect, the present invention provides a microelectronic device comprising: a substrate comprising a plurality of superimposed metallic interconnection levels, a non-volatile memory structure arranged on a first conductive line of a first metallic interconnection level, the non-volatile memory structure comprising a stack having a lower electrode and an upper electrode and at least one layer of active material between the lower and upper electrodes, the device further comprising: the first conductive line of the first interconnection level, and a second conductive line of said first metallic interconnection level, the second conductive line being distinct from the first conductive line, the first conductive line and the second conductive line being arranged in the same first plane parallel or substantially parallel to a principal plane of the substrate,a third conductive line belonging to a second, higher metallic interconnection level relative to said first interconnection level, the third conductive line being arranged in a second plane parallel to the principal plane of the substrate and above the first plane such that the first plane is arranged between the second plane and the principal plane of the substrate, the third conductive line being connected to the second conductive line via a conductive via, the conductive via extending in an intermediate region between said first plane and said second plane, the lower electrode, the upper electrode, and said at least one layer of active material of said stack of the non-volatile structure extending into the higher metallic interconnection level and into said intermediate region.

[0013] With such a configuration, it is possible to implement a memory stack with a large developed area while limiting the footprint in the plane of the memory structure and moving away from a so-called "front-end" area corresponding to the level in which components such as transistors are formed.

[0014] The non-volatile memory (NVM) structure may advantageously comprise an upper portion of a given cross-section and a lower portion of a different cross-section than the given cross-section.

[0015] Advantageously, the third conducting line and the via conductor passing through an insulating thickness, the insulating thickness extending over the first conducting line and the second conducting line, said stacking of the non-volatile structure lining side walls as well as a bottom of a trench and a hole situated in the extension of that trench, the hole and the trench being arranged in said insulating thickness, the stacking being disposed at the bottom of the hole on the first conducting line.

[0016] Advantageously, the hole is designed with a width W1 and the trench with a width W2 such that W2 > W1, so that the non-volatile structure has a lower portion and an upper portion that is wider than the lower portion. This configuration facilitates contact with the upper part of the memory structure.

[0017] According to one implementation possibility, the cumulative height H of the hole and trench is substantially equal to the cumulative height hc of the conductor via and the third conductor line.

[0018] Such a configuration contributes to the implementation of an integrated memory structure within standard / conventional interconnection levels and having a large developed area but without having to provide specific design rules for its design.

[0019] According to one possible implementation, the process further includes: a first upper conductor via having a lower end disposed on and in contact with the non-volatile memory structure (NVM) and extending, within an insulating thickness, between this lower end and an upper end, a second upper conductor via having a lower end disposed on and in contact with the third conductor line, and extending within said insulating thickness between its lower end and an upper end, the first via upper conductor and the second via upper conductor having equal respective heights measured between their lower end and their upper end.

[0020] Advantageously, said via conductor has a lower end in contact with the second conducting line and an upper end in contact with the third conducting line, said via conductor and the third conducting line being arranged in at least one insulating layer, a lower face of the insulating layer being disposed on and in contact with the first conducting line and the second conducting line,

[0021] the non-volatile structure extending entirely within said insulating layer, between the lower face of the insulating layer and a plane passing through both an upper face of the insulating layer opposite the lower face, the lower end of the first via upper conductor and through the lower end of the second via upper conductor.

[0022] According to one possible implementation, the lower electrode, the upper electrode and at least one layer of active material of said stack of the non-volatile structure (NVM) extend in the form of a fourth conductive line, distinct from the third conductive line and belonging to the second metallic interconnection level and in the form of at least one other via conductor in the extension of the fourth conductive line and to contact the first conductive line.

[0023] In this case, advantageously, the fourth conducting line and said other via have a cross-sectional profile (or cross-section) substantially identical to that (respectively) of the third conducting line and said conducting via.

[0024] Advantageously, the device can also be provided with an additional conductor via arranged on and in contact with an upper portion of the memory structure.

[0025] Preferably, the upper electrode is provided or coated with a zone of conductive material for filling the hole and trench, the additional conductive via being disposed on and in contact with the upper portion of the memory structure without being disposed in contact with the active material or the lower electrode.

[0026] Similarly, another additional conductor via can advantageously be provided on the third conductor line.

[0027] Thus, depending on one implementation possibility, one or more additional conductive or metallic interconnection levels may be provided on or above the non-volatile memory structure.

[0028] According to one particular first implementation, the non-volatile memory structure can be of the FeRAM type, the active material then being formed of a ferroelectric dielectric layer.

[0029] According to one implemented variant, the non-volatile memory structure can be of the OXRAM type, with the active material consisting of at least one layer of dielectric oxide.

[0030] According to another implemented variant, the non-volatile memory structure can be of the FTJ type, the active material being formed of at least one layer of ferroelectric dielectric in contact with a layer of another dielectric material.

[0031] According to another implemented variant, the non-volatile memory structure can be of the CBRAM type, with the active material being formed of at least one electrolyte layer.

[0032] According to another aspect, the present invention provides for the implementation of a method for making a microelectronic device as defined above.

[0033] According to another aspect, the present invention relates to a method for manufacturing a microelectronic device equipped with a non-volatile memory (NVM) structure formed from a stack comprising at least one lower electrode and at least one upper electrode and at least one active material between the lower and upper electrodes, the method comprising the following steps: provide a substrate coated with at least one insulating layer, a first conductive line and a second conductive line of a given interconnection level (Mx-1) extending into the insulating layer and in the same first plane parallel to a principal plane of the substrate, form an insulating thickness on the first conductive line, the second conductive line and said insulating layer, form in said insulating thickness, a hole exposing the first conductive line and a trench in the extension of this hole, deposit in the trench and in the hole a stack comprising at least one lower electrode layer, at least one active material layer and at least one upper electrode layer, said stack lining side walls and bottom of hole and trench.

[0034] Such a process makes it possible to reconcile a large developed surface area of ​​the memory structure with the size of this structure.

[0035] Such a process also makes it possible to create the memory structure without necessarily planning for specific drawing rules.

[0036] In addition to the aforementioned advantages, carrying out the stacking at a level far removed from the components formed in a semiconductor layer of the substrate helps to protect it from steps with a high thermal budget.

[0037] Advantageously, the deposit in the trench and in the hole of said stack is followed by the filling of the trench and the hole by depositing a metallic material, so as to fill the hole and the trench.

[0038] The stacking deposition is typically a conformal deposition and can be advantageously performed by ALD.

[0039] According to one possible implementation, the process may further include the formation in the insulating thickness of a conductive via in contact with the second conductive line and of a third conductive line on the conductive via.

[0040] According to one possible implementation of the process, the construction of the conductor via and the third conductor line may include the following steps: construction of a first masking in relation to the first conductive line and having at least one opening in relation to the second conductive line, engraving through the opening of the first masking of another trench and another hole in the extension of the other trench and having a bottom exposing the second conductive line, filling the other trench and the other hole with at least one conductive material, the process also including: removal of the first masking and formation of a second masking having at least one opening opposite the first conductive line, engraving of the insulating thickness through the opening of the second masking to form the trench and the hole.

[0041] According to a second possible implementation of the process, the construction of the conductor via and the third conductor line may include the formation of another trench and another hole in the extension of the other trench, the other hole having a bottom exposing the second conductor line, the hole exposing the first conductor line and the other hole exposing the second conductor line being formed simultaneously.

[0042] Advantageously, the trench, the other trench, the hole, and the other hole can be formed by engraving the insulating layer through one or more openings in a first masking. The process can then further include the following steps: filling the trench, the other trench, the hole and the other hole with at least one conductive material, removal of the first masking and formation of a second masking opposite the second conductive line and the third conductive line, the second masking having at least one opening opposite the first conductive line, the process also includes the following steps: removal of conductive material from the trench and hole by engraving through the opening of the second masking, so as to free the trench and hole again, formation of the pile in the trench and hole.

[0043] Depending on the implementation method, the active material layer(s) may be formed: of a ferroelectric dielectric, in particular an oxide such as Si-doped HfO2 or HfZrO2, or of a dielectric oxide such as HfO2, or of an electrolyte layer, in particular based on a metallic oxide such as HfO2 or Al2O3 or Ta2O5 or based on a chalcogenide such as GeSe or GeTe or GeSbTe, of a stack of a ferroelectric dielectric and another dielectric.

[0044] Preferably, the other dielectric is chosen so as to exhibit a large band gap (i.e. a large difference between its valence band and its conduction band) in order to exhibit a large tunnel resistance at a small thickness.

[0045] According to one possible implementation, the lower electrode and the lower electrode can be formed: of a layer in a first material chosen in particular from one or more of the following materials: Ti, TiN, W of a layer in a metallic material chosen in particular from one or more of the following materials: W, Cu, Al, AlCu, AlSi. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The present invention will be better understood upon reading the description of the given exemplary embodiments, provided for illustrative purposes only and in no way limiting the application, with reference to the accompanying drawings in which: THE Figures 1A and 1B illustrate a particular arrangement of a non-volatile memory structure formed by a stack and integrated at the same level as, respectively, a conductive via and an interconnecting conductive line. figures 2A, 2B And 2C illustrate different examples of stacking from which the non-volatile memory structure is likely to be formed. figure 3illustrates a possible starting structure for implementing a microelectronic device according to the invention. figures 4A to 4F illustrate a first example of a manufacturing process for a non-volatile memory structure formed by a stack within an insulating layer, in which one or more conductive vias and one or more conductive lines of a metallic interconnecting layer are also formed. Figures 5A to 5D illustrate a second example of a manufacturing process for a non-volatile memory structure in which the location of the stacking in the form of a hole and trench in an insulating thickness is located at the same location as a conductive via and a conductive line in that same thickness. Figures 6A and 6B illustrate stacking arrangements that are not part of the claimed invention. figure 7This illustrates an example of an implementation in which the non-volatile memory structure is formed by a stack of layers and is connected to a conductor via arranged on this stack. figure 8 illustrates a particular arrangement of a non-volatile memory structure with an upper part that forms a conducting line.

[0047] Identical, similar or equivalent parts of the different figures carry the same numerical references in order to facilitate the transition from one figure to another.

[0048] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible. DETAILED DESCRIPTION OF SPECIFIC METHODS OF IMPLEMENTATION

[0049] We refer first to Figures 1A and 1Bgiving respectively, from a top view and from a perspective view, an example of a non-volatile NVM memory structure formed in an Mx level (with x greater than or equal to 1 and typically at least equal to 3) of interconnections of a microelectronic device.

[0050] The non-volatile NVM memory structure is here realized in a level commonly referred to as the "back end" of the device, above an underlying "front-end" level in which the semiconductor components, and in particular the transistors, are located.

[0051] The non-volatile memory structure NVM can be, for example, of the FeRAM, OxRAM, FTJ, or CBRAM type and has a lower portion 192A arranged on and in contact with a first conductive line 111, here a metallic line of a given interconnection level Mx-1 among a plurality of metallic interconnection levels of the microelectronic device.

[0052] This lower portion 192A may have the form of a conducting via and is located at the same level as another conducting via 161. By “conducting via” we mean a conducting element said to be “vertical” and extending between two conducting lines of different levels and located in distinct planes.

[0053] The via conductor 161 provides the connection between a second conducting line 112 at the same given level Mx-1 as the first line 111 and a third conducting line 163 at a level Mx higher than the given level. The first conducting line 111 and the second conducting line 112 are thus arranged in the same first plane P1. The first conducting line 111 and the second conducting line 112 are distinct and preferably unconnected and / or non-intersecting.

[0054] The non-volatile memory structure NVM also includes an upper portion 192B arranged at the same level Mx as the third conducting line 163. The third conducting line 163 is here arranged in the same second plane P2, parallel to the first plane P1, as the upper portion 192B of the NVM structure.

[0055] Preferably, the Mx level does not correspond to the last "back-end" level of the device, so that there are one or more metallic levels above the Mx level. Thus, one or more additional (not shown) conductive lines can be provided above the third conductive line 163. The non-volatile memory (NVM) structure is therefore advantageously located between the "front end" of the device and the last "back-end" level, on which contact pads or bumps are typically arranged.

[0056] The upper portion 192B of the NVM memory structure can here be designed with a width W2 or critical dimension greater than the width or critical dimension W1 of the upper portion 192A (W1 and W2 being dimensions measured parallel to the x-axis on the figure 1B and which correspond to the smallest dimension of a motif measured parallel to the plane [O; x; y]). The width W 2 can advantageously be provided on the order of that of a conducting line 163 located at the same level, for example between 20 nm and 60 nm.

[0057] The cumulative height H of the lower portion 192A and the upper portion 192B can be expected to be of the order of that cumulative of the via conductor 161 and the conducting line 163. Thus, the arrangement of the NVM memory structure does not necessarily induce here a modification of design rules or a loss of density.

[0058] The non-volatile memory (NVM) structure is formed from a stack comprising at least one lower electrode and one upper electrode, as well as at least one active material arranged between the lower and upper electrodes. The lower electrode, the upper electrode, and the active material of this memory stack extend both into the upper interconnecting metallic layer Mx and into an intermediate region R12 located between the first plane P1 and the second plane P2.

[0059] Different stacking compositions can be considered depending on the type of NVM memory structure implemented.

[0060] A specific example of a 60 stacking is given on the figure 2Afor a FeRAM-type structure. It has a lower electrode layer 63, coated with a ferroelectric dielectric layer 65, itself coated with an upper electrode layer 67. Advantageously, the lower electrode layer 63 can be arranged on and in contact with a metallic layer 61. Similarly, a metallic layer 69 can advantageously be arranged on and in contact with the upper electrode layer 67. The ferroelectric dielectric layer 65 can, for example, be based on HfO₂ doped in particular with Si or on HfZrO₂, optionally doped, for example, with lanthanum (La) or aluminum (Al). The lower and upper electrode layers 63 and 67 can be formed, for example, from TiN or W, or from a stack of Ti and TiN for the lower electrode layer 63. 61. Metallic layers 61, 69 can, for example, be based on W, Cu, Al, AlCu, AISi.

[0061] A specific example of stacking to implement an OxRAM-type NVM structure is given on the figure 2B It differs in particular from the stack described previously by the composition of at least one of its electrodes, here by the upper electrode layer 67', preferably containing an oxidizable conductive material such as, for example, Ta, Ti, or Hf. The active layer disposed between the electrodes is a dielectric 65' of the dielectric oxide type, in particular an oxide of one of the oxidizable conductive materials mentioned previously, for example, HfO2.

[0062] Another example of stacking is given on the figure 2Cto form this time a non-volatile memory structure of the FTJ type. The active layer located between the electrodes is unique in that it is formed from a stack of dielectric layers 65, 66 based on distinct dielectric materials. A first dielectric layer 65 corresponds in this particular example to a ferroelectric dielectric, for example, Si-doped HfO2 or HfZrO2; this first dielectric layer is coated here with a second dielectric layer 66, for example, based on Al2O3.

[0063] For the sake of simplicity, one or the other of the stackings of the figures represented on the Figure 2A, 2B , 2C are arranged in a planar pattern. However, as can be seen on the figure 1B, a particular 3D distributed stacking arrangement across several distinct and non-parallel planes is planned here so as to give the NVM memory structure a large developed area while limiting the footprint in the plane (in other words in a direction parallel to the [O;x;y] plane on the figure 1B .

[0064] An increase in the surface area of ​​the NVM memory structure, particularly in the case of FeRAM, allows for a larger memory window and better separation of its memory states. Such an improvement, especially in the case of FTJ, leads to a reduction in the structure's overall resistance and, at a constant current density, an increase in injected current. When the NVM structure is of the OxRAM type, an increase in surface area reduces the "forming" voltage required to change its conductive state by creating conductive filaments, thus limiting power consumption.

[0065] As an alternative to the examples described above, one can foresee an NVM structure formed of a CBRAM type memory stack, comprising between a lower electrode and an upper electrode, at least one layer of electrolyte.

[0066] One of the electrodes can be, for example, made of Cu or Ag, while the other electrode is made of Pt or TiN or TaN or W. The active material forming the electrolyte can be, for example, a chalcogenide such as GeSe, or GeTe, or GeSbTe or a metal oxide such as HfO2, or Al2O3, or Ta2O5.

[0067] We now refer to the figure 3 which illustrates an example of a possible S-structure from which a device such as previously described can be formed.

[0068] This structure S comprises a substrate 10 on which one or more electronic components, in particular transistors T11, T12, are arranged. The transistors T11, T12 have a channel region arranged in a superficial semiconductor layer 11 of the substrate 10. The substrate 10 can be, for example, a bulk substrate or a semiconductor-on-insulator substrate, and in particular of the SOI type ("Silicon On Insulator").

[0069] The transistors T11 and T12 are covered here with one or more insulating layers 12 and 13 through which one or more through-conductive elements 14, connected to the transistor(s), are provided. Manufacturing steps commonly referred to as "front-end-of-line" (FEOL), where components (transistors, capacitors, resistors) are formed from a semiconducting layer of the substrate, have thus been carried out to create such a device.

[0070] The whole can then be advantageously covered with a part, schematically represented by a block 20 in dashed line, formed of one or more insulating layers and at least one metallic interconnection stage or level formed of vias and horizontal conducting lines in this or these insulating layers.

[0071] A first example of a method for fabricating a microelectronic device as described above will now be given in connection with the figures 4A-4F .

[0072] The structure S described previously serves here in this example as the starting structure for the process.

[0073] First, this structure S is coated with one or more insulating layers, here for example with a stack of an insulating layer 103 in a first material such as for example silicon nitride and another insulating layer 105 in a second material such as for example silicon oxide.

[0074] A first conductive line 111 of an x-1th (with x greater than or equal to 2) interconnection level Mx-1 and a second conductive line 112 of the same metallic interconnection level Mx-1 are then formed. This is typically achieved by creating trenches in the insulating layers 103, 105, which are then filled with at least one conductive material, for example Cu.

[0075] The first conducting line 111 and the second conducting line 112 formed ( figure 4A ) are arranged in the same first plane parallel or substantially parallel to a principal plane of the substrate (i.e., a plane passing through the substrate 10 in the structure S and which is parallel to the plane [O; x; y] of the frame [O; x; y; z] given on the figure 4A ).

[0076] One or more insulating layers are then formed, covering the first conductive line 111, the second conductive line 112, and the insulating layer 105. In the embodiment example illustrated on the figure 4B , a stack formed of an alternation of layers 123a, 123b in a first insulating material such for example silicon nitride and layers 125a, 125b in a second insulating material such as silicon oxide is made.

[0077] In the insulating thickness 123a-125b thus created, at least one trench 134 and at least one hole 136 are then formed in the extension of this trench 134. The trench 134 has a critical dimension (smallest dimension measured parallel to the main plane of the substrate) greater than that of the hole 136. Typically, the trench 134 extends mainly in a horizontal direction, i.e. parallel to the main plane of the substrate, while the hole 136 extends mainly in a direction making a non-zero angle with that of the trench 134 and preferably vertical, i.e. orthogonally to the main plane of the substrate.

[0078] To create trench 134 and hole 136 as an extension of it, different methods can be used.

[0079] One method, commonly called "via-first," involves creating an opening through the entire thickness of the insulation layers 123a-125a to form the hole 136, and then creating the trench 134 in the insulation layers 123b-125b. Another method, commonly called "line-first," involves creating an opening through the upper insulation layers 125b-123b to form the trench 134, and then cutting into the bottom of the trench 134 to create the hole 136 in the insulation layers 123a-125a, extending from this trench 134.

[0080] The etching(s) of the insulating layer 123a-125a to form the hole 136 and the trench 134 are typically made through at least one opening in a masking 148 positioned opposite the first conductive line 111. The masking 148 can be a resin mask, in particular a photosensitive resin mask, or a hard mask, for example, made of amorphous carbon. For example, a dry etching based on CF4 can be implemented.

[0081] Next, trench 134 and hole 136 are filled with at least one conductive material 150, which may be formed from a stack of several metallic layers, for example, a stack of TaN, Ta, and Cu. Such a filling is typically carried out as shown in the figure 4D , after removing the first masking 148, by deposition then CMP planarization (CMP for “Chemical Mechanical Polishing”, i.e. mechanochemical polishing).

[0082] The trench 134 filled with conductive material 150 forms a third horizontal conductive line 163, while the hole 136 filled with conductive material 150 forms a conductive via 161, in other words, a vertical conductive element. The third conductive line 163 thus belongs to an xth level Mx of conductive or metallic lines.

[0083] A hole 176 is then formed in the insulating layer(s) 123a-125a, having a bottom that exposes the first conductive line 111, and a trench 174 is formed in the insulating layer(s) 123b-125b. This can also be achieved using a "line first" or "via first" sequence of steps. The trench 174 has a critical dimension W2 (the smallest dimension measured parallel to the principal plane of the substrate) larger than that W1 of the hole 176 and typically extends mainly in a horizontal direction. The hole 176 typically extends in a vertical direction.

[0084] A memory stack 190 is then formed, comprising at least one lower electrode layer, at least one active material layer, and at least one upper electrode layer, with the active material layer arranged between the lower and upper electrode layers. The stack is arranged to line the lateral walls 174a and the bottom 174b of trench 174 and to line the lateral walls 176a and the bottom 176b of bore 176. In the case of a FeRAM stack, the lower electrode layer can be, for example, wtstone-based, or TiN-based, or formed from a Ti / TiN stack. The upper electrode layer can be, for example, wtstone-based or TiN-based. The active material layer can be a ferroelectric dielectric layer such as, for example, silicon-doped HfO₂ or HfZrO₂.

[0085] According to a specific example of implementation illustrated on the figure 4FTo form the lower electrode, the hole 176 and the trench 174 are first coated with a stack of layers 181, 183, for example, based on Ti and TiN, with a thickness of, for example, between 5 nm and 20 nm. Next, a layer 185 of ferroelectric dielectric, for example based on HfZrO₂, with a thickness that can be, for example, between 5 nm and 15 nm, is deposited. Then, a layer 187, for example based on TiN, with a thickness that can be, for example, between 5 nm and 20 nm, is deposited. Layers 181, 183, 185, 187 can be formed, for example, by an ALD (Atomic Layer Deposition) type deposition process in order to obtain a conformal distribution on the lateral walls of trench 174 and hole 176 as well as at the bottom of hole 176. The filling of trench 174 and hole 176 can then be completed by depositing a metallic material 189, for example such as W. Trench 174 and hole 176 are then preferably completely filled.The central region of the memory structure is thus mainly formed of this metallic material 189.

[0086] In the embodiment example just described, the conductor via 161 and the third conductor line 163 are formed even before the hole 176 and the trench 174 are made in which the stacking of non-volatile NVM memory is planned.

[0087] One alternative embodiment involves simultaneously creating the holes 136 and 176 for the conductor via and the memory stack, respectively. Preferably, the trenches 174 and 184 for the third conductor line 163 and the memory stack, respectively, are also created simultaneously.

[0088] Thus, in the example of implementation illustrated on the figure 5AAfter forming the conductive lines 111, 112 and then covering these lines with insulating layers 123a-125b, the holes 176, 136 and the trenches 174, 134 are formed by a "line first" or "via first" process, by making one or more simultaneous engravings in the insulating layer 123a-125b. The engraving can be carried out through a masking 248.

[0089] Afterwards ( figure 5B ), the holes 136, 176 and trenches 134, 174 are filled by means of at least one conductive material 150, typically deposited concomitantly in the holes 176, 136 and in the trenches 174, 134 and for example formed of a stack of TaN, Ta, and copper.

[0090] Then, a masking 186 is formed opposite the second conductive line 112 and the third conductive line 163. This masking 186, typically in the form of a photosensitive resin or a hard mask, does not extend opposite the first conductive line 111 and thus has an opening opposite the first conductive line 111.

[0091] Next, we perform ( figure 5C ) a removal of the conductive material 150 from the hole 176 and the trench 174 not protected by the masking 186. An etching for example using wet etching, typically using HNO 3 or NH 4 OH can be implemented for this purpose.

[0092] Then, after removing the masking layer 186, for example using a plasma, hole 176 and trench 134 are refilled, this time using a memory stack. A memory stack of layers 181, 183, 185, 187, 189, as described previously, can be used, for example, or a stack as described previously in connection with one or the other of the figures 2A to 2C .

[0093] As an alternative to either of the implementation examples described above, it is possible to form the NVM structure from a structure different from that described in the figure 3 For example, one can start from a structure such as the one illustrated on the figure 4A and in which the conductor lines 111, 112 have already been installed or of such a structure on the figure 4B and in which the conductive lines 111, 112 have already been made and covered with an insulating layer.

[0094] The NVM memory structure, the fabrication of which has just been described, has, due to the configuration of the trench and the hole in which it is formed, a particular characteristic of its upper surface (FS): the area occupied by the upper electrode and the metallic material(s) in contact with this electrode is significantly larger than the area occupied by the active material layer(s) and the lower electrode. This facilitates contact with the upper electrode and prevents short circuits.

[0095] In an alternative design illustrated on the figure 6A , which is not part of the present invention and where a MEM memory stack is formed only in a portion of hole between two portions of conductive vias Vx+1, Vx, there is a risk, contrary to the arrangement proposed for the NVM structure, of creating a short circuit in case of misalignment.

[0096] Similarly, in another alternative design illustrated on the figure 6B (which is not part of the present invention) where a MEM memory stack is formed only in a via hole between two conductive lines 211, 213 of distinct levels, a short circuit is created, contrary to the arrangement proposed for the NVM structure.

[0097] Once the NVM memory structure is formed, further metallic interconnection levels can then be realized on the Mx level in which the third conductive line 163 and the upper part of the NVM structure are located.

[0098] Thus, it is possible to form, in particular, a conductive element or a via conductor 221 on the NVM structure whose implementation has just been described. In the specific implementation example illustrated on the figure 7This conductor 221 makes contact with the enlarged upper portion 192A of the stacked memory structure, and in particular with a layer or the metallic filler material 199 forming the electrode or disposed on the upper electrode of the NVM memory structure. The shape of this upper portion and the configuration of the stacked layers 181, 183, 185, 187, 189 forming the NVM structure prevent any risk of short circuit.

[0099] The conductor via 221 can be arranged at the same Vx level of via as another conductor via 231 making contact on the third conductor line 163 at the Mx level of metallic lines.

[0100] To form these conducting vias 221, 231, one can start from a device such as the one described previously in connection with the figure 4F or the figure 5D, which is coated with one or more insulating layers, for example with a 223a insulating layer of silicon nitride and a 223a insulating layer of silicon oxide.

[0101] Holes are then made in the insulating layers 223a, 223a which are then filled with at least one conductive material.

[0102] Other metallic levels and in particular one or more additional conductive lines on and in contact with the conductive vias 221, 231 (not shown in the figure 7 ) can then possibly be formed.

[0103] In a particular example of implementation illustrated on the figure 8 , an upper portion of the non-volatile structure (NVM) forms a fourth conductive line 194 of the same metallic interconnection level Mx as the third conductive line 163 and extends into another via conductor 191 to contact the first conductive line 111.

[0104] The assembly formed by the fourth conductor line 194 extended by the other via conductor 191 can have, in a transverse cutting plane (plane parallel to the plane [O; x; z] on the figure 8and passing through the fourth conducting line 194 and the other via conductor 191) a profile substantially identical to that of the assembly formed by the third conducting line 163 and the via conductor 161. The NVM structure in the form of a fourth conducting line 194 and the via conductor 191 can thus advantageously present a total cross-section (section taken parallel to the plane [O;x;z]) substantially identical to the cross-section of the third conducting line 163 and the via conductor 161. Here again, the NVM structure can be integrated into a metal level Mx and an inter-level region R12, following drawing rules similar to those adopted to form the conducting lines of the level Mx and vias Vx without having to provide specific dimensions for this structure.

Claims

1. Microelectronic device comprising: - a substrate (10) comprising a plurality of superimposed metal interconnection levels (Mx-1, Mx), - a non-volatile memory (NVM) structure arranged on a first conductive line (111) of a first metal interconnection level (Mx-1), the non-volatile memory (NVM) structure comprising a stack (190, 60) comprising a lower electrode (63, 183) and an upper electrode (67, 67', 187) and at least one active material layer (65, 65', 66, 185) between the lower electrode and the upper electrode, the device further comprising: - a second conductive line (112) of said first metal interconnection level (Mx-1), the second conductive line being distinct from the first conductive line, the first conductive line and the second conductive line being arranged in the same first plane (P1) parallel or substantially parallel to a main plane of the substrate, - a third conductive line (163) belonging to a second upper metal interconnection level (Mx) in relation to said first interconnection level (Mx-1), the third conductive line (163) being arranged in a second plane (P2) parallel to the main plane of the substrate and above the first plane such that the first plane is arranged between the second plane and the main plane of the substrate, the third conductive line (163) being connected to the second conductive line (112) by means of a conductive via (161), the conductive via (161) extending into an intermediate region (R12) located between said first plane (P1) and said second plane (P2), the lower electrode (63, 183), the upper electrode (67, 67', 187) and said at least one active material layer (65, 65', 66, 185) of said stack (190, 60) of the non-volatile memory (NVM) structure extending into the upper metal interconnection level (Mx) and into said intermediate region (R12), the third conductive line (163) and the conductive via (161) passing through an insulating thickness (123a-125b), the insulating thickness extending over the first conductive line (111) and the second conductive line (112), said stack (190, 60) of the non-volatile memory (NVM) being disposed at the bottom of hole (176) on the first conductive line (111), characterized in that said stack lines the side walls as well as a bottom of a trench (174) and of the hole (176) located in the extension of this trench, the hole and the trench being arranged in said insulating thickness (123a-125b).

2. Microelectronic device according to claim 1, further comprising: - a first upper conductive via (221) having a lower end disposed on and in contact with the non-volatile memory (NVM) structure and extending, in an insulating thickness (225a-225b), between this lower end and an upper end, - a second upper conductive via (231) having a lower end disposed on and in contact with the third conductive line (163), and extending in said insulating thickness (225a-225b) between the lower end thereof and an upper end, the first upper conductive via (221) and the second upper conductive via (231) having equal respective heights measured between the lower end thereof on the one hand and the upper end thereof on the other hand.

3. Microelectronic device according to claim 2, wherein said conductive via (161) has a lower end in contact with the second conductive line (112) and an upper end in contact with the third conductive line (163), said conductive via (161) and the third conductive line (163) being arranged in at least one insulating layer (123a-125b), a lower face of the insulating layer (123a-125b) being disposed on and in contact with the first conductive line (111) and with the second conductive line (112), the non-volatile memory (NVM) structure extending entirely in said insulating layer, between the lower face of the insulating layer and a plane passing through both an upper face of the insulating layer opposite the lower face, the lower end of the first upper conductive via (221) and through the lower end of the second upper conductive via (231).

4. Microelectronic device according to one of claims 1 to 3, wherein the non-volatile memory (NVM) structure comprises an upper portion (192B) and a lower portion (192A), the lower portion (192A) extending into said intermediate region (R12) and having a height equal to or substantially equal to the height of said conductive via (161), the upper portion (192B) being arranged in the second plane and having a given cross section, the lower portion (192A) having a cross section different from the given cross section.

5. Microelectronic device according to one of claims 1 to 4, wherein the cumulative height H of the hole (176) and of the trench (174) is substantially equal to the cumulative height hc of the conductive via (161) and of the third conductive line (163).

6. Microelectronic device according to one of claims 4 or 5, wherein said hole (176) is provided with a width W1 and wherein the trench (174) is provided with a width W2 such as W2 > W1, such that the non-volatile memory (NVM) structure comprises a lower portion (192A) and an upper portion (192B) enlarged in relation to the lower portion.

7. Microelectronic device according to one of the preceding claims, the lower electrode (63, 183), the upper electrode (67, 67', 187) and the at least one active material layer (65, 65', 66, 185) of said stack (190, 60) of the non-volatile memory (NVM) structure extend in the form of a fourth conductive line (194) distinct from the third conductive line (163) and belonging to the second metal interconnection level (Mx) and in the form of at least one other conductive via (191) in the extension of the fourth conductive line (194), said other conductive via (191) being provided to make contact on the first conductive line (111).

8. Microelectronic device according to claim 7, wherein the fourth conductive line (194) and said other via (191), have a cross section substantially identical to the cross section of the third conductive line (163) and of said conductive via (161).

9. Microelectronic device according to one of claims 1 to 8, further comprising an additional conductive via (221) arranged on and in contact with an upper portion (192B) of the memory structure.

10. Microelectronic device according to claim 9, wherein the upper electrode layer is provided or coated with an area of conductive material (189) for filling the hole (176) and the trench (174), said additional conductive via (221) being disposed on and in contact with said upper portion (192B) of the memory structure without being disposed in contact with the active material or the lower electrode.

11. Microelectronic device according to one of the preceding claims, wherein the non-volatile memory (NVM) structure is: - of the FeRAM type, the active material being formed of at least one layer of ferroelectric dielectric, or - of the OXRAM type, the active material being formed of at least one dielectric layer, or - of the CBRAM type, the active material being formed of at least one layer forming an electrolyte, or - of the FTJ type, the active material being formed of at least one layer of ferroelectric dielectric in contact with a layer of another dielectric material.

12. Method for manufacturing a microelectronic device according to one of claims 1 to 11, provided with a non-volatile memory (NVM) structure formed of a stack comprising at least one lower electrode and at least one upper electrode and at least one active material between the lower electrode and the upper electrode, the method comprising the following steps of: - providing a substrate (10) coated with at least one insulating layer (103, 105), a first conductive line (111) and a second conductive line (112) of a given interconnection level (Mx-1) extending in the insulating layer and in the same first plane (P1) parallel to a main plane of the substrate (10), - forming an insulating thickness (123a-125b) on the first conductive line (111), the second conductive line (112) and said insulating layer (103, 105), - forming in said insulating thickness (123a-125b), a hole (176) revealing the first conductive line (111) and a trench (174) in the extension of this hole (176), - depositing in the trench (174) and in the hole (176) a stack comprising at least one lower electrode layer (181, 183, 61, 63), at least one active material layer (185, 65, 65', 66) and at least one upper electrode layer (187, 199, 67, 69), said stack lining the side walls (174a, 176a) and a bottom (176b, 174b) of the hole (176) and of the trench (174).

13. Method according to claim 12, further comprising forming in said insulating thickness (123a-125b) a conductive via (161) in contact with the second conductive line (112) and a third conductive line (163) on said conductive via (161).

14. Method according to claim 13, wherein producing the conductive via (161) and the third conductive line (163) comprises steps of: - producing a first masking (148) facing the first conductive line (111) and comprising at least one opening facing the second conductive line (112), - etching through said opening of the first masking (148) another trench (134) and another hole (136) in the extension of said other trench (134) and having a bottom revealing the second conductive line (112), - filling the other trench (134) and the other hole (136) using at least one conductive material (150), - removing said first masking (148) and forming a second masking (186) comprising at least one opening facing the first conductive line (111), etching the insulating thickness (123a-125b) through said opening of said second masking (186) to form said trench (174) and said hole (176).

15. Method according to claim 13, wherein producing the conductive via (161) and the third conductive line (163) comprises forming another trench (134) and another hole (136) in the extension of said other trench (134), said other hole (136) having a bottom revealing the second conductive line (112), said hole (176) revealing the first conductive line (111) and said other hole (136) revealing the second conductive line (112) being formed concomitantly.

16. Method according to claim 15, wherein said trench (174), said other trench (134), said hole (176) and said other hole (136) are formed by etching the insulating thickness (123a-125b) through several openings of a first masking (248), the method comprising steps of: - filling said trench (174), said other trench (134), said hole (176) and said other hole (136) using at least one conductive material (150), - removing said first masking (248) and forming a second masking (186) facing the second conductive line (112) and the third conductive line (163), the second masking (186) comprising at least one opening facing the first conductive line (111), - removing said conductive material (150) from said trench (174) and from said hole (176) by etching through the opening of said second masking (186), so as to again release said trench (174) and said hole (176), - forming said stack in said trench (176) and said hole (174).

17. Method according to one of claims 12 to 16, the deposition of the stack (190) being a compliant deposition performed in particular by ALD.

18. Method according to one of claims 12 to 17, wherein said at least one active material layer (185, 65, 65', 66) is formed: - of a ferroelectric dielectric, in particular an oxide such as Si-doped HfO2 or HfZrO2, or - of a dielectric oxide such as HfO2, or - of a metal oxide such as HfO2 or Al2O3 or Ta2O5 or of a chalcogenide such as GeSe or GeTe or GeSbTe, or - of a stack of a ferroelectric dielectric and of another dielectric.

19. Method according to claim 18, wherein the lower electrode and the upper electrode are formed: - of a layer made of a first material selected from one or more of the following materials: Ti, TiN, W, and / or - of a layer made of a metal material selected from one or more of the following materials: W, Cu, Al, AlCu, AlSi.

20. Manufacturing method according to one of claims 12 to 19, wherein the deposition in the trench (174) and in the hole (176) of said stack is followed by filling the trench (174) and the hole (176) by depositing a metal material (189), so as to fill the hole (176) and the trench (174).