Display device for processing a dual input signal

Abstract

The invention relates to an electroluminescent visual display unit (1) comprising: a matrix of electroluminescent pixels (38) formed from a plurality of pixels arranged on a substrate, in a matrix arrangement in lines and columns, each pixel being formed by at least one elementary emitting zone (225, 325, 425); a first control block (2) designed to control a graphic and / or alphanumeric data stream that can be displayed on said matrix of pixels (38); a second control block (3) designed to control a video data stream that can be displayed on said matrix of pixels (38); and a unit (4) for generating a reference voltage, said device being characterised in that: each elementary emitting zone is connected to a static memory, addressed by said first control block (2), and to a dynamic memory, addressed by said second control block (3); said first (2) and second (3) control blocks being designed to be able to display data alternately or simultaneously on the same matrix of pixels (38).

Description

Technical field of the invention

[0001] The invention falls within the field of electronics, and more specifically within that of matrix display devices. It concerns a matrix display of the LED, OLED, or any other type. This matrix display allows for the dynamic or static display of images; to enable this dual display, it incorporates a novel architecture for each sub-pixel. State of the art

[0002] We know of matrix display systems which implement a different architecture on each sub-pixel depending on the type of static or dynamic display desired on the interface.

[0003] The publication "Ultra High Resolution AMOLED" by Wacyk et al., published in Proc. SPIE 8042, Display Technologies and Applications for Defense, Security, and Avionics V; and Enhanced and Synthetic Vision 2011, 80420B (doi: 10.1117112.886520), describes an active matrix circuit with an analog memory architecture. This type of circuit is well-suited for displaying video image sources, as these circuits require periodic addressing, on the order of 25 Hz to 125 Hz, to avoid data loss. However, in this circuit, static display results in excessive power consumption because its architecture is designed for dynamic display.

[0004] On the other hand, the publication "Ultra-low Power OLED Microdisplay for Extended Battery Life" by Uwe Vogel et al., published in SID 2017 Digest, pp. 1125-1128, describes a memory cell matrix circuit of the SRAM (Static Random Access Memory) type. In this circuit, the image is stored in a memory matrix, and the state of this matrix only changes when the data to be displayed changes. This type of circuit does not require periodic refresh; it is a static display that is well-suited to graphic displays. Its main advantages are low power consumption for static images or images with a low change rate, as well as the ability to address the matrix directly from a microcontroller without going through a video controller.

[0005] WO 2014 / 108741 describes a method for superimposing static and dynamic modes, enabling the display of either a dynamic or static source on the same display. The device includes a data processing unit that adapts the signals for display on the display matrix. This data post-processing allows for superimposition, but it relies on a dynamic display; consequently, the device's power consumption remains significant. Another device for superimposing images is described in US 2002 / 0093472.

[0006] In light of the foregoing, one objective of the present invention is to remedy, at least partially, the drawbacks of the prior art mentioned above by providing a display with very low power consumption, similar to that used in static mode, but which also allows for high-quality dynamic display (video mode). This display should also allow for the simple overlaying of graphic images onto video images. Object of the invention

[0007] An obvious solution for enabling the overlay of graphic images onto video images would be to use a screen with an SRAM matrix circuit and optimize the memory levels and addressing speed to display video-quality images with a suitable refresh rate. However, this solution faces several difficulties. In particular, displaying a good-quality video image requires at least eight-bit, or even ten-bit, encoding per subpixel. However, with currently available CMOS technologies (200 mm silicon wafer, with a resolution of 130 nm), this leads to excessively large pixel sizes. For example, a subpixel as described in the article by Vogel et al., cited above, with only four bit levels measures 12 µm x 12 µm, while AMOLED screens as described in the publication by Wacyk et al., cited above, now have sub-pixels with a size of around 4 µm x 4 µm.

[0008] According to the invention, the problem is solved by using an array of elementary electroluminescent emitting areas which has two addressing modes: a first mode (called "video mode") using a video type interface, preferably standardized, which allows the display of good quality video images (with typically eight to ten bits of grey levels and a good refresh rate (also called refresh rate), typically between 30 Hz and 120 Hz, preferably between 60 Hz and 120 Hz), but which does not need to keep the image in permanent memory, and a second mode (called "graphics mode") using a data type interface, preferably standardized (for example of the SPI type) which keeps the image in memory, knowing that this graphics mode only requires a small number of grey levels (for example one or two bits per subpixel).Note that the expression "grey level" here refers to a level of emission intensity by an elementary electroluminescent emitting area, regardless of the colour of that emission.

[0009] Each elementary light-emitting zone can be a sub-pixel or a pixel. Each elementary light-emitting zone has two independent memories: a static memory, of the SRAM type, intended for graphic data, and an analog, dynamic memory, intended for data from the video stream; said dynamic memory can be a capacitor.

[0010] For video mode the data is synchronous data, refreshed (updated) periodically, this refresh being typically controlled by a clock.

[0011] In graphics mode, the image can be static and reprogrammed (i.e., updated) as needed (meaning each elementary transmitting area can be refreshed by sending new data only when the contents of its static memory change as a result of this new data being recorded in said static memory), or refreshed periodically. In the first case, the data is asynchronous and does not depend on a clock; in the second case, it can be synchronous.

[0012] When the graphic image is refreshed periodically, the image refresh rate can be low, even below 0.1 Hz (or even 0 Hz); advantageously, it is in the range of 0.1 Hz to 1 Hz, but can reach a frequency greater than 10 Hz. During the refresh of graphic data, updated data is recorded in all static memories simultaneously, although for some elementary transmitting areas, this updated data is identical to the previous data, which is replaced by the newly recorded data. The refresh rate can be fixed or variable. The refresh rate of the graphic data is independent of that of the video data; it is advantageously lower, but can also be higher.

[0013] The object of the invention is an electroluminescent display device (1) comprising: an electroluminescent pixel matrix (38) formed of a plurality of pixels deposited on a substrate, in a matrix arrangement of rows and columns, each pixel being formed of at least one elementary emitting area, each elementary emitting area being connected to two independent memories, namely to a static memory of the SRAM type, and to a dynamic memory; a first control block (2) configured to control a stream of asynchronous graphic and / or alphanumeric data to be displayed on said pixel matrix (38), said asynchronous data not depending on a clock; a second control block (3) controlled by a clock and configured to control a stream of video data to be displayed on said pixel matrix (38), said video data being synchronous data, said video data stream being refreshed periodically, this refresh being controlled by a clock;a unit (4) for generating a reference voltage, said matrix (38) having two addressing modes, namely: a first mode, called "video mode", using a video-type interface for displaying video images but which does not store the image in permanent memory, and a second mode, called "graphics mode", using a data-type interface which stores the image in memory; said static memory being addressed by said first control block (2), and said dynamic memory is addressed by said second control block (3); said first (2) and second (3) control blocks being configured to be able to alternately display data on the same pixel matrix (38); said first control block (2) being configured to allow the image to be updated by sending new data only when the content of said static memory changes following the recording of new data in said static memory.

[0014] The said first and second control blocks are configured to be able to display on the pixel matrix only the video data stream, or only the graphic and / or alphanumeric data stream.

[0015] The said first control block is configured to send images to the static pixel memory matrix, for example via a first system of "select" rows and "data" columns.

[0016] The first control block may include a clock or be controlled by a clock. The second control block is configured to send: a video data stream to a horizontal shift register that controls the addressing system of the columns provided for this purpose in the electroluminescent pixel matrix, a control signal to a line driver element that controls the addressing system of the lines provided for this purpose in the electroluminescent pixel matrix, for displaying said video data stream on said matrix of electroluminescent pixels. The second control block must include a clock or be controlled by a clock, the video data stream being a synchronous data stream.

[0017] According to the invention, each elementary emitting zone comprises a dynamic memory, preferably a capacity, for video data. Each elementary emitting zone is connected to at least one, and preferably several (for example two or three), static SRAM type memories, intended for static display or display with a lower refresh rate and / or with a lower number of intensity levels; this data may be graphic and / or alphanumeric data, static images, or video data with a lower temporal and / or visual resolution than the video data passing through the dynamic memory.

[0018] In a preferred device of the invention, the first and second control blocks are configured such that the first control block has fewer emission intensity level bits than the second control block. Advantageously, the first control block is configured with three to eight emission intensity level bits, and / or the second control block is configured with at least eight emission intensity level bits; for example, the second control block can be configured with ten, twelve, or even fourteen emission level bits. Advantageously, the second control block has a higher refresh rate than the first control block.This refresh rate is preferably at least 25 Hz, more preferably at least 30 Hz, even more preferably at least 60 Hz, and optimally at least 90 Hz, and / or said second control unit includes a memory unit for storing said graphic and / or alphanumeric data for static display. Description of the figures

[0019] The invention will be described below, with reference to the accompanying drawings, given solely by way of non-limiting examples, in which: There figure 1 This is an overview of the display element's architecture, illustrating an installation that allows the display of a video stream and / or graphic data. figure 2a This is an overview of the display element's architecture, illustrating an installation that allows the display of a video stream. figure 2bThis is an overview of the display element's architecture, illustrating a setup for displaying graphical data. figure 3 is a representation of the electrical diagram of a sub-pixel for the first embodiment. figure 4 is a representation of the electrical diagram of a sub-pixel for the second embodiment. figure 5 is a representation of the electrical diagram of a sub-pixel for the third embodiment. figure 6 is a timing diagram of transmission duration control signals applied to inputs S1 to S4 of the pixel circuits. figure 7 is a representation of the electrical diagram of a sub-pixel showing a variant implementation.

[0020] The following numerical references are used in this description 1 Installation according to the invention 2 First control block 3 Second control block (video stream management) 4 Reference voltage generation unit 31 Video stream 32 Control signal 33 Sequencer 34 horizontal shift register 35 Digital comparator 36 Sampling and maintenance circuit 37 vertical shift register 38 Pixel matrix 41 Meter module 42 Cross-reference table 43 Power source 44 Reference voltage generator 45 Signal from 41 47 Reference voltage output of 44 121 Serial data bus 122 Decoder module 123 Signal processor 131 Data signal 132 Horizontal Addressing Table 133 horizontal addressing signal 134 Vertical addressing signal 137 Vertical Addressing Table 145 PWM signal generator 146 Control signals 147 Reference voltages 200 Electrical circuit of a sub-pixel 205 Transistor 210 Capacitor 215, 220 Transistor 235,240, 245,250 Transistor 270 Dynamic section of circuit 200 255,260 Static memory (SRAM) 280 Static section of circuit 200 300 Installation according to the invention 290 Sub-pixel 310 Capacitor 305 Transistor 325 OLED element 315,320 Transistor 355, 360 Static memory (SRAM cell or register) 345,350 Transistor 370 Dynamic section of the 300 circuit 380 Static section of circuit 300 390 Sub-pixel 400 Installation according to the invention 405,415 Transistors 410 Capacitor 420,435 Transistor 425 OLED element Transistor 470 Dynamic section of the 400 circuit 440,445, 450,455, 460 480 Static section of the 400 circuit 441,446, 451,456 Static memory (SRAM) 490 Sub-pixel 500 Installation according to the invention 505 Static memory (SRAM) Detailed description

[0021] There figure 1 It involves two different display modes which are implemented on a single matrix of elementary electroluminescent emitting zones, which bears the reference 38 on the figure 1This may include, in particular, an OLED pixel matrix, and the present description refers to this case, although the present invention also applies to an electroluminescent pixel matrix using inorganic semiconductors or light-emitting diodes (LEDs). For a pixel matrix of a monochrome electroluminescent display, each elementary emitting area generally corresponds to a pixel; for a color display, each pixel is broken down into several individually addressed sub-pixels, and these sub-pixels then correspond to the elementary emitting areas.

[0022] There figure 1 describes a general overview of the architecture of a facility 1According to the invention, which has two separate image paths, namely a video path (with an incoming stream of digital data) and a graphics path (with an incoming stream of digital data). These two paths are connected within the pixel only; each video and graphics path has its own addressing system and separate wiring at the elementary emitting area. This architecture is designed to drive each elementary emitting area (i.e., each OLED sub-pixel) with constant current, but it can also be applied to voltage control, with minor modifications (not shown in the figures).In the video channel, for each elementary transmitting zone, the incoming digital video signal is converted into an analog signal corresponding to the gray levels by a system that includes a counter, a current source, a reference voltage generator, and optionally a correction table, along with comparators at the column level. The resulting analog video signal is temporarily stored in a dynamic memory associated with the elementary transmitting zone. The graphics data channel addresses a direct-access digital RAM matrix of the SRAM type via a write (and optionally also read) procedure for this type of memory.

[0023] More specifically, the device's video block includes a counter (for example, eight bits) and a comparator at the end of each column that compares the counter values ​​with the video data. Simultaneously, the counter feeds a system of weighted current sources (i.e., a reference voltage generator). When the counter and video data values ​​are equal, the reference voltage from the generator is first transferred to the column's buffer, and then, during the next cycle, to the elementary transmitting area via the column. Between the counter and the reference voltage generator, there may be a conversion table to apply a non-linear correction (gamma factor); in this case, a higher number of bits in the reference voltage generator may be beneficial.

[0024] The reference voltage generator generates a voltage which introduces into the elementary emitting area a current proportional to the value applied to the input.

[0025] There figure 2a shows the video path circuit enabling the display of a video stream 31 on the matrix of electroluminescent pixels 38. This figure shows a first block called the control block 2 which will not be used in this display mode and whose operation will be explained below in relation to the second display mode. It is a second block 3 which allows for the management of the video stream 31 until it is displayed on the pixel matrix 38. The said video stream 31, which is a stream of digital data, is sent to a horizontal shift register demultiplexer 34 then to a digital comparator 35(which generates an analog data stream) then to a sampling and hold circuit 36 and finally towards the vertical gates of the pixel matrix 38. In this second block 3, a control signal 32 is sent to a sequencer 33 which allows power to be supplied to a line control element 37 (typically a vertical shift register or a demultiplexer) which gives commands on the horizontal lines of the pixel matrix 38.

[0026] A reference voltage generation unit 4 generates the reference voltage. It includes an eight-bit counter module 41 which sends a signal 45 to a correspondence table 42 (known as a "LUT" for "Look-Up Table"), optional but recommended, which allows for non-linear encoding. The value comes from the look-up table. 42is transmitted to a reference voltage generator 44 coded on ten bits. The latter includes another input allowing a current source to be supplied 43 weighted on ten bits. The output reference voltage 47 of the voltage generator 44 powers the sampling and maintenance circuit 36 of the second control block 3.

[0027] The functioning linked to the figure 1 is based on a video data stream 31 digital technology that is transformed by a set of digital comparators 35, counter 41, correspondence table 42 (optional) and reference voltage generator 44 into an analog signal at the end of each column and transmitted to the pixel matrix 38. This type of stream requires rapid processing for instant display. The video stream 31 is broken down by the demultiplexer 34to address each pixel of the pixel matrix 38 The information to be displayed. The sequencer 33 transmits to the vertical shift register 37 the order to display information on each pixel. This order is based on a control signal 32 which could be of the type: Pixel Clock (PCLK): The pixel clock changes on each pixel. Horizontal Synchronization (HSYNC): This is a special signal that indicates that a line of the frame has been transmitted. Vertical Synchronization (VSYNC): This signal is transmitted after the entire frame has been transferred. This signal is often used to indicate that an entire frame has been transmitted.

[0028] There figure 2b is a general view of the architecture illustrating an installation 1 enabling the display of graphical data on said matrix of electroluminescent pixels 38. This architecture includes a first control block 2,mentioned above, which includes a serial data bus 121 transmitted to a module 122 capable of decoding signals and sending them to a signal processor 123 allowing the signals to be decoded and sent to the static memories of the pixel matrix 38, in a manner known and used in memory circuits. Said signal processor 137 is a control unit that generates the row and column signals for the first control block 2. This could be a signal generator, a microcontroller, or, for more complex systems, a microprocessor.

[0029] We describe here, for a particular embodiment, the display of said data 131 graphical and / or alphanumeric characters on the electroluminescent pixel matrix 38. The first control block 2 sends the data signal 131graphical and / or alphanumeric characters to the addressing table 132 of the second control block 3. The addressing table 132 is a horizontal addressing array that controls the addressing of the columns of the matrix of electroluminescent pixels 38 ; it also receives the horizontal addressing signal 133. The second control block 3 also includes a line control element 137 (vertical addressing table) which receives the vertical addressing signal 134 which controls the addressing of the electroluminescent display lines 38. The pixel matrix 38 also receives a reference voltage from unit 4 said unit for generating the reference voltage. This last unit 4 includes a reference voltage generator 44, a power source module 43and, optionally, a pulse width modulation (PWM) type signal generator. 145.

[0030] The functioning linked to the figure 2b results from digital processing in a slow display process that uses SRAM memory at the pixel level. The information is broken down in the first control block. 2, all the information, data 131 and addressing 133,134, allows the display of graphical data on the pixel matrix 38. Reference voltages 147 (here Vref, Vref1 and Vref2) are generated by a reference voltage generator 44. They define the current or output voltage value of the transistors whose gate they drive, and therefore the current or voltage on the pixel matrix. 38.The reference voltages are therefore common to the matrix of light-emitting pixels and provide continuous signals to define gray levels. Specifically, these voltages allow each pixel to maintain power and compare its values ​​to those stored in memory. figures 1, 2a And 2b These correspond to implementation methods for dynamic or static display, distinguished by their data flow management and the refresh rate of the information displayed on the pixel matrix. The device architecture according to the invention combines these two functions on the same pixel matrix. 38.

[0031] The pixel matrix architecture 38comprises a plurality of pixels aligned horizontally and vertically. In this embodiment, each pixel comprises four sub-pixels as elementary emitting areas; these sub-pixels may be primarily red, green, and blue, while the fourth sub-pixel may be a complement in white or any other color. It is obviously possible to provide only three sub-pixels per pixel, or alternatively, each pixel may be formed from a single elementary emitting area.

[0032] As mentioned above, each elementary light-emitting zone has two independent memories: a static memory, intended for graphic data, and a dynamic memory, intended for data from the video stream. figures 3 , 4 , 5 And 7show circuit embodiments at the level of an elementary electroluminescent emitting zone, the structure and operation of which, in particular in relation to static or dynamic type memory units, will be explained in greater detail below.

[0033] There figure 3 shows the electrical diagram 200 of a single elementary emitting zone 290 (which can be a sub-pixel) according to a first embodiment. The circuit comprises three parts, one for the dynamic part 270, another one for the static part 280, and the display on the sub-pixel 290.

[0034] The dynamic part 270 the circuit includes the arrival of the analog video stream 31 and a selection voltage 47 sequencer output 33 on the gate of a transistor SW1 205. The cathode of the transistor 205 powers a capacitor 210as well as the gate of a T ANA1 transistor 215. The anode of the T ANA1 transistor 215 is connected to a voltage V ANA. The cathode of transistor T ANA1 215 is linked to the sub-pixel 290 display. This sub-pixel consists of a SW2 transistor 220 connected to an OLED element 225. The SW2 transistor 220 This is also optional and allows, for example, the modulation of the OLED element's emission. 225.

[0035] The static part 280 of the circuit (circled on the figure 3 (of a dotted line), intended for displaying graphical data, consists of a T ANA2 transistor 235 in series with a SW3 transistor 245 in parallel with a T ANA3 transistor 240 the latter in series with a SW4 transistor 250. The anodes of T ANA2 235 and T ANA3 240 are connected to the anode of T ANA1 215 and the cathodes of SW3 245 and SW4250 are connected to the cathode of SW2 220 or T ANA1 215 (when SW2 is optional). Each of the T ANA2 grids 235 and T ANA3 240 is connected to the reference voltage Vref 147. Each of the gates of the two SW3 transistors 245 and SW4 250 is controlled by an SRAM cell type memory function 255,260. The memory cell is typically of the six-transistor type. In the diagram, only the BL ("Bit line") and WL ("word line") inputs are shown, which are respectively powered by the line addressing signal. 134 (vertical addressing signal) and the data line 131,are used. Memory programming is done by establishing a digital signal, '0' or '1', on the BL column and its opposite digital signal, '1' or '0', on the BLB (Bit Line Bar) column of each SRAM cell. Then, a pulsed signal, generally positive, on the WL (Word Line) signal records the BL and BLB signals in the memory of the SRAM cell.

[0036] The circuit according to the figure 3 It can be used in three different ways. The first use is video mode, which mainly involves the dynamic part 270, That is, memory is set to level 0 everywhere in the matrix, and data is transmitted only through the video interface; in other words, the pixel is controlled solely by the video data path. A video stream 31 powers the anode of SW1 205. The transistor only becomes conductive when the V select voltage allows it to illuminate the display sub-pixel.290. The CS capacitor 210 allows limiting the overload and maintaining voltage for a period of time on the power supply to the terminals of T ANA1 215 ; Thus, it acts as dynamic memory. This will only be the case when this capacitor 210 can be functionally substituted by the gate capacitance of the T ANA1 transistor 215, particularly when the video stream refresh rate is sufficiently high. The static part 280 Since it is not powered in this video operating mode, no current flows in this part.

[0037] The second use is the graphical mode, which mainly involves the static part 280. The memory function of SRAM cells 245,250 allows the SW3 transistors to remain open or closed 245 and SW4 250. SW3 Controlled Openings 245 and SW4 250allow the passage of the reference voltage V ref 147 up to the OLED element 225. The assembly of T ANA2 235 and T ANA3 240 In parallel with the two-bit analog-to-digital converter function, the converter offers four possible modes: Mode 00 When the two transistors SW3 245 and SW4 250 are not conducting, the current flowing through the circuit is zero, as mentioned earlier in the pure dynamic mode. Mode 01 : the SW4 transistor 250 is conducting, the relative current is sent to the sub-pixel display device 290. Mode 10 : the SW3 transistor 245 is conducting, the relative current is sent to the sub-pixel display device 290. Mode 11 : SW3 transistors 245 and SW4 250 are conducting, the relative current is sent to the sub-pixel display device 290.

[0038] The third use, according to an unclaimed example, is a mixed mode known as superposition: a video signal is applied simultaneously via the dynamic path. 270 and a graphic signal from the static part 280. The current in the OLED therefore corresponds to the superposition of the two signals; the display of the sub-pixel 290 is controlled by the converter formed by T ANA2 235 in series with SW3 245 and T ANA3 240 in series with SW4 250 as well as T ANA1 215.

[0039] The diagram shown on the figure 3 proposes an advantageous implementation of a four-level (two-bit) display for the graphics portion using two SRAM memory cells 255,260 ; it may include additional memory cells (for example 3, 4 or 5 SRAM cells) which will increase the capacity of the analog-to-digital converter in terms of the number of bits and therefore possible modes.

[0040] The architecture shown above is designed to power the OLED 225 in constant current, however it can also be applied to a voltage supply with minor modifications.

[0041] There figure 4 describes a second embodiment 300 of the arrangement at the level of one of the sub-pixels. The circuit comprises three parts, the first for the dynamic part 370, a second one for the static part 380, and a third for display on the sub-pixel 390. The dynamic part 370 includes the arrival of the analog video signal 31 on the anode and a line selection voltage 47 on the gate of a transistor SW1 305. The cathode of the transistor 305 powers a capacitor 310 (acting as dynamic memory) as well as the gate of another T ANA transistor 315. The anode of the T ANA1 transistor 315is connected to a voltage Vana. The cathode of transistor TANA1 315 is linked to the sub-pixel display 390. The latter includes a SW2 transistor 320 (optional) connected to an assembly including the OLED element 325.

[0042] The static part 380 (circled on the figure 4 (of a dotted line) consists of two SW3 transistors 345 and SW4 350 which are connected by their cathode to that of transistor SW1 305. The anode of these two transistors is each connected to a reference voltage. 147 Vref1 and Vref2. Each of the gates of the two transistors SW3 and SW4 is controlled by an SRAM cell-type memory function. 355,360. The memory cell is of the 6-transistor or more type. On the figures 3 , 4 , 5 And 7 The BL ("Bit Line") and WL ("Word Line") inputs are respectively supplied by the line address134 and the data line 131.

[0043] The output of an SRAM cell 355,360 allows the respective transistors to conduct 345 And 350, A predetermined reference voltage (Vref) is applied to the gate of the transistor T ANA 315 which is the current source for the OLED; no specific current sources are needed, but one SRAM cell per level is required (not per bit as in the first embodiment). This is shown in the following table for the case of four current sources: the reference voltages Vref1 and Vref2, when the SW3 transistors 345 and SW4 350 are passing through, they end up on the T ANA transistor: level SRAM1 SRAM2 SRAM3 SRAM4 V gate (T ANA) 0 0 0 0 0 Video data 1 1 0 0 0 V Ref1 2 0 1 0 0 V Ref2 3 0 0 1 0 V Ref3 4 0 0 0 1 VR ef 4

[0044] The circuit according to the figure 4can be used in three different ways. According to the first mode of use, only the dynamic part 370 The circuit is used. A video stream 31 powers the anode of SW1 305. The transistor only conducts when the V select voltage allows it to power on the display section. 390. The CS capacitor 310 allows the voltage to be maintained for a period of time on the power supply of the T ANA1 grid 315. The static part 380 Since it is not powered, no voltage flows through this part. According to a second operating mode, only the static part 380 The circuit is used. The memory function of the SRAM cells 345,350 allows the SW3 transistors to remain open or closed 345 and SW4 350.

[0045] Depending on the number of memory cells present in the circuit, the display part 390reacts to the different tensions applied to T ANA 315, as shown for example in the table above.

[0046] In this operating mode, the gate voltage state of the T ANA transistor is not necessarily known and may be in a high-impedance state, in which case the transistor remains off. To overcome this problem, the applicant proposes using a V-select voltage to initialize the T ANA transistor. For this purpose, in the case of graphic mode only, the V-select voltage is not controlled by the sequencer. 33 but originates from the reference voltage generation unit 4.

[0047] The V select voltage signal allows the T ANA transistor to be reset before each write operation to the memory cells.

[0048] The third mode of use, which corresponds to an unclaimed example, is a mixed mode known as superposition, which involves both the static part 280 and the dynamic part 270 of the circuit. The sub-pixel display 290 is controlled by the converter formed by T ANA 315. In this case, the display section 390 allows the video signal to pass through at the same time 31 and the data stream from the different memory cells 355,360.

[0049] As mentioned above, this describes circuits in which the display of sub-pixels 290 is controlled by current, but the circuits can be controlled by voltage with minor modifications.

[0050] There figure 5 describes the third embodiment 400of the circuit layout at the level of one of the sub-pixels, for a specific case with four bits of gray levels. The circuit comprises three parts, a first part 470 for dynamic display, a second part 480 one for static display, and a third for sub-pixel display 490. The dynamic part 470 includes the arrival of the analog video signal 31 on the anode of a SW2 transistor 405 and a line selection voltage 47 on the gate of transistor SW2 405. The cathode of the transistor 405 powers a capacitor 410 (acting as dynamic memory) as well as the gate of a T ANA transistor 415. The anode of the T ANA transistor 415 is connected to a voltage V ANA. The cathode of the transistor T ANA 415 is linked to the sub-pixel display 490. The latter consists of a SW2 transistor 420connected to the OLED element 425. The static part 480 (circled on the figure 5 (of a dotted line) consists of a transistor SW1 435 which is connected by its cathode to the grid of the T ANA transistor 415. The anode of transistor SW1 435 is connected to a reference voltage Vref 147. The cathode of transistor SW1 435 is controlled by five signals from the transistor anode 440, 445, 450, 455, 460 arranged in parallel.

[0051] In this embodiment, and by way of example comprising four bits of gray levels, the four control signals 146, S1, S2, S3, S4 control the gates of the four transistors 440, 445, 450, 455 which allow the transmission of data from the memory cells 441, 446, 451, 456 respectively arranged on their anode towards the SW1 grid 435. The fifth transistor 460 is connected by its cathode to the anode of SW1 435and includes an analog power supply (V ANA) on its anode and a reset signal (V reset) on its gate. The memory cell can be of the six-transistor or more type. The sub-pixel 425 of the display section 480 operates at a single luminance level, therefore the grey levels are achieved by controlling the emission time of the latter.

[0052] The circuit according to the figure 5 can be used in three different ways. According to the first mode of use, only the dynamic part 470 The circuit is used. A video stream 31 powers the SW2 anode 405. The transistor only becomes conductive when the V select voltage (from the module) 33 ) allows it to turn on the display part 490. The CS capacitor 410 allows the voltage to be maintained for a period of time on the power supply at the T ANA terminal 415. The static part 480transmits signals S1, S2, S3, and S4 with a logic level of 1, and the level of the memory cells then has no effect on the voltage of the sampling capacitance of capacitor CS 410 and therefore on the video signal 31.

[0053] According to a second mode of use, only the static part 480 The circuit is used. Writing to the memory cells 441, 446, 451, 456 is done completely randomly. In order to avoid any visible flickering effect on the display 490,The signal refresh rate must be greater than 85 Hz or less than 12 ms. It is preferable to use an even higher frequency, around 120 Hz, to limit interference with the write and write times of the memory cells. In this operating mode, the gate voltage state of the T ANA transistor is not necessarily known and may be in a high-impedance state, in which case the transistor remains off. To overcome this problem, the applicant proposes using a V-select voltage to initialize the T ANA transistor. For this purpose, in the case of graphics mode only, the V-select voltage is not controlled by the sequencer. 33 but comes from the generator 44 reference voltage 147.

[0054] The V select voltage signal allows the T ANA transistor to be reset before each write operation to the memory cells.

[0055] The third mode of use, which corresponds to an unclaimed example, is a mixed mode known as superposition, which involves both the static part 480 and the dynamic part 470 of the circuit. The dynamic part 270 sends the video signal 31 on CS sampling capacity 410. The voltage level on the capacitor can be forced by the data coming from the memory cells. 441, 446, 451, 456 which will force the display of the static part 480 on the video stream 31 of the dynamic part 470. The V select voltage reflects the characteristics of the sequencer signal. 33 through the vertical shift register 37.

[0056] There figure 6 describes a timing diagram of control signals 146The transmission duration applied to inputs S1 to S4 of the pixel circuits blocks the T ANA transistor between two conductions. This timing diagram is presented as an example. It includes four grayscale bits modulated by the four control signals. 146, S1, S2, S3, S4. The timing diagram describes the control signals S1, S2, S3, and S4 per gray level bit. The emission time generated by S1 corresponds to the first gray level, S2 to the second gray level bit, and so on up to S4. Maximum luminance is reached when S1, S2, S3, and S4 are all at 1. A way to vary the luminance via the T / Td ratio can be added; the gray levels remain at 1. The control signals 146 which control S1, S2, S3, S4 are generated by the reference voltage generation unit 4 and more specifically by the pulse width modulation (PWM) signal generator 145.

[0057] There figure 6It also presents the V select voltage signal. This modulated signal allows the T ANA gate to be reset before each write operation to the memory cells. This signal applies to the last two embodiments.

[0058] The diagram shown offers an advantageous embodiment; however, it can be composed of additional memory cells to increase the number of grey levels.

[0059] There figure 7 presents a variant 500of the first embodiment, but adaptable to all three embodiments. This variant consists of adding a 505 memory cell connected to the SW2 gate in each embodiment. Regardless of the OLED's biasing mode (voltage or current) and regardless of the embodiment using SRAM memory, this memory cell allows the pixel's video data to be switched off, leaving only the graphics channel on the pixel. This modification simplifies the implementation of the overlay mode.

[0060] All embodiments rely on reference voltages or currents. 47 which are ideally generated by the reference voltage generation unit 4.It is possible to generate these reference currents or voltages locally via the power supply voltages or analog-to-digital converters. This approach requires integrating electrical components into each sub-pixel group to construct these reference voltages.

[0061] All embodiments use current-driven OLEDs. For voltage-driven OLEDs, all PMOS transistors shown must be replaced with NMOS transistors.

[0062] The V ANA voltage is typically in the range of 1.0 V to 3.3 V (e.g. 1.8 Volt), the V cath voltage is typically in the range of -2 V to -9 V (e.g. -8 Volt).

[0063] When the screen is configured according to an unclaimed example to display graphics data simultaneously with video data, the graphics data may have either priority (in the embodiment shown on the figure 4) or overlap (in the embodiments shown on the figures 3 , 5 And 7 ) ; in this latter case the currents in the OLED diode add up.

[0064] More specifically, in the embodiment described in relation to the figure 4 During pixel writing by the V select signal, the reference voltages Vref1 and VRef2 connected to the graphics data by transistors SW3 and SW4 balance with the voltage 305 controlled by the block 36. After writing, transistor SW1 is open, and therefore the graphic value is written to capacitor CS, thus taking priority over the video signal. Consequently, in this operating mode, the voltages Vref1 and Vref2 are likely to vary, which can, in some cases, have a visible effect on the graphic display. This effect can be minimized if the block impedance is low. 37 is significantly lower than that of the block 36,because in this case, control by the Vref and VRef2 voltages takes precedence over control by the video voltages 305.

Claims

1. Electroluminescent display device (1) comprising - a matrix of electroluminescent pixels (38) formed of a plurality of pixels deposited on a substrate, in a matrix arrangement in rows and columns, each pixel being formed of at least one elementary emitting zone, each elementary emitting zone being connected to two independent memories, namely to a static memory of the SRAM type, and to a dynamic memory; - a first control block (2) configured to control a flow of asynchronous graphic and / or alphanumeric data to be displayed on said matrix of pixels (38), said asynchronous data not depending on a clock; - a second control block (3) controlled by a clock and configured to control a flow of video data to be displayed on said matrix of pixels (38), said video data being synchronous data, said flow of video data being refreshed periodically, this refresh being controlled by a clock; - a unit (4) for generating a reference voltage, - said matrix (38) having two addressing modes, namely: a first mode, called "video mode", using a video-type interface for displaying video images but which does not permanently store the image, and a second mode, called "graphics mode", using a data-type interface which stores the image; - said static memory being addressed by said first control block (2), and said dynamic memory is addressed by said second control block (3); - said first (2) and second (3) control blocks being configured to be able to alternately display data on the same pixel matrix (38); - said first control block (2) being configured to allow the image to be updated by sending new data only when the content of said static memory changes following the recording of the new data in said static memory.

2. Device according to claim 1, wherein the dynamic memory is a capacitor (210, 310, 410).

3. Device according to any one of claims 1 to 2, wherein each elementary emitting zone is connected to several static memories of the SRAM type.

4. Device according to any one of claims 1 to 3, comprising an addressing table (132) which controls the addressing of the static memories of the electroluminescent pixel matrix (38) and a line driver element (137) which controls the addressing of the lines of the electroluminescent display (38), said first control block (2) being configured to send: - to the addressing table (132): -- the asynchronous graphic and / or alphanumeric data stream (131), -- a horizontal addressing signal (133); - to the line control element (137): -- an addressing signal (134) for displaying said asynchronous graphic and / or alphanumeric data stream (131) on said electroluminescent pixel matrix (38).

5. Device according to any one of claims 1 to 3, comprising a horizontal shift register (34) which controls the addressing of the columns of the matrix of light-emitting pixels (38) and a line driver (37) which controls the addressing of the rows of the matrix of light-emitting pixels (38), said second control block (3) being configured to send: - the video data stream (31) to the horizontal shift register (34), - a control signal (32) to the line driver (37), for displaying said video data stream (31) on said matrix of light-emitting pixels (38).

6. Device according to any one of claims 1 to 5, wherein said first (2) and second (3) control blocks are configured such that said second block has a number of emission intensity level bits greater than that of said first control block (2).

7. Device according to any one of claims 1 to 6, wherein said second control block is configured on at least eight bits of emission intensity levels, and / or said first control block is configured on two to six bits of emission intensity levels.

8. Device according to any one of claims 1 to 7, wherein said second control block (3) has a refresh rate greater than or equal to 25 Hz, preferably greater than or equal to 60 Hz, and even more preferably at least 90 Hz, and / or in that said first control block (2) comprises a memory unit for storing said graphic and / or alphanumeric data for static display.

9. Device according to any one of claims 1 to 8, wherein said matrix of electroluminescent pixels (38) is an OLED type matrix.

10. Device according to claim 1, wherein each elementary emitting zone comprises three parts, namely: - a display sub-pixel (290) comprising an OLED element (225) and optionally a transistor SW2 (220) connected to said OLED element (225); - a dynamic part (270) comprising a transistor SW1 (205) configured to receive the video data stream (31) and a reference voltage (47) from a sequencer (33), a capacitor (210) connected to the cathode of the transistor SW1 (205) and a transistor TANA1 (215) whose gate is connected to the cathode of the transistor SW1 (205) and whose cathode is connected to the display sub-pixel (290); - a static part (280), intended for displaying the flow of asynchronous graphic and / or alphanumeric data, consisting of a transistor TANA2 (235) in series with a transistor SW3 (245) in parallel with a transistor TANA3 (240), the latter in series with a transistor SW4 (250), the anodes of said transistor TANA2 (235) and TANA3 (240) being connected to the anode of said transistor TANA1 (215) and the cathodes of said transistors SW3 (245) and SW4 (250) being connected to the cathode of said transistor SW2 (220) or of said transistor TANA1 (215) when SW2 is not present; each of the gates of said transistors TANA2 (235) and TANA3 (240) being connected to a reference voltage Vref (147), and each of the gates of the two transistors SW3 (245) and SW4 (250) being controlled by an SRAM type memory (255,260).

11. Device according to claim 1, wherein each elementary emitting zone comprises three parts, namely: - a display sub-pixel (390) comprising an OLED element (325) and optionally a transistor SW2 (320) connected to said OLED element (325); - a dynamic part (370) comprising a transistor SW1 (305) configured to receive the video data stream (31) and a reference voltage (47), a capacitor (310) acting as a dynamic memory connected to the cathode of the transistor SW1 (305), as well as a transistor TANA (315) whose gate is connected to the cathode of the transistor SW1 (305) and whose cathode is connected to the display sub-pixel (390); - a static part (380), intended for displaying the flow of asynchronous graphic and / or alphanumeric data, consisting of two transistors SW3 (345) and SW4 (350) connected by their cathode to that of said transistor SW1 (305), the anode of said transistors SW3 (345) and SW4 (350) each being connected respectively to a reference voltage (147) Vref1 and Vref2, and each of the gates of said transistors SW3 (345) and SW4 (350) being controlled by an SRAM type memory (355,360).

12. Device according to claim 1, wherein each elementary emitting zone comprises three parts, namely: - a display sub-pixel (490) comprising a transistor SW2 (420) connected to said OLED element (425); - a dynamic part (470) comprising a transistor SW2 (405) configured to receive the video data stream (31) and a line selection voltage (47), a capacitor (410) acting as a dynamic memory connected to the cathode of transistor SW2 (305), as well as a transistor TANA (415) whose gate is connected to the cathode of transistor SW2, whose anode is connected to a voltage VANA and whose cathode is connected to said display sub-pixel (490); - a static part (480), intended for displaying the flow of asynchronous graphic and / or alphanumeric data, consisting of five transistors (440,445,450,455,460) arranged in parallel and a transistor SW1 (435) connected by its cathode to the gate of said transistor TANA (415) and the anode of which is connected to a reference voltage (147) Vref, o the cathode of said transistor SW1 (435) being controlled by five signals coming from the anode of the five transistors (440, 445, 450, 455, 460) arranged in parallel, o one (460) of said five transistors (440, 445, 450, 455, 460) being connected by its cathode to the anode of said transistor SW1 (435) and comprises an analog power supply VANA on its anode and a signal Vreset on its gate, o the gates of the other four transistors (440, 445, 465, 455) being controlled by four control signals S1, S2, S3, S4, allowing the transmission of data coming from the SRAM type memories (441, 446, 451, 456) respectively connected to their anode to the gate of SW1 (435).

13. The device of claim 12, wherein the sub-pixel (490) of the display portion (480) operates at a single luminance level, the gray levels being achieved by controlling the emission time of the latter.

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