Apparatus for a tiled learning processing element and architecture

Abstract

There is provided a processing apparatus for a Tsetlin Machine, comprising at least one Learning Processing Element (LPE) comprising, and operable to use, Tsetlin Machine logic, a data input, operable to receive one or more Literals for use by the Tsetlin Machine logic of the at least one LPE, a settings input, operable to receive control values for the Tsetlin Machine logic of the at least one LPE, an data output, and internal data communications links, operable to couple the Tsetlin Machine logic of the at least one LPE to the data input, settings input and the data output of the at least one LPE, wherein the LPE is operable to output a class at the data output determined by the Tsetlin Machine logic based on the Literals and control values.

Description

[0001] APPARATUS FOR A TILED LEARNING PROCESSING ELEMENT AND ARCHITECTURE FIELD OF THE INVENTION The present invention relates to an apparatus for a tileable learning processing element (LPE) and architecture for Tsetlin Machines. BACKGROUND OF THE INVENTION The Tsetlin Machine (TM) is an existing machine learning algorithm, as disclosed in Ole-Christoffer Granmo, in his academic paper entitled “The Tsetlin Machine -- A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic,” ArXiv: 1804.01508v6, pp.1-42, 16 April 2018, the teaching of which is herein incorporated by reference in its entirety, but especially the portions detailing how a Tsetlin Machine operates in general theory such as, but not limited to Section 3. A particular strength of the Tsetlin Machine approach is that it provides state-of-the-art performance when problem properties are unknown and stochastic, while the problem must be solved as quickly as possible through trial and error, which is an often seen set of circumstances in the Machine Learning area. Unlike traditional Machine Learning (ML) approaches (e.g. deep learning and neural networks), the Tsetlin Machine approach is fundamentally based on logic rather than arithmetic (i.e. uses Boolean values and AND, OR and NOT Boolean functions). However, whilst Tsetlin Machine circuits have been produced, there is still a need to improve the performance of those circuits, particularly when applied to real-world ML problems, especially in the field of Internet of Things (IoT) devices. For example, Tsetlin Machines consume processing resources (e.g. power, die area, processing time) when being trained, and in their subsequent use after training, so there is a need to improve the physical architecture of Tsetlin Machines to reduce their use of such processing resources. SUMMARY Examples of the present disclosure provide an architecture for hardware implementation of a Tsetlin Machine that enables high power efficiency, and modularization / scalability, by way of using a scalable array of multiple instances of the disclosed Learning Processing Elements (LPEs). In some examples, the LPE may be implemented using asynchronous logic, with asynchronous communications between the individual LPEs in an overall Tsetlin Machine, and may include asynchronous implementation of feedback logic. BRIEF DESCRIPTION OF THE DRAWINGS Examples of the invention are further described hereinafter with reference to the accompanying drawings, in which: Figure 1 shows an example of a generalised Tsetlin Machine according to an example of the disclosure; Figure 2 shows an example of a Tsetlin Automaton according to an example of the disclosure; Figure 3 shows a generalised tiled Tsetlin Machine architecture, according to an example of the disclosure; Figure 4 shows high level schematic view of a tileable learning processing element for a Tsetlin Machine architecture, according to the disclosure;

[0002] HGF Ref: P341493WO Figure 5 shows lower level schematic view of the learning processing element of Figure 4, according to an example of the disclosure; Figure 6 shows a more detailed schematic view of the learning processing element of Figure 5, according to an example of the disclosure; Figure 7 shows a more detailed schematic view of a bottom portion 700 of the learning processing element of Figure 6, according to an example of the disclosure; Figure 8 shows a more detailed schematic view of a top row LPE 800 of the learning processing element of Figure 6, according to an example of the disclosure; Figure 9 shows a more detailed view of a middle / inner row LPE 900 of the learning processing element of Figure 6, according to an example of the disclosure; Figure 10 shows a more detailed view of a lower row LPE 1000 of the learning processing element of Figure 6, according to an example of the disclosure; Figure 11 shows an example logical implementation of the disclosed Tsetlin Machine apparatus. DETAILED DESCRIPTION The technical operation and advantages of the present disclosure shall now be provided by way of a plurality of examples that are merely illustrative of the novel and inventive features, and the disclosed examples are intended to be fully combinable in any reasonable combination (i.e. not otherwise explicitly called out as being excluded from combination in the disclosure, or where the combination defines the laws of physics). This is to say, as per usual patent practice, the disclosure is written to be inclusive. We refer to the textbook “An Introduction to Tsetlin Machines”, by Ole-Christoffer Granmo, published at https: / / tsetlinmachine.org, that describes the basic principles of Tsetlin Machines, which is hereby incorporated A block diagram of a basic Tsetlin Machine algorithm is shown in Figure 1, which is composed of a collective of Tsetlin Automata, known as a Team of Tsetlin Automata. These use propositional logic to map an arbitrary sequence of input bits to an arbitrary sequence of output bits, to thereby classify an input data set – i.e. for example pattern match the input. To solve ML problems with the Tsetlin Machine, the input data are first encoded into terms of Boolean Literals. These Literals form part of one or more logic proposition units, called Clauses, which select different patterns of Boolean expressions. Some Clauses propose in favour of a certain class (where a class is a definable item that will be inferred during use, typically after suitable training has occurred - as will be appreciated, the present disclosure relates to a classification problem in machine learning, in which a class label is anticipated for a specific example of input data), while some Clauses oppose the definition of that class. When a majority of Clauses can provide enough confidence in their propositions, that class is selected as the outcome (i.e. resultant output data). In brief summary, to derive a proposition from each Clause, a supervised training process is used. As will be appreciated by the skilled person in the art of Tsetlin Machines, a Feature is a single Boolean variable corresponding to a particular element of a Boolean vector describing an input data item. This is to say, a Boolean vector comprises one or more Features, and a set of such Boolean vectors may form the data set used by examples of the present disclosure for Machine Learning. Furthermore, according to a more general definition: Machine Learning Features may be thought of as the independent (Boolean) variables that are in the form of columns in a structured dataset that acts as input to the learning model. As such, a Feature is a

[0003] HGF Ref: P341493WO measurable property of the objects that need to be analysed. By way of a very brief example, a ‘car’ may be defined as a (specific form of) vehicle that has wheels (which may be defined as a positive feature of having wheels), and transports people (which may be defined as a positive feature of being able to transport people), but does not fly because it does not have wings (which may be defined as a negative feature of having wings). Similarly, using the same basic feature definitions, an airplane can be defined as a vehicle that has wheels (defined as a positive feature of having wheels), and transports people (defined as a positive feature of being able to transport people), and does fly (defined as a positive feature of having wings). Thus, in these examples, it can be seen that the Features that define the type of vehicle are: wheels (or not), transport people (or not) and has wings (or does not). For training, each of these Features, as part of a Clause, is then included or excluded based on a finite state machine, called a Tsetlin Automaton (TA) (see Figure 2, explained in more detail below). As shown in Figure 1, an example of a Tsetlin Machine algorithm according to an example of the present disclosure comprises two portions, one responsible for inference (i.e. classification) 102, and the other responsible for reinforcement and feedback for learning (i.e. training) 103. The following describes the different parts of these two portions, and their usage parameters. As briefly described above, the input data of a Tsetlin Automata according to an example is defined as a set of Boolean (i.e. binarized) variables, called Features, which are represented by what are called Literals 105. To explain further, Features and negated Features are called Literals, as customary in Boolean algebra, where if the Features are called X1, X2, … XN, then the corresponding Literals are typically X1, ¬X1, X2, ¬X2, ..XN, ¬XN (where is the negated version of the variable). Hence there are 2 literals per Feature. In the above example of a car and airplane, X1 is ‘has wheels’, X1 is ‘does not have wheels’, X2 is ‘transports people’, X2 is ‘does not transport people’, etc. The Boolean Literals 105 are fed into both portions of the Tsetlin Automaton, i.e. into both the inference portion 102 and the reinforcement portion 103. The use of two arrows 104 signifies that any Literal can potentially be involved in multiple Clauses - so there is a fan-out from Literals to Clauses. Likewise the use of two arrows 138 signifies any Clause can potentially vote for or against multiple classes - so there is a fan-out from Clauses to classes. There is also proved a further data input, called Expected-Out 106, which is an expected class output that is fed into a Sum and threshold unit 140, which may be thought of as an initial classification decision that may be reinforced or diminished as the overall TM learns from the data inputs, etc., as discussed in more detail below. Inference: The main inference component is the conjunctive Clause 130, which uses propositional logic expressions for output classification. The composition of each Clause (C1132, C2134, …CM 136) is controlled by a Team of Tsetlin Automata 110 (comprising individual Tsetlin Automatons TA1112, TA2114… TAN 116), each of which has a pre-defined number of states, divided between Actions (i.e. Include or Exclude - see Figure 2). In summary, the individual Tsetlin Automata 112-116 decide whether their associated Literal should be included in the Clause or not, following a number of reinforcement steps. The Clauses are controlled by the TAs using suitable control and feedback signals propagated through the system as described in detail below. Each inference class (i.e. classification type) has a set of Clauses associated with it, which is to say the set of Clauses defines how to decide whether a given input data point is of that class, or not. When applied to the input data, each Clause produces a yes vote or no vote on whether the input data is of that class. Half of the

[0004] HGF Ref: P341493WO Clauses can vote positively, and half of the Clauses can vote negatively. The inclusion of inhibition (i.e. negative voting) in the voting system of the (Team of) Tsetlin Automaton is what enables non-linearity in the inference process. The votes, communicated by the outputs of the Clauses 138, are summed, for example in a Sum and Threshold function 140 (i.e. comprising a Sum and Threshold per class – items 142 to 146) to produce a collective result which gives an indication of confidence in the respective classification decision. This confidence in the form of feedback: Type I, Type II or None (as will be explained later) and the outputs of the Clauses are communicated, via 129 and 137, respectively, to the feedback section 120 (see details of feedback below), to influence future decisions of the Team of Tsetlin Automata 110. The output 150 of the Sum and Threshold function 140 is a set of classifications. In a single-class inference problem, the output layer may be a simple thresholding function (e.g. set by a threshold settings value). For example, if enough (i.e. above the threshold) of the votes are positive (or zero = inaction), the input data is determined to belong to the class. The opposite is true for a negative sum (i.e. the Input Data is determined to not be part of the class). For multi-class problems, instead of a simple threshold function, an argmax function can be used to determine the output class, where the Argmax function chooses the class with the highest confidence. In this case, the class summation becomes indicative of confidence for that particular class. Reinforcement: Fundamental to reinforcement are the Team of Tsetlin Automata 110, where, in the example shown, the team comprises N Tsetlin Automatons (i.e. state machines, like Figure 2), where N is derived from the number of Features (L) and the number of Clauses (M) in use, specifically where N = 2 x L x M (there are 2, because Features can be true or false, represented by Literals X and ¬X). Such a Team of Tsetlin Automata are also known as Team of Tsetlin Automata with linear tactics (which means they change states in equal and discrete steps, and that makes them readily implementable in digital hardware, e.g. using up / down counters or shift registers), to emphasize the fact that they allow gradual ascent, or reinforcement, in performing a particular Action, and equally gradual descent (i.e. diminish) from the particular Action to performing another Action. The relative ‘speed’ of the ascent and decent may be set by variables, and it is common for the decent to be more rapid than the ascent, to ensure appropriate learning reinforcement levels. In practice there are a variety of different types of such learning automata which may also be applied to the present disclosure, for example as disclosed in the textbook: Narendra KS, Thathachar MAL.1989 Learning automata: an introduction. Upper Saddle River, NJ: Prentice-Hall, Inc., which is incorporated by reference (i.e. block 530 of Figure 5 may implement any suitable learning automaton). A state diagram of one exemplary Tsetlin Automata approach is shown in Figure 2, which shows an Exclude action (Action 1), and an Include action (Action 2), and how these may be reinforced by way of Penalty and Reward (and Inaction) functions. Half of the states within the TA favour Exclusion (i.e. states 1 to n), while the other half favours Inclusion (i.e. states n+1 to 2n). As training proceeds with more data and rounds, these states are reinforced until each Tsetlin Automaton offers sufficiently high confidence in the decision of including or excluding the input Boolean or its complement, for example ‘far enough away’ from the mid-point n in Figure 2 (to the left for Exclude, and to the right for Include). What constitutes ‘far enough away’ may also be set using a threshold settings value. As such, the confidence level is related to 2n. In more detail, Figure 2 shows the state diagram for a two-action Tsetlin Automaton as an example portion of an overall Tsetlin Machine implementation, having 2n states 201, and a centre point / midstate 250, also called the decision boundary. The current state of the automaton decides which action to perform. The

[0005] HGF Ref: P341493WO automaton in the figure has 2n states. Action 1= Exclude is performed in the states with index 1 to n, while Action 2 = Include is performed in states with index n + 1 to 2n. The state transitions of the automaton govern learning. One set of state transitions is activated on reward (solid lines), and one set of state transitions is activated on penalty (dotted lines). As seen, rewards and penalties trigger specific transitions from one state to another, designed to reinforce successful actions (i.e. those eliciting rewards), and diminish, or deprecate, the unsuccessful ones. Implementation-wise, a Tsetlin Automaton simply maintains an integer (the state index), and learning is performed through increment and decrement operations, according to the transitions specified in the figure. Thus the Tsetlin Automaton is extremely simple computationally, with a very small memory footprint. In more specific detail, according to this simple example, the Tsetlin Automaton may be given reward (solid arrows, e.g.202, going away from the centre point / midstate 250), causing it to reinforce the current action decision (e.g., in this case either Action 1 Exclude or Action 2 Include) by moving away from the midstate. Conversely, the Tsetlin Automaton may be given a penalty (dotted arrows, e.g.203, going towards the centre point / midstate 250), which moves the state towards the centre point decision boundary 250. In some cases, a state may be given an Inaction reward 204, which simply maintains the current state. When applied to processing the Boolean Literals 105 in Figure 1, i.e. through the Team of Tsetlin Automata operating on Clauses 132-136, the two actions may be Include and Exclude 118. The update of the Tsetlin Automata 110 uses reinforcement through Penalty, Reward and Inaction 128. The decision on whether to update individual Tsetlin Automata (112-116) may be controlled by a number of conditions based on: 1) the values of Literals, 2) votes from Clauses described earlier (i.e. a data input from a previous LPE), and 3) current Actions of Tsetlin Automata in terms of Include and Exclude. For further details of how algorithm reinforces these updates, we again refer to the document O.-C. Granmo, “The Tsetlin Machine - A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic,”, and the Tsetlin Machine manual that can be found at https: / / tsetlinmachine.org noted above). Returning to the newly disclosed specific form of Tsetlin Machine architecture, to support scalability, in terms of its functional capability, performance and energy efficiency, as well as its verifiability (especially of the resulting training and subsequent machine learning inference outcomes, including the reasoning therefor), examples according to the present disclosure distribute the architecture, for example in the form of a multidimensional array of individual LPEs. In the simplest example, as shown in Figure 3, there is provided a regular 2 Dimensional array 300 of individual learning processing elements (LPEs) 301. The array may be of any size in both horizontal and vertical directions, depending on the use-case and associated design parameters. This figure shows how, conceptually, the 2D array 300 has a number of different inputs and outputs (typically carried over buses, but other communication architectures may also be used) that are shared by the LPEs, by any suitable means. This is to say, the figure shows how each LPE in the 2D array is able to access the following: an Input Data Bus (IDB) 310, operable to present labelled Input Data items to the LPEs 301 in the form of Boolean vectors of input Literals and expected classification outcomes (class labels – e.g. ‘Expected-Out’ in later figures); an Output Data Bus (ODB) 320, operable to output Boolean vectors for the produced classification outcomes (see item 150 in Figure 1); one or more Settings buses, providing settings (i.e. control values) including s, T (see more detail below) and a pseudo-random number generator (PNRG) value; an internal asynchronous communications bus operable to allow communications between all of the individual LPEs within the array to allow passing of data such as the output of a previous LPE in the chain and other signals used within the LPE (in effect this provides the communications for arrows 104, 118, 129, 137 and 138 in Figure 1); and one or more

[0006] HGF Ref: P341493WO internal feedback busses 350, which provide the feedback to and from the LPEs, as described with reference to Figures 1 and 2 above (and may also include debug, and other internal data passing functions). Any suitable bus architecture may be used for each of the above buses, however according to one example, the overall Tsetlin Machine architecture, and the individual LPEs, are constructed without a global clock, i.e. operate asynchronously. Asynchronous implementation may be used because this approach maximally exploits temporal and spatial distribution of the LPEs in a tile-based design, such as the 2D array shown in Figure 3, thereby allowing for delay variations in logic to be mitigated naturally, without the need for providing circuit wide accurate clocking that is based on the worst-case delays that may happen for a given layout (as is the case for synchronous / global clock based solutions). An example of a suitable asynchronous implementation is the use of asynchronous request / acknowledgement (req / ack) signals that are responsible for coordinating data transfer over the Async bus 340, thereby replacing the global clock signal which is traditionally used in synchronous digital designs. According to an example, the asynchronous implementation may be in the form of a ring architecture having distributed point-to-point links between the individual LPEs (also known as tiles), for example in a circular fashion, which can vastly reduce fanout and therefore power consumption of the data transfer process. Amongst different topologies that support asynchronous communication, ring architecture is a known circular means of point-to-point interconnection between communicating entities (the LPEs, or tiles, in this case). The circuit complexity in terms of fanout is reduced, which also reduces the communication power consumption, because a ring architecture provides simple layout of communication including single sender and single receiver. The herein proposed architecture for a Tsetlin Machine, i.e. having modular, tileable, LPEs, allows for scalable expansion of the number of LPEs depending on the machine learning problem and dataset. Learning Processing Element (LPE) Figure 4 shows an example connectivity of a single LPE 301 according to the present disclosure. As shown, each LPE includes at least the following inputs: a data input, Input Data 411, operable to receive Input Data (i.e. Boolean Vector(s)), an Expected-Out 412 which is an expected class output (as discussed in detail below), an internal data input, Internal Data-in 421, operable to receive internal data, such as a partial sum (PSUM) of Clauses from a previous LPE in the chain; a settings / configuration input 431 operable to receive settings data for example the values n (of 2n), s, T (i.e. the thresholds), PRNG, etc, and an internal feedback input (e.g. as part of an internal bi-directional i / o comms link, Internal Feedback 441). In effect, each LPE implements the logical structure shown in Figure 1, and uses these bus connections to provide the communications across arrows 104, 118, 128, 129, 137, 138, etc (and of course could be implemented in other ways, such as direct wires between the respective entities, and is merely a design implementation decision by the skilled person). Each LPE 301 also includes at least the following outputs: Output Data 451 operable to output the Output Data (again as a Boolean vector), the output portion of Internal Feedback 441, for example operable to share some feedback conditions calculated in this LPE with other LPEs (within the respective LPE chain, or even wider groupings, implementation dependent), and an internal data output, Internal Data-Out 461, for example operable to output PSUM to the next LPE 301 in the relevant chain. These inputs and outputs are connected to the respective buses discussed above with respect to Figure 3. Internal Data-Out 461 may also be comprised of two portions, e.g. a first portion called Internal Data-Out_1461a and a second portion called Internal Data-Out_2461b, as detailed below.

[0007] HGF Ref: P341493WO Figure 5 shows an example specific implementation of a single LPE 301 according to the present disclosure. As shown, in addition to the above disclosed inputs / outputs 411 - 461, the LPE of Figure 5 comprises a number of internal functional units (also known as a block, or circuitry), including: Interference Logic block 510, Feedback Logic block 520, and a Team of TA memory block 530 (i.e. the portion of memory, e.g. shift registers / counters, that implements the one or more TAs used by this individual LPE for processing the clause(s)). These may be interconnected internally within the LPE 301, using suitable communications links, which includes: a communications link to send Update commands 525 from the Feedback logic block 520 to the Team of TA memory block 530; a communications link to send Action(s) values data 535 from the Team of TA memory block 530 to the inference logic block 510, and also back to the Feedback Logic block 520. There are also communications links Internal Data-Out_1461a coming from the Inference Logic block 510, and Internal Data-Out_2461b coming from the Feedback Logic block 520 that operate to send Inference results between the Inference logic block 510 and the Feedback logic block 520 as will be described in more detail below. As can be seen, internally the settings data may be split, so as to feed the configuration settings (e.g. Thresholds n, s and T) 431a for the Team of TA memory block 530 separately to the configuration settings 431b for the Feedback logic block 520. The PNRG 540 may also be split so as to provide Prob 432 to the Feedback Logic 520. Input Data 411 is copied to both Inference Logic 510 and Feedback Logic 520. As can be seen, each LPE 301 therefore comprises a number of functional processing units / blocks for providing learning capability, parametric optimisation and inference-only operation. As will now be appreciated, the disclosed architecture may be seen as providing an on-chip learning capability – i.e. the learning feedback function is baked into disclosed hardware architecture itself, and not hived off separately. Accordingly, the resultant architecture as a whole may be seen as a hardware accelerated form of compute architecture for ML learning, which as a result may provide improvements to efficiency, power usage, and the like. An important feature of the disclosed LPE 301 is that it works as a basic building block (i.e. tile) from which any form (e.g. size) of an overall Tsetlin Machine architecture may be built. The contribution of the individual LPE 301 to the inference functionality of any resulting overall Tsetlin Machine architecture is fundamentally partial (i.e. may only operate on part of the overall data set being operated upon, e.g. a Boolean sub-vector), which is analogous to the role of, for example, a full 1-bit adder within an N-bit ripple-carry adder. A main function of the LPE 301 as part of the, for example 2D, array structure of an overall Tsetlin Machine architecture, is thus to receive input Boolean sub-vectors (i.e. the subsets of literals involved in a given clause or portion thereof, called a clause-part, that is being handled by this LPE, which in the simplest case could be one literal), compute a partial inference operation on those Literals, such as a subset of Conjunctive Clauses (i.e. AND-functions) on these Literals (both direct and inverted) and / or partial sums of votes for and against a particular class generated by the outputs of the Clauses. In computing its partial Clauses and / or partial sums (PSUM – i.e. a partial-Clause), the LPE’s inference logic block 510 may use the output of the inference logic block 510 from another LPE 301 in the array, for example (and typically) the LPE 301 immediately above it in the same column of the 2D array (i.e., in the example shown in Figure 3, LPEK+1 takes the output of the LPE1 block). Likewise, the inference block’s outputs of the current LPE (e.g. LPE1) can be used as inputs to the inference logic block 510 of the LPE (LPEK+1) immediately below it in the same column. In determining whether input Literals are to be included in or excluded from the partial Clauses (i.e. the portion of the overall Conjunctive Clause set being operated on by the particular LPE within that chain – partial

[0008] HGF Ref: P341493WO clauses are split vertically in Figure 3) in the inference logic of the current LPE, signals called Action 535 generated by the LPE’s Team of TA memory 530 are used. In order to maintain the principle of modularity, i.e. use each LPE 301 as a basic building block, or tile, for creating an overall TM architecture of any size, in the simplest case of an LPE 301, the LPE granularity may be a single bit. Thus, according to an example, the internal structure of an example LPE 301 is bit-sliced, which is determined by individual bits of the Boolean sub-vector of input Boolean Literals. However, each LPE 301 may be formed to operate upon any number of bits at a time (i.e. N-bit sliced). In the example of an elementary one bit (1-bit) form of LPE, for one-bit output of a partial Clause, the inference logic may be described by the following Boolean function: "Clause-Out"="Clause-In"∧"Clause-Part" (1) where ∧ is the Boolean AND operation, and "Clause-Part"="Action-Exclude"∨("Action-Include" ∧ "Input-Data" ), where ∨ is the Boolean OR operation, and “Input-Data” is a single Boolean literal, either Xi or ¬Xi, where i is from 1 to L (L = total number of Features). If “Action-Exclude” is always the inversion of “Action-Include” (as is the case in the present disclosure), then it follows that: "Clause-Part"=¬"Action-Include"∨"Input-Data" (2) where is the inversion, i.e. Boolean NOT operation, hence expression (1) can be re-expressed using (2), as follows: "Clause-Out"="Clause-In"∧(¬"Action-Include"∨"Input-Data") (3) which now clearly defines what “Clause-Out” (of this individual LPE) will be relative to “Clause-In” (for this LPE), and its other inputs – Actions (from 535 in Figure 5) and Input Data (411 from Figure 5). By way of further explanation, the Clause value propagates through each LPE in a chain that deals with a particular clause, by each LPE taking as input the Clause-Out from the previous LPE (now called Clause-In, for this current LPE), applying the above equation (3), to thereby result in the Clause-Out for the current LPE. This process carries on until the last LPE’s Clause-Out is the value of total Clause for the whole chain. This process is described in more detail with reference to Figures 6 to 10, below. Feedback logic 520 receives as its inputs, the values of Input Data 411, Action(s) 535, Settings (such as thresholds) 431b, plus a value from a pseudo-random number generator (PRNG) 432, where the PRNG is mapped on to a Boolean domain, called “Prob”, where "Prob"∈0,1 (i.e. randomly a 0 or a 1, where it is assumed the following correspondence between binary and Boolean: true = 1 and False = 0), and determines the value of Update Commands values 525 (i.e. Penalty, Reward or Inaction) issued to the Team of TA memory 525. Besides that, Feedback Logic 520 is involved in receiving some internal feedback 441 from other LPEs and producing internal feedback for other LPEs over bidirectional comms link Internal Feedback 441, as well as producing Internal Data-Out_2461b. The Boolean function that describes the function of the Update Commands 525 is as follows: "Reward"≝("Action-Include" ∧("Input-Data" ="Clause")∧"Prob" )∨("Action-Exclude" ∧("Input-data" ≠ "Clause")∧"Prob" ) (4)

[0009] HGF Ref: P341493WO where "Input-Data" ="Clause" means the Input-Data matches the clause, and "Input-data" ≠"Clause" means the Input-Data does not match the clause, and so the function as a whole acts, subject to a randomisation factor provided by “Prob”, to reward the inclusion of this input data if the input data is in agreement with the clause (i.e. helps in a good way), or if the input data is not in agreement with the clause, then the exclusion of this input data is rewarded. As such, this works to provide the reinforcement. "Penalty"≝("Action-Include" ∧("Input-Data" ≠"Clause" )∧"Prob" )∨("Action-Exclude" ∧("Input-Data" ="Clause" )∧"Prob" ) (5) i.e. subject to a randomisation factor, if the input data is in disagreement with the clause, then the inclusion of this data is penalised, or if the input data is in agreement with the clause, then the exclusion of this input data is penalised. As such, this works to provide the diminishment. "Inaction"≝¬"Prob" (6) Where ≝ means ‘defined by’, “Prob” is the output of the PRNG, and “Clause” = Clause-Out (i.e. total clause) from the last LPE in the chain of all the LPEs involved with calculating this particular clause (i.e. decision on a single clause). According to the above disclosed example functions, the feedback logic block 520 rewards the include action (i.e. “Action-Include”) if it helps the input data (i.e. Input-Data 411) to be coherent with the Clause, or partial Clause, as applicable to the single LPE involved – i.e. any Clause portion existing between the Clause-In and Clause-Out, taken as a whole across all the LPEs in the array involved with the Clause assessment / calculation (e.g. going upwards between the LPEs), or rewards the exclude action (“Action- Exclude”) if the input data is not in agreement with the Clause. On the other hand, the feedback logic penalises the include action if it leads to having a disagreement between input data and the (total) Clause, or penalises the exclude action if the input data is in agreement with the (total) Clause. In both situations, penalty or reward is only issued if the probabilistic input (from the PRNG) is true, such that active state change in the TA is selected, i.e. "Prob"=1 coming out of the PNRG for that portion. Whereas, if the probabilistic input is false, i.e. "Prob"=0, the feedback logic produces Inaction, which equates to the state staying the same. As noted above, the Team of TA memory 530 is organised in such a way that for each pair of elementary actions, i.e. Action-Include / Action-Exclude, a 2n-state linear structure Tsetlin Automaton is used, as shown in Figure 2. The first n states, 1 to n, correspond to the output action “Action-Exclude”, and the second n states, from n+1 to 2n, correspond to output action “Action-Include”. The moves or transitions between the states is controlled by inputs Penalty 203, Reward 202 and Inaction 204. NB - the Inaction transitions are omitted in the figure (they are self-loops). The Team of TA memory 530 is an array of elementary TAs, comprising one or more TAs (for example, there is only one TA in a 1-bit LPE). Each TA can be implemented as a shift-register or up-down counter to carry out the functionality of the state-transition graph in Figure 2. Each of such elementary TAs can be accessed via “Update commands” 525 signal(s) (i.e. values) that comprise a unique address (Binary code) together with a command (i.e. one of the Reward / Penalty / Inaction). In response to that update command(s), the respective TA produces an action (i.e. one of Exclude / Include) depending on its state (i.e. where it is in the state diagram, for example according to Figure 2). In order to control the depth 2n of the TA, and hence the position of the border between the Action- Include and Action-Exclude actions – i.e. the value of n or another variable, which relates to the confidence level sought, inputs configuration Settings 431a are used.

[0010] HGF Ref: P341493WO In summary, the circuit of Figure 5 operates as follows: Inference Part: ^ Input data in the form of Boolean Literals corresponding to the LPE are fed into the inference logic block 510. ^ Each Clause output (i.e. Total Clause) can take a 1 or 0 value, depending on the input Literals and TA Actions, as follows: Clause output = AND for all Literals [NOT(TA) OR Literal (i.e.0 or 1)] (7) The partial sum of Clauses are called PSUM. Partial sum (PSUM) constituting the partial votes from the previous LPE is used for further Clause processing in the (next) LPE. ^ The Actions from the TAs are extracted from the Team of TA memory 530 according to their current states (i.e. states 1 to n are excluded, states n+1 to 2n are included). ^ Output data based on Boolean partial sum of the Clauses are generated at the level of LPEs using the above inputs. ^ The first portion of Internal data (i.e. Internal-Data-Out_1461a) generates partial sums (PSUMs) which can be used by other LPEs to produce classification outcomes, as described above. Feedback Part: ^ The configuration settings inputs 431b determine the hyperparameters of training: s and T. The s parameter defines the probabilistic learning rate; the higher the s value, the higher the number of ‘include’ reinforcements per training cycle will be. The T parameter defines the voting threshold; if the total sum of clauses (CSUM) is higher than other CSUMs by T or more, the Class definition is accepted. ^ The pseudorandom number generator (PRNG) 540 provides a sequence of random numbers required for probabilistic selection of actions as explained above. ^ The Settings (thresholds) 431a input determines the way of allocating include and exclude Actions based on the total number of TA states (i.e. sets 2n). ^ Internal feedback 441, both input and output, determines the type of feedback depending on the current Literal and Clause values, according to usual Tsetlin Machine operation as disclosed in the above-referenced work paper and Textbook by O. C. Granmo. By way of brief explanation, Type I feedback refers to determination of the ‘include’ reinforcements, as well as boosting the ‘true positive’ feedback. Meanwhile, Type II feedback refers to training strategies to combat the ‘false positive’ output classifications. The internal feedback mechanism looks at the current classification together with Literal and Clause values to allocate Update Commands 525 suitably. Empty (None) feedback is produced if no particular class has been identified, and hence the Clause voting for it or against it cannot receive any feedback. The output element of Internal Feedback 441 can be communicated to other LPEs to help them to generate their Update Commands 525 and Internal Data-Out 461b. ^ The Expected-Out 412 data input provides an initial or expected classification decision of class to be reinforced or diminished during learning as the processing apparatus operates, for example on the Literals and control values input over time during operation of the disclosed TM. HGF Ref: P341493WO ^ The second portion of Internal data, i.e. Internal-Data-Out_2461b, generates data elements which can be used by other LPEs to produce classification outcomes, as described above. For example, for use by item 604 in Figure 6. There now follows a detailed explanation of an example bitwise 2D tiled implementation of the proposed Tsetlin Machine circuitry. This type of structure is shown in Figures 6-10. According to this example implementation, the ordering principle is based on partial clause calculation to generate Clause-out (i.e. Total- Clause) rather than on partial sums (i.e. PSUM). Figures 6, 8, 9 and 10 illustrate example circuitry that applies the above described calculation of the Total-Clause (see equations (1)-(3), where Total-Clause is the result of lots of partial-clause assessments using Equation (3)). In particular, Figure 6 shows an example of a 2D array of LPEs, now labelled as elements LPE1,1to LPE2L,M and now referred to as items 601 (top, upper, row), 602 (middle, inner, row) or 603 (bottom, lower, row), depending on which row location they are in. (To explain further, it will be recalled that there are in total 2L*M LPEs, and so this figure uses a subscript labelling scheme to show both how the labels apply logically, but also a reference number scheme to show how the different LPE may be structurally different in minor aspects to take into account whether they are the very first LPE (= top row), one of the none, or potentially very numerous middle / inner LPEs (i.e. middle row in this figure), or the final LPEs (= lower / bottom row). To show all this, Figure 6 uses an LPE naming protocol that is labelled 1 to M horizontally left to right, using variable ‘j’, and is labelled 1 to 2L vertically top to bottom, using variable ‘i’. To re-iterate, this convention is used here since the top row of LPEs may be of one form, the (various number, including none, of) “inner” LPEs may be of another form, different to the top and bottom row LPE types, and the bottom row may be again of the same form (potentially different to the other two forms)). To be clear, some examples may have no “inner” row of LPEs (i.e. only top and bottom row LPEs). In operation, vertically, these LPEs, indexed with i from 1 to 2L, calculate one Total-Clause, and indexed horizontally with j from 1 to M, process a plurality of Total-Clauses. In this example, the LPEs are labelled as follows: LPEs 601 (for the top row), 602 (for an inner row) and 603 (from the bottom row), in order to show that each LPE belonging to one row is identical. So, according to this example, the LPEs are different within a column, but identical in a row. The internal structures of LPE 601 (top row), LPE 602 (inner row) and LPE 603 (bottom row) are shown in Figures 8, 9 and 10 respectively, and discussed in more detail below. By way of a specific example, in a top row LPE 601, if Clause-In_1641 is set to a Boolean constant True (i.e. logical 1). Then Clause-Out_1671 is directly connected to Clause-In of the subsequent (vertically) row (in this case Clause-In_i of Figure 9), and this cascading methodology repeats in the same way for all inner-row LPEs 602 (i.e. if the previous LPE Clause-Out_i is logic 1, then Clause-In_i+1 also = 1, and this means the previous LPE directly connects to the next LPE) until the bottom row LPE 603. Finally, Clause-Out of the bottom row LPE 603, which by now is also known as Clause-Out_2L), is generated as the Total-Clause_1651. Similarly, Total-Clause_j 652 and (all the way up to) Total-Clause_M 653 of other columns are produced in the same way, cascading down vertically through the LPEs starting from Clause-In_j 642 and Clause-In_M 643, respectively). All these Total-Clauses are fed back to all LPEs of the corresponding column. Figure 6 also shows a Shared Final Feedback Logic (SFFL) block 604, which is responsible for calculating the output data classification. The inputs of block 604 are Total-Clause_1 (leftmost clause) 651, Total-Clause_j (inner clause) 652 and Total-Clause_M (rightmost clause) 653, input data Expected-out 621 (i.e. expected classification result) and Thresholds 431b. The outputs of block 604 are Output-Data (i.e. Learned- HGF Ref: P341493WO Out) 631 and clause-level feedbacks FB-Clause_1661, FB-Clause_j 662 and FB-Clause_M 663. All the clause- level feedbacks are fed back to all LPEs of the corresponding columns. The internal structure of Shared Final Feedback Logic (SFFL) block 604 is shown in Figure 7. In Figure 7, Clause-Sum block 701 calculates a sum of votes (some positive and some negative) produced by all M total clause inputs from Total-Clause_1651 to Total-Clause_M 653, and acting in line with values s, T supplied by Threshold 431b, and produces a Boolean output Learned-Out 711 (which is Output-Data 631 in Figure 6). FB_TM block 702 takes as inputs Learned-Out 711 and Expected-Out 621 and generates Tsetlin-Machine level feedback, FB_TM 712. Then, using this Tsetlin-Machine level feedback FB_TM 712, a set of FB_Clause blocks 703 (FB_Clause_j to FB_Clause_M) calculates M outputs of clause-level feedbacks FB-Clause_1661 to FB- Clause_M 663 from their corresponding inputs Total-Clause_1651 to Total-Clause_M 653 and corresponding values Prob_T_1721 to Prob_T_M 722, all produced by pseudo-random number generators (PRNG_1 to PRNG_M) 704, where these random-numbers are mapped on to a Boolean domain "Prob"∈0,1 (i.e. randomly a 0 or a 1). The internal structure of bit wise LPEs 601, 602 and 603 are shown respectively in Figures 8, 9 and 10, in the form of a single instance in each row (item 800 = an instance of an upper row LPE, 900 = an instance of an middle, inner, row LPE, 1000 = an instance of lower row LPE). The middle, inner, row may be repeated as many times as needed to provide a suitably sized chain of LPEs suitable for a given use-case scenario. Equally, the number of columns (i.e. number of chains) may also be of any size, to thereby create any desired size of 2D array of LPEs. The person skilled in the art will note there is a clear correspondence between bit-level signals of these Figures 6 - 8, and their corresponding more generalised form of the links in Figures 4 and 5, for example. In brief summary, for a comparison of Figure 4 with Figure 6, they may have a correspondence for example, as follows: Input-Data 411 is represented in the bit-level LPEs by data lines: Input-Data_1611, Input-Data_i 612, and Input- Data_2L 613; the input ‘Expected-Out’ 412 is represented by Expected-Out 621; Internal Data-In 421 is represented in the bit-level LPEs by 641 (642, 643), 671 as it goes into LPEi,2602 (672, 673, in similar fashion for the rest of this middle / inner row of LPEs) and 681 as it goes into LPE2L, 1603 (682, 683, in similar fashion for the rest of this bottom row of LPEs), Internal Data-Out_1461a is represented in the bit-level LPEs by 671 as it comes out of LPE1,1601 (672, 673, again in similar fashion, but for the rest of this top row of LPEs), 681 as it comes out of LPEi,1601 (682, 683, again in similar fashion, but for the rest of this middle / inner row of LPEs) and 651 as it comes out of LPE2L,1603 (652, 653, again in similar fashion, but for the rest of this bottom row of LPEs), noting that data out of one LPE becomes the data in of another, hence references double up. Similarly, for Figure 5 compared to Figure 6, Action 535 is represented in the bit-level-LPEs by Actions Action_1811 to Action_2L 813; Update Commands is represented by Command_1911 to Command_2L 913; Prob 432 is represented by Prob_s_11011 to Prob_s_2L 1013 (coming out of PRNG_1804 to PRNG_2L 804); settings (thresholds) 431b is shown in Figure 6 , but settings 431a, which is the thresholds for each LPE, are not shown in Figure 6, for clarity as there is one per LPE, which would otherwise clutter up the figure; and (for Figures 4 and 5, compared to Figure 6) Internal Feedback 441 is represented by signals Total-Clause 651 (652, 653) and FB-Clause 661 (662, 663). Feedback Logic An implementation of Feedback logic according to an example involves representing each multivalued signal using a one-hot encoding scheme. This is to say, representing the particular value of the multivalued HGF Ref: P341493WO signal using a corresponding number of wires (called rails) in such a way that a predetermined signal (e.g. a logic ‘1’) on one out of how ever many rails are involved stands for a particular value of the signal. By way of example, if a Boolean signal is being represented (i.e. can be a 0 or a 1), then 2 rails are involved, whereas for a multivalued signal that has 8 possibilities, that would use 8 rails. By way of further explanation, the “one-hot” form of representation presumes that: (i) when a signal ‘x’ has the value of ‘a’, i.e. ‘x=a’, the corresponding combination of wires encoding signal ‘x’ are in the state 0 except for rail ‘xa=1’, and (ii) when a signal ‘x’ changes its value, e.g. from ‘x=a’ to ‘x=b’, the corresponding combination of wires encoding signal ‘x’ firstly goes from the state where rail ‘xa=1’ to a spacer state (where all rails of ‘x’ are equal to 0), and then transitions to the state where rail ‘xb=1’. In line with this representation, Feedback logic is constructed by using sets of equations for the individual rails of each signal, both inputs and outputs. Example equations for implementing the feedback logic 520 in a one-hot encoded circuit are as follows. fbTAp= fbclauseT2^ ¬inc ^ c ^ ¬x ^ fbclauseT1^ inc ^ ¬c ^ ¬probs^ fbclauseT1^ ¬inc ^ c ^ x ^ probs (8) fbTAr= fbclauseT1^ (inc ^ c ^ probs ^ ¬inc ^ (¬c ^ ¬probs ^ c ^ ¬x ^ probs) (9) fbTAi= fbclausenone^ fbclauseT2^ (inc ^ ¬c) ^ fbclauseT1^ inc ^ (¬c ^ probs^ c ^ ¬probs) ^ fbclauseT1^ ¬inc ^ (¬c ^ probs ^ c ^ ¬probs) (10) fbTMnone= ¬learned-out (11) fbTMT1= learned-out ^ expected-out (12) fbTMT2= learned-out ^ expected-out (13) fbClausenone= fbTMnone^ fbTMT1^ ¬probT^ fbTMT1^ probT(14) fbCl auseT1= ¬total-clause ^ fbTMT2^ ¬probT^ total-clause ^ fbTMT1^ probT(15) fbClauseT2= ¬total-clause ^ fbTMT1^ probT ^ total-clause ^ fbTMT2^ ¬probT (16) Where: Signals x and ¬x stand for the positive and negative Boolean literals as per arrows 104 in Figure 1, and in a more generalised form, they are represented by arrows Input Data 411, whilst in a more specific form, they are represented by arrows Input-Data 611-613 in Figures 6 and 8-10; Signals c and ¬c stand for Boolean clauses (same as Total-Clause and ¬Total-Clause) as per arrows 138 in Figure 1. In a more specific form they are represented by arrows 651 in Figures 8-10 and arrows 651-653 in Figures 6 and 7; Signals inc and ¬inc stand for Include and Exclude actions respectively, represented by arrow 535 in Figure 5, and in a more specific form by arrows 811-813 in Figures 8-10; HGF Ref: P341493WO Signals learned-out and ¬learned-out stand for the positive and negative classification outcome (same as Output data), represented by arrow 451 in Figures 4 and 5, and in a more specific form by arrows 631 and 711 in Figures 6 and 7 respectively; Signals expected-out and ¬expected-out stand for the positive and negative expected classification outcome (same as input data Expected-out), represented by arrow 412 in Figures 4 and 5, and in a more specific form by arrow 621 Figures 6 and 7; Superscripts ‘T1’, ‘T2’ and ‘none’ for fbTM stand for the Type I, Type II and Empty (none) feedbacks. These are represented as arrow 712 in Figure 7. With regards to the structure of TM in Figure 1, fbTM can be implemented as part of Sum & Threshold (per class) block 140 (inference part 102) or inside the Feedback for TAs block 120 (reinforcement part 104); Superscripts ‘T1’, ‘T2’ and ‘none’ for fbclause stand for the Type I, Type II and Empty (none) feedbacks. These are represented as arrow 661 for a generic clause (i.e. column in the 2D array of bit-level tiles) in Figures 8-10, and more individual arrows for specific clauses 661-663 in Figures 6 and 7. These are also represented in a more general form as arrow 129 in Figure 1; Superscripts for FBTA ‘p’, ‘r’ and ‘i’ stand for penalty, reward and inaction signals (Update commands). These are represented as Command arrows 812 for a generic clause (i.e. column in the 2D array of bit-level tiles) in Figures 8-10, and as Update Commands 525 in Figure 5. These are also represented in a more general form as arrow 128 Figure 1; probs and ¬probs stand for the positive and negative Boolean probability values 0 or 1, as generated by the PRNG, at the level of individual TAs, as discussed previously ("Prob"∈0,1), represented by arrow 432 in Figure 5 and more specifically for bit-level by arrows 813 in Figures 8-10; and probT and ¬probT stand for the positive and negative Boolean probability values 0 or 1, at the as generated by the PRNG, at the level of TM for FB-Clause calculation, as discussed previously ("Prob"∈0,1), represented by arrow 432 in Figure 5 and more specifically for bit-level by arrows 721-722 in Figure 7. In a further example, using One-hot and dual-rail encoded asynchronous circuit, the feedback equations then become: fbTAp= fbclauseT2^ incN^ cP^ xN^ fbclauseT1^ incP^ cN^ probsN ^ fbclauseT1^ incN^ cP^ xP^ probsP(17) fbTAr= fbclauseT1^ (incP^ cP^ probsP^ incN^ cN^ probsN^ incN^ cP^ xN^ probsP) (18) fbTAi= fbclausenone^ fbclauseT2^ (incP^ incN^ cN) ^ fbclauseT1^ incP^ (cN^ probsP^ cP^ probsN) ^ fbclauseT1^ incN(cN^ probsP^ cP^ xN^ probsN^ cP^ xP^ probsN) (19) Where: Superscripts ‘N’ and ‘P’ stand for negative and positive rails of a dual-rail encoding of the corresponding Boolean signals (i.e. a “1” may be indicated by one rail set to high / 1 and the other low / 0, a “0” is the corresponding inverse of the signals on the two rails, and requiring a special “spacer” state between two adjacent “1” or “0” values; namely, for operating with an all-0 spacer both rails are set to low / 0 in the spacer HGF Ref: P341493WO state, otherwise if working with an all-1 spacer both rails are set to high / 1). These are represented as arrow 137 for Clauses (CN / CP) and 104 for Literals (X1 / X1, etc) in Figure 1; incNand incPare the Exclude (i.e. negative Include) and Include Actions respectively, shown as arrow 118 (going to the feedback section) in Figure 1; Superscripts ‘T1’, ‘T2’ and ‘none’ for fbclause stand for the Type I, Type II and Empty (none) feedbacks. These are represented as arrow 129 in Figure 1; Superscripts for FBTA ‘p’, ‘r’ and ‘i’ stand for penalty, reward and inaction signals. These are represented as arrow 128 in Figure 1; probsNprobsPare the dual rail random probability values 0 or 1, as generated by the PRNG, as discussed previously ("Prob"∈0,1); The fbclause signal is shared throughout the TAs within the same Clause. Therefore, when the fbclause signal is zero (Empty feedback), the computation on the corresponding fbTA rails will conclude rapidly, and for all TAs in the Clause; and Equations (17) to (19) above are the one-hot / Dual Rail versions of equations (8) to (10), and the remaining questions (11) to (16) may be adapted for Dual Rail in a similar fashion, as would now be understood by the skilled person. Examples of the present disclosure may be implemented by suitably programmed computer hardware, for example as shown in Figure 11. Figure 11 is a block diagram 1100 illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and operable to create structures as disclosed here, or perform any one or more of the methodologies discussed herein, hence providing the Tsetlin machine apparatus as disclosed herein. Specifically, Figure 11 shows a diagrammatic representation of hardware resources 1105 including one or more processors (or processor cores) 1110, one or more memory / storage devices 1120, and one or more communication resources 1130, each of which may be communicatively coupled via a bus 1140. The processors 1110 (e.g., an FPGA, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a cloud processing function (such as an AWS instance), another processor, or any suitable combination thereof) may include, for example, a processor 1112 and a processor 1114. The memory / storage devices 1120 may include main memory, disk storage, or any suitable combination thereof. The memory / storage devices 1120 may include, but are not limited to any type of volatile or non-volatile memory such as dynamic random access memory (DRAM), static random-access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), Flash memory, solid-state storage device (SSD), magnetic storage based hard disk drive (HDD) media, etc. The optional communication resources 1130 may include interconnection or network interface components or other suitable devices to communicate with one or more peripheral devices 1104 or one or more databases 1106 via a network 1108. For example, the communication resources 1130 may include wired communication components (e.g., for coupling via Ethernet, a Universal Serial Bus (USB) or the like), cellular communication components (e.g.3GPP 4G, 5G, etc standards based communications), NFC components, HGF Ref: P341493WO Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components. Instructions 1150 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least any of the processors 1110 to perform, or be arranged to perform, any one or more of the methodologies discussed herein. The instructions 1150 may reside, completely or partially, within at least one of the processors 1110 (e.g., within the processor’s cache memory), the memory / storage devices 1120, the databases 1106, or any suitable combination thereof. Furthermore, any portion of the instructions 1150 may be transferred to the hardware resources 1105 from any combination of the peripheral devices 1104 or the databases 1106. Accordingly, the memory of processors 1110, the memory / storage devices 1120, the peripheral devices 1104, and the databases 1106 are examples of computer-readable and machine-readable media. The databases 1106 may also store the data upon which the disclosed Tsetlin machine is trained and / or the date on which it carries out inference. In some embodiments, the electronic device(s), network(s), system(s), chip(s) or component(s), or portions or implementations thereof, of Figures 11, or any other figure herein, may be configured to perform one or more processes, techniques, or methods as described herein, or portions thereof. In the foregoing, functions are described as modules or blocks, i.e. functional units that are operable to carry out the described function, algorithm, or the like. These terms may be interchangeable. Where modules, blocks, or functional units have been described, they may be formed as processing circuitry, where the circuitry may be general purpose processor circuitry configured by program code to perform specified processing functions. The circuitry may also be configured by modification to the processing hardware. Configuration of the circuitry to perform a specified functions may be entirely in hardware, entirely in software or using a combination of hardware modification and software execution. Program instructions may be used to configure logic gates of general purpose or special-purpose processor circuitry to perform a processing function. Circuitry may be implemented, for example, as a hardware circuit comprising custom Very Large Scale Integrated, VLSI, circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. Circuitry may also be implemented in programmable hardware devices such as field programmable gate arrays, Field Programmable Gate Array (FPGA), programmable array logic, programmable logic devices, a System on Chip, SoC, or the like. Machine readable program instructions may be provided on a transitory medium such as a transmission medium or on a non-transitory medium such as a storage medium. Such machine readable instructions (computer program code) may be implemented in a high level procedural or object oriented programming language. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations. Program instructions may be executed on a single processor or on two or more processors in a distributed manner. Examples may be implemented in the form of physical circuits, or hardware description language (HDL) (e.g. VHSIC Hardware Description Language (VHDL), Verilog, or the like) describing the structure of those circuits, operable to form the disclosed structures, interconnections and / or logical processing methodologies, in order to provide a hardware processing apparatus in accordance with the disclosure herein. Examples provide a processing apparatus for a Tsetlin Machine, comprising at least one Learning Processing Element (LPE) comprising, and operable to use, Tsetlin Machine logic, a data input, operable to receive one or more Literals for use by the Tsetlin Machine logic of the at least one LPE, a settings input, HGF Ref: P341493WO operable to receive control values for the Tsetlin Machine logic of the at least one LPE, an data output, and internal data communications links, operable to couple the Tsetlin Machine logic of the at least one LPE to the data input, settings input and the data output of the at least one LPE, wherein the LPE is operable to output a class at the data output determined by the Tsetlin Machine logic based on the Literals and control values. In some examples, the at least one LPE is tileable. In some examples, the processing apparatus comprises a plurality of LPE arranged in an array. In some examples, the processing apparatus comprises a plurality of LPEs arranged in a 2D array, wherein each vertical column of the array comprises a chain of LPEs, operable to apply Tsetlin Machine Logic to a determine a class based on Literals inputted into the vertical column. In some examples, the at least one LPE further comprises: an LPE instance specific set of inputs comprising: a data input to receive Input Data; a settings input to receive settings control values; an internal data input to receive internal data of the Tsetlin Machine logic from another LPE; and an Internal feedback input to receive Internal feedback data of the Tsetlin Machine logic; an LPE instance specific set of outputs comprising: a data output to output Output Data from the Tsetlin Machine logic; an internal data output to output internal data of the Tsetlin Machine logic to another LPE; and an internal data feedback output to output Internal feedback data of the Tsetlin Machine logic; and further data internal to the at least one LPE. In some examples, the output internal data of the Tsetlin Machine logic comprises first and second output data, for example Internal Data-Out_1461a and Internal Data-Out_2461b, outputted from the inference logic 510 and feedback logic 520, respectively. In some examples, the further data internal to the at least one LPE comprises Update Commands data and Actions data. The feedback logic may also receive an Expected-Out data input 412. In some examples, ‘LPE instance specific’ means those items are for, or apply to (as an input or output) a given LPE instance, where the instance is one of the LPEs in the array (e.g. as per Figure 3, or 6) In some examples, the at least one LPE further comprises: an inference logic block operable to receive Input Data values, Action values, and partial result values from a previous LPE, and output Output Data values, and first Internal Data values indicative of partial result values for use by a subsequent LPE; a feedback logic block operable to receive Input Data values, Action data values, settings values and Internal Feedback values, and to provide Update Commands values, and second Internal Data values of indicative of partial result values for use by another, subsequent, LPE; and a Team of TA operable to receive the Update Commands values, settings values and to provide Action values to the inference logic block and feedback logic block. In some examples, partial result values comprises Partial Sum values and / or Partial Clause values. In some examples, the partial result data is derived from a previous LPE in the chain of LPE’s operating on a Clause In some examples, the Team of TA comprises one or more learning automata. In some examples, the learning automata are Tsetlin Automata. In some examples, all Boolean values are dual-rail encoded. In some examples, the array comprises: a top row of LPEs of identical construction and operable to receive input Boolean values for processing in to partial result values; and a bottom row of LPEs of identical construction and operable to output a class based on a final total clause derived from the partial clauses from the previous LPEs of the inner and top rows. In further examples, the array further comprises at least one inner row of LPEs of identical construction and operable to process the output of the top row of LPEs to form further HGF Ref: P341493WO partial result values. As such, the array may be of any size, and include the different type of LPEs as discussed in Figures 6 to 10. In some examples, the processing apparatus for a Tsetlin Machine further comprises SFFL logic, the SFFL logic comprising: a Clause-Sum logic block operable to process the Total-Clause values from the plurality of LPE chains in the LPE array based on a plurality of thresholds, to produce a Learned-Out value; a plurality of Clause feedback (FB_Clause) logic blocks; a total feedback logic block (FB_TM) to receive the Learned-Out value and an Expected-Out value, and produce Tsetlin Machine level feedback (FB_TM) values for use in the plurality of Clause feedback (FB_Clause) logic blocks; wherein the plurality of Clause feedback (FB_Clause) logic blocks operate across the 2D array horizontally, with each one of plurality of Clause feedback (FB_Clause) logic blocks operating on the Total-Clause output of one of the Chains of LPEs, using the FB_TM value, and a respective PRNG value, to form internal feedback specific to each chain of LPEs, said feedback guiding the Tsetlin Machine logic in its decision making process. In some examples, the Clause-Sum logic block is operable to compute Total-Clause according to equation (7) by means of inference logic elements 510 using equation (3). In some examples, the thresholds are the values s, T. In some examples, the Tsetlin Machine level feedback comprises Type I or Type II feedback. In some examples, the processing apparatus is formed using one hot signalling, and the feedback logic outputs may be formed from any one or more of the above described equations (8) – (19). Or variants based on different encoding methodologies used for the overall processing apparatus, data signalling used, or the like. In some examples, the Action values comprises Penalty, Reward or Inaction Action values, wherein the Penalty, Reward or Inaction Action data values are defined, on a bitwise basis, by any one or more of the following equations: "Reward"≝("Action-Include" ∧("Input-Data" ="Clause" )∧"Prob" )∨("Action-Exclude" ∧ ("Input-data" ≠"Clause" )∧"Prob"); "Penalty"≝("Action-Include" ∧("Input-Data" ≠"Clause" )∧"Prob" )∨ ("Action-Exclude" ∧("Input-Data" ="Clause" )∧"Prob"); "Inaction"≝¬"Prob". In some examples, the chain of LPEs comprises a team of N Tsetlin Automatons, where N is derived from the number of Features (L) and the number of Clauses (M) in use, specifically where N = 2 x L x M. In some examples, the at least one LPE is N-bit sliced, for example, one or more LPE is 1-bit sliced In some examples, the settings control values comprise thresholds values and Pseudo Random Number Generator values. In some examples, the processing apparatus comprises asynchronous logic to couple the plurality of LPEs together for communicating values between the LPEs and between the LPEs and input / output buses providing the input, outputs and other communications links for use within the processing apparatus. In some examples, the asynchronous logic comprises a ring communications architecture. In some examples, the values are Boolean values. In some examples, the feedback logic comprises one-hot encoding of Update commands values, Actions values, and Internal Feedback values. In some examples, the dual-rail representation of values in asynchronous circuits can operate with all- zero spacers or with all-one spacers. Some examples further comprise a data input, Expected-Out, providing an initial or expected classification decision of class to be reinforced or diminished during learning as the processing apparatus HGF Ref: P341493WO operates on the Literals and control values, for example during a classification process carried out by the processing apparatus. Examples provide an improved Tsetlin Machine architecture including an on-chip learning capability (i.e. the learning feedback function is baked into disclosed hardware architecture itself), thereby providing a hardware accelerated form of compute architecture for ML learning, which as a result may also provide improvements to efficiency (e.g. power usage, and the like), as well as scalability through use of a modular, tileable, processor design. In the foregoing, references to “value(s)” (i.e. singular or plural) are largely synonymous to refence to “data”, where that refers to data generally, and is not part of a specific name of a particular input, output, signal path or communications link, or otherwise. Communications links are also largely synonymous to (data) signal paths, or any other means to refer to data transfer means within the disclosed processing apparatus. While preferred embodiments of the present invention have been shown and described herein, in particular in the above numbered examples, it will be readily apparent to those skilled in the art that such embodiments are provided by way of example only. In any case, we explicitly state that this application has been drafted so that any of the disclosed subject matter / examples may be combined in any reasonable combination (i.e. other than is explicitly stated as not possible, or against the laws of physics) in order to arrive at any and all mixture of examples. Every reasonable combination has been considered, and is intended to be disclosed by this application, but has not been explicitly recited in order to not obfuscate the invention by means of an overly long and complex document, and in order to keep within the reasonable page limits set by numerous patent offices around the world. In particular, we categorically state no claim dependency is to be construed as the only combination that the disclosure contemplates and teaches overall. A particular example of this issue, is that, during prosecution, different one(s) of the dependent claims may be combined into the independent claim together with subject matter from yet further, different one(s) of the dependent even if there was no direct link of the dependencies before that combination (because it is not practical to explicitly list every combination in the usual claim dependency regime). This is to say that numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the scope of the disclosure. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in any combination in practicing the disclosure. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby. HGF Ref: P341493WO

Claims

Claims:

1. A processing apparatus for a Tsetlin Machine, comprising: at least one Learning Processing Element (LPE) comprising, and operable to use, Tsetlin Machine logic; a data input, operable to receive one or more Literals for use by the Tsetlin Machine logic of the at least one LPE; a settings input, operable to receive control values for the Tsetlin Machine logic of the at least one LPE; a data output; and internal data communications links, operable to couple the Tsetlin Machine logic of the at least one LPE to the data input, settings input and the data output of the at least one LPE; wherein the LPE is operable to output a class at the data output determined by the Tsetlin Machine logic based on the Literals and control values.

2. The processing apparatus of any claim 1, wherein the at least one LPE is tileable.

3. The processing apparatus of any preceding claim, wherein the processing apparatus comprises a plurality of LPE arranged in an array.

4. The processing apparatus of claim 3, wherein the processing apparatus comprises a plurality of LPEs arranged in a 2D array, wherein each vertical column of the array comprises a chain of LPEs, operable to apply Tsetlin Machine Logic to a determine a class based on Literals inputted into the vertical column.

5. The processing apparatus of any preceding claim, wherein the at least one LPE further comprises: an LPE instance specific set of inputs comprising: a data input to receive Input Data; a settings input to receive settings control values; an internal data input to receive internal data of the Tsetlin Machine logic from another LPE; and an Internal feedback input to receive Internal feedback data of the Tsetlin Machine logic; an LPE instance specific set of outputs comprising: a data output to output Output Data from the Tsetlin Machine logic; an internal data output to output internal data of the Tsetlin Machine logic to another LPE; and an internal data feedback output to output Internal feedback data of the Tsetlin Machine logic; and further data internal to the at least one LPE.

6. The processing apparatus of claim 5, wherein the further data internal to the at least one LPE comprises Update Commands data and Actions data.

7. The processing apparatus of any preceding claim, wherein the at least one LPE further comprises: HGF Ref: P341493WOan inference logic block operable to receive Input Data values, Action values, and partial result values from a previous LPE, and output Output Data values, and first Internal Data values indicative of partial result values for use by a subsequent LPE; a feedback logic block operable to receive Input Data values, Action data values, settings values and Internal Feedback values, and to provide Update Commands values, and second Internal Data values of indicative of partial result values for use by another, subsequent, LPE; and a Team of TA operable to receive the Update Commands values, settings values and to provide Action values to the inference logic block and feedback logic block.

8. The processing apparatus of claim 7, wherein partial result values comprises Partial Sum values and / or Partial Clause values.

9. The processing apparatus of claim 7 or 8, wherein the Team of TA comprises one or more learning automata.

10. The processing apparatus of claim 9, wherein the learning automata are Tsetlin Automata.

11. The processing apparatus of any of claims 3 to 10, wherein the array comprises: a top row of LPEs of identical construction and operable to receive input Boolean values for processing in to partial result values; and a bottom row of LPEs of identical construction and operable to output a class based on a final total clause derived from the partial clauses from the previous LPEs of the inner and top rows.

12. The processing apparatus of claim 11, wherein the array further comprises at least one inner row of LPEs of identical construction and operable to process the output of the top row of LPEs to form further partial result values.

13. The processing apparatus of claim 11 or 12, wherein the processing apparatus for a Tsetlin Machine further comprises SFFL logic (604), the SFFL logic comprising: a Clause-Sum logic block operable to process the Total-Clause values from the plurality of LPE chains in the LPE array based on a plurality of thresholds, to produce a Learned-Out value; a plurality of Clause feedback (FB_Clause) logic blocks; a total feedback logic block (FB_TM) to receive the Learned-Out value and an Expected-Out value, and produce Tsetlin Machine level feedback (FB_TM) values for use in the plurality of Clause feedback (FB_Clause) logic blocks; wherein the plurality of Clause feedback (FB_Clause) logic blocks operate across the 2D array horizontally, with each one of plurality of Clause feedback (FB_Clause) logic blocks operating on the Total- Clause output of one of the Chains of LPEs, using the FB_TM value, and a respective PRNG value, to form internal feedback specific to each chain of LPEs, said feedback guiding the Tsetlin Machine logic in its decision making process. HGF Ref: P341493WO14. The processing apparatus of any of claims 7 to 13, wherein the processing apparatus is formed using one hot signalling, and wherein the feedback logic outputs are formed from any one or more of the following equations: fbTAp= fbclauseT2^ ¬inc ^ c ^ ¬x ^ fbclauseT1^ inc ^ ¬c ^ ¬probs^ fbclauseT1^ ¬inc ^ c ^ x ^ probsfbTAr= fbclauseT1^ (inc ^ c ^ probs ^ ¬inc ^ (¬c ^ ¬probs ^ c ^ ¬x ^ probs) fbTAi= fbclausenone^ fbclauseT2^ (inc ^ ¬c) ^ fbclauseT1^ inc ^ (¬c ^ probs^ c ^ ¬probs) ^ fbclauseT1^ ¬inc ^ (¬c ^ probs^ c ^ ¬probs) fbTMnone= ¬learned-out fbTMT1= learned-out ^ expected-out fbTMT2= learned-out ^ expected-out fbClausenone= fbTMnone^ fbTMT1^ ¬probT ^ fbTMT1^ probT fbCl auseT1= ¬total-clause ^ fbTMT2^ ¬probT^ total-clause ^ fbTMT1^ probTfbClauseT2= ¬total-clause ^ fbTMT1^ probT^ total-clause ^ fbTMT2^ ¬probT15. The processing apparatus of any of claims 7 to 14, wherein the Action values comprises Penalty, Reward or Inaction Action values; wherein the Penalty, Reward or Inaction Action data values are defined, on a bitwise basis, by any one or more of the following equations: "Reward"≝("Action-Include" ∧("Input-Data" ="Clause" )∧"Prob" )∨("Action-Exclude" ∧("Input-data" ≠ "Clause" )∧"Prob") "Penalty"≝("Action-Include" ∧("Input-Data" ≠"Clause" )∧"Prob" )∨("Action-Exclude" ∧("Input-Data" ="Clause" )∧"Prob") "Inaction"≝¬"Prob" 16. The processing apparatus of any of claims 4 to 15, wherein the chain of LPEs comprises a team of N Tsetlin Automatons, where N is derived from the number of Features (L) and the number of Clauses (M) in use, specifically where N = 2 x L x M.

17. The processing apparatus of any preceding claim, wherein the at least one LPE is N-bit sliced.

18. The processing apparatus of claim 17, wherein the at least one LPE is 1-bit sliced. HGF Ref: P341493WO19. The processing apparatus of any preceding claim, wherein the settings control values comprise thresholds values and Pseudo Random Number Generator values.

20. The processing apparatus of any of claims 2 to 19, wherein the processing apparatus comprises asynchronous logic to couple the plurality of LPEs together for communicating values between the LPEs and between the LPEs and input / output buses providing the input, outputs and other communications links for use within the processing apparatus.

21. The processing apparatus of any preceding claim, wherein the asynchronous logic comprises a ring communications architecture.

22. The processing apparatus of any preceding claim, wherein the values are Boolean values.

23. The processing apparatus of any of claims 7 to 22, wherein feedback logic comprises one-hot encoding of Update commands values, Actions values, and Internal Feedback values.

24. The processing apparatus of any of claims 7 to 23, wherein all Boolean values are dual-rail encoded.

25. The processing apparatus of any preceding claim, further comprising a data input, Expected-Out, providing an initial or expected classification decision of class to be reinforced or diminished during learning as the processing apparatus operates on the Literals and control values. HGF Ref: P341493WO

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