Microdisplay

Abstract

The invention relates to a microdisplay architecture (10) with the following features: an optical plane (20) with a plurality of pixel elements; and a circuit plane (30) on which the optical plane (20) is arranged, wherein the circuit plane (30) comprises one or more interfaces (32a, 32b), a pixel matrix actuator (34), and an image memory (36) for actuating (34) the plurality of light-emitting or light-modulating elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) in dynamically selectable operating modes.

Description

[0001] Microdisplay

[0002] Description

[0003] Embodiments of the present invention relate to a microdisplay and to an operating method. Preferred embodiments relate to a microdisplay with at least one memory-based operating mode. Further embodiments relate to a microdisplay with a leakage circuit. According to embodiments, the operating method can be computer-implemented. In general, the invention lies on the path of scalable microdisplay architectures.

[0004] Microdisplays are displays with a typical display diagonal of 0.1" to typically 1.5", and some selected ones even up to 2.5". Such microdisplays are usually stacked, i.e. the control circuit is located directly beneath (hence also referred to as the backplane below) the elements to be controlled (hereinafter collectively referred to as the frontplane). Depending on the application and optical use of the microdisplay, the elements to be controlled can be a layer system for the realization of an organic LED, an inorganic LED or even an LC material. Accordingly, one speaks of an OLED microdisplay, a micro-LED microdisplay (also commonly written as uLED or pLED) or an LCOS (liquid crystal on silicon) microdisplay.

[0005] The control circuit is adapted to the specific properties of the element to be controlled. Examples include: precise electrical control in the typical voltage range of 3V or higher, good current injection into the layer and measures for aging compensation in OLED microdisplays, and high current densities of > 1A / cm 2 for uLED microdisplays or no static current flow into the element to be controlled in LCOS microdisplays.

[0006] To implement an active matrix display, the backplane contains circuit components such as transistors, capacitors, or resistors. These can be implemented using various technologies. Examples include thin-film transistors (TFTs such as IGZO, a-Si, or LTPS) or implementation in monocrystalline silicon. The following explanation will be based, without limitation, on monocrystalline silicon with CMOS circuit technology (others are also conceivable). However, due to the ongoing advancement of TFT miniaturization, partial implementation using TFTs is also conceivable in the future.

[0007] Microdisplays based on a silicon backplane are currently mainly realized in the technology nodes 0.25um...90nm.

[0008] A distinction can be made between different control variants for microdisplays, whereby the architecture, i.e. the system architecture and pixel architecture, usually differs depending on the control variant. The vast majority of microdisplays are driven by a video stream with a constant refresh rate, e.g., a video data stream with 30Hz, 60Hz, 90Hz, 120Hz, or 240Hz. In the following, this type of architecture is referred to as "refresh rate-based architecture." There are few control schemes that deviate from this - one example is [1], which presents an architecture for the partial update of pixels (hereinafter always describes the smallest element that can be controlled independently of others). In the following, this type of architecture is referred to as "memory-based architecture."

[0009] The selected architecture is understood in conjunction with the technological platform, since, especially with microdisplays, the space requirements for the respective architecture are such that not every system or pixel architecture can be manufactured with every technological platform.

[0010] What all of these architectures have in common so far is that, in addition to the control circuit for the optical elements, they contain a row and column decoder as additional circuit blocks, possibly a DAC functionality for "translating" the digital pixel data into current and voltage values ​​for the pixel, as well as a block for implementing a display data interface (parallel interface, LVDS, SPI, or similar) depending on the above-mentioned control principle.

[0011] This dependency results from the required data bandwidth:

[0012] For example, a "refresh rate-based architecture" requires a much higher data rate because all display pixels are constantly overwritten - even if this is not necessary because, for example, the value of the pixel has not changed at all. Typically, a parallel interface (i.e., parallel digital, single-ended lines which together transmit the data value of the pixel or multiple pixels, as well as additional control lines, also known as digital RGB) or serial transmissions (e.g., LVDS low-voltage differential signaling) are used here. Such systems require quite complex external video control electronics which implement the conversion to the aforementioned interfaces. This is usually done using a separate integrated circuit or an FPGA.This increases the required power consumption and the installation space (and thus has a detrimental effect on the ergonomics of a system) - both factors that are of great importance in numerous mobile ("wearable") applications.

[0013] For the "memory-based architecture," however, simply transmitting the changing pixels is sufficient. Depending on the application, this significantly reduces the required transmission bandwidth, allowing less complex interfaces, such as SPI, to be considered. An example of this can be found in [1]. In each of these cases, a customized control circuit is required.

[0014] State-of-the-art microdisplays have pixel sizes in the range of 4.3um x 4.3um ... 6.3um x 2.1um ... 9.3um x 3.1um.

[0015] The object of the present invention is to create a microdisplay architecture that provides an improved compromise between flexibility of control, flexibility of display performance, flexibility of combination with different display technologies, energy efficiency and cost efficiency.

[0016] The problem is solved by the subject matter of the independent patent claims.

[0017] Embodiments of the present invention provide a microdisplay architecture with an optical layer and a circuit layer. The optical layer, oriented upwards in the explanation, comprises a plurality of light-emitting or light-modulating elements, which are arranged, for example, in an nxm pixel matrix. The underlying circuit layer consists of various circuit components, but at least one circuit group for controlling the individual optical elements (also called pixel circuitry), a programming circuit for the circuit groups assigned to the individual optical elements (also called pixel matrix control), an integrated image memory, and one or more interfaces, such as wired and wireless interfaces. According to embodiments, the pixel control comprises a switch and a driver for each pixel.

[0018] According to further embodiments, the use of smaller technology nodes (e.g., <90 nm) can enable the integration of more functionality directly into the backplane (circuit level). This is accompanied by a significant simplification of the system architecture if the previously external connections to layered standard display interfaces can be replaced, allowing the interfaces to be integrated directly into the backplane.

[0019] According to further embodiments, the use of small technology nodes (e.g., <90 nm) and a special pixel circuit can make it possible to realize very small pixels, for example, 3.5 um x 3.5 um, 3 um x 3 um, 2.5 um x 2.5 um, 2 um x 2 um, or smaller. The individual pixels do not necessarily have to be square. For example, it may be advantageous to design them in a rectangular (so that 3 pixels combined in a group, e.g., consisting of a red, green, and blue pixel, again form a square) or hexagonal shape.

[0020] According to further embodiments, the pixel matrix controller can be configured to control the plurality of light-emitting / modulating elements using a refresh rate-based operating mode or a memory-based operating mode. Preferably, the operating mode is switchable (e.g., depending on the application or current area of ​​use).

[0021] Embodiments of the present invention are based on the realization that the use of a highly scaled technology (e.g., <90 nm) allows the circuits of the external components to be integrated directly into the backplane, eliminating the need for additional driver circuits. The integration of a framebuffer into the backplane enables the microdisplay to be operated as a "memory-based architecture" or as a "refresh-rate-based architecture" as needed. The definition of memory-based architecture or refresh-rate-based architecture is given above in connection with the prior art and applies here. As a result, the aspects of technological platform, system architecture, and pixel architecture go hand in hand and create the following advantages or the basis for achieving the following advantages:

[0022] • Drastic simplification of the complexity of the system architecture

[0023] • Significantly reduced AVT complexity (assembly and connection technology) by utilizing integration options for external components (such as framebuffer, CPU / GPU, wireless interface, etc.)

[0024] • This results in cost savings as well as 300mm wafer processes which are standard for <90nm technologies (more chips per wafer), such as 65nm, 45nm, 32nm, 28nm, 22nm, 12nm, and smaller

[0025] • Realization of extremely high frame rates through highly parallel image memory connected to the pixel matrix

[0026] • Flexible architecture for controlling a wide variety of frontplane technologies OLED / uLED (common cathode, common anode) and LCOS

[0027] • Flexible adaptation of the power consumption to the application by switching off building blocks or adapting the control

[0028] According to the exemplary embodiments, the above-defined backplane (circuit level) can be combined with different frontplane architectures (OLED, uLED, LCOS) and used to control them. This creates a flexible architecture for controlling a wide variety of frontplane technologies: OLED / uLED (common cathode, common anode) and LCOS.

[0029] According to embodiments, the circuit level or the backplane can directly comprise the circuits or circuits of the one or more interfaces, the pixel matrix control and the image memory. This means that the circuits or circuits of the one or more interfaces, the pixel matrix control and the image memory are directly integrated into the circuit level. Thus, an integrated circuit is arranged in the circuit level, i.e., an integrated circuit in the form of the backplane with the mentioned functional blocks is created. According to further embodiments, additional, i.e., one or more additional functional blocks can be present as additional components of the integrated circuit. Each of the functional blocks shown, for example, in Fig. 6 would in principle be suitable for this purpose. In this respect, a further embodiment creates a circuit level orBackplane with circuits or an integrated circuit comprising the functional blocks interface, pixel control and image memory as well as one or more further functional blocks from the example in Fig. 6.

[0030] According to the examples, the upscaled technology also allows for a small pixel cell. The main driver for this requirement is always higher resolution. Furthermore, thanks to a flexible design of the overall architecture, the backplane can be used for a wide variety of frontplane architectures.

[0031] According to embodiments, the microdisplay architecture comprises not only one but also multiple interfaces, e.g., multiple interfaces of different types (wired and wireless) and / or multiple interfaces of different bandwidths.

[0032] Examples of suitable wired interfaces include HDMI, DisplayPort, MIPI, Thunderbolt, and USB. Furthermore, the direct integration of wireless interfaces into the backplane is conceivable – examples include Bluetooth, Wi-Fi, openThread, LoRaWAN, AirTag, and RFID. A third possibility, according to exemplary embodiments, with suitable circuit complexity on the display, is the transmission of information instead of video data. The information is then displayed directly on the display, for example, on suitable hardware (e.g., an integrated GPU / CPU) and, if appropriate, only in the required display areas currently being used for display (foveated rendering). What all examples have in common is that they dramatically simplify the remaining system electronics and thus reduce power consumption, any bandwidth required to be transmitted, the form factor, and thus the system costs.

[0033] Furthermore, according to embodiments, the integration of multiple interfaces directly into the backplane results in adaptation to a wide variety of systems, which represents a significant cost advantage, since multiple system applications can be served with the identical integrated backplane circuit, and in the semiconductor industry, pricing is highly dependent on unit volume. Furthermore, the implementation of multiple interfaces according to embodiments leads to the possibility of flexibly adapting the interface to the current operating mode. According to embodiments, the selection of the transmission interface or the corresponding transmission mode depends on the selected operating mode.For example, in a memory-based operating mode, a low-bandwidth interface such as a Bluetooth interface may be used, while in a refresh-rate-based operating mode, a higher-bandwidth interface such as an Ml Pl interface may be used.

[0034] According to embodiments, not only pixel data can be transmitted via the interface of the microdisplay chip. Rather, the abstract transmission of information to be displayed can occur if the pixel data is generated directly by integrating a suitable CPU / GPU in the backplane. By transmitting information instead of individual pixel data, the required bandwidth of the interface can be significantly reduced, which brings advantages to the system (reduced power consumption, reduced complexity of external circuit components and thus system costs). The CPU / GPU can be switched off or put into sleep mode, for example, when the memory-based operating mode is activated. This allows for flexible adaptation of power consumption to the application by switching off components or adapting the control.

[0035] According to embodiments, this conversion of information into display data can occur directly in the display backplane for all pixels or only for a portion of the pixels that currently contribute to the actual display (so-called foveated rendering). By generating only the display data that is actually used in the backplane, a flexible adaptation of power consumption to the application is possible.

[0036] According to embodiments, regions of the microdisplay architecture, i.e., multiple light-emitting / modulating elements assigned to a first group and multiple light-emitting / modulating elements assigned to a further group, can be operated in different ways (different sequences and / or amplitudes) or even in different operating modes (simultaneous control of different regions in video / memory mode). This means that a first display part, or display region by region, is operated in a refresh rate-based operating mode, while another display part is operated in a memory-based operating mode. It is also conceivable that only parts of the display are operated at the current time.All of these measures advantageously serve to increase energy efficiency, as the overall power consumption is reduced by switching off components or display areas, or even operating display areas in a more energy-efficient operating mode. A key difference between the various operating modes is the update rate. This can be varied according to the exemplary embodiments. For example, a 1 Hz update rate can be used for the memory-based operating mode (low update rate), or if the display content remains the same, an update of the data can even be dispensed with entirely, i.e. a frame rate of 0 Hz can be used (equivalent to no activity on the external interface and the associated extreme energy savings), while higher update rates, e.g. 30 Hz, 60 Hz, 90 Hz or even >120 Hz, are used for the refresh rate-based operating mode.In general, the update rate is variable, i.e., it can be varied in a range of >30, >60, >90, or >120 Hz. Adapting the frame rate to the application's needs also allows for flexible adjustment of the power consumption, since higher frame rates are associated with higher power consumption.

[0037] By using the memory, local frame rate adjustment (from input to output of the memory) as well as advanced processing (insertion of intermediate frames) can be performed.

[0038] At this point, it should be noted that there is a difference between frame rate, which refers to the provision of new data on the input side of the frame buffer, and frame refresh rate, which describes the transfer rate of the frame buffer data to the pixels on the output side of the frame buffer. According to embodiments, a first refresh rate can be applied to the pixel control and frame buffer on the input side, and a second refresh rate can be applied to the output side, with the second refresh rate being at least the same or higher.

[0039] According to exemplary embodiments, the data transmission from the integrated image memory is designed with a very high bandwidth. This is made possible by the direct integration of the memory into the backplane, especially when using small technology nodes (<90 nm). This allows for significantly higher refresh rates, e.g., 240 Hz, 480 Hz, 1 kHz, 5 kHz, 10 kHz, 20 kHz, 50 kHz, 100 kHz, or higher. Adapting the refresh rate to meet application requirements also allows for flexible adjustment of power consumption, since higher refresh rates are associated with higher power consumption.According to embodiments, the transfer of data from the image memory to the pixels is carried out by a freely programmable cyclic transfer mechanism (also called sequence), which, in addition to the transfer of the data itself, enables extended processing such as the insertion of generically generated data frames (without using data from the image memory, such as black images) and delaying elements for the temporal weighting of the currently displayed data.

[0040] According to embodiments, individual pixel subgroups can be controlled with different sequences (and / or different amplitudes). Different operating modes are achieved through different sequences and / or different amplitudes. This allows individual groups of optical elements to be controlled differently (including, but not limited to, the individual insertion of generically generated data frames and delay elements), thus enabling the optical characteristics of these pixel subgroups to be tuned (e.g., tuning of red, green, and blue subpixels for white point adjustment).

[0041] According to another embodiment, it is also conceivable for the bit depth, e.g., the bit depth that describes the brightness / grayscale per light-emitting / modulating element or the color per light-emitting element with subpixels, to be variable. Some applications require high color / grayscale resolutions, so a high bit depth is desired, while individual bit levels can be deactivated for other applications. This reduces computational effort and thus increases energy efficiency.

[0042] At the CMOS technology nodes below 90nm mentioned above, leakage currents are increasingly occurring, which can be compensated for by a leakage circuit at the circuit level, thus leaving no impact on the optical level. Therefore, according to further embodiments, the microdisplay architecture includes a leakage circuit at the circuit level of the microdisplay architecture. According to some embodiments, this circuit can comprise two additional transistors.

[0043] At this point it should be noted that, according to embodiments, the image memory can be implemented completely in the pixel, partially in the pixel, or even outside the display pixels but within the same integrated circuit. In the minimal configuration, a 1-bit memory per pixel is integrated in the pixel control circuit. Of course, several 1-bit memories, i.e. a memory with a greater memory depth, can be provided per pixel. The greater memory depth can also be achieved by arranging the additional bits outside the display pixels but within the same integrated circuit (memory partially integrated in pixels). According to embodiments, the image memory can be switched off partially, completely, or gradually.Especially in the variant explained above according to the exemplary embodiments, with different bit depths depending on the operating mode or application, the gradual shutdown is useful, as it eliminates the need for the entire memory space per cell. According to the exemplary embodiments, the memory can also be bypassed, e.g., for the refresh rate-based operating mode.

[0044] From a geometric perspective, according to embodiments, a pixel extends both in the circuit level and in the optical level. In the circuit level, each pixel comprises, for example, a driver (per pixel) and one or more memory cells (per pixel). In the optical level, one optical element, such as an OLED, is provided for each pixel.

[0045] Two different embodiments for the optical layer are explained below. One variant uses a so-called common anode circuit, while another variant can be implemented using a common cathode circuit.

[0046] According to embodiments, the plurality of light-emitting elements are implemented as a common cathode circuit. Here, the pixel control for each light-emitting element can be implemented as follows: the pixel control has a transfer gate and a driver (in the simplest case, an inverter), wherein the driver switches an LED with a common electrode to the reference voltage Vref; for example, the pixel matrix control is designed to lower the reference voltage V re f or by increasing the pixel voltage V PjXiTo increase the brightness; in general: the difference Vpix - Vref is changed to change the brightness of the light-emitting / modulating elements. Alternatively, the control system is designed to control different light-emitting elements or pixel sub-elements using different pixel voltages.

[0047] According to embodiments, the multiple light-emitting elements of the microdisplay architecture are designed as a common anode circuit. Here, the pixel matrix control can be configured to control a common anode as a counter electrode with the same backplane. For brightness control: for example, the pixel matrix control is configured to increase the reference voltage V re f or by lowering the pixel voltage V PjX to increase the brightness.

[0048] According to embodiments, individual pixel subgroups can be controlled with different pixel voltages / currents. This allows individual groups of optical elements to be controlled with different voltages, thus enabling the optical characteristics of these pixel subgroups to be tuned (e.g., tuning of red, green, and blue subpixels for white point adjustment).

[0049] Another embodiment of a further aspect provides a microdisplay architecture with an optical layer and a circuit layer. The optical layer has a plurality of light-emitting / modulating elements. Furthermore, the circuit layer includes a leakage compensation circuit. According to embodiments, this circuit may include two additional transistors. According to embodiments, the microdisplay architecture has a technological platform <90 nm.

[0050] Implementation variants discussed in connection with the main aspect can of course also be used for this additional aspect.

[0051] Another embodiment provides a method for operating a microdisplay architecture. The method comprises the steps:

[0052] Operating the pixel matrix control in memory-based mode using the image memory; or

[0053] Operating the pixel matrix drive in a memory-based operating mode using the frame buffer or operating the pixel matrix drive in a frame rate-based operating mode.

[0054] According to embodiments, the method can of course also be computer-implemented, e.g., as software on the playback device that instructs the display architecture to activate the respective operating mode. Embodiments of the present invention are explained with reference to the accompanying drawings. It shows:

[0055] Fig. 1 is a schematic representation of the cross section of a microdisplay structure according to a basic embodiment;

[0056] Fig. 2 is a schematic representation of a simple basic pixel circuit for explaining embodiments;

[0057] Fig. 3a shows a schematic representation of a circuit implementation of a simple basic pixel circuit (variant with common cathode front plane) according to embodiments;

[0058] Fig. 3b shows a schematic representation of a circuit implementation of a simple basic pixel circuit (variant with common anode front plane) according to further embodiments;

[0059] Fig. 4 shows a schematic representation of a circuit implementation of a simple basic pixel circuit with leakage current compensation according to further embodiments / in further aspects;

[0060] Fig. 5 is a schematic representation of a complex example of a pixel cell with (partial) implementation of the frame buffer in the pixel cells according to embodiments; and

[0061] Fig. 6 is a schematic block diagram of a flexible microdisplay architecture according to embodiments.

[0062] Exemplary embodiments of the present invention are explained below with reference to the figures. It should be noted that similarly functioning elements and structures are provided with the same reference numerals, so that the descriptions of them are applicable to one another and interchangeable.

[0063] Fig. 1 shows a schematic representation of a microdisplay architecture 10. This comprises an optical plane (frontplane) 20 and a circuit plane (backplane) 30. The optical plane 20 is arranged on the circuit plane 30. The optical plane 20 has a plurality of optical elements. These can be arranged, for example, side by side or preferably in an n×m pixel matrix, i.e., in a planar arrangement.

[0064] The circuit level 30 has a pixel matrix control 34 and a memory, such as a frame memory 36. The pixel control can be provided for each pixel (cf. 34a-f) and thus form a direct coupling / geometric relationship to the light-emitting elements 22a, 22b, 22c, 22d, 22f. For example, a driver can be provided for each element 34a-f. The memory 36 can also have one or more memory cells per pixel. The memory is designed as a minimum as a 1-bit memory (1 bit per pixel), but can also comprise multiple memory cells per pixel (e.g., 8 bits). The memory is primarily implemented as an internal memory. It can also be partially external, i.e., several memory cells are arranged externally for each pixel. The internal memory cell is arranged, for example, in the pixel area itself. The external memory cell can, for example, be provided in the edge regions of the same integrated circuit.

[0065] In addition, the backplane 30 has one or more interfaces, such as communication interfaces, each designated by reference numerals 32a and 32b. It should be noted that interface 32b is an optional interface.

[0066] The controller 34 can either directly control the plurality of light-emitting elements 22a-22f using refresh rate-based operation or control the plurality of light-emitting elements using the memory 36 in the memory-based operating mode. The processors for the memory-based operating mode and the transfer rate-based operating mode can be separate from one another, i.e., individual processors can be provided for the individual modes, so that—if the respective mode is not activated—the corresponding processor is deactivated or placed in standby mode. This makes it possible to save power. The information to be displayed using the plurality of pixels 22a-22f is received via the one or more interfaces 32a and 32b, e.g., in a directly displayable data format (image stream) or as a "compressed" data format.The interfaces 32a and 32b typically have different bandwidths, so that the data rates to be transmitted vary. For example, a higher data rate is required in the refresh rate-based mode than in the memory-based mode, since in the latter only the changes to the image need to be transmitted. According to embodiments, only one piece of information can be transmitted, which is then converted into an image using a GPU. The control 34 can be expanded by a GPU / CPU, which serves as an alternative interface and can thus, for example, graphically display information played externally using the arrangement 10. The control of the individual light-emitting elements 22 takes place as shown, for example, in Fig. 2.

[0067] To illustrate this advantage, a microdisplay 10 with a MIPI interface 32a and a Bluetooth interface 32b will be discussed in a maintenance scenario when used in smart glasses. This scenario begins with the assignment of a task (including work order and work location) to a maintenance technician. The smart glasses are then supposed to show the maintenance technician the way to the work location. The display is therefore responsible for transmitting the corresponding route instructions to the smart glasses. In this operating mode, the information on the display changes only within a very small range (for example, directional arrows and the time are displayed) and at a very moderate frequency (a display update at 1 Hz is perfectly sufficient).The data can thus be easily supplied via Bluetooth directly from the maintenance technician's mobile phone or via a GPS / Galileo / GLONASS / Beidou (or similar satellite navigation systems) module integrated into the microdisplay architecture, along with the associated data processing and display unit (CPU / GPU). Finally, the critical work location is reached. Since the maintenance technician is responsible for various systems, they require appropriate technical support from an expert from the central support center. For this video call and maintenance support, a complete video must be shown on the microdisplay in the data glasses, meaning that all of the display's pixels must be described. Furthermore, for satisfactory interaction, this must be presented at a high refresh rate of at least 60Hz, 90Hz, 120Hz, 240Hz, or more.The data for this comes, for example, via a MIPI interface 32a from an external mobile processor. Following the support agent's instructions, the task can be completed, the call is terminated, the entire data processing pipeline of the video call, including the mobile processor, can return to idle / standby mode, and navigation to the next location continues.

[0068] This scenario demonstrates the advantage of the different operating modes according to the invention when it is possible to flexibly switch between a "memory-based architecture" (e.g., in the navigation case, with few image changes at a low refresh rate, or even idle data transmission with no changes in the display) and a "refresh rate-based architecture" (in the support case, when displaying a video, or during latency-critical interaction). In a portable system, any advantage in power consumption is particularly exponentially increased, since the system can be used for longer between charging cycles, or a smaller energy storage device can be integrated into the system, thereby reducing the size and / or weight of the system, which in turn improves the ergonomics of the system. This represents a significant system requirement in a portable system.

[0069] The data from the standard interface 32a / b (wired or wireless) is received and stored in a frame buffer 36. Implementing a complete frame buffer with a memory depth of 8 bits per pixel or more was previously not possible, as the memory would have taken up too much of the chip in technologies typically used for microdisplays >90nm or would have led to a dramatic increase in chip size, resulting in fewer chips on a wafer and, in turn, an excessive increase in the cost per individual backplane chip. This changes dramatically with smaller process nodes <90nm, as the memory density (i.e., realizable memory cells per area) increases significantly with smaller process nodes.

[0070] For example, the frame buffer (also known as image buffer) acts as a crucial intermediary between the flexible external circuit architecture of the standard 32a / b interface and the internal control of the pixels. The image buffer can be implemented outside the pixels, partially within the pixels, or even entirely within the pixel.

[0071] Implementation entirely in the pixels generally results in larger pixels (e.g., as dynamic memory (DRAM), static memory (SRAM), or non-volatile memory (NVRAM), since a driver circuit must be integrated in addition to the memory. However, this inventive architectural variant requires less circuitry outside the matrix. Likewise, cyclic data transfer to the pixels is eliminated.

[0072] In contrast, there is the second pixel variant, in which the circuit complexity of the pixel is reduced to a minimum, thus enabling a very small pixel (i.e., the highest pixel density and thus a higher resolution on a given microdisplay area). Such a minimally reduced pixel circuit contains only a switch that separates the actual driver from the column line (see Fig. 2). In certain applications, the driver can also be a simple storage element (e.g., a capacitor).

[0073] Fig. 2 shows a light-emitting element with associated pixel control, here, for example, with a common electrode (common cathode / anode electrode of the optical elements). The light-emitting or light-modulating element 22 is controlled by a driver 34t, which in turn is programmed and controlled by the column data via a row selection switch. The switch is designated by reference numeral 34sw. Switch 34sw receives a corresponding signal for row selection.

[0074] A circuit implementation of these basic elements is shown in Fig. 3a. In this example, the switch 34sw is implemented by a transfer gate and the driver by an inverter 34t. In the front-plane element, a light-emitting diode 22' (corresponding to 22 with a common cathode circuit) is assumed to act as the load, which is connected to a common electrode V ref is connected. In this representation, the common electrode is a common cathode, i.e. a so-called "common cathode", since the (O)LEDs 22' of all pixels have a common cathode as a counter electrode.

[0075] In this example, the global brightness can be adjusted in two different ways: lowering the Vref or raising the Vpixl voltage. To achieve this, both voltages are implemented separately and can also be controlled separately. For correct control of the pixel cell, adjusting Vpixl also adjusts the column voltage levels on the vertical data lines (corresponding to the implementation of voltage converters / level shifters in the column header of the pixel matrix). In a version with a statically fixed pixel voltage, this can be omitted - in which case a global brightness setting is possible, for example, by adjusting the sequence - e.g. by inserting black images or controlling the common electrode. It should be noted at this point that when using a CPU / GPU or.the integrated pixel matrix control in the circuit level these black images can also be generated locally and thus do not have to be transmitted externally.

[0076] In a further embodiment, it is also conceivable for pixels which are provided with different frontplane elements to be designed with differently adjustable Vpixl,1, Vpixl,2, Vpixl,3, etc. This is particularly useful when different electrical control parameters are required for the different frontplane elements. An example of this is the design of red, green and blue frontplane elements with different electrical characteristics, which can be suitably controlled by the separate design. Furthermore, the brightness of the individual pixels and thus, for example, also the white point of the microdisplay can be adjusted using these different setting options. The same advantages arise for the separate design of the Vref in the form Vrefl,1, Vref1,2, Vrefl,3, etc.

[0077] Likewise, the inventive embodiment allows for individual control of different pixel groups, which in turn are assigned to different and independently adjustable sequences. This embodiment also makes it possible to adjust different groups of front-plane elements (e.g., different current efficiency) independently of one another (for example, as previously described for the white point adjustment of R, G, and B pixels).

[0078] However, according to embodiments, a "common anode" design, i.e. a front plane with a common anode as the counter electrode, can also be controlled with the same backplane. This is shown in Fig. 3b using the circuit of 22" (22" corresponds to 22 with a common anode circuit). In such an arrangement, the voltage of the common counter electrode is in the positive range (cf. Fig. 3b), i.e. brightness control can be achieved by raising Vref or lowering Vpix2. It is obvious that the digital data in a "common anode" design must be inverted compared to the data of a "common cathode" design. According to embodiments, this can be done either in the column header or before saving in the frame buffer. Furthermore, the implementation of different voltages for separate pixel groups, as explained above, can also be implemented in an adapted form for the "common anode" design.The same applies to pixel groups that are designed differently with regard to the sequence as before.

[0079] In both cases, this simplified pixel cell implements only two states—referred to below as "on" and "off." To implement grayscale, a temporal pulse sequence of "on" and "off" states must be written into the pixel cell. This temporal sequence is implemented by a programmable sequencer. This sequencer controls both the reading of the correct data from the framebuffer and the correct selection of the display line corresponding to the data. The more grayscale resolution requires, the more transfers are required, as well as a larger framebuffer. According to exemplary embodiments, this is designed to meet the maximum requirements.In applications with lower bit depths (e.g., the display of navigation instructions does not require 8 bits or more of resolution per color channel), the inventive flexible architecture includes the option of gradually switching off the unused memory cells of the framebuffer (e.g., from 16 bits to 8 bits per pixel, 8 bits to 4 bits, or even 13 bits to 7 bits, etc.). This also results in an adapted sequence for transmitting data from the framebuffer to the pixels, since fewer "on" and "off" states need to be implemented. Both of these are associated with considerable savings in power consumption and underline the flexibility of the inventive, new architecture. While maintaining the same transmission frequency but with a shorter sequence length for the transmission from the framebuffer to the pixels, a higher frame rate is enabled by reducing the bit depth.

[0080] The above explanation assumes light-emitting elements such as OLEDs or uLEDs. Alternatively, a light-modulating element such as LCOS can also be used.

[0081] The above embodiments from Figs. 3a and 3b can thus be summarized in such a way that a switch 34sw, for example implemented by a transfer gate, and a driver 34t, for example implemented by an inverter, can be provided for each pixel or pixel group to be controlled. The light-emitting diode (for example, an OLED or LED) is coupled to the output of the inverter and thus has an anode or common cathode. In the case of LCOS (light-modulating element), cyclic polarity reversal occurs.

[0082] Depending on the nature of the technology, additional transistors in this simplified pixel cell are useful. Since these exemplary embodiments particularly refer to technologies with smaller feature sizes (required for the inventive implementation of flexible interface modules, the frame buffer, and others), another embodiment of the pixel cell is presented here. Smaller technology nodes are characterized by so-called leakage currents (e.g., drain-source leakage current, gate leakage current, or bulk leakage currents). These parasitic currents generally increase with more advanced technology nodes and, in pixel cells according to the state of the art, lead to an unwanted current flow through the optical element and thus possibly to a reduced contrast ratio (since the optical element cannot be completely switched off).Furthermore, the previous example pixel cell assumed that the inner node of the pixel cell retains the stored digital value after programming. Due to the previously discussed leakage currents, this may only be the case for a limited time and also depends largely on the circuit conditions (such as pixel voltage and temperature). Fig. 4 therefore shows a pixel circuit expanded by two transistors 29 to compensate for these leakage currents. The two transistors 29 form a leakage current compensation circuit.

[0083] The two transistors of the leakage compensation circuit 29 have a common control electrode coupled to the output of the inverter. The transistors coupled back to the input node of the driver compensate for the leakage current. The optical element 22 is controlled by the inverter 34t.

[0084] In addition, they ensure that leakage currents (e.g., from the driver) are dissipated through the circuitry and not flowing through the front plane. For example, this leakage current compensation circuit ensures two crucial properties of the new architecture:

[0085] - A good contrast ratio even with increasing leakage currents: Leakage currents conducted through the frontplane element lead to a distortion of the control, especially in the desired "off" state of the pixel cell, and thus to a "residual glow" of the pixels even in the "off" state, thus reducing the crucial parameter of a microdisplay: the contrast ratio. This is thus avoided.

[0086] - Permanent preservation of the state of the pixel cell: The two additional transistors 29 ensure that the programmed state is maintained even over a longer period of time.

[0087] Referring to Fig. 5, the control of an optical element 22 by means of the driver 34t and a readout amplifier 24 implemented in the pixel control for the memory elements (36a-d) also implemented in the pixel is explained. The switches 34sw are connected to the eight memory cells 36a, 36b, 36c, and 36d shown as examples per pixel. The eight memory cells 36a-36d enable the implementation of an 5-bit memory. These memory cells can, of course, be supplemented by additional pixel-internal and external memories (but integrated in the same circuit). Here, the memory cells are (partially) implemented directly in the pixel cell. The readout amplifier 24 (for DRAM embedded in the pixel) can be provided between the memory cells 36a-36d and the driver 34t.

[0088] Referring to Fig. 6, functional blocks belonging to the front plane of the display architecture (see reference numeral 20) as well as the circuit level of the display architecture (see reference numeral 30), and in particular the control 34, will now be discussed in detail. Fig. 6 shows a block diagram of a flexible microdisplay architecture. This primarily comprises the pixel array 22p, which is controlled as a matrix via a row driver 23l and a column driver 23r. Furthermore, Fig. 6 shows further functional blocks for controlling the pixel area 22p. The pixel area 22p comprises elements for each pixel at the circuit level, such as drivers 34t and switches 34sw, as well as the light-emitting elements 22 at the optical level.

[0089] According to embodiments, the circuit level includes a column driver 23r and / or a row driver 23l. These are both controlled via a sequencer 34sq and a data flow controller. The data flow controller / sequencer 34sq provides interfaces to the control unit 34 and the memory 36, respectively.

[0090] The controller 34 may additionally comprise functional blocks that may be implemented either in software or in hardware, i.e., as separate components or separate circuit groups, such as configuration unit 34k, processor (CPU) or graphics processor (GPU) 34p, white balance 34w, external synchronization unit 34s, pad array for the wired interfaces 32a, power management 34pwr, temperature sensor 34temp, test pattern generator 34tg, test unit 34test, and internal clock 34cl. These units are to be understood as optional units, so they may occur separately.

[0091] The functionality of the elements just listed is explained below. According to exemplary embodiments, the flexible architecture also includes the pure 1-bit display mode. In this case, according to exemplary embodiments, the use of the framebuffer can be completely eliminated even for this simple pixel, since there is no need to store data in the framebuffer, as the pixel cell stores the value until new data is received. To enable complete disabling of the framebuffer, this mode offers the option of programming the pixels by direct writing, i.e., bypassing the framebuffer.

[0092] For the implementation of the partial integration of the framebuffer into the pixel cell (with more than 1 bit), the limit of the part of the framebuffer implemented in the pixel cell therefore applies.

[0093] The connection of the framebuffer 36 to the pixel matrix (cf. 23I and 23r in Fig. 6 or also Fig. 2, column R and row Z) is explained below. The connection of the framebuffer 36 to the pixel matrix 22 with the line drivers 23I and 23r can be implemented in different ways. According to the prior art, the pixels 22 are programmed according to the successively arriving data stream, or the data of a line is collected and then written into the pixel matrix 22 - thus, the duration of a line typically comprises at least the number of clock cycles corresponding to the number of optical elements in a line. The complete implementation of a complete framebuffer 36 results in a further possibility according to the invention: The data is not fetched individually from the memory 36, but rather the data of an entire line with one clock cycle. Depending on the sequence length (this is, however, limited by the scan scheme, for example,(also determined by the bit depth) and implemented clock frequency, this results in image refresh rates and data transfer rates previously unattainable in microdisplays. This is due to the fact that the new architecture contains all of these building blocks on a single integrated circuit. In a conventional, separate implementation, such a bandwidth would simply require so many signals between the driver module and the backplane that it is not feasible to implement it sensibly (neither in terms of wiring nor in terms of driver power consumption). In a highly integrated chip, it is possible to read all columns from the memory in parallel, even at high resolutions. The actual transfer rate can be influenced by the sequencer, thus corresponding to the maxim of the present invention to implement a very flexible architecture.The range for this transfer is between 0 Hz and several 1, 5, 10, 20, 50, 100 kHz or more, depending on the resolution and frequency. Depending on the application, the refresh rate can be balanced against power consumption as required. Furthermore, the sequencer enables other important features in the areas of augmented reality (AR) and virtual reality (VR), such as the insertion of black images (to prevent motion blur and motion sickness). In other words, this means that 36 and 34 sq. MHz allow variations in the trigger clock and thus the refresh rate as well as the transmitted bit depth, thus bringing flexibility to the microdisplay architecture.In the flexible microdisplay architecture, it is thus possible to influence the connection of the framebuffer 36 through the transmitted bit depth, the used transmission frequency, the insertion of generically generated data frames (without using data from the framebuffer, such as black images), and delay elements for temporal weighting of the currently displayed data. All of these parameters allow a compromise between the displayed content and the system's power consumption. This is even more true if the actual data (this includes the display data itself as well as display data generated on-chip from information data) is also adjusted. For example, an adjusted bit depth ensures a lower data bandwidth of the input interface or lower utilization of the CPU / GPU 34p, lower utilization of the framebuffer 36, a lower required transmission to the pixel matrix 22, and thus a reduction in power consumption.Due to the architecture of the system, this adaptability can be used down to a single frame.

[0094] According to embodiments, one of the following units or functions can be integrated into the microdisplay 10 or the data processing means 34 of the microdisplay 10:

[0095] Implementation of a temperature sensor 34temp for system-internal compensation of temperature effects. This enables integrated temperature-dependent tracking of the pixel voltage or the common counter electrode. In other words, this means that, according to embodiments, the circuit level has a temperature sensor 34temp, and the control circuit 34 is configured to track the pixel voltage based on the temperature signal.

[0096] According to the further embodiments, the unit 34 or the 34k can perform an auto-calibration function of the brightness by measuring the brightness against a reference structure.

[0097] The 34test functional unit is used for integrated memory and system testing for internal system monitoring. The 34tg functional unit features a test pattern generator for generating test data on the chip itself. Production testing, i.e., production testing, can also be performed using these 34test and 34tg units.

[0098] According to further embodiments, the functional unit 34pwr comprises a central power management unit, which implements the previously explained scaling of power consumption by appropriately switching off power domains. According to further embodiments, external synchronization (see 34s) would also be conceivable.

[0099] This is used to provide various synchronization signals for external voltage generation, such as inversion signals for the LCOS case or synchronization to the end of a sequence (e.g. for targeted synchronization with the optical system).

[0100] Furthermore, an adjustable clock generator 34cl is conceivable for adapting the chip's different frequency domains to the requirements of the respective application (e.g., clock frequency for controlling the frame buffer and the sequence memory). According to further embodiments, an integrated white value calculation can be performed, for example, when the backplane is operated in a quad-pixel arrangement consisting of red (r), green (g), blue (b), and white (w) (see 34w).

[0101] According to a further embodiment, the backplane can, for example, have an integrated voltage regulator for Vm, V ref and the pixel voltages. Gamma adjustment would also be possible. These elements are intended as circuit-level modules.

[0102] In addition, the circuit level can also include interfaces 32, and in particular, an interface 32p. This interface controls the selection of interfaces 32 or interfaces 32b, 32a, or, if applicable, the data transfer to the CPU / GPU 34p, as well as the feeding of the display data generated by the CPU / GPU into the frame buffer (in the case of an information data interface). Pad row 32a is configured to couple a physical input. Switching between 32a and 32b is performed using unit 32p (digital interface protocol) as the protocol level.

[0103] Below, exemplary embodiments of the present invention will be considered separately again, with particular attention being given to alternative implementations and detailed implementations. One exemplary embodiment provides a flexible microdisplay architecture characterized in that one or more frontplane elements are arranged on a backplane and can be controlled by the backplane, several wired and / or wireless interfaces are available for data transmission, and a complete or partial image memory is implemented on the backplane.

[0104] According to the exemplary embodiments, it would be conceivable for the backplane to be implemented using CMOS technology. CMOS technology <90 nm is preferred.

[0105] According to embodiments, the backplane can be implemented using TFT technology.

[0106] According to embodiments, the backplane has one or more interfaces. According to embodiments, the interfaces or a standard interface of the one or more interfaces can be selected depending on the application.

[0107] According to embodiments, the backplane can be operated both as a memory-based architecture and as a refresh rate-based architecture. According to embodiments, the operating mode of the microdisplay depends on an algorithm implemented in hardware or software, allowing dynamic adaptation to image content and / or current applications.

[0108] With regard to the image memory, it should be noted that it can be implemented entirely, partially, or with only one bit in the pixel cell. In this respect, according to embodiments, the memory can be arranged partially externally or in the edge region of the backplane instead of entirely in the pixel. Regarding the bit memory, it should be noted that it can be partially or completely switched off and / or bypassed. According to embodiments, the controlled bit depth of the pixels can be variably adjustable. According to embodiments, special leakage compensation measures are provided in pixels.

[0109] According to embodiments, special measures for leakage compensation are implemented in the pixel cell. Additional transistors between the driver of the optical element and the optical element itself are conceivable here. It should be noted here that the unit generally described above as a light-emitting element can be implemented as an LED, OLED, or pLED. Each pixel can comprise an LED or subpixels (multiple LEDs, e.g., for RGB). According to embodiments, the front plane can be implemented in a light-modulating LCOS or light-emitting pLED or OLED.

[0110] According to embodiments, in addition to the image memory, a driver adapted to the front-plane technology can also be implemented. Depending on the backplane configuration, the pixel cell is implemented as a common anode and / or common cathode, which serves for control. Alternatively, the front-plane can be designed without a common electrode.

[0111] According to one embodiment, a high-bandwidth image buffer can be connected to the pixel matrix and can realize both frame rates (e.g., 240 Hz, 480 Hz, 1 kHz, 5 kHz, 10 kHz, 20 kHz, 50 kHz, 100 kHz, and more). According to embodiments, the actual bandwidth between the frame buffer and the pixel matrix is ​​adjustable. According to embodiments, system-internal compensation for temperature effects in the backplane would be possible by implementing a temperature sensor. According to embodiments, an integrated temperature-dependent tracking of the pixel voltage or the common counter electrode in the backplane can be implemented.

[0112] According to embodiments, an auto-calibration of the brightness is possible by measuring the brightness against a reference structure.

[0113] According to embodiments, an integrated memory and system test unit is provided for its own system monitoring or for carrying out a simplified production test.

[0114] According to embodiments, a test pattern generator is used to generate test data on the backplane.

[0115] Another embodiment provides an arrangement as previously explained, with a central power management unit for scaling power consumption by appropriately shutting down power domains. Another embodiment provides a unit for synchronizing the microdisplay architecture with other external components.

[0116] According to embodiments, an adjustable clock generation can be implemented to adapt the different frequency domains of the chip to the requirements of the respective application field (for example, clock frequency for controlling the frame buffer and the sequence memory).

[0117] According to embodiments, the pixel matrix control may comprise a sequencer configured to provide different refresh rates (e.g., 240 Hz, 480 Hz, 1 kHz, 5 kHz, 10 kHz, 20 kHz, 50 kHz, 100 kHz and more) from the memory to the light-emitting or light-modulating elements (internal refresh rate).

[0118] According to embodiments, the pixel matrix control may comprise a programmable and / or dynamically configurable cyclic transfer mechanism configured to control a transfer between the memory and the light-emitting or light-modulating elements (dynamically and / or according to the programming).

[0119] According to one embodiment, the backplane can be configured for operation in a quad pixel arrangement, e.g., consisting of red (r), green (g), blue (b), and white (w), and the data value of the white pixel is determined, for example. According to one embodiment, automatic adjustment of the microdisplay's white point is possible. For this purpose, a white balance unit is provided according to embodiments.

[0120] According to some embodiments, an integrated voltage regulator is provided to generate the pixel voltage. According to further embodiments, a gamma adjustment is provided in the backplane.

[0121] Although some aspects have been described in connection with a device, it should be understood that these aspects also represent a description of the corresponding method, so that a block or component of a device can also be understood as a corresponding method step or as a feature of a method step. Analogously, aspects described in connection with or as a method step also represent a description of a corresponding block, detail, or feature of a corresponding device. Some or all of the method steps may be implemented by (or using) a hardware apparatus, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the key method steps may be performed by such an apparatus.

[0122] Depending on specific implementation requirements, embodiments of the invention may be implemented in hardware or software. The implementation may be performed using a digital storage medium, such as a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM, or a FLASH memory, a hard disk, or other magnetic or optical storage device storing electronically readable control signals that can interact or cooperate with a programmable computer system to perform the respective method. Therefore, the digital storage medium may be computer-readable.

[0123] Some embodiments according to the invention thus comprise a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is carried out.

[0124] In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is effective to perform one of the methods when the computer program product is run on a computer.

[0125] The program code can, for example, also be stored on a machine-readable medium.

[0126] Other embodiments include the computer program for performing one of the methods described herein, wherein the computer program is stored on a machine-readable medium. In other words, one embodiment of the method according to the invention is thus a computer program that has program code for performing one of the methods described herein when the computer program runs on a computer. Another embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the methods described herein is recorded.

[0127] A further embodiment of the method according to the invention is thus a data stream or a sequence of signals that represents the computer program for carrying out one of the methods described herein. The data stream or the sequence of signals can be configured, for example, to be transferred via a data communication connection, for example, via the Internet.

[0128] A further embodiment comprises a processing device, for example a computer or a programmable logic device, which is configured or adapted to carry out one of the methods described herein.

[0129] A further embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.

[0130] A further embodiment according to the invention comprises a device or system designed to transmit a computer program for performing at least one of the methods described herein to a recipient. The transmission can be electronic or optical, for example. The recipient can be, for example, a computer, a mobile device, a storage device, or a similar device. The device or system can, for example, comprise a file server for transmitting the computer program to the recipient.

[0131] In some embodiments, a programmable logic device (e.g., a field-programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field-programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. Generally, in some embodiments, the methods are performed by any hardware device. This may be general-purpose hardware such as a computer processor (CPU) or hardware specific to the method, such as an ASIC. The embodiments described above are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art.Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

[0132] References

[0133] 5 [1] Vogel - 77-1.pdf, Vogel et al., “Ultra-Iow Power OLED Microdisplay for Extended Battery

[0134] Life in NTE Displays”.

Claims

Patent claims 1. A microdisplay architecture (10), comprising: an optical plane (20) with a plurality of light-emitting or light-modulating elements; a circuit plane (30) on which the optical plane (20) is arranged; wherein the circuit plane (30) comprises one or more interfaces (32a, 32b), a pixel matrix control (34), and an image memory (36) for controlling the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

2. Microdisplay architecture (10) according to claim 1, wherein the circuits of the one or more interfaces (32a, 32b), the pixel matrix control (34) and the image memory are integrated directly into the circuit level.

3. Microdisplay architecture (10) according to claim 1 or 2, wherein the pixel matrix control (34) is configured to control the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) in a refresh rate-based operating mode.

4. Microdisplay architecture (10) according to claim 1 or 2 or 3, wherein the pixel matrix control (34) is configured to control the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) in a memory-based operating mode.

5. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) is designed to selectively switch between a plurality of operating modes.

6. Microdisplay architecture (10) according to one of the preceding claims, wherein the same has a plurality of interfaces (32a, 32b) and / or a plurality of interfaces (32a, 32b) different bandwidths and / or multiple interfaces (32a, 32b) of different communication topologies, comprising wired and wireless communication topologies (32a, 32b).

7. Microdisplay architecture (10) according to claim 6, wherein the selection of the transmission interface and / or a transmission mode is made depending on an operating mode, including memory-based operating mode.

8. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) has a programmable and / or dynamically configurable cyclic transfer mechanism configured to control the data flow between the memory (36) and the light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

9. Microdisplay architecture (10) according to one of the preceding claims, wherein the microdisplay architecture (10) internally comprises a CPU / GPU (34p) configured to translate received or stored information into display pixel data and to display the same in a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

10. Microdisplay architecture (10) according to one of the preceding claims, wherein the microdisplay architecture (10) internally comprises a graphics processor which is designed to control the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) in a refresh rate-based operating mode and which can be switched off and / or put into a sleep state in the memory-based operating mode.

11. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) is designed to control a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) grouped into a first group and to control a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) grouped into a second group.

12. The microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix controller (34) is configured to vary the update rate; and / or, in the memory-based operating mode, to control the plurality of light-emitting elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) with a low update rate or no update rate; or, in a refresh rate-based operating mode, to control the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) with a high update rate, in particular higher than 30, higher than 60, higher than 90, or even higher than 120 Hz.

13. Microdisplay architecture (IO) according to one of the preceding claims, wherein the pixel matrix control (34) is designed to vary and / or reduce a bit depth for controlling one or more respective ones of the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

14. Microdisplay architecture (10) according to one of the preceding claims, wherein the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) of the optical level (20) and / or the image memory (36) of the circuit level (30) has technology nodes <90 nm or <45 nm.

15. Microdisplay architecture (10) according to one of the preceding claims, wherein the circuit level (30) comprises transistors having an additional leakage circuit (29).

16. Microdisplay architecture (10) according to claim 15, wherein the leakage circuit (29) comprises two transistors per light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

17. Microdisplay architecture (10) according to one of the preceding claims, wherein the image memory (36) is completely integrated in the circuit level (30) associated with a light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) or wherein the image memory (36) is implemented as an image memory (36) arranged partially in the edge region or externally associated with a light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d); and / or wherein the image memory (36) has one or more bits per light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

18. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) is designed to partially, and / or gradually, and / or completely switch off the image memory (36) or to bypass it or to bypass it for the refresh rate-based operating mode 19. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) has at least one switch (34sw) and driver (34t) for each light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

20. Microdisplay architecture (10) according to one of the preceding claims, wherein the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) are implemented as a common cathode circuit; and / or wherein the pixel matrix control (34) is configured to lower the reference voltage Vref or to raise the pixel voltage V PjXito increase the brightness (or by changing the difference between the pixel voltage V PjXi and the reference voltage re f the brightness of the light-emitting / modulating elements is changed) or wherein the control (34) is designed to control different light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) or pixel sub-elements by means of different pixel voltages.

21. Microdisplay architecture (10) according to one of the preceding claims, wherein the plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) are designed as a common anode circuit; and / or wherein the pixel matrix control (34) is designed to be controlled by raising the reference voltage Vref or by lowering the pixel voltage V P ix2 the brightness or by changing a difference between the pixel voltage Pix2 and the reference voltage re f the brightness of the light-emitting / modulating elements is changed.

22. Microdisplay architecture (10) according to one of the preceding claims, wherein the input frequency for image data at an input of the pixel matrix controller (34) and / or the memory (36) is less than or equal to an output frequency for image data at an output of the pixel matrix controller (34) and / or the memory (36).

23. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) is designed to control a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) grouped into a first group and a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) grouped into a second group; wherein a sequence and / or amplitude differs when controlling the first group and the second group.

24. Microdisplay architecture (10) according to one of the preceding claims, wherein the pixel matrix control (34) comprises a sequencer which is designed to provide different refresh rates from the memory (36) to the light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

25. Microdisplay architecture (10) according to one of the preceding claims, wherein the light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d) are implemented as OLEDs, uLEDs or pLEDs or as LCOS.

26. A microdisplay architecture (10), comprising: an optical plane (20) with a plurality of light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d); a circuit plane (30) on which the optical plane (20) is arranged, wherein the circuit plane (30) comprises a pixel matrix control (34) for controlling (34) the light-emitting or light-modulating elements (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d), wherein the pixel matrix control (34) has one or more transistors forming an additional leakage circuit (29).

27. Microdisplay architecture (10) according to claim 26, wherein the leakage circuit (29) two further transistors per light-emitting or light-modulating element (22, 22', 22", 22a, 22b, 22c, 22d, 22e, 22d).

28. A method for controlling (34) a microdisplay architecture (10) according to one of claims 1 to 25, comprising the following steps: Operating the pixel matrix control (34) in the memory-based operating mode using the image memory (36); or Operating the pixel matrix control (34) in a memory-based operating mode with / without use of the image memory (36).

29. Computer program for carrying out the method according to claim 28, when the method runs on a pixel matrix control (34).

Images