Computing system and corresponding method

Abstract

A computing system (100) and a corresponding method (200) are disclosed, wherein the computing system (100) comprises a processor (102) which is designed: to receive a computing request (106), which comprises a computing task (108) and associated conditions (110), the conditions (110) comprising an energy consumption condition and a latency condition and / or an accuracy condition; to select at least one computing unit from a plurality of computing units (104(n = 1 to N)), each computing unit of the plurality of computing units having a computing architecture, at least one computing unit of the plurality of computing units having a computing architecture different from at least one other computing unit of the plurality of computing units (104(n = 1 to N)), and each computing unit (104(n)) being assigned computing architecture information (112(n)) containing information about properties of the n computing unit with respect to the energy consumption and at least one latency and / or accuracy in an execution of a computing task (108); wherein the at least one computing unit is selected using the computing architecture information (112(n = 1 to N)).

Description

[0001] Description

[0002] Calculation system and related procedure

[0003] Various embodiments relate to a computing system and a related method.

[0004] Traditionally, silicon-based computing architectures (also called computer architectures) are used to perform a wide variety of computing tasks.

[0005] However, some computational tasks using a silicon-based computing architecture are time-consuming, and others cannot be computed using a silicon-based computing architecture at all. For example, in Boche, Holger et al., "On the Need of Neuromorphic Twins to Detect Denial-of-Service Attacks on Communication Networks," arXiv:2210.16690, 2022, and Boche, Holger et al., "Non-Computability of the Pseudoinverse on Digital Computers," arXiv:2212.02940, 2022, it was demonstrated that digital computing units (also referred to as computers) are incapable of computing the inverse problem in artificial intelligence (AI) applications. However, some such computational tasks can be computed by other computing architectures. However, these, in turn, can compute other computational tasks with less efficiency than the digital computing units.

[0006] According to various embodiments, a computing system is provided in which different computing architectures can be used, and in which at least one of these computing architectures is selected to solve a computing task depending on a wide variety of criteria. For example, a computing task can be associated with multiple conditions, and the at least one computing architecture can be selected such that, on the one hand, the multiple conditions are met and, on the other hand, the energy required to calculate the computing task is reduced (e.g., minimized).

[0007] In this way, for example, lower latencies are enabled for time-critical computing tasks, since a computing unit can be selected for the time-critical computing task that can calculate the computing task with the lower latency. If a time-noncritical computing task is present, a computing unit can be selected that can calculate the computing task with the lowest energy consumption. Various embodiments relate to a computing system, comprising: a processor configured to: receive a computing request comprising a computing task and associated conditions, wherein the conditions comprise an energy consumption condition and at least one of the latency condition and / or accuracy condition;to select at least one computing unit from a plurality of computing units, wherein each computing unit of the plurality of computing units has a computing architecture, wherein at least one computing unit of the plurality of computing units has a computing architecture different from at least one other computing unit of the plurality of computing units, wherein each computing unit is assigned computing architecture information which contains information about properties of the n computing unit with regard to energy consumption and at least one latency and / or accuracy when executing a computing task; wherein the at least one computing unit is selected using the computing architecture information.

[0008] It shows

[0009] Figures 1A to 1D each show a computing system according to various embodiments;

[0010] Figure 2 shows a flowchart of a method for assigning computing tasks according to various embodiments;

[0011] Figure 3 is an exemplary flowchart for generating computing architecture information according to various embodiments;

[0012] Figures 4A to 4C show an exemplary flow diagram for selecting at least one computing unit for calculating a computing task according to various embodiments;

[0013] Figure 5 shows an exemplary flow diagram for dividing a computing task into multiple subtasks in accordance with a security requirement according to various embodiments;

[0014] Figure 6 shows an exemplary flowchart for dividing a computing task into several subtasks to reduce a calculation time according to various embodiments; and

[0015] Figure 7 shows an exemplary flowchart for calculating a computational task by a computing unit according to various embodiments. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which, by way of illustration, specific embodiments in which the invention may be practiced are shown.

[0016] In general, a computing system can have multiple computing units with a silicon-based computing architecture, and computing tasks to be calculated can be assigned to these computing units for calculation. However, computing units with a silicon-based computing architecture cannot solve some computing tasks and can only solve others with a comparatively high time expenditure. For some applications, however, it may be desirable and / or necessary to calculate computing tasks with a short time expenditure (i.e., with low latency). Other computing architectures can be used for this purpose, although these in turn can only calculate other computing tasks with less efficiency. Various aspects relate to a computing system in which different computing architectures can be used and in which, depending on a wide variety of criteria, at least one of these computing architectures is selected to calculate a computing task.In this way, energy efficiency and calculation time can be adjusted (e.g. optimized) in an application-specific manner (e.g. depending on whether the calculation task is time-critical or non-time-critical).

[0017] FIG. 1A through FIG. 1D each show a computing system 100 according to various embodiments. Computing system 100 may include a processor 102. Although one processor 102 is described herein for illustrative purposes, it is understood that multiple processors may be included. For example, processor 102 (or multiple processors) may be part of a selection unit (also referred to as a selector unit).

[0018] Computing system 100 may include a plurality of computing units 104 (n = 1 to N). Where "N" may be an integer greater than or equal to two. For illustrative purposes, computing system 100 will be described below as including the plurality of computing units 104 (n = 1 to N). It is understood that processor 102 may also be configured as described herein without computing system 100 necessarily including the plurality of computing units 104 (n = 1 to N).

[0019] In some embodiments, the computing system 100 described herein may be an embedded system. In other embodiments, the processor 102 and the plurality of computing units 104 (n = 1 to N) may be part of a network. The network may, for example, be a physical network or a virtual network.

[0020] A computing unit, as described herein, can be any type of computing unit capable of computing (e.g., solving) computational tasks. A computing unit can have or be a computing unit (also referred to as an execution unit). The computing unit can generally be a unit for executing corresponding machine instructions. It is understood that this computing unit can be specific to a particular computing architecture of the computing unit. For example, the computing unit of a computing unit with a digital computing architecture can be configured to execute digital machine instructions. The computing unit of a computing unit with a quantum-based computing architecture can be configured to execute quantum machine instructions; the computing unit of a computing unit with a biological computing architecture can be configured to execute organic machine instructions; etc.

[0021] Each computational unit can have a respective computational architecture. A computational architecture (can also be referred to as a computer architecture) can specify a structure of the computational unit. The structure of the computational unit can, for example, specify an umbrella term (e.g., category term) of the way in which or by what means a computational task is computed, and disregard details of the explicit implementation. For example, a computational architecture can be a (e.g., silicon-based or gallium nitride-based) digital computational architecture, an analog (e.g., neuromorphic) computational architecture, a quantum-based computational architecture, a biological computational architecture, or a molecular-based computational architecture. It is understood that these are example computational architectures and that the principles described herein can apply accordingly to any other computational architecture.For example, if a new or different computing architecture is developed in the future, at least one computing unit of the computing system 100 can have this computing architecture.

[0022] According to various aspects, at least two computing units of the plurality of computing units 104(n = 1 to N) have a different computing architecture from one another. Consequently, in some embodiments, each computing unit of the plurality of computing units 104(n = 1 to N) may have a respective computing architecture that is different from the computing architectures of all other computing units of the plurality of computing units 104(n = 1 to N). In other embodiments, at least two computing units of the plurality of computing units 104(n = 1 to N) may have the same computing architecture, as long as at least one other computing unit of the plurality of computing units 104(n = 1 to N) has a different computing architecture. Depending on the computing architecture, a computing unit may require a certain computing latency (also referred to as computation time) and a certain energy consumption (also referred to as energy consumption) for a particular computing task.The accuracy with which a computational task can be calculated can also depend on the type of computing architecture.

[0023] Therefore, the computing system 100 can also be referred to as a heterogeneous computing system.

[0024] The computing units of the plurality of computing units 104 (n = 1 to N) may optionally further differ with regard to other components, properties, etc.

[0025] According to various aspects, processor 102 may be configured to receive a compute request 106. Compute request 106 may include a compute task 108 and at least one associated condition (e.g., multiple conditions 110). For example, a compute request 106 may be a tuple (Ti, Ci) of compute task 108, Ti, and conditions 110, Ci.

[0026] For example, conditions 110 may include an energy consumption condition. The energy consumption condition (may also be referred to as an energy requirement condition) may specify a maximum energy consumption that must be applied to calculate the computational task 108.

[0027] Conditions 110 may include a latency condition. The latency condition may specify a maximum latency for calculating the computational task 108 and providing the result. The latency may depend on a computational latency (also referred to as calculation time or computing time) for calculating the computational task 108 by a computing unit 104(n) and on transmission times (e.g., between processor 102 and computing unit 104(n)). If processor 102 and the plurality of computing units 104(n = 1 to N) are part of a physical network, for example, the transmission path between processor 102 and a respective computing unit 104(n) may influence the transmission times and thus the latency.

[0028] The conditions 110 can include an accuracy condition. The accuracy condition can specify a minimum accuracy with which the computational task 108 is to be calculated. The processor 102 can be configured to select at least one computing unit 104* from the plurality of computing units 104(n = 1 to N) for calculating the computational task 108. The processor 102 can be configured to select the at least one computing unit 104* using computing architecture information 112(n = 1 to N). In this case, each computing unit 104(n) of the plurality of computing units 104(n = 1 to N) can be assigned a respective piece of computing architecture information 112(n) of the computing architecture information 112(n = 1 to N). The computing architecture information 112(n = 1 to N) can be stored, for example, in a memory assigned to the processor 102.

[0029] The computing architecture information 112(n) of a computing unit 104(n) may contain information about properties of the computing unit 104(n) with regard to energy consumption when executing a computing task. The computing architecture information 112(n) may contain information about properties of the computing unit 104(n) with regard to latency (e.g., a computing latency and / or transmission latency) and / or accuracy when executing a computing task. For example, the computing architecture information 112(n) of a respective computing unit 104(n) may comprise the above information for each computing task of a plurality of (e.g., predefined) computing tasks.For example, the computing architecture of the computing unit 104(n) may calculate one compute task with a first energy consumption, a first compute latency, and a first accuracy, and another compute task with a second energy consumption, a second compute latency, and a second accuracy, where, for example, the first energy consumption and the second energy consumption are different from each other and / or the first compute latency and the second compute latency are different from each other and / or the first accuracy and the second accuracy are different from each other.

[0030] Optionally, the conditions 110 can include a security condition. The security condition (can also be referred to as a security requirement) can specify the minimum number of different computational units into which the computational requirement must be divided. The security condition can optionally also specify in which region (e.g., country, area covered by one or more laws, etc.) the computation is to be performed.

[0031] In some embodiments, the constraints 110 may include additional constraints, and the compute architecture information 112(n = 1 to N) may optionally include corresponding associated information regarding this additional constraint for each compute unit 104(n). For example, the constraints 110 may include a platform constraint. A compute unit 104(n) may be part of a platform. The platform constraint may specify constraints regarding the platform.

[0032] For example, conditions 110 may include regulatory requirements (e.g., for compliance with laws) or company-specific requirements. In some aspects, the regulatory requirements may be stored in the memory associated with processor 102 and, for example, may not be part of computational requirements 106. Such a requirement may, for example, be algorithmic transparency and / or a right to explanation of the algorithms.

[0033] In some embodiments, the respective computing architecture information 112(n) may indicate which computing architecture the computing unit 104(n) has, and the computing architecture information may further include the respective information described herein for each computing architecture (e.g., having at least one of the computing units).

[0034] In some embodiments, the computing architecture information 112 (n = 1 to N) can be dynamically adapted. Consequently, the processor 102 can select the at least one computing unit 104* using the mapping function, f, based on the computing architecture information 112 and the i-th computing request 106, (Ti , Ci). In this case, the processor 102 can, for example, create an allocation table which can have fi (Ti , Ci, required computing time, energy consumption, etc.) as the i-th entry, i.e., a mapping depending on the requested computing request 106, the conditions 110 (these can also be referred to as target costs), and the computing architecture information (e.g., having a cost table of the computing units and / or computing architectures).

[0035] According to various aspects, processor 102 may be configured to implement a mapping function, f. Relevant information (e.g., code) may be stored, for example, in the associated memory. The mapping function, f, may map the compute request 106 (Ti, Ci) to the at least one compute unit 104* (in order to select it).

[0036] According to various aspects, the processor 102 may be configured to determine (to select the at least one computing unit 104* for calculating the computing task 108) for each computing unit 104(n) of the plurality of computing units 104(n = 1 to N) using the respective computing architecture information 112(n). For example, the conditions 110 may include the energy consumption condition, and the computing architecture information 112(n) may include the information regarding energy consumption during execution of the computing task 108, and the processor 102 may determine an expected energy consumption for calculating the computing task 108 of the computing request 106.For example, the conditions 110 may include the latency condition, and the compute architecture information 112(n) may include the information regarding the latency in executing the compute task 108, and the processor 102 may determine an expected compute latency for the computation of the compute task 108 of the compute request 106. For example, the conditions 110 may include the accuracy condition, and the compute architecture information 112(n) may include the information regarding the accuracy in executing the compute task 108, and the processor 102 may determine an expected compute accuracy for the computation of the compute task 108 of the compute request 106.

[0037] The processor 102 can then determine, based on the determined expected values ​​(e.g., the expected computing accuracy and / or the expected computing latency and / or the expected energy consumption), whether one or more computing units of the plurality of computing units 104(n = 1 to N) can satisfy the conditions 110. According to various aspects, the processor 102 can be configured to take into account the computing tasks already transmitted to this computing unit 104(n) when determining the expected computing latency of a respective computing unit 104(n). It is understood that the utilization of a computing unit directly influences the latency, i.e., the time until the result of the calculation is provided. According to various aspects, the processor 102 can be configured to take into account whether the computing unit 104(n) can calculate the computing task 108 (at all) or not when determining the expected computing latency of a respective computing unit 104(n).This information may, for example, be contained in the associated computing architecture information 112(n). In some embodiments, this information may be part of the latency information. It is understood that if a computing unit 104(n) cannot compute a particular computational task, the computational latency and / or accuracy approaches infinity. Therefore, in this case, for example, the latency condition and / or the accuracy condition may not be met.

[0038] If it is determined that one or more computing units of the plurality of computing units 104 (n = 1 to N) can satisfy the conditions 110, the processor 102 can select the at least one computing unit 104* from these. For example, the processor 102 can be configured to select the at least one computing unit 104* from these one or more computing units that has the lowest expected energy consumption. In this way, the energy efficiency of the computing system 100 can be increased. As shown in FIG. 1B, the processor 102 can be configured to generate an (e.g., respective) instruction 114 to the at least one computing unit 104*. The instruction 114 can instruct the at least one computing unit 104* to execute the computational task 108 of the computation request 106. The processor 102 can be configured to transmit the (e.g., respective) instruction 114 to the at least one computing unit 104*.

[0039] In some embodiments, instruction 114 may include computation task 108 of computation request 106.

[0040] In other embodiments, the computational task 108 of the computational request 106 can include a generic description of the computational task. The computing units of the plurality of computing units 104 (n = 1 to N) can be configured to read a specific machine code depending on the respective computing architecture. The processor 102 can be configured to generate the (respective) instruction 114 such that it includes a description of the computational task that is (respectively) readable by the at least one computing unit 104*.

[0041] According to various aspects, the processor 102 can be configured to transmit a request to the at least one computing unit 104* as to whether it expects to be able to calculate the computational task 108 and satisfy the associated conditions 110. The at least one computing unit 104* can then, for example, communicate that it cannot or (only) possibly can satisfy the conditions 110. If this is the case (or if the at least one computing unit 104* does not respond to the requests), the processor 102 can be configured to select a different computing unit 104(n) than the at least one computing unit 104*. Optionally, the processor 102 can then transmit a corresponding request to this computing unit 104* again as to whether it expects to be able to calculate the computational task 108 and satisfy the associated conditions 110.

[0042] With reference to FIG. 1C, the selected at least one computing unit 104* may be configured to provide (e.g., transmit) a result 118 of the calculation of the computing task 108 to the processor 102. The processor 102 may, for example, receive the computing request 106 from a unit 116, then assign the computing request 106 to the selected at least one computing unit 104*, and provide (e.g., transmit) the result 118 provided by the at least one computing unit 104* to the unit 116.

[0043] According to various aspects, the processor 102 can be configured to transmit feedback to the unit 116. If the processor 102 determines, for example, that no computing unit of the plurality of computing units 104 (n = 1 to N) can fulfill the computing request 106 (e.g., because none of the computing units can calculate the computing task 108 or because none of the computing units can fulfill the conditions 110 of the computing request 106), the processor 102 can transmit corresponding feedback to the unit 116. In this case, the feedback can indicate, for example, that none of the computing units can fulfill the computing request 106. Optionally, the feedback can provide information about the conditions under which the computing task could be calculated. This allows the unit 116 to provide a new computing request with changed conditions to the processor 102, if desired.

[0044] Feedback described herein from a computing unit 104(n) to the processor 102 may also be referred to as internal feedback. Feedback described herein from the processor 102 to the unit 116 may also be referred to as external feedback. The unit 116 may also be referred to as the requesting unit (or requestor for short).

[0045] In some embodiments, the processor 102 may be configured, after transmitting the instruction 114 to the at least one computing unit 104* (e.g., after starting and before completing the calculation of the computational task 108 by the selected at least one computing unit 104*), to receive prediction information from the at least one computing unit 104* indicating whether or not the selected at least one computing unit 104* is likely to satisfy the conditions 110 of the computational request 106. In some embodiments, the prediction information may directly indicate whether the conditions 110 are likely to be satisfied.In other embodiments, the prediction information may indicate information regarding an expected computing time and / or an expected accuracy and / or an expected energy consumption, and the processor 102 may be configured to determine whether or not the selected at least one computing unit 104* is likely to satisfy the conditions 110 of the computing request 106.

[0046] In some embodiments, the processor 102 may determine that multiple computing units can calculate the computational task 108 and satisfy the conditions 110. In this case, the processor 102 may, for example, select the computing unit that has the lowest expected energy consumption as the at least one computing unit from the plurality of computing units. If the prediction information indicates that the selected at least one computing unit 104* is unlikely to satisfy the conditions 110 of the computational request 106, the processor 102 may be configured to determine, using the computational architecture information 112, whether at least one other computing unit of the previously determined plurality of computing units can calculate the computational task 108 and satisfy the conditions 110 of the computational request 106 in the remaining time.If it is determined that at least one other computing unit can calculate the computing task 108 and can fulfill the conditions 110 of the computing request 106 in the remaining time, the processor 102 can select it and, for example, transmit a corresponding instruction 114 to it.

[0047] Referring to FIG. 1D, in response to receiving the computation request 106, the processor 102 may be configured to divide the computation task 108 and the associated constraints 110 into a plurality of subtasks 108(m = 1 to M) with respective constraints 110(m = 1 to M). Here, M may be any integer greater than or equal to two. If the computation task 108 is not divided into subtasks, then M = 1.

[0048] The processor 102 may be configured to select at least one computing unit 104*(m) from the plurality of computing units 104(n = 1 to N) using the computing architecture information for each subtask 108(m) of the plurality of subtasks 108(m = 1 to M).

[0049] The processor 102 may be configured to generate (and optionally further transmit) for each subtask 108(m) a respective instruction 114(m) to execute the respective subtask 108(m) to the respectively selected at least one computing unit 104*(m).

[0050] According to various aspects, the processor 102 may be part of a selection unit and this may include a multiplexer that may be configured to transmit the instructions 114 to the computing units by means of multiplexing.

[0051] As described above, the safety condition can specify a number of different computing units among which the computing request must be divided at least. If the computing request 106 has the safety condition, the processor 102 can be configured to divide the computing task 108 and the associated conditions 110 into a plurality of subtasks 108(m) with respective conditions 110(m) using the computing architecture information 112 such that the plurality of subtasks 108(m = 1 to M) can be divided at least among the number of different computing units specified by the safety condition, in order to select at least one computing unit from the plurality of computing units for each of the plurality of subtasks and thus fulfill the safety condition. Consequently, in this case, M can be greater than or equal to the number specified by the safety condition.

[0052] FIG. 2 shows a flowchart of a method 200 for allocating compute tasks according to various embodiments. The method 200 may include receiving a compute request (in 202). The compute request may include a compute task and associated conditions. The conditions may include a power consumption condition and at least one of a latency condition and / or an accuracy condition.

[0053] The method 200 may include selecting at least one computing unit from a plurality of computing units (in 204). Each computing unit of the plurality of computing units may have a respective computing architecture. At least one computing unit of the plurality of computing units may have a computing architecture that is different from at least one other computing unit of the plurality of computing units. Each computing unit may be assigned computing architecture information that contains information about properties of the respective computing unit with regard to energy consumption and at least one latency and / or accuracy when executing a computing task. The selection of the at least one computing unit may be performed using the computing architecture information.

[0054] Various aspects of this method 200 and of the computing system 100 are described below using flow diagrams of an exemplary embodiment. It is understood that the computing system 100 and the method 200 can also have individual aspects of these aspects without necessarily implementing the entire embodiment. Rather, it is understood that these aspects represent various exemplary embodiments of the processes described with reference to FIG. 1A to FIG. 1D (or of the method 200). Therefore, individual processes described below can be part of the method 200, or the respective unit (e.g., the processor 102 or one of the computing units 104) of the computing system 100 can be configured to execute a respective process.

[0055] Nevertheless, it is understood that the computing system 100 and / or the method 200 may also be implemented according to this exemplary embodiment.

[0056] FIG.3 shows an exemplary flowchart 300 for generating the computing architecture information 112(n = 1 to N) according to various embodiments. This can be an initialization process. The initialization process can start in 302. The processor 102 (e.g., as part of the selection unit) can establish a connection (in 304) to the computing units of the plurality of computing units 104(n = 1 to N). In this case, the plurality of computing units 104(n = 1 to N) can be available computing hardware. The processor 102 can be configured to generate the computing architecture information 112(n = 1 to N) (in 306). For this purpose, the processor 102 can generate the respective computing architecture information 112(n) for each computing unit 104(n) of the plurality of computing units 104(n = 1 to N). The processor 102 may be configured to generate the respective computing architecture information 112(n) using meta-information (308).For example, to generate the respective computing architecture information 112(n), the processor 102 may use information from third parties (e.g., those hosting the respective computing unit 104(n) (e.g., in the case where the computing system 100 is part of a network)), hardware capabilities, properties, latencies, hardware metrics, etc. of the respective computing unit 104(n). The information from third parties may contain information regarding security and may be taken into account with regard to the security condition. For example, when dividing the computing task 108 into multiple subtasks by the processor 102, when selecting the respective computing unit 104(n), it may be taken into account that the multiple subtasks 108(m = 1 to M) are distributed among computing units of different third parties (e.g., third-party providers). In this way, it can be prevented that a third party has access to the results of all subtasks and can thus derive the overall result.This not only increases security but also ensures anonymity.

[0057] FIG. 4A shows an exemplary flowchart 400 for selecting the at least one computing unit 104* for calculating the computing task 108 according to various embodiments. The processor 102 may wait (in 402) for computing requests. The processor 102 may be configured to determine (in 404) whether a computing request 106 has been received. If the computing request 106 is received, the processor 102 may determine (in 406) whether at least one computing unit 104(n) of the plurality of computing units 104(n = 1 to N) can fulfill the computing request 106 (i.e., calculate the computing task 108 according to the conditions 110). If it is determined (in 406) that no computing unit of the plurality of computing units 104 (n = 1 to N) can satisfy the computing request 106, the processor 102 can (in 408) generate and optionally transmit a corresponding feedback to the unit 116.If it is determined (in 406) that at least one computing unit of the plurality of computing units 104 (n = 1 to N) can satisfy the compute request 106, the processor 102 may determine (in 410) whether multiple computing units of the plurality of computing units 104 (n = 1 to N) can satisfy the compute request 106. If it is determined that only one computing unit can satisfy the compute request 106 ("No" in 410), the processor 102 may select that computing unit as the at least one computing unit 104* and optionally further (in 412) generate the instruction 114 (and optionally transmit it to the at least one computing unit 104*).

[0058] If it is determined that multiple computing units can fulfill the computing requirement 106 ("Yes" in 410), the processor 102 can select one or more of these computing units (in 414). With reference to FIG.4B and FIG.4C, the processor 102 can be configured to determine (in 416) whether there are safety requirements (e.g., as a safety condition of the conditions 110 and / or as a general safety requirement stored, for example, in the memory associated with the processor 102) for dividing the computing task 108 into a plurality of subtasks 108 (m = 1 to M).

[0059] If there are no security requirements ("No" in 416), the processor 102 can be configured in some embodiments (see, for example, FIG. 4B) to select (in 420) a computing unit 104* from the plurality of computing units that can satisfy the computing requirement 106. In other embodiments (see, for example, FIG. 4C), the processor 102 can be configured to determine whether the computing task 108 has a high level of complexity or not. A computing task with a high level of complexity can be understood to mean that it can be broken down into sub-problems. If it is determined that the computing task 108 has a high level of complexity ("No" in 418), the one computing unit 104* can be selected (in 420) from the plurality of computing units that can satisfy the computing requirement 106.

[0060] If safety requirements exist ("Yes" in 416), the computational task 108 can be divided into several subtasks 108(m) with respective conditions 110(m), as described herein. An exemplary flowchart 500 for this is shown in FIG. 5. Optionally, the processor 102 can be configured to divide the computational task 108 into several subtasks 108(m = 1 to M) with respective conditions 110(m), as described herein, if the computational task 108 has a high complexity ("Yes" in 418). An exemplary flowchart 600 for this is shown in FIG. 6.

[0061] With reference to FIG. 5, the processor 102 may be configured to divide the computing task 108 (in 502) into the plurality of subtasks 108(m = 1 to M). The processor 102 may be configured to select a respective computing unit 104(n, m) for each subtask 108(m). The processor 102 may then generate the respective instruction 114(m) and optionally transmit it to the selected computing unit 104(n, m). Selecting the computing units for the plurality of subtasks 108(m = 1 to M) may involve distributing the subtasks among multiple computing units (in 504).

[0062] Processor 102 may be configured to determine (in 506) whether parallel computing of the multiple subtasks 108 (m = 1 to M) is possible or not. Parallel computing may be understood as computing that overlaps at least partially in time.

[0063] If parallel calculation of the multiple subtasks 108(m = 1 to M) is possible ("Yes" in 506), the parallel calculation can be performed (in 508) by the multiple computing units (i.e., the computing unit 104(n, m) selected for each subtask 108(m). Each selected computing unit 104(n, m) can provide a respective result 118(m) of the calculation of the respective subtask 108(m) to the processor 102. The processor 102 can be configured to combine these results 118(m = 1 to M) into an overall result 514.

[0064] If parallel calculation of the plurality of subtasks 108(m = 1 to M) is not possible ("No" in 506), the processor 102 can (in 510) provide the respective subtask 108(m) (e.g., as instruction 114(m)) to the associated selected computing unit 104(n, m)). Each selected computing unit 104(n, m) can then provide the respective result 118(m) of the calculation of the respective subtask 108(m) to the processor 102. The processor 102 can be configured to determine (in 512) whether all subtasks have been calculated. Once all subtasks have been calculated, the processor 102 can combine the results 118(m = 1 to M) into the overall result 514.

[0065] Processor 102 may be configured to generate (in 516) a feedback signal according to the overall result 514 and optionally transmit it further to unit 116. This may complete the calculation of computation request 106, and processor 102 may wait (according to 402) for further computation requests.

[0066] Flowchart 600 may differ from flowchart 500 in that flowchart 600 has no security requirements ("No" in 416). Therefore, the multiple subtasks 108(m = 1 to M) may be distributed among different computing units (e.g., different third parties), but this is not required. For example, more than one subtask may be assigned to a computing unit, provided the associated conditions 110(m) are met. Therefore, processor 102 may be configured to determine (in 602) whether or not to distribute the subtasks.

[0067] FIG. 7 shows an exemplary flowchart 700 for calculating the computational task 108 by the computing unit according to various embodiments. This can also apply accordingly to the calculation of a subtask 108(m).

[0068] In response to receiving instruction 114 (or 114(m)), the selected computing unit 104* may calculate the computational task 108 (in 702). The computing unit 104* may provide feedback to the processor 102. This feedback may, for example, include the result of the calculation. If the computing unit 104* cannot calculate the computational task 108, the feedback may include corresponding information. The processor 102 may be configured to determine (in 704) whether the computing unit 104* has successfully calculated the computational task 108 (i.e., provided a result of the computational task 108). If the computing unit 104* has not successfully calculated the computational request 106 (“No” in 704), the processor 102 may exclude this computing unit 104*. The processor 102 may then determine (in 708) whether the computational task 108 should be recalculated.If the calculation task 108 is to be recalculated and the computing unit 104* has not successfully calculated the calculation request 106, it can be determined according to 410 whether at least one other computing unit can fulfill the calculation request 106. Consequently, the computing unit 104* that did not successfully calculate the calculation request 106 can be excluded. If the calculation task 108 is not to be recalculated ("No" in 708), the processor 102 can generate a corresponding feedback according to the result of the calculation (e.g., information regarding the result if the computing unit 104* successfully calculated the calculation task 108, or otherwise information indicating that the calculation task 108 could not be calculated) and optionally transmit it to the unit 116.

[0069] The processor 102 described herein may be part of a selection unit that can be used in a (e.g., virtual or physical) network or as part of an embedded system. The processor 102 may receive a computation request 106 with a computational task 108 and conditions 110 and then select at least one computational unit 104* from a plurality of computational units 104(n = 1 to N) to calculate the computational task 108. For this purpose, the processor 102 may use computational architecture information 112 that, for each computational unit 104(n) of the plurality of computational units 104(n = 1 to N), contains respective computational architecture information 112(n) regarding energy consumption and, optionally, further regarding latency and / or accuracy and / or security and / or platform.Here, at least one computing unit 104(n) of the plurality of computing units 104(n = 1 to N) can have a computing architecture that is different from at least one other computing unit. For example, the plurality of computing units 104(n = 1 to N) can have at least one computing unit with a digital computing architecture and at least one computing unit with a different computing architecture (e.g., an analog (e.g., neuromorphic) computing architecture, a quantum-based computing architecture, a biological computing architecture, and / or a molecular-based computing architecture).

[0070] Each computing architecture can have certain advantages and disadvantages compared to other computing architectures. For example, molecular-based computing architectures can perform computations with significantly lower energy consumption compared to digital computing architectures, but require longer computing times (i.e., have higher computational latency). For example, quantum-based computing architectures can perform computations with significantly less time (i.e., lower computational latency) compared to digital computing architectures, but require higher energy consumption (e.g., for cooling, since quantum-based computing architectures typically operate at lower temperatures). In this regard, for example, computational tasks where the computation time in digital computing architectures scales exponentially with the size of the task can be computed with linearly scaling time in quantum-based computing architectures.As described herein, some computational problems cannot be solved by digital computing architectures at all, such as the inverse problem in AI applications, whereas this problem can be solved by analog (e.g., neuromorphic) computing architectures. Other problems, in turn, can be solved by digital computing architectures with lower energy requirements and / or lower computational overhead compared to analog computing architectures.

[0071] Therefore, the processor 102 may, for example, assign a latency-critical computational task to a computation unit 104(n) with a quantum-based computing architecture in order to compute the computational task more quickly, and assign a (e.g., quantitatively large) time-noncritical computational task to a computation unit 104(n) with a molecular-based computing architecture (also referred to as a molecular computer) in order to save energy.

[0072] It is understood that the computing architectures described herein are exemplary and that at least one computing unit 104(n) may also have a different computing architecture.

[0073] In an example illustrating the principle described herein, processor 102 may be part of a selector at an interface between a data center with multiple, heterogeneous computing systems and the outside world. Processor 102 may receive a first compute request (Ti, Ci) and a second compute request (T2, C2). In this example, the first compute task, Ti, may be related to a latency-critical application (e.g., command and / or control of cyber-physical systems), and the first constraints, Ci, may require low-latency computation without regard to the power consumption of the process. In this example, the second compute task, T2, may not be latency-critical; therefore, the second constraints, C2, may relate to lower power consumption.For example, the processor 102 may be connected to three computing units (i.e., N = 3): a first computing unit 104(1) with a molecular-based computing architecture, a second computing unit 104(2) with a quantum-based computing architecture, and a third computing unit 104(3) with a silicon-based digital computing architecture. As described herein, the molecular-based computing architecture is very energy-efficient but also very slow; the silicon-based digital computing architecture belongs to the traditional, modern electrical computers with medium energy consumption; and the quantum-based computing architecture is very inefficient in terms of energy consumption, but it is capable of solving some problems in practical time that the silicon-based digital computing architecture cannot solve.For the first computational task, Ti , the processor 102 may then select the second computational unit 104(2) or the third computational unit 104(3) to solve the latency-critical problem (e.g., the third computational unit 104(3) if the problem can practically be solved using classical means, or the second computational unit 104(2) if non-classical approaches are required). For the second computational task, T2 , the processor 102 may select the first computational unit 104(1) because the molecular-based computational architecture has the lowest energy requirements.

[0074] If everything goes successfully, the computation units return the computation results to processor 102. The first computation task Ti would be completed quickly, and the results of the low-latency computation would be communicated to the requester. The slower process of molecular computation, on the other hand, would be communicated to the requester as soon as it is completed. The second computation unit 104(2) could transmit an estimate of the time required to complete the computations via internal feedback. This information could also be provided to the requester via external feedback.

[0075] Various examples are provided below that describe one or more aspects of computing system 100 and method 200. It is understood that aspects described with respect to the computing system may also apply to the method, and vice versa. For example, operations described with respect to the computing system may correspondingly be embodied as a method. Accordingly, the computing system (e.g., the processor) may be configured to perform an operation described herein.

[0076] Example 1 is a computing system comprising: a processor configured to: receive a computing request comprising a computing task and associated conditions, wherein the conditions comprise a power consumption condition and at least one of the latency condition and / or accuracy condition; select at least one computing unit from a plurality of computing units, wherein each computing unit of the plurality of computing units comprises a respective computing architecture, wherein at least one computing unit of the plurality of computing units comprises a computing architecture different from at least one other computing unit of the plurality of computing units, wherein each computing unit is assigned computing architecture information containing information about properties of the respective computing unit with regard to power consumption and at least one latency and / or accuracy when executing a computing task;wherein the at least one computing unit is selected using the computing architecture information;

[0077] Example 2 is configured according to Example 1, wherein the processor is further configured to generate an instruction to the at least one computing unit to perform the computing task of the computing request.

[0078] Example 3 is configured according to Example 2, wherein the instruction comprises the computation task of the computation request.

[0079] Example 4 is configured according to Example 2, wherein the computational task of the computational request comprises a generic description of the computational task; and wherein the instruction comprises a description of the computational task readable by the selected at least one computing unit.

[0080] Example 5 is configured according to any one of Examples 1 to 4, wherein the processor is further configured to select the at least one computing unit for a plurality (e.g., all) computing units of the plurality of computing units using respective computing architecture information to determine, respectively: an expected computing latency for the computation of the computation task of the computation request, and / or an expected computation accuracy for the computation of the computation task of the computation request, and / or an expected energy consumption for the computation of the computation task of the computation request, and / or platform requirements for the computation of the computation task of the computation request, and / or security requirements for the computation of the computation task of the computation request, and / or legislative requirements regarding the computation of computation requests;and wherein the processor is further configured to determine whether one or more computing units of the plurality of computing units can meet the conditions of the computing requirement using the respective expected computing latency and / or the respective expected computing accuracy and / or the respective expected energy consumption and / or the platform requirements and / or the security requirements and / or the regulatory requirements;

[0081] Example 6 is configured according to Example 5, wherein the processor is configured to: determine, for the plurality of computing units, the expected energy consumption for calculating the computational task of the computation request using the respective computational architecture information; and if it is determined that several computing units of the plurality of computing units can satisfy the conditions of the computation request, select the computing unit having the lowest expected energy consumption as the at least one computing unit.

[0082] Example 7 is configured according to example 5 or 6, wherein the processor is configured to: determine a respective utilization for the plurality of computing units using computing tasks transmitted to the respective computing unit; and to determine, for the plurality of computing units, the respective expected computing latency for calculating the computing task using the respective utilization using the respective computing architecture information.

[0083] Example 8 is configured according to any one of Examples 1 to 7, wherein the computing architecture of the at least one computing unit and the different computing architecture of the at least one other computing unit for the computing task differ with respect to energy consumption and / or computing time and / or computing capacity.

[0084] Example 9 is configured according to any one of Examples 1 to 8, wherein the plurality of computing units comprises one or more of the following computing architectures: a (e.g., silicon-based or gallium nitride-based) digital computing architecture, an analog (e.g., neuromorphic) computing architecture, a quantum-based computing architecture, a biological computing architecture, and / or a molecular-based computing architecture.

[0085] Example 10 is configured according to any one of Examples 1 to 9, wherein the computing architecture information of a respective computing unit further indicates whether or not the computing unit can compute the computing task.

[0086] Example 11 is configured according to Example 10, wherein the processor is further configured to consider, when selecting the at least one computing unit, whether the computing unit can calculate the computing task.

[0087] Example 12 is configured according to any one of Examples 1 to 11, wherein the processor is configured: in response to receiving the compute request, to divide the compute task and the associated conditions of the compute request into a plurality of subtasks with respective conditions; and using the compute architecture information, to select at least one compute unit from the plurality of compute units for each subtask of the plurality of subtasks. Example 13 is configured according to Example 12, wherein the processor is further configured to generate, for each subtask, a respective instruction to the respectively selected at least one compute unit to execute the respective subtask.

[0088] Example 14 is configured according to Example 13, wherein the respective instruction comprises the respective subtask of the computation request.

[0089] Example 15 is configured according to Example 13, wherein the computational task of the computational request comprises a generic description of the computational task; and wherein the respective instruction comprises a description of the respective subtask readable by the respectively selected at least one computational unit.

[0090] Example 16 is configured according to any one of Examples 1 to 15, wherein the conditions of the computation request further comprise a safety condition that specifies a number of at least how many different computation units the computation request is to be divided into.

[0091] Example 17 is configured according to Example 16, wherein the processor is configured, in response to receiving the computation request, to divide the computation task and the associated conditions into a plurality of subtasks with respective conditions using the computation architecture information such that the plurality of subtasks can be divided at least among the number of different computation units specified by the safety condition, in order to select at least one computation unit from the plurality of computation units for each of the plurality of subtasks and thus to fulfill the safety condition.

[0092] Example 18 is configured according to any one of examples 1 to 17, if in combination with example 2 or 13, wherein the processor is configured to transmit the (respective) instruction to the selected at least one computing unit.

[0093] Example 19 is configured according to any one of Examples 1 to 17, wherein the processor is configured, after transmitting the instruction to the at least one computing unit (e.g., after starting and before completing the calculation of the computing task by the selected at least one computing unit), to receive (e.g., from the latter) prediction information indicating whether the selected at least one computing unit is likely to meet the conditions of the computing request or not (e.g., directly indicating whether the conditions are likely to be met; or indicating an expected computing time and / or an expected accuracy and / or an expected energy consumption, wherein the processor may be configured to determine whether the selected at least one computing unit is likely to meet the conditions of the computing request or not).

[0094] Example 20 is configured according to Example 19, wherein the processor is configured to: if the prediction information indicates that the selected at least one computing unit is unlikely to meet the conditions of the computing request, determine using the computing architecture information whether one or more other computing units of the plurality of computing units can meet the conditions of the computing request in the remaining time; and if it is determined that one or more other computing units can meet the conditions of the computing request in the remaining time, select at least one computing unit from the one or more other computing units.

[0095] Example 21 is configured according to any one of Examples 1 to 20, wherein the computing system is an embedded computing system; or wherein the plurality of computing units are part of a (physical or virtual) network.

[0096] Example 22 is configured according to any one of examples 1 to 21, when combined with example 2 or 13, wherein the (respective) instruction comprises a query as to whether the selected at least one computing unit expects to be able to calculate the computing task and satisfy the associated conditions.

[0097] Example 23 is configured according to examples 18 and 21, wherein the processor is configured to: if the selected at least one computing unit does not indicate, in response to the request for the instruction, that it expects to be able to calculate the computational task and satisfy the associated conditions (e.g., if it indicates that it cannot or may possibly satisfy the conditions), select at least one other computing unit from the plurality of computing units (and optionally transmit an instruction with the request to it).

[0098] Example 24 is configured according to any one of Examples 1 to 23, wherein the computing architecture of the at least one computing unit is configured to calculate at least one computing task of a plurality of computing tasks with a lower energy consumption than the different computing architecture of the at least one other computing unit, whereas the computing architecture of the at least one other computing unit is configured to calculate at least one other computing task of the plurality of computing tasks with a lower energy consumption than the different computing architecture of the at least one computing unit.Example 25 is configured according to any one of Examples 1 to 24, wherein the processor is configured to: determine, using the compute architecture information, whether one or more compute units of the plurality of compute units can satisfy the conditions of the compute request; and if it is determined that one or more compute units of the plurality of compute units can satisfy the conditions of the compute request, select the at least one compute unit from the one or more compute units.

[0099] Example 26 is configured according to Example 25, wherein the processor is configured to, when determining that multiple computing units of the plurality of computing units can satisfy the conditions of the computing request, select the computing unit among those computing units as the at least one computing unit having a lowest expected power consumption.

[0100] Example 27 is configured according to example 25 or 26, wherein the processor is configured, when it is determined that no computing unit of the plurality of computing units can fulfill the computing request (e.g., because no computing unit can solve the computing task or because no computing unit can fulfill the conditions of the computing request), to generate (and optionally transmit) a notification to a unit from which the processor received the computing request, indicating that no computing unit of the plurality of computing units can fulfill the computing request (e.g., that no computing unit can solve the computing task or which conditions of the computing request cannot be met).

[0101] Example 28 is configured according to any one of Examples 1 to 27, further comprising the plurality of computing units.

[0102] Example 29 is configured according to Example 28, wherein each computing unit of the plurality of computing units is configured to provide a result of the calculation of a computing task transmitted thereto to the processor.

[0103] Example 30 is configured according to Example 29, wherein the processor is configured to transmit the result of the calculation to a unit from which the processor received the calculation request.

[0104] Example 31 is a method comprising: receiving a compute request comprising a compute task and associated conditions, wherein the conditions comprise a power consumption condition and at least one of the latency condition and / or accuracy condition; selecting at least one compute unit from a plurality of compute units, wherein each compute unit of the plurality of compute units comprises a respective compute architecture, wherein at least one compute unit of the plurality of compute units comprises a different compute architecture than at least one other compute unit of the plurality of compute units, wherein each compute unit is associated with compute architecture information containing information about properties of the respective compute unit with regard to power consumption and at least one of a latency and / or accuracy when executing a compute task;wherein the at least one computing unit is selected using the computing architecture information;

[0105] Example 32 is configured according to Example 31, further comprising: generating an instruction to the at least one computing unit to perform the computing task of the computing request.

[0106] Example 33 is configured according to Example 32, wherein the instruction comprises the computation task of the computation request.

[0107] Example 34 is configured according to Example 32, wherein the computational task of the computational request comprises a generic description of the computational task; and wherein the instruction comprises a description of the computational task readable by the selected at least one computing device.

[0108] Example 35 is configured according to any one of Examples 31 to 34, wherein selecting the at least one computing unit for a plurality (e.g., all) computing units of the plurality of computing units using respective computing architecture information comprises determining, respectively: an expected computing latency for the computation of the computation task of the computation request, and / or an expected computation accuracy for the computation of the computation task of the computation request, and / or an expected energy consumption for the computation of the computation task of the computation request, and / or platform requirements for the computation of the computation task of the computation request, and / or security requirements for the computation of the computation task of the computation request, and / or legislative requirements regarding the computation of computation requests;and wherein the method further comprises: determining, using the respective expected computational latency and / or the respective expected computational accuracy and / or the respective expected energy consumption and / or the platform requirements and / or the security requirements and / or the regulatory requirements, whether one or more computational units of the plurality of computational units can meet the conditions of the computational requirement. Example 36 is configured according to Example 35, further comprising: determining a respective expected energy consumption for calculating the computational task of the computational requirement for the plurality of computational units using the respective computational architecture information; and if it is determined that multiple computational units of the plurality of computational units can meet the conditions of the computational requirement, selecting the computational unit as the at least one computational unit among these that has the lowest expected energy consumption.

[0109] Example 37 is configured according to example 35 or 36, further comprising: for the plurality of computing units, determining a respective utilization using compute tasks transmitted to the respective computing unit; and for the plurality of computing units, determining the respective expected compute latency for computing the compute task using the respective compute architecture information and the respective utilization.

[0110] Example 38 is configured according to any one of Examples 31 to 37, wherein the computing architecture of the at least one computing unit and the different computing architecture of the at least one other computing unit for the computing task differ with respect to energy consumption and / or computing time and / or computing capacity.

[0111] Example 39 is configured according to any one of Examples 31 to 38, wherein the plurality of computing units comprises one or more of the following computing architectures: a (e.g., silicon-based or gallium nitride-based) digital computing architecture, an analog (e.g., neuromorphic) computing architecture, a quantum-based computing architecture, a biological computing architecture, and / or a molecular-based computing architecture.

[0112] Example 40 is configured according to any one of Examples 31 to 39, wherein the computing architecture information of a respective computing unit further indicates whether or not the computing unit can compute the computational task.

[0113] Example 41 is configured according to Example 40, wherein when selecting the at least one computing unit, consideration is given to whether the computing unit can calculate the computing task.

[0114] Example 42 is configured according to any one of Examples 31 to 41, further comprising: in response to receiving the compute request, dividing the compute task and the associated conditions of the compute request into a plurality of subtasks with respective conditions; and for each subtask of the plurality of subtasks, selecting at least one respective compute unit from the plurality of compute units using the compute architecture information.

[0115] Example 43 is configured according to Example 42, further comprising: for each subtask, generating a respective instruction to the respectively selected at least one computing unit to execute the respective subtask.

[0116] Example 44 is configured according to Example 43, wherein the respective instruction comprises the respective subtask of the computation request.

[0117] Example 45 is configured according to Example 43, wherein the computational task of the computational request comprises a generic description of the computational task; and wherein the respective instruction comprises a description of the respective subtask readable by the respectively selected at least one computational unit.

[0118] Example 46 is configured according to any one of Examples 31 to 45, wherein the conditions of the compute request further comprise a safety condition that specifies a number of at least how many different compute units the compute request is to be divided into.

[0119] Example 47 is configured according to Example 46, further comprising: in response to receiving the computation request, dividing the computation task and the associated conditions using the computation architecture information into a plurality of subtasks with respective conditions such that the plurality of subtasks can be divided into at least the number of different computation units specified by the safety condition, so as to select at least one computation unit from the plurality of computation units for each of the plurality of subtasks and thereby satisfy the safety condition.

[0120] Example 48 is configured according to any one of examples 31 to 47, if in combination with example 32 or 43, further comprising: transmitting the (respective) instruction to the selected at least one computing unit.

[0121] Example 49 is configured according to any one of Examples 31 to 47, further comprising: after transmitting the instruction to the at least one computing unit (e.g., after starting and before completing the calculation of the computing task by the selected at least one computing unit), (e.g., from the latter) receiving prediction information indicating whether the selected at least one computing unit is likely to meet the conditions of the computing request or not (e.g., directly indicating whether the conditions are likely to be met; or indicating an expected computing time and / or an expected accuracy and / or an expected energy consumption, wherein the processor may be configured to determine whether the selected at least one computing unit is likely to meet the conditions of the computing request or not).

[0122] Example 50 is configured according to Example 49, further comprising: if the prediction information indicates that the selected at least one computing unit is unlikely to meet the conditions of the compute request, determining, using the compute architecture information, whether one or more other computing units of the plurality of computing units can meet the conditions of the compute request in the remaining time; and if it is determined that one or more other computing units can meet the conditions of the compute request in the remaining time, selecting at least one computing unit from the one or more other computing units.

[0123] Example 51 is configured according to any one of Examples 31 to 50, wherein the computing system is an embedded computing system; or wherein the plurality of computing units are part of a (physical or virtual) network.

[0124] Example 52 is configured according to any one of examples 31 to 51, when combined with example 32 or 43, wherein the (respective) instruction comprises a query as to whether the selected at least one computing unit expects to be able to calculate the computing task and satisfy the associated conditions.

[0125] Example 53 is configured according to examples 48 and 51, further comprising: if the selected at least one computing unit does not indicate in response to the request for the instruction that it expects to be able to calculate the computational task and satisfy the associated conditions (e.g., if it indicates that it cannot or may not satisfy the conditions), selecting at least one other computing unit from the plurality of computing units (and optionally transmitting an instruction with the request to it).

[0126] Example 54 is configured according to any one of Examples 31 to 53, wherein the computing architecture of the at least one computing unit is configured to calculate at least one computing task of a plurality of computing tasks with a lower energy consumption than the different computing architecture of the at least one other computing unit, whereas the computing architecture of the at least one other computing unit is configured to calculate at least one other computing task of the plurality of computing tasks with a lower energy consumption than the different computing architecture of the at least one computing unit.Example 55 is configured according to any one of Examples 31 to 54, further comprising: determining, using the compute architecture information, whether one or more compute units of the plurality of compute units can satisfy the conditions of the compute request; and if it is determined that one or more compute units of the plurality of compute units can satisfy the conditions of the compute request, selecting the at least one compute unit from the one or more compute units.

[0127] Example 56 is configured according to Example 55, further comprising: if it is determined that multiple computing units of the plurality of computing units can satisfy the conditions of the compute request, selecting the computing unit as the at least one computing unit of them that has a lowest expected power consumption.

[0128] Example 57 is configured according to example 55 or 56, further comprising: if it is determined that no computing unit of the plurality of computing units can satisfy the computation request (e.g., because no computing unit can solve the computational task or because no computing unit can satisfy the conditions of the computation request), generating (and optionally transmitting) a notification to a unit from which the processor received the computation request, indicating that no computing unit of the plurality of computing units can satisfy the computation request (e.g., that no computing unit can solve the computational task or which conditions of the computation request cannot be satisfied).

[0129] Example 58 is configured according to any one of examples 31 to 57, further comprising: providing a result of the calculation of the computational task by the at least one (selected) computing unit.

[0130] The term "processor," as used herein, can be understood as any type of entity that allows the processing of data or signals. The data or signals can, for example, be processed according to at least one (i.e., one or more than one) specific function performed by the processor. A processor can include or be formed from an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a programmable gate array (FPGA), an integrated circuit, or any combination thereof. It is understood that the foregoing circuits are exemplary ways of implementing a processor, and that the processor described herein can also be implemented in any other suitable manner to process data or signals.Thus, the principle described herein of selecting one or more computing units can be independent of the manner in which the processor is implemented. Any other type of implementation of the respective functions, which are described in more detail below, can also be understood as a processor or logic circuit. It is understood that one or more of the method steps described in detail herein can be carried out (e.g., realized) by a processor, through one or more specific functions performed by the processor. The processor can therefore be configured to carry out one of the methods described herein or its components for information processing.

[0131] A memory used in the embodiments may be a volatile memory, for example, a DRAM (Dynamic Random Access Memory), or a non-volatile memory, for example, a PROM (Programmable Read-Only Memory), an EPROM (Erasable PROM), an EEPROM (Electrically Erasable PROM), or a flash memory, such as a floating gate memory device, a charge trap memory device, an MRAM (Magnetoresistive Random Access Memory), or a PCRAM (Phase Change Random Access Memory). It is understood that these are examples of memory used in the embodiments, and that the memory may be implemented in any other suitable way to store data.

Claims

Patent claims 1. A computing system (100), comprising: a processor (102) configured to: • receive a computation request (106) comprising a computation task (108) and associated conditions (110), wherein the conditions (110) comprise a power consumption condition and at least one of the conditions (110) comprising a latency condition and / or an accuracy condition; • to select at least one computing unit (104*) from a plurality of computing units (104(n = 1 to N)), wherein each computing unit (104(n)) of the plurality of computing units (104(n = 1 to N)) has a respective computing architecture, wherein at least one computing unit of the plurality of computing units (104(n = 1 to N)) has a computing architecture different from at least one other computing unit of the plurality of computing units (104(n = 1 to N)), wherein each computing unit (104(n)) is assigned computing architecture information (112(n)) which contains information about properties of the respective computing unit with regard to energy consumption and at least one latency and / or accuracy when executing a computing task (108); • wherein the at least one computing unit (104*) is selected using the computing architecture information (112(n = 1 to N)).

2. Computing system (100) according to claim 1, wherein the processor (102) is further configured to generate an instruction (114) to the at least one computing unit (104*) to execute the computing task (108) of the computing request (106).

3. Computing system (100) according to claim 1 or 2, wherein the processor (102) is further configured to select the at least one computing unit (104*) for a plurality of computing units of the plurality of computing units (104(n = 1 to N)) using a respective computing architecture information (112(n)) to determine: • an expected computational latency for the computation of the computational task (108) of the computational request (106), and / or • an expected calculation accuracy for the calculation of the calculation task (108) of the calculation request (106), and / or • an expected energy consumption for the calculation of the computing task (108) of the computing request (106), and / or • Platform requirements for the calculation of the calculation task (108) of the calculation requirement (106), and / or • Safety requirements for the calculation of the calculation task (108) of the calculation request (106), and / or • legislative requirements regarding the calculation of computational requirements; and wherein the processor (102) is further configured to determine, using the respective expected computational latency and / or the respective expected computational accuracy and / or the respective expected energy consumption and / or the platform requirements and / or the security requirements and / or the legislative requirements, whether one or more computing units of the plurality of computing units (104(n = 1 to N)) can satisfy the conditions (110) of the computational requirement (106).

4. Computing system (100) according to claim 3, wherein the processor (102) is configured: • to determine the expected energy consumption for the calculation of the computing task (108) of the computing request (106) for the plurality of computing units using the respective computing architecture information (112(n)); and • if it is determined that several computing units of the plurality of computing units (104(n = 1 to N)) can satisfy the conditions (110) of the computing request (106), to select the computing unit from these as the at least one computing unit (104*) that has the lowest expected energy consumption.

5. Computing system (100) according to claim 3 or 4, wherein the processor (102) is configured to: determine a respective utilization for the plurality of computing units using computing tasks transmitted to the respective computing unit; and • to determine the expected computing latency for the calculation of the computing task (108) for the plurality of computing units using the respective computing architecture information (112(n)) using the respective utilization.

6. The computing system (100) of any one of claims 1 to 5, wherein the plurality of computing units (104(n = 1 to N)) comprises one or more of the following computing architectures: a digital computing architecture, an analog computing architecture, a quantum-based computing architecture, a biological computing architecture, and / or a molecular-based computing architecture.

7. Computing system (100) according to one of claims 1 to 6, wherein the conditions (110) of the computing request (106) further comprise a security condition that specifies a number of at least how many different computing units the computing request (106) is to be divided into.

8. The computing system (100) of claim 7, wherein the processor (102) is configured, in response to receiving the computing request (106), to divide the computing task (108) and the associated conditions (110) using the computing architecture information into a plurality of subtasks with respective conditions (110) such that the plurality of subtasks can be divided at least among the number of different computing units specified by the safety condition, in order to select at least one computing unit from the plurality of computing units (104(n = 1 to N)) for each of the plurality of subtasks and thus to fulfill the safety condition.

9. Computing system (100) according to one of claims 1 to 8, if in combination with claim 2, wherein the processor (102) is configured: • to transmit the instruction (114) to the selected at least one computing unit; • after transmitting the instruction (114) to the at least one computing unit, to receive prediction information indicating whether the selected at least one computing unit is expected to meet the conditions (110) of the computing request (106) or not; • if the prediction information indicates that the selected at least one computing unit is unlikely to meet the conditions (110) of the computing request (106), to determine, using the computing architecture information (112(n = 1 to N)), whether one or more other computing units of the plurality of computing units (104(n = 1 to N)) can meet the conditions (110) of the computing request (106) in the remaining time; and • if it is determined that one or more other computing units can meet the conditions (110) of the computing request (106) in the remaining time, to select at least one computing unit from the one or more other computing units.

10. The computing system (100) according to any one of claims 1 to 9, wherein the computing system (100) is an embedded computing system (100); or wherein the plurality of computing units (104(n = 1 to N)) are part of a network.

11. Computing system (100) according to one of claims 1 to 10, wherein the processor (102) is configured: • using the computing architecture information (112(n = 1 to N)) to determine whether one or more computing units of the plurality of computing units (104(n = 1 to N)) can satisfy the conditions (110) of the computing request (106); and • if it is determined that several computing units of the plurality of computing units (104(n = 1 to N)) can satisfy the conditions (110) of the computing request (106), to select the computing unit of these as the at least one computing unit that has a lowest expected energy consumption.

12. Computing system (100) according to one of claims 1 to 11, further comprising the plurality of computing units (104(n = 1 to N)).

13. Computing system (100) according to claim 12, wherein each computing unit of the plurality of computing units (104(n = 1 to N)) is configured to provide a result of the calculation of a computing task (108) transmitted thereto to the processor (102).

14. Method (200), comprising: • Receiving (202) a computation request (106) comprising a computation task (108) and associated conditions (110), wherein the conditions (110) comprise a power consumption condition and at least one of the conditions (110) comprising a latency condition and / or an accuracy condition; • Selecting (204) at least one computing unit from a plurality of computing units (104(n = 1 to N)), wherein each computing unit of the plurality of computing units (104(n = 1 to N)) has a respective computing architecture, wherein at least one computing unit of the plurality of computing units (104(n = 1 to N)) has a computing architecture different from at least one other computing unit of the plurality of computing units (104(n = 1 to N)), wherein each computing unit (104(n)) is assigned computing architecture information (112(n)) which contains information about properties of the respective computing unit with regard to energy consumption and at least one latency and / or accuracy when executing a computing task (108); • wherein the at least one computing unit is selected using the computing architecture information (112(n = 1 to N)).

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