Display panel and display apparatus

Abstract

The present disclosure relates to a display panel and a display device, and relates to the field of display technology. The display panel includes a driving backplane and a light-emitting device; the driving backplane has a pixel circuit located in a display area and a peripheral circuit located in a peripheral area, and the peripheral circuit includes a plurality of cascaded shift registers; a shift register is configured to scan at least one row of pixel circuits; the pixel circuit and the shift register both include a plurality of transistors; the transistors of the pixel circuit include a driving transistor, and the driving transistor and at least some of the other transistors are metal oxide transistors; the transistors in the shift register are polysilicon transistors; the light-emitting device is arranged on one side of the driving backplane; the light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light-emitting device, the second electrode is connected to the first power line transmitting the first power signal, and the second electrode of the light-emitting device is configured to receive the second power signal.

Description

CROSS REFERENCE

[0001] The present disclosure claims priority to Chinese Patent Application No. 202311279584.6, filed on September 28, 2023, and entitled "DISPLAY PANEL AND DISPLAY APPARATUS", and the entire contents thereof are incorporated herein by reference.TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device.BACKGROUND

[0003] For display panels that use organic light-emitting diodes as light-emitting devices, the uniformity of image quality is low, especially for large-sized display panels, it is difficult to improve the uniformity of image quality. Also, the frame of the display panel is wide, making it difficult to increase the screen-to-body ratio.

[0004] It should be noted that, information disclosed in the above background portion is provided only for better understanding of the background of the present disclosure, and thus it may contain information that does not form the prior art known by those ordinary skilled in the art.SUMMARY

[0005] The purpose of the present disclosure is to provide a display panel and a display device, which can improve image quality and increase screen-to-body ratio.

[0006] According to one aspect of the present disclosure, there is provided a display panel having a display area and a peripheral area outside the display area; the display panel includes: a driving backplane, including a pixel circuit located in the display area and a peripheral circuit located in the peripheral area, wherein the peripheral circuit includes a plurality of cascaded shift registers; one shift register is configured to scan at least one row of the pixel circuit; the pixel circuit and the shift register both include a plurality of transistors; the transistors of the pixel circuit include a driving transistor, and the driving transistor and at least part of other transistors in the pixel circuit are metal oxide transistors; and the transistors in the shift register are polysilicon transistors; and a plurality of light-emitting devices, disposed on a side of the driving backplane; one light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence in a direction away from the driving backplane; a first electrode of the driving transistor is connected to a first electrode of the light-emitting device, a second electrode of the driving transistor is connected to a first power line transmitting a first power signal; and a second electrode of the light-emitting device is configured to receive a second power signal.

[0007] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit and a writing circuit; the first reset circuit is connected to a gate electrode of the driving transistor, and is configured to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor, and is configured to transmit a second reset signal in response to a second reset scan signal; and the writing circuit is connected to the gate electrode of the driving transistor, and is configured to transmit a data signal in response to a write scan signal.

[0008] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a light-emitting control circuit and a storage capacitor; the first power line is connected to the second electrode of the driving transistor through the light-emitting control circuit, and the light-emitting control circuit is configured to be turned on in response to a light-emitting scan signal; and the storage capacitor is connected to the gate and the first electrode of the driving transistor.

[0009] In an exemplary embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the writing circuit includes a writing transistor, and the light-emitting control circuit includes a light-emitting control transistor; a gate of the first reset transistor is configured to receive the first reset scan signal, a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; a gate of the second reset transistor is configured to receive the second reset scan signal, a first electrode of the second reset transistor is configured to receive the second reset signal, and a second electrode of the second reset transistor is connected to the first electrode of the driving transistor; a gate of the writing transistor is configured to receive the write scan signal, a first electrode of the writing transistor is configured to receive the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor; a gate of the light-emitting control transistor is configured to receive the light-emitting scan signal, a first electrode of the light-emitting control transistor is connected to the first power line, and a second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor.

[0010] In an exemplary embodiment of the present disclosure, the shift register includes an input circuit, a first control circuit, a second control circuit and a first output circuit; the input circuit is connected to an input terminal, a first node and a first clock signal line providing a first clock signal, and is configured to transmit an input signal of the input terminal to the first node in response to the first clock signal; the first control circuit is connected to the first node, a second node, the first clock signal line and a first voltage line providing a first voltage, and is configured to control a voltage of the second node in response to the first clock signal, the first voltage and a voltage of the first node; the second control circuit is connected to the first node, the second node, a second voltage line providing a second voltage, and a second clock signal line providing a second clock signal, and is configured to control a voltage of the first node in response to the second clock signal, the second voltage, and the voltage of the second node; and the first output circuit is connected to the first node, the second node, a third voltage line providing a third voltage, a third clock signal line providing a third clock signal, and a first output terminal, and is configured to output the third voltage or the third clock signal through the first output terminal under control of the voltages of the first node and the second node.

[0011] In an exemplary embodiment of the present disclosure, the first output circuit includes a first output sub-circuit and a second output sub-circuit; the first output sub-circuit is connected to the first node, the first output terminal and the third clock signal line, and is configured to control the first output terminal and the third clock signal line to be connected or disconnected under the control of the voltage of the first node; and the second output sub-circuit is connected to the second node, the third voltage line and the first output terminal, and is configured to control the first output terminal and the third voltage line to be connected or disconnected in response to the voltage of the second node.

[0012] In an exemplary embodiment of the present disclosure, the shift register further includes a second output circuit, the second output circuit being connected to the first node, the second node, the second voltage line, the second clock signal line and a second output terminal, and being configured to output the second voltage or the second clock signal through the second output terminal under control of the voltages of the first node and the second node.

[0013] In an exemplary embodiment of the present disclosure, the second output circuit includes a third output sub-circuit and a fourth output sub-circuit; the third output sub-circuit is connected to the first node, the second voltage line and the second output terminal, and is configured to control the second output terminal and the second clock signal line to be connected or disconnected in response to the voltage of the first node; and the fourth output sub-circuit is connected to the second node and the second output terminal, and is configured to control the second output terminal and the second voltage line to be connected or disconnected in response to the voltage of the second node.

[0014] In an exemplary embodiment of the present disclosure, the shift register further includes a first isolation circuit and a second isolation circuit; first isolation circuit is connected to the first node and the first output sub-circuit, and is connected to the first voltage line; and the second isolation circuit is connected to the first node and the third output sub-circuit, and is connected to the first voltage line.

[0015] In an exemplary embodiment of the present disclosure, the third output sub-circuit is connected to the first node via a third node; and the shift register further includes a third control circuit connected to the first node, the third node and a fourth voltage line providing a fourth voltage, and configured to control the voltage of the first node in response to voltages of the third node and the fourth voltage.

[0016] In an exemplary embodiment of the present disclosure, the input circuit includes an input transistor, a gate of the input transistor is connected to the first clock signal line, a first electrode of the input transistor is connected to the input terminal, and a second electrode of the input transistor is connected to the first node; the first control circuit includes a first control transistor and a second control transistor, wherein a gate of the first control transistor is connected to the first clock signal line, a first electrode of the first control transistor is connected to the first voltage line, and a second electrode of the first control transistor is connected to the second node; a gate of the second control transistor is connected to the first node, a first electrode of the second control transistor is connected to the first clock signal line, and a second electrode of the second control transistor is connected to the second node; the second control circuit includes a third control transistor and a fourth control transistor, wherein a gate of the third control transistor is connected to the second node, a first electrode of the third control transistor is connected to the second voltage line, a second electrode of the third control transistor is connected to a first electrode of the fourth control transistor, the second electrode of the fourth control transistor is connected to the first node, and a gate of the fourth control transistor is connected to the second clock signal line; the first output sub-circuit includes a first output transistor, and the first isolation circuit includes a first isolation transistor; a gate of the first isolation transistor is connected to the first voltage line, a first electrode of the first isolation transistor is connected to the first node, and a second electrode of the first isolation transistor is connected to a gate of the first output transistor; a first electrode of the first output transistor is connected to the third clock signal line, and a second electrode of the first output transistor is connected to the first output terminal; and the second output sub-circuit includes a second output transistor and a first capacitor, a gate of the second output transistor is connected to the second node, a first electrode of the second output transistor is connected to the third voltage line, and a second electrode of the second output transistor is connected to the first output terminal; the first capacitor is connected to the gate and the first electrode of the second output transistor.

[0017] In an exemplary embodiment of the present disclosure, the third output sub-circuit includes a third output transistor and a second capacitor, and the second isolation circuit includes a second isolation transistor; a gate of the second isolation transistor is connected to the first voltage line, a first electrode of the second isolation transistor is connected to the first node, and a second electrode of the second isolation transistor is connected to the third node; a gate of the third output transistor is connected to the third node, a first electrode of the third output transistor is connected to the second clock signal line, and a second electrode of the third output transistor is connected to the second output terminal; and the second capacitor is connected to the gate and the second electrode of the third output transistor; and the fourth output sub-circuit includes a fourth output transistor, a gate of the fourth output transistor is connected to the second node, a first electrode of the fourth output transistor is connected to the second voltage line, and a second electrode of the fourth output transistor is connected to the second output terminal.

[0018] In an exemplary embodiment of the present disclosure, the third control circuit includes a fifth control transistor, a gate of the fifth control transistor is connected to the third node, a first electrode of the fifth control transistor is connected to the fourth voltage line, and a second electrode of the fifth control transistor is connected to the first node.

[0019] In an exemplary embodiment of the present disclosure, each transistor of the pixel circuit is a metal oxide transistor; and each transistor of the shift register is a polysilicon transistor.

[0020] In an exemplary embodiment of the present disclosure, the driving backplane includes a substrate and a light shielding layer, a polysilicon semiconductor layer, a first gate layer, a second gate layer, an oxide semiconductor layer, a third gate layer, a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate; the first electrode is disposed on a side of the second source-drain layer away from the substrate; a channel portion of the transistor of the shift register is located in the polysilicon semiconductor layer; and a channel portion of each transistor of the pixel circuit is located in the oxide semiconductor layer; a first electrode plate of the first capacitor and a first electrode plate of the second capacitor are located in the first gate layer, and a second electrode plate of the first capacitor and a second electrode plate of the second capacitor are located in the second gate layer; a first electrode plate of the storage capacitor is located in the light shielding layer, and a second electrode plate of the storage capacitor is located in the second gate layer; and the first clock signal line, the second clock signal line, the third clock signal line, the first voltage line, the second voltage line and the third voltage line are located in the first source-drain layer; and the fourth voltage line is located in the second source-drain layer.

[0021] In an exemplary embodiment of the present disclosure, orthographic projections of the first clock signal line, the second clock signal line, the second voltage line, the first voltage line, the fourth voltage line, the third clock signal line and the third voltage line on the substrate are all extended along a column direction and are sequentially arranged along a row direction toward the display area; and in one shift register, the first output transistor and the second output transistor are located between orthographic projections of the third voltage line and the pixel circuit on the substrate, and orthographic projections of other transistors and the first capacitor on the substrate are located between orthographic projections of the second voltage line and the third clock signal line on the substrate.

[0022] In an exemplary embodiment of the present disclosure, orthographic projections of channel portions of the input transistor, the first control transistor, the second control transistor, the third control transistor and the fourth control transistor are located between orthographic projections of the first voltage line and the second voltage line on the substrate; and orthographic projections of the third output transistor, the fourth output transistor, the fifth control transistor, the first isolation transistor, the second isolation transistor and the first capacitor on the substrate are located between orthographic projections of the first voltage line and the third clock signal line on the substrate.

[0023] In an exemplary embodiment of the present disclosure, a channel portion of at least one of the input transistor, the first output transistor, and the second output transistor includes at least two channels connected in series.

[0024] In an exemplary embodiment of the present disclosure, the polysilicon semiconductor layer includes a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, a fourth semiconductor portion, a fifth semiconductor portion, a sixth semiconductor portion, a seventh semiconductor portion, an eighth semiconductor portion, and a ninth semiconductor portion; orthographic projections of the first semiconductor portion to the fourth semiconductor portion on the substrate are located between the orthographic projections of the second voltage line and the first voltage line on the substrate; the first semiconductor portion, the second semiconductor portion and the third semiconductor portion are distributed along the row direction; and the first semiconductor portion and the fourth semiconductor portion are distributed along the column direction; orthographic projections of the fifth semiconductor portion to the eighth semiconductor portion on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate; and the fifth semiconductor portion to the eighth semiconductor portion are distributed along the column direction; an orthographic projection of the ninth semiconductor portion on the substrate is located between the third voltage line and the pixel circuit; the channel portion of the input transistor is located in the first semiconductor portion; the channel portion of the second control transistor is located in the second semiconductor portion; the channel portion of the first control transistor is located in the second semiconductor portion; the channel portion of the third control transistor and the fourth control transistor are located in the fourth semiconductor portion; the channel portion of the first isolation transistor is located in the fifth semiconductor portion; the channel portion of the second isolation transistor is located in the sixth semiconductor portion; the channel portion of the fifth control transistor is located in the seventh semiconductor portion; the channel portions of the three output transistors and the fourth output transistor are located in the eighth semiconductor portion; the channel portions of the first output transistor and the second output transistor are located in the ninth semiconductor portion.

[0025] In an exemplary embodiment of the present disclosure, the first gate layer includes a first gate portion, a second gate portion, a third gate portion, a fourth gate portion, a fifth gate portion, a sixth gate portion and a seventh gate portion; the first gate portion is overlapped with the first semiconductor portion and the third semiconductor portion to form the input transistor and the first control transistor, and the first gate portion is connected to the first clock signal line through a contact hole; the second gate portion is overlapped with the second semiconductor portion to form the second control transistor; the third gate portion is overlapped with the fourth semiconductor portion to form the fourth control transistor, and the third gate portion is connected to the second clock signal line through a contact hole; the fourth gate portion is overlapped with the fourth semiconductor portion, the eighth semiconductor portion and the ninth semiconductor portion to form the third control transistor, the fourth output transistor and the second output transistor; and the third gate portion includes a first electrode plate of the second capacitor; the fifth gate portion is overlapped with the fifth semiconductor portion and the sixth semiconductor portion to form the first isolation transistor and the second isolation transistor; and the fifth gate portion is connected to the first voltage line through a contact hole; the sixth gate portion is overlapped with the seventh semiconductor portion and the eighth semiconductor portion to form the fifth control transistor and the third output transistor; and the sixth gate portion includes a first electrode plate of the first capacitor; and the seventh gate portion is overlapped the ninth semiconductor portion to form the first output transistor.

[0026] In an exemplary embodiment of the present disclosure, in the shift register, widths of the channel portions of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor in the row direction are greater than widths of the channel portions of other transistors in the row direction.

[0027] In an exemplary embodiment of the present disclosure, the first gate layer further includes a cascade jumper portion; the second gate layer includes a first transfer portion and a second transfer portion; the first source-drain layer includes a scan output portion, a cascade output portion, a cascade line, a first connection portion, a second connection portion and a third connection portion; the scan output portion is overlapped with the ninth semiconductor portion and is connected through a contact hole to connect the second electrode of the first output transistor and the second electrode of the second output transistor; cascade output portion is overlapped with the eighth semiconductor portion and is connected through a contact hole to connect the second electrode of the third output transistor and the second electrode of the fourth output transistor; the cascade line extends along the column direction and is located between the second voltage line and the first voltage line; the cascade jumper portion is extended along the row direction and is overlapped with the first voltage line, and the cascade output portion and the cascade line are connected through a contact hole; the first connecting portion is overlapped with the ninth semiconductor portion and is connected through a contact hole to connect the first electrode of the first output transistor; the first switching portion is extended along the row direction and is overlapped with the first connecting portion and the third voltage line, and is connected to the third clock signal line and the first connecting portion through a contact hole; and the second connection portion is overlapped with the eighth semiconductor portion and is connected through a contact hole to connect to the first electrode of the fourth output transistor; the third connection portion is connected to the second voltage line; the second transfer portion is extended along the row direction and is overlapped with the first voltage line, and the second transfer portion is connected to the second connection portion and the third connection portion through a contact hole.

[0028] According to one aspect of the present disclosure, there is provided a display device including anyone of the above the display panel.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for those skilled in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative effort. FIG. 1 is a schematic top view of an embodiment of a display panel according to the present disclosure. FIG. 2 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure. FIG. 3 is a schematic diagram of a pixel circuit of an embodiment of a display panel according to the present disclosure. FIG. 4 is a timing diagram of a driving method of a pixel circuit of an embodiment of a display panel according to the present disclosure. FIG. 5 is a schematic diagram of a shift register of an embodiment of a display panel according to the present disclosure. FIG. 6 is a timing diagram of a driving method of a shift register of an embodiment of a display panel according to the present disclosure. FIGS. 7 to 10 are schematic diagrams of the shift register in FIG. 5 during the first to fourth stages. FIG. 11 is a partial top view of a display area in an embodiment of a display panel according to the present disclosure. FIG. 12 is a partial top view of the light shielding layer to the first source-drain layer in the display area of an embodiment of the display panel according to the present disclosure. FIG. 13 is a partial top view of the light shielding layer to the third gate layer in the display area of an embodiment of the display panel according to the present disclosure. FIGS. 14 to 19 are partial top views of a portion of the film layer in the display area of an embodiment of the display panel according to the present disclosure. FIG. 20 is a partial top view of the peripheral area of an embodiment of a display panel according to the present disclosure. FIG. 21 is a partial top view of the polysilicon semiconductor layer to the first source-drain layer in the peripheral region of an embodiment of the display panel according to the present disclosure. FIG. 22 is a partial top view of the polysilicon semiconductor layer to the second gate layer in the peripheral region of an embodiment of the display panel according to the present disclosure. FIG. 23 is a partial top view of the polysilicon semiconductor layer to the first gate layer in the peripheral region of an embodiment of the display panel according to the present disclosure. FIGS. 24 to 28 are partial top views of a portion of the film layer in the peripheral area of an embodiment of the display panel according to the present disclosure. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0032] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0033] The row direction X and the column direction Y herein are two intersecting directions, which may be perpendicular to each other or may be at an angle other than a right angle. In the drawings of the present disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limited thereto. It is known to those skilled in the art that if the display panel is rotated, the actual directions of the row direction X and the column direction Y may change.

[0034] Herein, "overlapping" of A and B means that the orthographic projection of A on the substrate SU and the orthographic projection of B on the substrate SU at least partially overlap. Of course, it may also be that the orthographic projections of A and B on a plane parallel to the substrate SU at least partially overlap.

[0035] The transistor in this disclosure includes a gate, a first electrode, and a second electrode. The first electrode and the second electrode can be turned on and off by controlling the voltage of the gate; the first electrode can be a source electrode, and the second electrode can be a drain electrode; of course, the first electrode can also be a drain electrode, and the second electrode can also be a source electrode. Specifically, if the signal is input from the first electrode, the first electrode is the source electrode and the second electrode is the drain electrode; if the signal is input from the second electrode, the second electrode is the source electrode and the first electrode is the drain electrode; that is, the source electrode and the drain electrode can be interchanged depending on the change of the input signal.

[0036] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0037] An embodiment of the present disclosure provides a display panel, as shown in FIG. 1, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA.

[0038] As shown in FIG. 2, the display panel may include a driving backplane BP and a plurality of light-emitting devices LD disposed on a side of the driving backplane BP. Each light-emitting device LD may be distributed in an array along a row direction X and a column direction Y. The driving circuit in the driving backplane BP may drive the light-emitting device LD to emit light to display an image.

[0039] As shown in FIG. 2, the light-emitting device LD may be an OLED (organic light-emitting diode) made of organic light-emitting materials; or an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); or devices such as QLED (quantum dot diode) may be used. No special limitation is made to the specific structure of the light-emitting device LD herein.

[0040] Taking the light-emitting device LD being the OLED as an example, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying a first power signal to the first electrode ANO and a second power signal to the second electrode CAT, the light-emitting layer EL may be excited to emit light. The specific principle will not be described in detail here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL may be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL may have a pixel opening exposing each first electrode ANO, so that the range of the light-emitting device LD may be limited by each pixel opening.

[0041] The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit PC may be distributed in an array along the row direction X and the column direction Y. A pixel circuit PC may be connected to a first electrode ANO of a light-emitting device LD. Of course, one same pixel circuit PC may also be connected to the first electrodes ANO of multiple light-emitting devices LD.

[0042] As shown in FIG. 3, the pixel circuit PC may include a plurality of transistors, and any of the transistors of the pixel circuit PC includes at least a driving transistor M5, and the driving transistor M5 may be a metal oxide transistor, and at least a portion of the other transistors may also be metal oxide transistors. Of course, it may also be that only the driving transistor M5 is a metal oxide transistor. A metal oxide transistor refers to a material of its active layer IGZO (Indium Gallium Zinc Oxide), and may also be IZO (Indium Zinc Oxide) etc., the active layer of the transistor includes a channel portion and a conductor portion connected to the channel.

[0043] Taking a pixel circuit PC as an example, as shown in FIG. 3, the pixel circuit PC may include a driving transistor M5, a writing circuit 1, a first reset circuit 2, a second reset circuit 3 and a light-emitting control circuit 4, wherein:

[0044] The first reset circuit 2 is connected to the gate of the driving transistor M5, and can be turned on or off in response to the first reset scan signal Gate2. The first reset circuit 2 can receive the first reset signal Vref, and can transmit the first reset signal Vref when turned on.

[0045] The second reset circuit 3 is connected to the first electrode of the driving transistor M5, and can be turned on or off in response to the second reset scan signal Gate3. The second reset circuit 3 can receive the second reset signal Vinit, and can transmit the second reset signal Vinit when turned on.

[0046] The writing circuit 1 is connected to the gate of the driving transistor M5, and the writing circuit 1 can be turned on or off in response to the write scan signal Gate1. The writing circuit 1 can receive the data signal Data and can transmit the data signal Data when turned on.

[0047] The light-emitting control circuit 4 can receive the first power supply signal VDD and be connected to the second electrode of the driving transistor M5. The light-emitting control circuit 4 can be turned on or off in response to the light-emitting scan signal EM, and when turned on, it can transmit the first power supply signal VDD to the driving transistor M5. The storage capacitor Cst is connected to the gate and the first electrode of the driving transistor M5.

[0048] Further, in some embodiments of the present disclosure, as shown in FIG. 3, the pixel circuit PC is a 5T1C structure, that is, 5 transistors and 1 capacitor, specifically: the first reset circuit 2 includes a first reset transistor M2, the second reset circuit 3 includes a second reset transistor M3, the writing circuit 1 includes a writing transistor M1, and the light-emitting control circuit 4 includes a light-emitting control transistor M4. Each transistor of the pixel circuit PC is a metal oxide transistor.

[0049] As shown in FIG. 11- FIG. 13, in order to facilitate signal transmission, the driving backplane BP may further include a first power line VDL, a data line DAL, a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, a light-emitting scan line EML, a first reset signal line VRL, and a second reset signal line VIL; wherein: the first power line VDL and the data line DAL may be extended along the column direction Y, and may be distributed along the row direction X. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting scan line EML, the first reset signal line VRL, and the second reset signal line VIL may be extended along the row direction X, and may be distributed along the column direction Y.

[0050] The first reset scan line GL2 is connected to the gate of the first reset transistor M2 and is used to transmit the first reset scan signal Gate2. The first reset signal line VRL is connected to the first electrode of the first reset transistor M2 and can transmit the first reset signal Vref. The second electrode of the first reset transistor M2 is connected to the gate of the driving transistor M5 and is connected to the N1 node. The first reset transistor M2 can be controlled to be turned on or off by the first reset scan signal Gate2, and when turned on, the first reset signal Vref can be transmitted to the gate of the driving transistor M5 through the first reset transistor M2, that is, the first reset signal Vref is transmitted to the N1 node.

[0051] The second reset scan line GL3 is connected to the gate of the second reset transistor M3 and is used to transmit the second reset scan signal Gate3; the second reset signal line VIL is connected to the first electrode of the second reset transistor M3 and can transmit the second reset signal Vinit; the second electrode of the second reset transistor M3 is connected to the first electrode of the driving transistor M5 and can be connected to the N3 node. The second reset scan signal Gate3 can control the second reset transistor M3 to be turned on or off, and when turned on, the second reset signal Vinit can be transmitted to the first electrode of the driving transistor M5 through the second reset transistor M3, that is, the second reset signal Vinit is transmitted to the N3 node.

[0052] The light-emitting scan line EML is connected to the gate of the light-emitting control transistor M4, and is used to transmit the light-emitting scan signal EM; the first power line VDL is connected to the first electrode of the light-emitting control transistor M4, and the second electrode of the light-emitting control transistor M4 is connected to the second electrode of the driving transistor M5, and can be connected to the N2 node. The first power line VDL is used to transmit the first power signal VDD. The light-emitting scan signal EM can control the light-emitting control transistor M4 to be turned on or off, and when turned on, the first power signal VDD can be transmitted to the second electrode of the driving transistor M5 through the light-emitting control transistor M4.

[0053] The write scan line GL1 is connected to the gate of the writing transistor M1 and is used to transmit the write scan signal Gate1; the data line DAL is connected to the first electrode of the writing transistor M1 and can transmit the data signal Data; the second electrode of the writing transistor M1 is connected to the gate of the driving transistor M5 and can be connected to the N1 node. The write scan signal Gate1 can control the writing transistor M1 to be turned on or off, and when turned on, the data signal Data can be transmitted to the gate of the driving transistor M5 through the writing transistor M1, that is, the data signal Data is transmitted to the N1 node.

[0054] Meanwhile, the storage capacitor Cst has a first electrode Cst1 and a second electrode Cst2 opposite to each other, the first electrode Cst1 is connected to the first electrode of the driving transistor M5 and can be connected to the N3 node, the second electrode Cst2 is connected to the gate of the driving transistor M5 and can be connected to the N1 node. The first electrode of the driving transistor M5 and the second electrode of the second reset transistor M3 can be connected to the first electrode ANO of the light-emitting device LD and can be connected to the N3 node.

[0055] In some embodiments of the present disclosure, as shown in FIGS. 11-13, the driving backplane BP further includes a second power line, a first auxiliary first power line VDLs, and a second auxiliary power line VSLs, wherein:

[0056] The second power line may extend along the column direction Y, may be multiple in number, and may be distributed along the row direction X. Of course, the number of the second power line may also be one. The second power line is used to transmit the second power signal VSS, and may be connected to the second electrode CAT of the light-emitting device LD. For example, the driving backplane BP is provided with a first power bus for transmitting the first power signal VDD and a second power bus for transmitting the second power signal VSS in the peripheral area WA. Each first power line VDL may be connected to the first power bus, and the second power line may be connected to the second power bus. At the same time, the second electrode CAT of the light-emitting device LD may extend to the peripheral area WA and be directly or indirectly connected to the second power bus. The second power line and the second power bus may form a whole for transmitting the second power signal VSS. While transmitting the second power signal VSS to the second electrode through the second power bus, the second power line may play a role in reducing resistance and voltage drop, which is conducive to maintaining signal stability and uniformity. Of course, in some embodiments, the second power line may not be provided.

[0057] The first auxiliary first power line VDLs may extend along the row direction X, and the number of the first auxiliary first power line VDLs may be multiple and distributed along the column direction Y. Of course, there may be only one first auxiliary first power line VDLs. Meanwhile, the first auxiliary first power line VDLs may cross the first power line VDL in space, but be located in different layers and may be connected through contact holes, so that the first auxiliary first power line VDLs and the first power line VDL form a network for transmitting the first power signal VDD, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0058] The second power line may extend along the row direction X, may be multiple in number, and may be distributed along the column direction Y. Of course, there may also be only one second power line. Meanwhile, the second auxiliary power line VSLs may cross the second power line in space, but be located in different layers, and may be connected through a contact hole, so that the second auxiliary power line VSLs and the second power line form a network for transmitting the second power signal VSS, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0059] Further, in some embodiments of the present disclosure, as shown in FIG. 10 to FIG. 12, the driving backplane BP further includes a first auxiliary reset line extending along the column direction Y, and the number of the first auxiliary reset line may be multiple and distributed along the column direction Y. Of course, there may also be only one. At the same time, the first auxiliary reset line and the first reset signal line VRL are located in different layers and are connected through contact holes, so as to form a network for transmitting the first reset signal Vref, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0060] Further, in some embodiments of the present disclosure, as shown in FIG. 10 to FIG. 12, the driving backplane BP further includes a second auxiliary reset line VILs extending along the column direction Y, and the number of the second auxiliary reset lines VILs may be multiple and distributed along the column direction Y. Of course, there may also be only one. At the same time, the second auxiliary reset line VILs and the second reset signal line VIL are located in different layers and are connected through contact holes, thereby forming a network for transmitting the second reset signal Vinit, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0061] The following is an exemplary description of the distribution of the above wiring:

[0062] In some embodiments of the present disclosure, as shown in FIG. 1 and FIG. 11 - FIG. 13, a data line DAL is connected to the writing transistors M1 of a column of pixel circuits PC; a first power line VDL is connected to the light-emitting control transistors M4 of a column of pixel circuits PC. The data line DAL and the first power line VDL connected to the same column of pixel circuits PC can be defined as a column line group, that is, each column of pixel circuits PC can be connected to a column line group. At the same time, one of the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs can be provided between two adjacent column line groups, that is, the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs are distributed in the space between the column line groups; at the same time, two of the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs are provided on the two sides of the same column line group. In this way, the space can be fully utilized to make the distribution of the wiring in the column direction Y more uniform.

[0063] For example, as shown in FIG. 1, FIG. 11- FIG. 13, the second power line, the first auxiliary reset line and the second auxiliary reset line VILs can be defined as auxiliary lines, and the auxiliary lines and the above-mentioned column line groups can be alternately distributed along the row direction X. In the row direction X, if the nth auxiliary line is the second power line, then the n+1th auxiliary line is the second auxiliary reset line VILs, and the n+ 2th auxiliary line is the first auxiliary reset line, and n is a positive integer. Of course, the auxiliary lines can also be arranged in other arrangement orders, which will not be described in detail here.

[0064] In some embodiments of the present disclosure, as shown in FIG. 11 - FIG. 13, a row of pixel circuits PC is simultaneously connected to a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, a light-emitting scan line EML, a first reset signal line VRL, and a second reset signal line VIL. The specific connection relationship has been described in the above content of the pixel circuit PC, and will not be repeated here. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting scan line EML, the first reset signal line VRL, and the second reset signal line VIL connected to the same row of pixel circuits PC can be defined as a row line group, that is, each row of pixel circuits PC is connected to a row line group. At the same time, a first auxiliary first power line VDLs and a second auxiliary power line VSLs can be provided between two adjacent row line groups. A row line group is located between a first auxiliary first power line VDLs and a second auxiliary power line VSLs.

[0065] Hereinafter, the driving method of the pixel circuit PC is described based on the structure of the pixel circuit PC of the above embodiment:

[0066] As shown in FIG. 3 and FIG. 4, taking the above-mentioned pixel circuit PC of 5T1C structure as an example, each transistor is a metal oxide transistor and an N-type transistor, which is convenient for improving the uniformity of the transistors in the display area AA. The driving method of the pixel circuit may include:

[0067] In the initialization stage t1: the first reset scan signal Gate2 is at a high level, the first reset transistor M2 and the second reset transistor M3 are turned on, the first reset signal Vref is transmitted to the gate of the driving transistor M5, and the second reset signal Vinit is transmitted to the first electrode of the driving transistor M5 and the first electrode ANO of the light-emitting device, that is, the second reset signal Vinit is transmitted to the N3 node; at the same time, the write scan signal Gate1 and the light-emitting scan signal EM are at a low level, and the writing transistor M1 and the light-emitting control transistor M4 are turned off. The gate and the first electrode of the driving transistor M5 and the first electrode ANO of the light-emitting device are initialized by the first reset signal Vref and the second reset signal Vinit, that is, the N1 node and the N3 node are initialized. At this time, the voltage of the N1 node = Vref, and the voltage of the N3 node = Vinit.

[0068] Compensation stage t2: The first reset scan signal Gate2 maintains a high level, the second reset scan signal Gate3 is a low level, the first reset transistor M2 continues to be turned on, and transmits the first reset signal Vref to the gate of the driving transistor M5, that is, transmits the first reset signal Vref to the N1 node, and the second reset transistor M3 is turned off. At the same time, the light-emitting scan signal EM is a high level, and the light-emitting control transistor M4 is turned on.

[0069] When the voltage difference between the first reset signal Vref and the second reset signal Vinit is greater than the threshold voltage of the driving transistor M5, that is, when the voltage difference between the N1 node and the N3 node is greater than the threshold voltage, the driving transistor M5 is turned on; the first power supply signal VDD charges the first electrode of the driving transistor M5 until reaching the difference between the first reset signal Vref and the threshold voltage of the driving transistor M5, that is, when the voltage of the N3 node is Vref-Vth, the driving transistor M5 is turned off, thereby writing the threshold voltage into the first electrode of the driving transistor M5. At this time, the voltage of the N1 node = Vref, and the voltage of the N3 node = Vref-Vth.

[0070] In the writing stage t3, the first reset scan signal Gate2, the second reset scan signal Gate3 and the light-emitting scan signal EM are all at low level, and the writing scan signal Gate1 is at high level; the first reset transistor M2, the second reset transistor M3 and the light-emitting control transistor M4 are turned off, and the writing transistor M1 is turned on. The data signal Data is written to the N1 node through the writing transistor M1, that is, the data signal Data is written to the gate of the driving transistor M5 and the second electrode plate Cst2 of the storage capacitor Cst; at this time, the voltage of the N1 node Vg = Vdata, the voltage of the N3 node = Vld + Vss = Vref - Vth, Vld is the voltage of the light-emitting device LD, that is, the voltage of the capacitor Co of the light-emitting device LD itself.

[0071] In the light-emitting stage t4: the light-emitting scan signal EM is at a high level, the first reset scan signal Gate2, the second reset scan signal Gate3 and the write scan signal Gate1 are at a low level, the light-emitting control transistor M4 is turned on, and the first reset transistor M2, the second reset transistor M3 and the writing transistor M1 are turned off; under the action of the storage capacitor Cst, the driving transistor M5 outputs a current, and the output current satisfies the following formula: I = μWCox / 2 L Vgs − Vth 2 ;

[0072] I is the output current of the driving transistor M5; µ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor M5, and L is the channel length of the driving transistor M5.

[0073] According to the above formula of output current, it can be obtained by substituting the voltage difference Vgs between the gate voltage and the source voltage of the driving transistor M5 in the pixel circuit PC of the present disclosure into the above formula: the output current of the driving transistor M5 I = (µWCox / 2L)(Vdata-Vref) 2< .

[0074] It can be seen that the threshold voltage compensation stage and the data signal Data writing stage are performed separately, and the output current (i.e., the current of the light-emitting device) is not affected by the voltage of the first power signal VDD or the threshold voltage Vth, but only by Vdata and Vref. The first reset signal Vref has a smaller current than the first power signal VDD, and has a smaller risk of IR Drop (voltage drop).

[0075] The peripheral area WA of the display panel may also be provided with a power bus connected to the second electrode CAT of the light-emitting device LD, and a second power signal is applied to the second electrode CAT. The current passing through the light-emitting device LD can be controlled through the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD.

[0076] As shown in FIGS. 1 to 3, the peripheral circuit may be connected to the light-emitting device LD through the pixel circuit PC, and a first power signal VDD may be applied to the first electrode ANO of the light-emitting device LD. The peripheral circuit may also include a gate driving circuit and a light-emitting driving circuit for scanning the pixel circuit PC. At the same time, the peripheral circuit may also be connected to the second electrode CAT of the light-emitting device LD, and a second power signal VSS may be applied to the second electrode CAT. The current passing through the light-emitting device LD may be controlled through the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD.

[0077] As shown in FIG. 1, a peripheral circuit may include a plurality of cascaded shift registers GOA, that is, the output end of the previous shift register GOA is connected to the input end IN of the next shift register GOA, so that the output signal of the previous shift register GOA is used as the input signal of the lower next register GOA. At the same time, the input signal of the first shift register GOA may be a trigger signal. In addition, in some embodiments, the first shift register GOA may be a dummy register, and its output end is not connected to the pixel circuit PC, but only serves as the input signal of the lower shift register GOA. Any shift register GOA may include a plurality of transistors and capacitors, which may be 12T2C, 8T2C, 10T3C and other structures, which are not specifically limited here. At least some of the transistors in the shift register are polysilicon transistors, because polysilicon transistors can obtain good mobility and good electrical characteristics at a smaller size, so that they can have good electrical characteristics while reducing the occupied space, which is conducive to reducing the width of the peripheral area, narrowing the frame, and increasing the screen ratio.

[0078] As shown in FIG. 4, the peripheral circuit can be connected to the light-emitting device LD through the pixel circuit PC, and a first power supply signal is applied to the first electrode ANO of the light-emitting device LD. The number of peripheral circuits can be multiple, and they are classified into multiple categories, which are used to scan the transistors in the pixel circuit. Taking the above-mentioned 5T1C pixel circuit as an example, the peripheral circuit may include a gate driving circuit for scanning some transistors in the pixel circuit PC (for example, at least one of the writing transistor M1, the first reset transistor M2, and the second reset transistor M3), that is, outputting a write scan signal Gate1, a first reset scan signal Gate2, and a second reset scan signal Gate3 to the gates of the writing transistor M1, the first reset transistor M2, and the second reset transistor M3. The peripheral circuit may also include a light-emitting driving circuit, which can be used to scan the light-emitting control transistor M4, that is, outputting a light-emitting scan signal EM to the gate of the light-emitting control transistor M4. The write scan signal Gate1, the first reset scan signal Gate2, the second reset scan signal Gate3, and the light-emitting scan signal EM are all scan signals output by the peripheral circuit. The scan signals output by the above-mentioned gate driving circuit and light-emitting driving circuit can control the on and off of the transistors in the pixel circuit PC, that is, scanning the pixel circuit PC.

[0079] The output signal of the output end of the shift register GOA includes the above-mentioned scan signal, and the gates of some transistors of one row of pixel circuits PC can be connected to the output end of one stage of shift register GOA; of course, the one stage of shift register GOA can be connected to multiple rows of pixel circuits PC to scan multiple rows of pixel circuits PC at the same time, but the output signal of the same shift register GOA may have different effects in different rows of pixel circuits PC. For example, when the pixel circuit PC of the i-th row is in the writing stage, the pixel circuit PC of the i+1-th row is in the first reset stage, and i is a positive integer.

[0080] In addition, as shown in FIG. 5, in some embodiments, the shift register GOA may have two output terminals, such as a first output terminal Gout1 and a second output terminal Gout2, wherein the output signal of the first output terminal Gout1 is a scan signal for scanning the pixel circuit PC. The second output terminal Gout2 may be connected to the input terminal IN of the next-stage shift register GOA, and the output signal of the second output terminal Gout2 is used as the input signal of the next-stage shift register, and does not scan the pixel circuit.

[0081] Hereinafter, one shift register GOA is taken as an example for description:

[0082] As shown in FIG. 1 and FIG. 5, the shift register may include an input circuit 10, a first control circuit 20, a second control circuit 30, a first output circuit 40 and a second output circuit 50, wherein:

[0083] The input circuit 10 is connected to the first node N11 of the input terminal IN and the first clock signal line CKL1 providing the first clock signal CK1, and is used to transmit the input signal of the input terminal IN to the first node N11 in response to the first clock signal CK1.

[0084] The first control circuit 20 is connected to the first node N11, the second node N12, the first clock signal line CKL1 and the first voltage line VGLL1 providing the first voltage VGL1, and controls the voltage of the second node N12 in response to the first clock signal CK1, the first voltage VGL1 and the voltage of the first node N11.

[0085] The second control circuit 30 is connected to the first node N11, the second node N12, the second voltage line VGHL providing the second voltage VGH and the second clock signal line CBL1 providing the second clock signal CB1, and is used to control the voltage of the first node N11 in response to the second clock signal CB1, the second voltage VGH and the voltage of the second node N12.

[0086] The first output circuit 40 is connected to the first node N11, the second node N12, the third voltage line VGLL2 providing the third voltage VGL2, the third clock signal line CKL2 providing the third clock signal CK2, and the first output terminal Gout1, and is used to output the third voltage VGL2 or the third clock signal CK2 through the first output terminal Gout1 under the control of the voltages of the first node N11 and the second node N12. The output signal of the first output terminal Gout1 is a scan signal, which can be used to scan at least part of the transistors of each pixel circuit in at least one row of pixel circuits.

[0087] Further, as shown in FIG. 5, in some embodiments of the present disclosure, the first output circuit 40 may include a first output sub-circuit 401 and a second output sub-circuit 402, wherein:

[0088] The first output sub-circuit 401 is connected to the first node N11, the first output terminal Gout1 and the third clock signal line CKL2, and is used to control the first output terminal Gout1 and the third clock signal line CKL2 to be connected or disconnected under the control of the voltage of the first node N11.

[0089] The second output sub-circuit 402 is connected to the second node N12, the third voltage line VGLL2, and the first output terminal Gout1, and is used to control the first output terminal Gout1 and the third voltage line VGLL2 to be connected or disconnected in response to the voltage of the second node N12.

[0090] For example, the third voltage VGL2 of the third voltage line VGLL2 can be a high level signal; the third clock signal CK2 is a pulse signal, which has low level and high level. By controlling the first output terminal Gout1 and the third clock signal line CKL2 to be connected or disconnected, the output signal of the first output terminal Gout1 can be made high level or low level.

[0091] In some embodiments of the present disclosure, as shown in FIG. 5, the shift register GOA may further include a second output circuit 50, which is connected to the first node N11, the second node N12, the second voltage line VGHL, the second clock signal line CBL1, and the second output terminal Gout2, and is used to output the second voltage VGH or the second clock signal CB1 through the second output terminal Gout2 under the control of the voltages of the first node N11 and the second node N12. The second output terminal Gout2 may be connected to the input terminal IN of the next stage shift register, and the output signal of the second output terminal Gout2 serves as the input signal of the next stage shift register.

[0092] Further, as shown in FIG. 5, the second output circuit 50 may include a third output sub-circuit 501 and a fourth output sub-circuit 502, wherein:

[0093] The third output sub-circuit 501 is connected to the first node N11, the second voltage line VGHL and the second output terminal Gout2, and is used to control the second output terminal Gout2 and the second clock signal line CBL1 to be connected or disconnected in response to the voltage of the first node N11;

[0094] The fourth output sub-circuit 502 is connected to the second node N12 and the second output terminal Gout2, and is used for controlling the second output terminal Gout2 and the second voltage line VGHL to be connected or disconnected in response to the voltage of the second node N12.

[0095] For example, the second voltage VGH of the second voltage line VGHL can be a high level; the second clock signal CB1 is a pulse signal, which has a low level and a high level. By controlling the second output terminal Gout2 and the second clock signal line CBL1 to be connected or disconnected, the output signal of the second output terminal Gout2 can be a high level or a low level.

[0096] In some embodiments of the present disclosure, the shift register GOA may further include a first isolation circuit 60 and a second isolation circuit 70, wherein:

[0097] The first isolation circuit 60 is connected to the first node N11 and the first output sub-circuit 401, and is connected to the first voltage line VGLL1. The first isolation circuit 60 can isolate the direct signal transmission between the first node N11 and the first output sub-circuit 401, thereby isolating the influence of the fluctuation of the first clock signal CK1 on the first output sub-circuit 401, and maintaining stability.

[0098] The second isolation circuit 70 is connected to the first node N11 and the third output sub-circuit 501, and is connected to the first voltage line VGLL1. The second isolation circuit 70 can isolate the direct signal transmission between the first node N11 and the third output sub-circuit 501, thereby isolating the influence of the fluctuation of the first clock signal CK1 on the third output sub-circuit 501, and maintaining stability.

[0099] Further, in some embodiments of the present disclosure, the third output sub-circuit 501 may be connected to the first node N11 via the third node N13. The shift register may further include a third control circuit 80, which may be connected to the first node N11, the third node N13, and a fourth voltage line VGLL3 providing a fourth voltage VGL3, and the third control circuit 80 may control the voltage of the first node N11 in response to the voltage of the third node N13 and the fourth voltage VGL3.

[0100] The specific structure of the above-mentioned shift register is exemplarily described below:

[0101] As shown in FIG. 5, the input circuit 10 includes an input transistor T1, a gate of the input transistor T1 is connected to the first clock signal line CKL1, a first electrode is connected to the input terminal, and a second electrode is connected to the first node N11.

[0102] The first control circuit 20 includes a first control transistor T3 and a second control transistor T2, wherein the gate of the first control transistor T3 is connected to the first clock signal line CKL1, the first electrode is connected to the first voltage line VGLL1, and the second electrode is connected to the second node N12; the gate of the second control transistor T2 is connected to the first node N11, the first electrode is connected to the first clock signal line CKL1, and the second electrode is connected to the second node N12.

[0103] The second control circuit 30 includes a third control transistor T6 and a fourth control transistor T7, wherein the gate of the third control transistor T6 is connected to the second node N12, the first electrode is connected to the second voltage line VGHL, the second electrode is connected to the first electrode of the fourth control transistor T7, the second electrode of the fourth control transistor T7 is connected to the first node N11, and the gate of the fourth control transistor T7 is connected to the second clock signal line CBL1;

[0104] The first output sub-circuit 401 includes a first output transistor T9, and the first isolation circuit 60 includes a first isolation transistor T12; the gate of the first isolation transistor T12 is connected to the first voltage line VGLL1, the first electrode is connected to the first node N11, and the second electrode is connected to the gate of the first output transistor T9; the first electrode of the first output transistor T9 is connected to the third clock signal line CKL2, and the second electrode of the first output transistor T9 is connected to the first output terminal Gout1.

[0105] The second output sub-circuit 402 includes a second output transistor T10 and a first capacitor C1. The gate of the second output transistor T10 is connected to the second node N12, the first electrode is connected to the third voltage line VGLL2, and the second electrode is connected to the first output terminal Gout1. The first capacitor C1 is connected to the gate and the first electrode of the second output transistor T10.

[0106] The third output sub-circuit 501 includes a third output transistor T5 and a second capacitor C2, and the second isolation circuit 70 includes a second isolation transistor T8; the gate of the second isolation transistor T8 is connected to the first voltage line VGLL1, the first electrode is connected to the first node N11, and the second electrode is connected to the third node N13; the gate of the third output transistor T5 is connected to the third node N13, the first electrode is connected to the second clock signal line CBL1, and the second electrode is connected to the second output terminal Gout2; the second capacitor C2 is connected to the gate and the second electrode of the third output transistor T5.

[0107] The fourth output sub-circuit 502 includes a fourth output transistor T4, a gate of the fourth output transistor T4 is connected to the second node N12, a first electrode is connected to the second voltage line VGHL, and a second electrode is connected to the second output terminal Gout2.

[0108] The third control circuit 80 includes a fifth control transistor T11, a gate of the fifth control transistor T11 is connected to the third node N13, a first electrode of the fifth control transistor T11 is connected to the fourth voltage line VGLL3, and a second electrode of the fifth control transistor T11 is connected to the first node N11.

[0109] The driving method of the above shift register is described in detail below: As shown in FIGS. 6 and 7, in the first stage t11, the first clock signal CK1 is at a low level, the second clock signal CB1 is at a high level, the third clock signal CK2 is at a low level, and the input signal is at a high level; the first voltage VGL1, the third voltage VGL2 and the fourth voltage VGL3 can be the same low level, and of course, can also be different low levels.

[0110] The input transistor T1, the first control transistor T3 and the fourth control transistor T7 are turned on, and the first isolation transistor T12 and the second isolation transistor T8 are normal conducting; the input signal is transmitted to the first node N11 and the third node N13, so that the second control transistor T2, the fourth output transistor T4, the first output transistor T9 and the fifth control transistor T11 are turned off; the first voltage VGL1 is transmitted to the second node N12 and charges the first capacitor C1, so that the third control transistor T6, the second output transistor T10 and the fourth output transistor T4 are turned on; at this time, the voltage of the output signal of the first output terminal Gout1 is the first voltage VGL1; the voltage of the output signal of the second output terminal Gout2 is the second voltage VGH.

[0111] As shown in FIG. 6 and FIG. 8, in the second stage t12, the first clock signal CK1 is at a high level, the second clock signal CB1 is at a low level, the third clock signal CK2 is at a high level, and the input signal is at a high level; The input transistor T1 and the first control transistor T3 are turned off, and the fourth control transistor T7 is turned on; the first isolation transistor T12 and the second isolation transistor T8 are normal conducting; under the action of the second capacitor C2, the first node N11, the second node N12 and the third node N13 maintain the voltage of the first stage, so that the second control transistor T2, the fourth control transistor T7, the fifth control transistor T11 and the first output transistor T9 are turned off. At the same time, under the action of the first capacitor C1, the third control transistor T6, the third output transistor T5 and the second output transistor T1010 continue to be turned on, so that the voltage of the second voltage VGH can be written into the first node N11 and the third node N13, so that the second control transistor T2, the fourth control transistor T7, the fifth control transistor T11 and the first output transistor T9 are stabilized in the off state; at this time, the voltage of the output signal of the first output terminal Gout1 is the first voltage VGL1; the voltage of the output signal of the second output terminal Gout2 is the second voltage VGH.

[0112] As shown in FIG. 6 and FIG. 9, in the third stage t13, the first clock signal CK1 is at a low level, the second clock signal CB1 is at a high level, the third clock signal CK2 is at a low level, and the input signal is at a low level; The input transistor T1 and the first control transistor T3 are turned on, the fourth control transistor T7 is turned off, and the first isolation transistor T12 and the second isolation transistor T8 are normal conducting; the input signal is transmitted to the first node N11 and the third node N13, so that the second control transistor T2, the fourth output transistor T4, the first output transistor T9 and the fifth control transistor T11 are turned off; the first voltage VGL1 is transmitted to the second node N12 and charges the first capacitor C1, so that the third control transistor T6, the second output transistor T10 and the fourth output transistor T4 are turned on; at this time, the voltage of the output signal of the first output terminal Gout1 continues to be high under the action of the first voltage VGL1 and the high-level second clock signal CB1; the voltage of the output signal of the second output terminal Gout2 continues to be low under the action of the second voltage VGH and the low-level third clock signal CK2.

[0113] As shown in FIG. 6 and FIG. 10, in the fourth stage t14, the first clock signal CK1 is at a high level, the second clock signal CB1 is at a low level, the third clock signal CK2 is at a high level, and the input signal is at a high level; The input transistor T1 and the first control transistor T3 are turned off, and the fourth control transistor T7 is turned on; the first isolation transistor T12 and the second isolation transistor T8 are normal conducting; under the action of the second capacitor C2, the first node N11, the second node N12 and the third node N13 maintain the voltage of the third stage, so that the second control transistor T2, the fifth control transistor T11, the third output transistor T5 and the first output transistor T9 continue to be turned on. At the same time, the high-level first clock signal CK1 is written into the second node N12, so that the third control transistor T6, the third output transistor T5 and the second output transistor T1010 are turned off; at this time, the voltage of the output signal of the first output terminal Gout1 is the high level of the third clock signal CK2; the voltage of the output signal of the second output terminal Gout2 is the low level of the second clock signal CB1. In this process, the fifth control transistor T11 can write the fourth voltage VGL3 of the fourth voltage line VGL L3 into the first node N11 and the third node N13, play a role in voltage stabilization, and keep the first output transistor T9 and the fourth output transistor T4 stably turned on.

[0114] It should be noted that, although the steps of the driving method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0115] The following is an exemplary description of the film layer of the driving backplane BP: As shown in FIG. 2, the driving backplane BP may include a substrate SU and a light shielding layer BSM, a polysilicon semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, an oxide semiconductor layer IG, a third gate layer GA3, a first source-drain layer SD1, and a second source-drain layer SD2, which are sequentially distributed in a direction away from the substrate SU, wherein: The light shielding layer BSM is disposed on a side of the substrate SU and can be made of metal or other conductive and light shielding materials. The light shielding layer BSM can at least overlap with the driving transistor M5 to prevent the bottom signal and light from affecting the driving transistor M5.

[0116] The polysilicon semiconductor layer SE is disposed on a side of the light shielding layer BSM away from the substrate SU. The polysilicon semiconductor layer SE may be made of polysilicon and may be manufactured using a low-temperature polysilicon process. The polysilicon semiconductor layer SE may include active portions of respective transistors of the shift register GOA.

[0117] The first gate layer GA1 is disposed on a side of the polysilicon semiconductor layer SE away from the substrate SU. The first gate layer GA1 may include the gates of some transistors and the first electrode plates of the first capacitor C1 and the second capacitor C2 in the shift register GOA.

[0118] The second gate layer GA2 is disposed on a side of the first gate layer GA1 away from the substrate SU, and includes second electrode plates of the first capacitor C1 and the second capacitor C2 of the shift register GOA.

[0119] The oxide semiconductor layer IG may be disposed on a side of the second gate layer GA2 away from the substrate SU. The material thereof may be a metal oxide such as IGZO (indium gallium zinc oxide). The oxide semiconductor layer IG may include active portions of transistors of the pixel circuit PC.

[0120] The third gate layer GA3 may be disposed on a side of the oxide semiconductor layer IG away from the substrate SU and overlap the oxide semiconductor layer IG. The third gate layer GA3 may include gates of at least some transistors of the pixel circuit PC.

[0121] The first source-drain layer SD1 may be disposed on a side of the third gate layer GA3 away from the substrate SU, and may be connected to some transistors and capacitors.

[0122] The second source-drain layer SD2 is disposed on a side of the first source-drain layer SD1 away from the substrate SU.

[0123] The pattern of part of the above-mentioned the film layers in the display area AA is described below in conjunction with the pixel circuit PC:

[0124] As shown in FIGS. 11-14, the light shielding layer BSM may include a plurality of light shielding portions BS, and the light shielding portion BS may overlap with the channel portion of the driving transistor M5, thereby shielding the driving transistor M5 from light on the side close to the substrate SU, thereby improving the stability of the driving transistor M5. The first gate layer GA1 may include a first electrode plate Cst1 of the storage capacitor Cst.

[0125] As shown in FIGS. 11-13 and 16, the oxide semiconductor layer IG may include a first oxide semiconductor portion IG1 and a second oxide semiconductor portion IG2 that are spaced apart along the row direction X, and the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2 both extend along the column direction Y. The channel portions of the first reset transistor M2 and the writing transistor M1 are located in the first oxide semiconductor portion IG1 along the column direction Y; the channel portions of the light-emitting control transistor M4, the driving transistor M5 and the second reset transistor M3 are located in the second oxide semiconductor portion IG2 along the column direction Y, and the channel portion of the driving transistor M5 is located between the channel portions of the light-emitting control transistor M4 and the second reset transistor M3. The channel portion of the driving transistor M5 protrudes toward both sides of the second oxide semiconductor portion IG2 along the row direction X, so that the width-to-length ratio of the driving transistor M5 is increased, which is beneficial to increase the output current.

[0126] The respective transistors of the pixel circuit can adopt a top gate + bottom gate structure, and the bottom gate and the top gate are connected to achieve equipotential, which is beneficial to improve the stability of the transistor and obtain a good SS (subthreshold swing). The bottom gate of each transistor can be located in the second gate layer GA2, and the top gate of each transistor can be located in the third gate layer GA3. For example:

[0127] FIG. 11- FIG. 13 and FIG. 15, for the pixel circuit, in addition to the second electrode plate Cst2 of the storage capacitor Cst, the second gate layer GA2 also includes a first pixel gate portion G1, a second pixel gate portion G2, a third pixel gate portion G3 and a fourth pixel gate portion G4; the second gate layer GA2 may include a fifth pixel gate portion G5, a sixth pixel gate portion G6, a seventh pixel gate portion G7, an eighth pixel gate portion G8 and a ninth pixel gate portion G9; wherein:

[0128] On the basis that both the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2 extend along the column direction Y, the first pixel gate portion G1 to the ninth pixel gate portion G9 may extend along the row direction X, and the width in the column direction Y is smaller than the length in the row direction X.

[0129] The first pixel gate portion G1 and the fifth pixel gate portion G5 may overlap with the channel portion of the first reset transistor M2, and the first pixel gate portion G1 and the fifth pixel gate portion G5 are connected. The second pixel gate portion G2 and the sixth pixel gate portion G6 may overlap with the channel portion of the writing transistor M1, and the second pixel gate portion G2 and the sixth pixel gate portion G6 are connected. The third pixel gate portion G3 and the seventh pixel gate portion G7 may overlap with the channel portion of the light-emitting control transistor M4, and the third pixel gate portion G3 and the seventh pixel gate portion G7 are connected. The fourth pixel gate portion G4 and the eighth pixel gate portion G8 overlap with the channel portion of the second reset transistor M3, and the fourth pixel gate portion G4 and the eighth pixel gate portion G8 are connected. The ninth pixel gate portion G9 overlaps with the channel portion of the driving transistor M5, and the length of the ninth pixel gate portion G9 in the row direction X is greater than the width of the channel portion of the driving transistor M5 in the row direction X. The orthographic projection of the ninth pixel gate portion G9 on the substrate SU is located within the orthographic projections of the second electrode plate Cst2 and the light shielding portion BS on the substrate SU, and the ninth pixel gate portion G9 serves as the gate of the driving transistor M5.

[0130] The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting scan line EML, the first reset signal line VRL, the second reset signal line VIL, the first auxiliary first power line VDLs and the second auxiliary power line VSLs mentioned above are located in the first source-drain layer SD1. FIG. 1 schematically shows a scan line SL (connected to the first output terminal Gout1) for each shift register GOA, which can be any one of the first reset scan line GL2, the second reset scan line GL3, the write scan line GL1 and the light-emitting scan line EML. Of course, one shift register GOA can be connected to multiple scan lines SL.

[0131] As shown in FIG. 11 to FIG. 13 and FIG. 18, the first source-drain layer SD1 may further include a first connection portion S1, a second connection portion S2 and a third connection portion S3, wherein: The first connection portion S1 can be connected to the second electrode of the first reset transistor M2 and the gate of the driving transistor M5 through contact holes, respectively. For example, one end of the first connection portion S1 can be connected to the area between the channel portions of the first reset transistor M2 and the writing transistor M1 in the first oxide semiconductor portion IG1 through a contact hole, and the other end can be connected to the ninth pixel gate portion G9 through a contact hole.

[0132] Furthermore, the first connection portion S1 may extend along a straight line, a broken line or a curved trajectory, as long as it can play the aforementioned connection role; for example, the first connection portion S1 may include a first connection segment and a second connection segment, the first connection segment may extend along the row direction X, and be located between the first reset scan line GL2 and the ninth pixel gate portion G9, the second connection segment may extend along the column direction Y, and be located between the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2; one end of the first connection segment is connected to the first oxide semiconductor portion IG1 between the channel portions of the first reset transistor M2 and the writing transistor M1 through a contact hole, and the other end is connected to one end of the second connection segment, and the other end of the second connection segment is connected to the ninth pixel gate portion G9 through a contact hole.

[0133] The second connection portion S2 may be connected to the second electrode plate Cst2 and the first electrode of the driving transistor M5 through a contact hole. For example, the second connection portion S2 may extend along the row direction X and be located between the write scan line GL1 and the first connection portion S1, and the orthographic projection on the substrate SU is located between the ninth pixel gate portion G9 and the orthographic projection of the write scan line GL1 on the substrate SU. At the same time, the orthographic projection of the second connection portion S2 on the substrate SU may be located within the orthographic projection of the second electrode plate Cst2 on the substrate SU. The second connection portion S2 is connected to the second oxide semiconductor portion IG2 between the channel portions of the driving transistor M5 and the second reset transistor M3 through the contact hole, respectively.

[0134] The third connection portion S3 can be connected to the first electrode of the writing transistor M1 and the data line DAL through the contact hole, respectively, to realize the transmission of the data signal Data. For example, the third connection portion S3 is located between the second reset scan line GL3 and the second reset signal line VIL, and between the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2. The third connection portion S3 is connected to one end of the first oxide semiconductor portion IG1 through the contact hole, and the end is located on the side of the channel portion of the writing transistor M1 away from the channel portion of the first reset transistor M2. The third connection portion S3 is also connected to the data line DAL through a contact hole.

[0135] The first power line VDL, the second power line, the data line DAL, the first auxiliary reset line and the second auxiliary reset line VILs are located in the second source-drain layer SD2.

[0136] As shown in FIG. 11 to FIG. 13 and FIG. 19, the second source-drain layer SD2 may further include a transfer portion S4, which may be connected to the first electrode of the driving transistor M5 and the second electrode of the second reset transistor M3. For example, the transfer portion S4 may be connected to the second connection portion S2 through a contact hole. At the same time, the transfer portion S4 may also be connected to the first electrode ANO of the light-emitting device LD through a contact hole.

[0137] The pattern of part of the above-mentioned the film layers in the display area is described below in conjunction with the shift register GOA: As shown in FIGS. 20, 21, 27 and 28, in some embodiments of the present disclosure, the orthographic projections of the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 on the substrate SU all extend along the column direction Y and are distributed at intervals along the row direction X, and the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 are arranged in sequence along the direction toward the display area.

[0138] As shown in FIGS. 20-23, 27 and 28, in a shift register GOA, the first output transistor T9 and the second output transistor T10 are located between the orthographic projections of the third voltage line VGLL2 and the pixel circuit PC on the substrate SU, and the orthographic projections of other transistors and the first capacitor C1 on the substrate SU are located between the orthographic projections of the second voltage line VGHL and the third clock signal line CKL2 on the substrate SU.

[0139] The orthographic projections of the channel portions of the input transistor T1, the first control transistor T3, the second control transistor T2, the third control transistor T6 and the fourth control transistor T7 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the second voltage line VGHL on the substrate SU; The orthographic projections of the third output transistor T5, the fourth output transistor T4, the fifth control transistor T11, the first isolation transistor T12, the second isolation transistor T8 and the first capacitor C1 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the fourth voltage line VGLL3 on the substrate SU.

[0140] The first clock signal line CKL1, the second clock signal line CBL1, the third clock signal line CKL2, the first voltage line VGLL1, the second voltage line VGHL, the third voltage line VGLL2 and the fourth voltage line VGLL3 all extend along the column direction Y, and are distributed in the first source-drain layer SD1 and the second source-drain layer SD2 at intervals along the row direction X. For example, the first clock signal line CKL1, the second clock signal line CBL1, the third clock signal line CKL2, the first voltage line VGLL1, the second voltage line VGHL and the third voltage line VGLL2 in the above text are located in the first source-drain layer SD1; the fourth voltage line VGLL3 is located in the second source-drain layer SD2.

[0141] As shown in FIGS. 20-23 and 24, in some embodiments of the present disclosure, the polycrystalline silicon semiconductor layer SE may include a first semiconductor portion SE1, a second semiconductor portion SE2, a third semiconductor portion SE3, a fourth semiconductor portion SE4, a fifth semiconductor portion SE5, a sixth semiconductor portion SE6, a seventh semiconductor portion SE7, an eighth semiconductor portion SE8 and a ninth semiconductor portion SE9, wherein:

[0142] The orthographic projections of the first semiconductor portion SE1, the second semiconductor portion SE2, the third semiconductor portion SE3 and the fourth semiconductor portion SE4 on the substrate SU are located between the orthographic projections of the second voltage line VGHL and the first voltage line VGLL1 on the substrate SU. The first semiconductor portion SE1, the second semiconductor portion SE2 and the third semiconductor portion SE3 are distributed along the row direction X; the first semiconductor portion SE1 and the fourth semiconductor portion SE4 are distributed along the column direction Y.

[0143] The orthographic projections of the fifth semiconductor portion SE5, the sixth semiconductor portion SE6, the seventh semiconductor portion SE7 and the eighth semiconductor portion SE8 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the third clock signal line CKL2 on the substrate SU; the fifth semiconductor portion SE5 to the eighth semiconductor portion SE8 are distributed along the column direction Y.

[0144] The orthographic projection of the ninth semiconductor portion SE9 on the substrate SU is located between the third voltage line VGLL2 and the pixel circuit.

[0145] The channel portion of the input transistor is located in the first semiconductor portion SE1; the channel portion of the second control transistor T2 is located in the second semiconductor portion SE2; the channel portion of the first control transistor T3 is located in the second semiconductor portion SE2; the channel portion of the third control transistor T6 and the fourth control transistor T7 are located in the fourth semiconductor portion SE4; the channel portion of the first isolation transistor T12 is located in the fifth semiconductor portion SE5; the channel portion of the second isolation transistor T8 is located in the sixth semiconductor portion SE6; the channel portion of the fifth control transistor T11 is located in the seventh semiconductor portion SE7; the channel portions of the three output transistors and the fourth output transistor T4 are located in the eighth semiconductor portion SE8; the channel portions of the first output transistor T9 and the second output transistor T10 are located in the ninth semiconductor portion SE9.

[0146] As shown in FIGS. 20-23 and 25, based on the pattern of the polysilicon semiconductor layer SE, for example, the first gate layer GA1 may include a first gate portion G11, a second gate portion G12, a third gate portion G13, a fourth gate portion G14, a fifth gate portion G15, a sixth gate portion G16 and a seventh gate portion G17, wherein: The first gate portion G11 may extend along the row direction X and overlap with the first semiconductor portion SE1 and the third semiconductor portion SE3 to form the input transistor T1 and the first control transistor T3, and the first gate portion G11 is connected to the first clock signal line CKL1 through a contact hole. The region where the first gate portion G11 overlaps with the first semiconductor portion SE1 is the gate of the input transistor, and the region where the first gate portion G11 overlaps with the third semiconductor portion SE3 is the gate of the first control transistor T3.

[0147] The second gate portion G12 may extend along the row direction X and overlap with the second semiconductor portion SE2 to form the second control transistor T2. The region where the second gate portion G12 overlaps with the second semiconductor portion SE2 is the gate of the second control transistor T2.

[0148] The third gate portion G13 may extend along the row direction X and overlap with the fourth semiconductor portion SE4 to form the fourth control transistor T7, and the third gate portion G13 is connected to the second clock signal line CBL1 through a contact hole. The region where the third gate portion G13 overlaps with the fourth semiconductor portion SE4 is the gate of the fourth control transistor T7.

[0149] The fourth gate portion G14 may extend along the row direction X, and overlap with the fourth semiconductor portion SE4, the eighth semiconductor portion SE8, and the ninth semiconductor portion SE9 to form the third control transistor T6, the fourth output transistor T4, and the second output transistor T10; the third gate portion G13 includes a first electrode plate of the second capacitor C2. The region where the fourth gate portion G14 overlaps with the fourth semiconductor portion SE4 is the gate of the third control transistor T6, the region where the fourth gate portion G14 overlaps with the eighth semiconductor portion SE8 is the gate of the fourth output transistor T4, and the region where the fourth gate portion G14 overlaps with the ninth semiconductor portion SE9 is the gate of the second output transistor T10; the third control transistor T6, the fourth output transistor T4, the first electrode plate of the second capacitor C2, and the second output transistor T10 are sequentially distributed in the direction toward the pixel circuit.

[0150] The fifth gate portion G15 at least partially extends along the column direction Y, and overlaps with the fifth semiconductor portion SE5 and the sixth semiconductor portion SE6 to form the first isolation transistor T12 and the second isolation transistor T8; and the fifth gate portion G15 is connected to the first voltage line VGLL1 through a contact hole. The area where the fifth gate portion G15 overlaps with the fifth semiconductor portion SE5 is the gate of the first isolation transistor T12, and the area where the fifth gate portion G15 overlaps with the sixth semiconductor portion SE6 is the gate of the second isolation transistor T8. Further, in order to facilitate connection with the first voltage line VGLL1, the fifth gate portion G15 at least partially extends along the row direction X, and the portion extending along the row direction X is connected to the portion extending along the column direction Y, and the portion extending along the row direction X is connected to the first voltage line VGLL1 through a contact hole.

[0151] The sixth gate portion G16 overlaps with the seventh semiconductor portion SE7 and the eighth semiconductor portion SE8 to form the fifth control transistor T11 and the third output transistor T5; the sixth gate portion G16 includes a first electrode plate of the first capacitor C1. The region where the sixth gate portion G16 overlaps with the seventh semiconductor portion SE7 is the gate of the fifth control transistor T11, and the region where the sixth gate portion G16 overlaps with the eighth semiconductor portion SE8 is the gate of the third output transistor T5. The orthographic projection of the first electrode plate of the first capacitor C1 on the substrate SU may be located between the orthographic projections of the seventh semiconductor portion SE7 and the eighth semiconductor portion SE8 on the substrate SU and the orthographic projection of the third clock signal line CKL2 on the substrate SU, and extends along the column direction Y.

[0152] The sixth gate portion G16 has a first segment and a second segment extending outward from the edge of the first electrode plate of the first capacitor C1 and distributed along the column direction Y. The first segment includes a first sub-segment extending along the row direction X and a second sub-segment extending along the column direction Y. One end of the first sub-segment is connected to the above-mentioned first electrode plate, and the other end is connected to one end of the second sub-segment. The second sub-segment overlaps with the seventh semiconductor portion SE7 to form the fifth control transistor T11. The second segment of the sixth gate portion G16 overlaps with the eighth semiconductor portion SE8 to form the third output transistor T5.

[0153] The seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 to form the first output transistor T9; the region where the seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 is the gate of the first output transistor T9.

[0154] Furthermore, in some embodiments of the present disclosure, in order to improve the width-to-length ratio of the first output transistor T9, the second output transistor T10, the third output transistor T5 and the fourth output transistor T4 and increase the current, the width of the eighth semiconductor portion SE8 and the ninth semiconductor portion SE9 in the row direction X can be greater than the width of the first capacitor C1 and the second capacitor C2 in the row direction X, and greater than the width of any one of the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 in the row direction X, and greater than the width of the channel portion of other transistors in the row direction X.

[0155] Further, as shown in FIG. 20- FIG. 23, in some embodiments of the present disclosure, the channel portion of at least one of the input transistor T1, the first output transistor T9, and the second output transistor T10 may include at least two channels connected in series to prevent leakage; for example: The first gate portion G11 may include two sub-gate portions extending along the row direction X, and the two sub-gate portions are distributed and connected along the column direction Y. The two sub-gate portions overlap with the first semiconductor portion SE1 to form two channels of the input transistor. Of course, more sub-gate portions may also be provided.

[0156] The part where the fourth gate portion G14 overlaps with the ninth semiconductor portion SE9 may include two sub-gate portions extending along the row direction X, and the two sub-gate portions are distributed and connected along the column direction Y, and the two sub-gate portions overlap with the ninth semiconductor portion at the same time, forming two channels of the second output transistor T10. Of course, more sub-gate portions may also be provided.

[0157] The part where the seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 may include four sub-gate portions extending along the row direction X, and the four sub-gate portions are distributed and connected along the column direction Y, and the four sub-gate portions overlap with the ninth semiconductor portion SE9 at the same time, forming two channels of the first output transistor T9. Of course, fewer or more sub-gate portions may also be provided.

[0158] As shown in FIG. 20- FIG. 26, in some embodiments of the present disclosure, the second output terminal Gout2 of the previous-stage shift register in two adjacent stages of shift registers is connected to the input terminal IN of the next-stage shift register, and the wiring connecting the second output terminal Gout2 and the input terminal IN can be distributed in the first source-drain layer SD1 and the first gate layer GA1. For example, the first gate layer GA1 further includes a cascade jumper portion G18, and the first gate layer GA1 can also include a cascade output portion S14 and a cascade line S15, wherein: The cascade output portion S14 overlaps with the eighth semiconductor portion SE8 and is connected through a contact hole, thereby connecting to the second electrodes of the third output transistor T5 and the fourth output transistor T4. The cascade line S15 extends along the column direction Y, and is located between the second voltage line VGHL and the first voltage line VGLL1, and is connected to the input terminal IN of the next stage shift register; the cascade jumper portion G18 can extend along the row direction X, and overlap with the first voltage line VGLL1 but be insulated from each other, and the cascade jumper portion G18 can connect the cascade output portion S14 and the cascade line S15 through a contact hole; thus, the cascade output portion S14, the cascade jumper portion G18 and the cascade line S15 can form a path connecting the two stages of the shift register. In the embodiment, the cascade jumper portion G18 and the first voltage line VGLL1 are located in different layers to prevent short circuits.

[0159] As shown in FIG. 20- FIG. 23, FIG. 26 and FIG. 27, the second gate layer GA2 may include a first transfer portion G21 and a second transfer portion G22; the first source drain layer SD1 includes a scan output portion S16, a first connection portion S11, a second connection portion S12 and a third connection portion S13; wherein: The scan output portion S16 may overlap with the ninth semiconductor portion SE9 and be connected through a contact hole to connect the second electrodes of the first output transistor T9 and the second output transistor T10. Further, the scan output portion S16 may include a plurality of sub-scan output portions extending along the row direction X and distributed along the column direction Y, each of the sub-scan output portions overlaps with the ninth semiconductor portion SE9, and is alternately distributed with each channel portion of the first output transistor T9 and the second output transistor T10 having a plurality of channel portions along the column direction Y, and each of the sub-scan output portions is connected to the ninth semiconductor portion SE9 through a contact hole.

[0160] Further, as shown in FIGS. 20-23, FIG. 26 and FIG. 27, the second gate layer GA2 may also include a scan switching portion G23, which may be connected to the scan output portion S16 through a contact hole, and may be connected to the scan line SL of the scan pixel circuit PC, and the scan line SL may be one or more of the first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, and the light-emitting scan line EML.

[0161] The first connection portion S11 may overlap with the ninth semiconductor portion SE9, and be connected through a contact hole, and connect the first electrode of the first output transistor T9. The first transfer portion G21 may extend along the row direction X, and overlap with the first connection portion S11 and the third voltage line VGLL2, and connect the third clock signal line CKL2 and the first connection portion S11 through a contact hole, thereby connecting the third clock signal line CKL2 to the first electrode of the first output transistor T9. The first transfer portion G21 is located in a different layer from the first connection portion S11 and the third voltage line VGLL2 to avoid short circuits.

[0162] The second connection portion S12 overlaps with the eighth semiconductor portion SE8 and is connected through a contact hole, and is connected to the first electrode of the fourth output transistor T4. The third connection portion S13 is connected to the second voltage line VGHL; the second transfer portion G22 extends along the row direction X and overlaps with the first voltage line VGLL1, and the second transfer portion G22 is connected to the second connection portion S12 and the third connection portion S13 through a contact hole. Thus, the second voltage line VGHL and the first electrode of the fourth output transistor T4 are connected through the second connection portion S12, the second transfer portion G22 and the third connection portion S13. The second transfer portion G22 and the first voltage line VGLL1 are located in different layers to avoid short circuit between the two.

[0163] The first source-drain layer SD1 may further include a trigger signal line STVL, which may be connected to the input terminal IN of the first stage of shift register in the cascaded shift register for transmitting a trigger signal. The trigger signal line STVL may extend along the column direction Y and be located on a side of the second clock signal line CBL1 away from the pixel circuit. In addition, the first source-drain layer SD1 may further include a fourth clock signal line CBL2, which may be provided between the third clock signal line CKL2 and the third voltage line VGLL2.

[0164] In addition, as shown in FIGS. 20-23 and 27, the first source-drain layer SD1 may also include a signal transfer portion S17, which may be connected to the gate of the fifth control transistor T11 and may be connected to the fourth voltage line VGLL3 through a contact hole so as to control the fifth control transistor T11 through the fourth voltage VGL3.

[0165] As shown in FIGS. 20-23 and 28, the second source-drain layer SD2 also includes a first auxiliary clock signal line CKL1s, a second auxiliary clock signal line CBL1s, a third auxiliary clock signal line CKL2s and a fourth auxiliary clock signal line CBL2s extending along the column direction Y, and the first auxiliary clock signal line CKL1s, the second auxiliary clock signal line CBL1s, the third auxiliary clock signal line CKL2s and the fourth auxiliary clock signal line CBL2s are sequentially spaced along the row direction X toward the pixel circuit.

[0166] The first auxiliary clock signal line CKL1s overlaps and connects with the first clock signal line CKL1, which is conducive to reducing resistance and improving the stability of the first clock signal CK1. The second auxiliary clock signal line CBL1s overlaps and connects with the second clock signal line CBL1, which is conducive to reducing resistance and improving the stability of the second clock signal CB1. The third auxiliary clock signal line CKL2s overlaps and connects with the third clock signal line CKL2, which is conducive to reducing resistance and improving the stability of the third clock signal CK2. The fourth auxiliary clock signal line CBL2s overlaps and connects with the fourth clock signal line CBL2, which is conducive to reducing resistance and improving the stability of the fourth clock signal CB2.

[0167] The present disclosure also provides a display device, which may include a display panel of any of the above embodiments. The display panel is a display panel of any of the above embodiments, and its specific structure and beneficial effects can be referred to the embodiments of the display panel above, which will not be repeated here. The display device of the present disclosure can be an electronic device such as a mobile phone, a tablet computer, a television, or a wearable device with an image display function such as a smart watch, a virtual reality device, an augmented reality device, or other electronic devices with a display function such as a vehicle-mounted display device, which will not be listed one by one here.

[0168] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a display area and a peripheral area outside the display area, and comprising: a driving backplane, comprising a pixel circuit located in the display area and a peripheral circuit located in the peripheral area, wherein the peripheral circuit comprises a plurality of cascaded shift registers; one shift register is configured to scan at least one row of the pixel circuit; the pixel circuit and the shift register both comprise a plurality of transistors; the transistors of the pixel circuit comprise a driving transistor, and the driving transistor and at least part of other transistors in the pixel circuit are metal oxide transistors; and the transistors in the shift register are polysilicon transistors; and a plurality of light-emitting devices, disposed on a side of the driving backplane; one light-emitting device comprises a first electrode, a light-emitting layer, and a second electrode stacked in sequence in a direction away from the driving backplane; a first electrode of the driving transistor is connected to a first electrode of the light-emitting device, a second electrode of the driving transistor is connected to a first power line transmitting a first power signal; and a second electrode of the light-emitting device is configured to receive a second power signal.

2. The display panel according to claim 1, wherein the pixel circuit further comprises a first reset circuit, a second reset circuit and a writing circuit; the first reset circuit is connected to a gate electrode of the driving transistor, and is configured to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor, and is configured to transmit a second reset signal in response to a second reset scan signal; and the writing circuit is connected to the gate electrode of the driving transistor, and is configured to transmit a data signal in response to a write scan signal.

3. The display panel according to claim 2, wherein the pixel circuit further comprises a light-emitting control circuit and a storage capacitor; the first power line is connected to the second electrode of the driving transistor through the light-emitting control circuit, and the light-emitting control circuit is configured to be turned on in response to a light-emitting scan signal; and the storage capacitor is connected to the gate and the first electrode of the driving transistor.

4. The display panel according to claim 3, wherein the first reset circuit comprises a first reset transistor, the second reset circuit comprises a second reset transistor, the writing circuit comprises a writing transistor, and the light-emitting control circuit comprises a light-emitting control transistor; a gate of the first reset transistor is configured to receive the first reset scan signal, a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; a gate of the second reset transistor is configured to receive the second reset scan signal, a first electrode of the second reset transistor is configured to receive the second reset signal, and a second electrode of the second reset transistor is connected to the first electrode of the driving transistor; a gate of the writing transistor is configured to receive the write scan signal, a first electrode of the writing transistor is configured to receive the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor; a gate of the light-emitting control transistor is configured to receive the light-emitting scan signal, a first electrode of the light-emitting control transistor is connected to the first power line, and a second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor.

5. The display panel according to claim 3, wherein the shift register comprises an input circuit, a first control circuit, a second control circuit and a first output circuit; the input circuit is connected to an input terminal, a first node and a first clock signal line providing a first clock signal, and is configured to transmit an input signal of the input terminal to the first node in response to the first clock signal; the first control circuit is connected to the first node, a second node, the first clock signal line and a first voltage line providing a first voltage, and is configured to control a voltage of the second node in response to the first clock signal, the first voltage and a voltage of the first node; the second control circuit is connected to the first node, the second node, a second voltage line providing a second voltage, and a second clock signal line providing a second clock signal, and is configured to control a voltage of the first node in response to the second clock signal, the second voltage, and the voltage of the second node; and the first output circuit is connected to the first node, the second node, a third voltage line providing a third voltage, a third clock signal line providing a third clock signal, and a first output terminal, and is configured to output the third voltage or the third clock signal through the first output terminal under control of the voltages of the first node and the second node.

6. The display panel according to claim 5, wherein the first output circuit comprises a first output sub-circuit and a second output sub-circuit; the first output sub-circuit is connected to the first node, the first output terminal and the third clock signal line, and is configured to control the first output terminal and the third clock signal line to be connected or disconnected under the control of the voltage of the first node; and the second output sub-circuit is connected to the second node, the third voltage line and the first output terminal, and is configured to control the first output terminal and the third voltage line to be connected or disconnected in response to the voltage of the second node.

7. The display panel according to claim 6, wherein the shift register further comprises a second output circuit, the second output circuit being connected to the first node, the second node, the second voltage line, the second clock signal line and a second output terminal, and being configured to output the second voltage or the second clock signal through the second output terminal under control of the voltages of the first node and the second node.

8. The display panel according to claim 7, wherein the second output circuit comprises a third output sub-circuit and a fourth output sub-circuit; the third output sub-circuit is connected to the first node, the second voltage line and the second output terminal, and is configured to control the second output terminal and the second clock signal line to be connected or disconnected in response to the voltage of the first node; and the fourth output sub-circuit is connected to the second node and the second output terminal, and is configured to control the second output terminal and the second voltage line to be connected or disconnected in response to the voltage of the second node.

9. The display panel according to claim 8, wherein the shift register further comprises a first isolation circuit and a second isolation circuit; first isolation circuit is connected to the first node and the first output sub-circuit, and is connected to the first voltage line; and the second isolation circuit is connected to the first node and the third output sub-circuit, and is connected to the first voltage line.

10. The display panel according to claim 9, wherein the third output sub-circuit is connected to the first node via a third node; and the shift register further comprises a third control circuit connected to the first node, the third node and a fourth voltage line providing a fourth voltage, and configured to control the voltage of the first node in response to voltages of the third node and the fourth voltage.

11. The display panel according to claim 10, wherein the input circuit comprises an input transistor, a gate of the input transistor is connected to the first clock signal line, a first electrode of the input transistor is connected to the input terminal, and a second electrode of the input transistor is connected to the first node; the first control circuit comprises a first control transistor and a second control transistor, wherein a gate of the first control transistor is connected to the first clock signal line, a first electrode of the first control transistor is connected to the first voltage line, and a second electrode of the first control transistor is connected to the second node; a gate of the second control transistor is connected to the first node, a first electrode of the second control transistor is connected to the first clock signal line, and a second electrode of the second control transistor is connected to the second node; the second control circuit comprises a third control transistor and a fourth control transistor, wherein a gate of the third control transistor is connected to the second node, a first electrode of the third control transistor is connected to the second voltage line, a second electrode of the third control transistor is connected to a first electrode of the fourth control transistor, the second electrode of the fourth control transistor is connected to the first node, and a gate of the fourth control transistor is connected to the second clock signal line; the first output sub-circuit comprises a first output transistor, and the first isolation circuit comprises a first isolation transistor; a gate of the first isolation transistor is connected to the first voltage line, a first electrode of the first isolation transistor is connected to the first node, and a second electrode of the first isolation transistor is connected to a gate of the first output transistor; a first electrode of the first output transistor is connected to the third clock signal line, and a second electrode of the first output transistor is connected to the first output terminal; and the second output sub-circuit comprises a second output transistor and a first capacitor, a gate of the second output transistor is connected to the second node, a first electrode of the second output transistor is connected to the third voltage line, and a second electrode of the second output transistor is connected to the first output terminal; the first capacitor is connected to the gate and the first electrode of the second output transistor.

12. The display panel according to claim 11, wherein the third output sub-circuit comprises a third output transistor and a second capacitor, and the second isolation circuit comprises a second isolation transistor; a gate of the second isolation transistor is connected to the first voltage line, a first electrode of the second isolation transistor is connected to the first node, and a second electrode of the second isolation transistor is connected to the third node; a gate of the third output transistor is connected to the third node, a first electrode of the third output transistor is connected to the second clock signal line, and a second electrode of the third output transistor is connected to the second output terminal; and the second capacitor is connected to the gate and the second electrode of the third output transistor; and the fourth output sub-circuit comprises a fourth output transistor, a gate of the fourth output transistor is connected to the second node, a first electrode of the fourth output transistor is connected to the second voltage line, and a second electrode of the fourth output transistor is connected to the second output terminal.

13. The display panel according to claim 12, wherein the third control circuit comprises a fifth control transistor, a gate of the fifth control transistor is connected to the third node, a first electrode of the fifth control transistor is connected to the fourth voltage line, and a second electrode of the fifth control transistor is connected to the first node.

14. The display panel according to claim 13, wherein each transistor of the pixel circuit is a metal oxide transistor; and each transistor of the shift register is a polysilicon transistor.

15. The display panel according to claim 14, wherein the driving backplane comprises a substrate and a light shielding layer, a polysilicon semiconductor layer, a first gate layer, a second gate layer, an oxide semiconductor layer, a third gate layer, a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate; the first electrode is disposed on a side of the second source-drain layer away from the substrate; a channel portion of the transistor of the shift register is located in the polysilicon semiconductor layer; and a channel portion of each transistor of the pixel circuit is located in the oxide semiconductor layer; a first electrode plate of the first capacitor and a first electrode plate of the second capacitor are located in the first gate layer, and a second electrode plate of the first capacitor and a second electrode plate of the second capacitor are located in the second gate layer; a first electrode plate of the storage capacitor is located in the light shielding layer, and a second electrode plate of the storage capacitor is located in the second gate layer; and the first clock signal line, the second clock signal line, the third clock signal line, the first voltage line, the second voltage line and the third voltage line are located in the first source-drain layer; and the fourth voltage line is located in the second source-drain layer.

16. The display panel according to claim 15, wherein orthographic projections of the first clock signal line, the second clock signal line, the second voltage line, the first voltage line, the fourth voltage line, the third clock signal line and the third voltage line on the substrate are all extended along a column direction and are sequentially arranged along a row direction toward the display area; and in one shift register, the first output transistor and the second output transistor are located between orthographic projections of the third voltage line and the pixel circuit on the substrate, and orthographic projections of other transistors and the first capacitor on the substrate are located between orthographic projections of the second voltage line and the third clock signal line on the substrate.

17. The display panel according to claim 16, wherein orthographic projections of channel portions of the input transistor, the first control transistor, the second control transistor, the third control transistor and the fourth control transistor are located between orthographic projections of the first voltage line and the second voltage line on the substrate; and orthographic projections of the third output transistor, the fourth output transistor, the fifth control transistor, the first isolation transistor, the second isolation transistor and the first capacitor on the substrate are located between orthographic projections of the first voltage line and the third clock signal line on the substrate.

18. The display panel according to claim 15, wherein a channel portion of at least one of the input transistor, the first output transistor, and the second output transistor comprises at least two channels connected in series.

19. The display panel according to claim 16, wherein the polysilicon semiconductor layer comprises a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, a fourth semiconductor portion, a fifth semiconductor portion, a sixth semiconductor portion, a seventh semiconductor portion, an eighth semiconductor portion, and a ninth semiconductor portion; orthographic projections of the first semiconductor portion to the fourth semiconductor portion on the substrate are located between the orthographic projections of the second voltage line and the first voltage line on the substrate; the first semiconductor portion, the second semiconductor portion and the third semiconductor portion are distributed along the row direction; and the first semiconductor portion and the fourth semiconductor portion are distributed along the column direction; orthographic projections of the fifth semiconductor portion to the eighth semiconductor portion on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate; and the fifth semiconductor portion to the eighth semiconductor portion are distributed along the column direction; an orthographic projection of the ninth semiconductor portion on the substrate is located between the third voltage line and the pixel circuit; the channel portion of the input transistor is located in the first semiconductor portion; the channel portion of the second control transistor is located in the second semiconductor portion; the channel portion of the first control transistor is located in the second semiconductor portion; the channel portion of the third control transistor and the fourth control transistor are located in the fourth semiconductor portion; the channel portion of the first isolation transistor is located in the fifth semiconductor portion; the channel portion of the second isolation transistor is located in the sixth semiconductor portion; the channel portion of the fifth control transistor is located in the seventh semiconductor portion; the channel portions of the three output transistors and the fourth output transistor are located in the eighth semiconductor portion; the channel portions of the first output transistor and the second output transistor are located in the ninth semiconductor portion.

20. The display panel according to claim 19, wherein the first gate layer comprises a first gate portion, a second gate portion, a third gate portion, a fourth gate portion, a fifth gate portion, a sixth gate portion and a seventh gate portion; the first gate portion is overlapped with the first semiconductor portion and the third semiconductor portion to form the input transistor and the first control transistor, and the first gate portion is connected to the first clock signal line through a contact hole; the second gate portion is overlapped with the second semiconductor portion to form the second control transistor; the third gate portion is overlapped with the fourth semiconductor portion to form the fourth control transistor, and the third gate portion is connected to the second clock signal line through a contact hole; the fourth gate portion is overlapped with the fourth semiconductor portion, the eighth semiconductor portion and the ninth semiconductor portion to form the third control transistor, the fourth output transistor and the second output transistor; and the third gate portion comprises a first electrode plate of the second capacitor; the fifth gate portion is overlapped with the fifth semiconductor portion and the sixth semiconductor portion to form the first isolation transistor and the second isolation transistor; and the fifth gate portion is connected to the first voltage line through a contact hole; the sixth gate portion is overlapped with the seventh semiconductor portion and the eighth semiconductor portion to form the fifth control transistor and the third output transistor; and the sixth gate portion comprises a first electrode plate of the first capacitor; and the seventh gate portion is overlapped the ninth semiconductor portion to form the first output transistor.

21. The display panel according to claim 20, wherein in the shift register, widths of the channel portions of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor in the row direction are greater than widths of the channel portions of other transistors in the row direction.

22. The display panel according to claim 20, wherein the first gate layer further comprises a cascade jumper portion; the second gate layer comprises a first transfer portion and a second transfer portion; the first source-drain layer comprises a scan output portion, a cascade output portion, a cascade line, a first connection portion, a second connection portion and a third connection portion; the scan output portion is overlapped with the ninth semiconductor portion and is connected through a contact hole to connect the second electrode of the first output transistor and the second electrode of the second output transistor; cascade output portion is overlapped with the eighth semiconductor portion and is connected through a contact hole to connect the second electrode of the third output transistor and the second electrode of the fourth output transistor; the cascade line extends along the column direction and is located between the second voltage line and the first voltage line; the cascade jumper portion is extended along the row direction and is overlapped with the first voltage line, and the cascade output portion and the cascade line are connected through a contact hole; the first connecting portion is overlapped with the ninth semiconductor portion and is connected through a contact hole to connect the first electrode of the first output transistor; the first switching portion is extended along the row direction and is overlapped with the first connecting portion and the third voltage line, and is connected to the third clock signal line and the first connecting portion through a contact hole; and the second connection portion is overlapped with the eighth semiconductor portion and is connected through a contact hole to connect to the first electrode of the fourth output transistor; the third connection portion is connected to the second voltage line; the second transfer portion is extended along the row direction and is overlapped with the first voltage line, and the second transfer portion is connected to the second connection portion and the third connection portion through a contact hole.

23. A display device comprising the display panel according to any one of claims 1 to 22.

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