Method and system for calculating forward error correction with a reduced number of gates in fec encoders

Abstract

The present invention relates to a method for improving forward error correction in serial coding during data transmission in a vehicle and, compared to the prior art, it offers, among other things, the advantage that the physical behaviour on a transmission channel can always be deterministically controlled despite a reduction in resource requirements. The proposed method reduces the number of gates in the forward error correction encoders by using the preliminary calculation of the forward error correction on individual subwords to minimise the exponential growth in the number of gates required compared to the prior art. Thus, according to the proposed method, bit errors are minimal and a transmission error can be corrected efficiently, i.e. with minimal technical effort. Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly includes a form of nesting that allows so-called burst errors to be corrected particularly advantageously. This implicit nesting makes it possible to eliminate the need for the conventional buffer memories required by explicit nesting. In addition, the invention ensures that user data, together with corrective metadata, can be encoded in a manner that is advantageous for transmission. According to the invention, it can be ensured that not only the user data is line-coded or channel-coded, but also the correction data. The present invention also relates to a similarly designed system arrangement for carrying out the method, and to a computer program product comprising control commands which execute the method.

Description

[0001] Method and system arrangement for calculating a forward error correction with reduced gate number in FEC encoders

[0002] The present invention is directed to a method for improving forward error correction in serial coding during data transmission in a vehicle. Compared to the prior art, it provides the advantage, among other things, that, despite a reduction in resource requirements, the physical behavior on a transmission channel can always be deterministically controlled. The proposed method reduces the number of gates in forward error correction coders by minimizing the exponential growth in the number of required gates compared to the prior art by calculating the forward error correction on individual subwords. According to the proposed method, bit errors are minimal, and a transmission error can be corrected efficiently, i.e., with minimal technical effort.Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly incorporates interleaving designed to allow so-called burst errors to be corrected particularly advantageously. This implicit interleaving eliminates the need for the conventional buffer memory required for explicit interleaving. Furthermore, the invention ensures that user data, including corrective metadata, can be advantageously coded for transmission. The invention ensures that not only the user data is line-coded or line-coded, but also the correction data. The present invention is likewise directed to an analog system arrangement for carrying out the method, and to a computer program product with control commands that execute the method.

[0003] Different versions of the Ethernet protocol are known from the state of the art. Ethernet uses a variety of techniques to detect and correct errors during data transmission. The error correction mechanisms are part of the Ethernet protocol and ensure that the received data is correct and complete. Cyclic Redundancy Check (CRC) is one of the most important error detection techniques in Ethernet. With CRC, a checksum is calculated over the sent data and appended to the packet. At the receiver, the checksum is recalculated and compared with the received checksum. If the checksums do not match, an error is detected and the packet is discarded. Also known from the state of the art is what is known as forward error correction. Forward Error Correction (FEC) is a method of error correction in which additional redundancy information is added to the data.This redundancy allows the receiver to detect and correct errors without having to resend the packet. FEC is often used in high-speed Ethernet connections such as 10 Gigabit Ethernet (10GbE) to ensure data integrity.

[0004] Link-level error correction is also known from the state of the art. At the physical layer, Ethernet can also perform error correction. Techniques such as signal amplification, noise suppression, and error correction codes are used to improve the stability of data transmission. These error correction mechanisms are implemented in the Ethernet transceivers, which perform the conversion between digital data and physical signals.

[0005] Error correction mechanisms play a crucial role in ensuring reliable data transmission in networks. They help detect, isolate, and correct transmission errors to ensure data integrity is maintained. Especially in mission-critical environments where large amounts of data are transmitted, error correction mechanisms are essential to maintaining connection quality.

[0006] The DisplayPort standard is also well-known. DisplayPort uses various error detection and correction methods to ensure that the transmitted data is reproduced accurately and without loss. These mechanisms are part of the DisplayPort protocol and contribute to the stability and quality of data transmission. Forward Error Correction (FEC) is an important error correction method in DisplayPort. It inserts additional redundancy information into the transmitted data. This redundancy allows the receiver to detect and correct erroneous data bits. This allows errors that occur during transmission to be effectively corrected without the need to retransmit the data.

[0007] Furthermore, it is generally known from the prior art that data transmission over a serial data channel is typically error-prone. To address this problem, the prior art recognizes various coding techniques, such as line coding. This is also referred to as line coding. The prior art recognizes the problem of erroneous data transmission over a serial communication link and provides for the line-coded data to be provided with forward error correction. The prior art thus addresses the problem of error correction by providing line-coded data with a non-line-coded addition, namely forward error correction, which in turn is not line-coded.Thus, the current state of the art presents the problem that even if line coding is provided, individual metadata is transmitted unencoded, and thus the benefits of line coding cannot be utilized for all transmitted data. This, in turn, represents a source of errors. The current state of the art partially addresses this problem by separately line-coding the forward error correction data and transmitting it thereafter. This creates additional overhead, and in order to protect the line-coded forward error correction data, a new forward error correction would have to be calculated. This, in turn, creates additional overhead and, in turn, creates a non-line-coded forward error correction.

[0008] Furthermore, the state of the art has the problem that forward error correction is always calculated over entire data words, resulting in enormous technical effort because an exponentially growing number of gates must be maintained and operated for an increasing word length. This makes state-of-the-art encoders that calculate forward error correction extremely expensive to manufacture and more prone to errors. Furthermore, they consume large amounts of power, which is undesirable in vehicles. Likewise, errors propagate over an entire word to a greater extent than if error corrections were calculated over partial words, which in turn increases the susceptibility to errors. This is also undesirable in vehicles, as data transmission is safety-critical, especially in vehicles.The susceptibility to errors is particularly significant in an automobile or a vehicle in general, as safety-critical functions must be provided.

[0009] Various coding and data transmission methods are known from the state of the art, but they all relate to application scenarios that are disadvantageous for use in an automobile. For example, the state of the art often assumes that high computing power is available and that high real-time requirements are not required. Furthermore, the state of the art often assumes that the weight or reliability of the components used plays a subordinate role. The state of the art often refers to conventional computer networks, where reliability or low technical complexity are less important.

[0010] Based on this state of the art, there is a need to create a method or system arrangement that enables data to be processed as quickly as possible, due to safety requirements in automobiles, while also requiring minimal technical effort and minimizing the error rate during transmission, since retransmission is not possible if an error is detected. The minimal technical effort should consist of installing the simplest possible components, which are lightweight and can also be efficiently manufactured in large quantities. Known methods and system arrangements from computer network technology are typically not applicable here, since weight savings and real-time operation are not crucial for a desktop PC or server.While heat removal generally presents a challenge in computer systems, energy efficiency in an automobile is even more important, as in electromobility, for example, power consumption even influences the range of the vehicle.

[0011] Further prior art relates to the transmission of data in a serial data stream. For example, the prior art provides for extensive descriptive data to be sent along with the payload, indicating where the payload is located and how it should be interpreted. Furthermore, it is known in the prior art to discard individual data packets if they are not transmitted correctly. Furthermore, it is known in the prior art to resend data packets if they do not arrive at a sender in a timely manner or in an unexpected format.

[0012] When transmitting data serially, it is necessary to keep the number of ones and zeros in the serial data stream as equal as possible. This is called disparity. A disparity of zero on average, but also over a short period of time, is desirable to prevent baseline drift during transmission. Baseline drift (DC voltage fluctuation) of the serial signal leads to bit errors. In extreme cases, transmission is not possible.

[0013] To reliably recover the serial bits in the serial data stream on the receiving side without the need to transmit a clock pulse, a minimum number of 0->1 or 1->0 transitions is required. This allows the clock pulse for recovering the serial data to be generated locally at the receiver from the serial data stream. The so-called run length specifies how many identical bits (ones or zeros) can occur consecutively without a change. A short run length is always desirable, as long run lengths make it impossible to reliably recover the clock pulse from the serial data stream.

[0014] The task of the line code (in this case a block code or line code) is to generate a symbol with guaranteed disparity and guaranteed run length from arbitrary data words with arbitrary disparity and infinite run length. This leads to transmission overhead. More bits (in the form of symbols) must be transmitted than the net data word to be transmitted. This means that the required transmission speed (bandwidth) must be greater than the data rate of the data to be transmitted. This, in turn, leads to systems requiring higher error rates or more overhead, power, etc., than would be necessary to transmit the raw data.

[0015] It is therefore an object of the present invention to propose a method for improving forward error correction in serial coding during data transmission in a vehicle. The proposed method is to be efficient, requires little technical effort, and is as error-robust as possible. Furthermore, it is an object of the present invention to provide a correspondingly configured system arrangement for carrying out the method. Furthermore, it is an object of the present invention to propose a computer program product that contains control commands that implement the method or operate the system arrangement. Furthermore, a storage medium with control commands is to be proposed.

[0016] The problem is solved by the features of patent claim 1. Further advantageous embodiments are specified in the subclaims.

[0017] Accordingly, a method for calculating a forward error correction with a reduced number of gates in FEC encoders is proposed, comprising decomposing a data word into a sequence of data subwords according to a provided data structure; decomposing further data words into data subwords of the data structure, wherein each position of the data subwords within the sequence is assigned a position index; concatenating all data subwords with the same position index to form a data subword block; and calculating a data subword block forward error correction over each data subword block.

[0018] In a preparatory process step, a serial data stream is optionally provided. This is payload data, or raw data, to be transmitted from a receiver to a transmitter. Since the communication channel is potentially error-prone, forward error correction must be performed, which requires appropriate forward error correction encoders, also known as FEC encoders. To transmit the raw data, it is divided into individual data words of equal length.

[0019] This is followed by breaking down a data word into a sequence of data subwords, also called segments, according to a provided data structure. The data structure can be a subdivision rule that specifies how many bits the individual data subwords comprise. Particularly preferably, the data structure takes the available encoders into account. According to the invention, two types of encoders can be used: these are forward error correction encoders and line encoders. The so-called FEC encoders are the computing units that calculate a forward error correction for an input signal or a data subword or segment. Overall, according to the invention, all data to be transmitted is line-coded, for which purpose correspondingly specialized line encoders are provided. If the line encoders are specialized for a certain bit length, the data structure or subdivision rule is selected accordingly.For example, individual line encoders encode 6 bits to 8 bits, which in turn favors the data structure being selected accordingly and the segments or data subwords being 6 bits long. The data subwords do not always have to be of the same length, although they are the same length with regard to the data words. This means that the data structure is the same for all data words, specifying the same bit length for each position of the data subwords. If, for example, the data structure stipulates that a first data subword is 6 bits, a second data subword is 8 bits, and a third data subword is 6 bits, this division or data structure is the same for all data words. However, the exemplary embodiment makes it clear that the individual segments can be of different lengths. This does not rule out the possibility of data subwords having the same bit length.The data structure thus relies on the line encoders, which then process data subwords of exactly the length for which they are optimized. This has the technical effect that the line encoders can be equipped with minimal coding and thus the gates to be used.

[0020] According to the invention, further data words are broken down into sub-data words of the data structure, with each position of the sub-data words within the sequence being assigned a position index. Overall, a serial data stream can therefore consist of data words, which in turn are broken down into sub-data words. These sub-data words are segments which are recognized in all provided data words and are given a position index. This position index reflects the order of the respective sub-data word. Since all data words are equally divided into sub-data words, the respective position indices are therefore the same. Figuratively speaking, the data words can be arranged one below the other, with the sub-data words representing columns of the data words. The columns have a uniform width which corresponds to the corresponding sub-data word.The position index does not need to be assigned explicitly, but can be assigned implicitly by the decomposition.

[0021] According to the invention, all data subwords with the same position index are concatenated to form a data subword block. Concatenation in this case means joining. Concatenation can be represented visually by arranging the data words one below the other, forming columns so that each data subword is appended to the upper data subword, as shown, for example, in the figures. The data subword blocks correspond, figuratively speaking, to the individual columns. Concatenation, i.e., logical joining, is not necessarily an explicit joining; rather, all data subwords in the same position are implicitly treated together.Therefore, an explicit concatenation step is not necessarily required; rather, it is an implicit concatenation, meaning that these data subword blocks are treated together in subsequent processing steps. The number of data subword blocks corresponds to the number of data subwords or segments. These are treated equally in each column.

[0022] A data subword block forward error correction is then calculated for each data subword block. This means that each column is treated separately, and a separate forward error correction is calculated for each column-wise segment or data subword.

[0023] In subsequent process steps, this calculated forward error correction can be line-encoded along with the data subwords, which in turn creates a line code for each data subword block. This line code then refers to the data subword block including the data subword block forward error correction. This is performed for all columns or segments, and thus a corresponding line code is output for all data words, which already contains the forward error correction.

[0024] The line-encoded data can then be transmitted over the potentially faulty line.

[0025] For this purpose, further method steps can be provided and, in particular, it is provided according to the invention that the method steps are carried out inversely on the receiver side, so that the error-corrected data words can ultimately be viewed at the receiver.

[0026] According to the invention, the forward error correction is improved by calculating it with respect to payload data and by first segmenting the payload data. A separate forward error correction is then calculated for each segment, so that the forward error correction does not refer to an entire data word, but to different subwords. This keeps the number of gates of the FEC encoders to be used low and avoids exponential growth. Furthermore, an improvement is achieved by the invention

[0027] Line coding is performed over the payload data along with forward error correction, thus overcoming the prior art disadvantage of forward error correction being transmitted in an uncoded form. Furthermore, it is advantageous that error correction can work more efficiently because it only applies to partial words, allowing fine-grained detection of where an error has occurred. Conventional error correction always applies to entire data words and is therefore inefficient, or can lead to errors in the prior art that cannot be corrected. This is avoided by segmentation according to the invention.

[0028] A further improvement is that all transmitted data is line-coded, allowing the entire data set to benefit from line coding. The transmission link is thus deterministically controllable, and bit errors are kept to a minimum. Furthermore, implicit interleaving results from sending smaller packets, resulting in implicit interleaving because not all data words are transmitted. This is achieved by using multiple forward error correction coders, each of which only applies to partial words. Thus, the present invention overcomes the disadvantage of the prior art, which requires the complex creation of explicit interleaving, which would also require additional buffer memory.

[0029] Due to the optimized disparity (line coding) of the bit sequence to be transmitted, errors can be avoided during interpretation on a serial channel. Thus, efficiency also refers to the fact that the bit sequence is particularly error-robust, allowing it to be reliably transmitted only once. Redundant transmission is avoided due to the high detectability, again due to the optimized disparity.

[0030] During serial data transmission, it is advantageous to maintain an equal number of ones and zeros in the serial data stream, if possible. This is generally referred to as disparity. For reliable clock recovery at the receiver, a run-length restriction can be imposed on the generated channel sequence. This limits the maximum number of consecutive ones and zeros. Thus, the proposed method can also be referred to as a method for efficiently encoding a bit sequence. According to the invention, the disparity is optimized by skillfully adjusting partial disparities. This can be particularly advantageous when the run length of the bit sequence is limited. The restricted disparity and the restricted run length can also refer to the arbitrary bit sequence provided. Thus, this does not have to be the efficiently transmittable bit sequence.Overall, the provided arbitrary bit sequence can be transmitted efficiently or a bit sequence to be transmitted is generated or created from this bit sequence, which can then be transmitted efficiently.

[0031] The proposed method can be used specifically in vehicles or is specifically tailored to their requirements. This is because vehicles offer safety-critical functions that must be appropriately protected. According to the invention, this is achieved in several ways. Firstly, through forward error correction and via line coding. Furthermore, the reduced number of gates required is particularly advantageous in electromobility. According to one aspect of the present invention, a line code segment is generated for each data subword block and / or each data subword block forward error correction. This has the advantage that the forward error correction does not have to be transmitted uncoded, but rather is line-coded. Thus, the advantages of line coding are available not only for the payload data but also for the forward error correction.

[0032] According to a further aspect of the present invention, a forward error correction for a data block is composed of multiple partial forward error corrections of the data word blocks. This has the advantage that not one entire forward error correction is initially generated, but rather many individual partial forward error corrections, which together form a total forward error correction. In this way, the number of gates of the required FEC encoders is kept to a minimum. Nevertheless, it is possible to protect all data using forward error correction and, furthermore, to transmit the data including the forward error correction (FEC) in line-coded form.

[0033] According to a further aspect of the present invention, the data structure is read out, and a forward error correction sub-encoder is selected depending on the respective bit lengths of the data subwords. This has the advantage that the FEC encoders are precisely tailored to the segment lengths or the bit lengths of the subwords. In this way, it is possible to minimize the number of gates such that the encoders only need to create codes for small subwords and not for the entire data words. Consequently, each FEC encoder is precisely tailored to the bit length of the data subword to be encoded.

[0034] According to a further aspect of the present invention, the number of gates of the FEC partial encoders is selected depending on the bit length of the data subwords. This has the advantage that, compared to the prior art, the number of gates required for the FEC encoders is reduced, thus creating an efficient system arrangement or method, which is particularly advantageous in automobiles or vehicles. In this way, no unnecessary gates need to be maintained. Thus, a deterministic and minimal number of gates is achieved.

[0035] According to a further aspect of the present invention, the number of all gates of all encoders is selected such that, when the method is executed iteratively, the number of gates increases linearly with increasing data word lengths. This has the advantage that, taking the data format into account, a minimal number of gates is provided or that the data format can be selected such that only a linear increase in the number of gates is necessary. In one embodiment, the maximum bit length can be 10, 11, or 12 bits, which results in the required gates or circuits of the FEC encoders only increasing linearly. Since an exponential growth of gates is necessary for larger values, the present invention creates the technical effect of minimizing power consumption or energy absorption, which in turn leads to less waste heat.Furthermore, the proposed method is particularly robust, which is particularly advantageous in automobiles, where safety-critical functions are offered.

[0036] According to a further aspect of the present invention, each data word has 112 bits. This has the advantage that 128-bit words can be created with line coding, which corresponds to a common format. According to the invention, it has been shown that 112 bits in particular can be encoded in a particularly error-robust 128-bit format. This ensures that the transmission is subject to a lossy or error-prone data channel.

[0037] According to a further aspect of the present invention, the bit length of the data subword block forward error correction is selected such that it matches the bit length of the data subwords. This has the advantage that both the forward error correction and the data subwords or segments can be encoded using the same encoder, which is the line encoder, not the FEC encoder. Thus, the present invention makes the technical contribution that not only a minimal number of gates is required, but rather the total number of encoders is also minimized. Thus, the forward error correction can be line-encoded using the same encoder as the actual payload data segments.

[0038] According to a further aspect of the present invention, the data subword block forward error correction and the data subword block on the basis of which the data subword block forward error correction is calculated are line-coded using the same line encoder. This has the advantage that a minimal number of line codes need be maintained. Figuratively speaking, virtually all columns, i.e. all subword blocks including the corresponding partial forward error correction, are each line-coded using the same segment encoder. According to a further aspect of the present invention, the data structure is selected depending on the bit length of the data words. This has the advantage that the different bit lengths can be addressed dynamically, even at runtime, and thus the same data format can be selected for further data words as for a first provided data word.If the first data words are available, a corresponding data structure can be applied to a further serial data stream and the further data words are structured in such a way that they correspond to the data structures of the first data words received.

[0039] According to a further aspect of the present invention, serial line coding is performed after calculating the data subword block forward error correction. This has the advantage that the order provided in the prior art is reversed, and the forward error correction is calculated first, which means that it can also be line-coded and does not have to be transmitted unencrypted or uncoded.

[0040] According to a further aspect of the present invention, the method steps are executed in a virtualized manner, and information about the underlying encoders and / or gates is generated. This has the advantage that the implementations can be evaluated in a preparatory method step, and thus it can be determined how many gates or how many FEC encoders and / or line encoders are to be provided. Furthermore, the entire method can be simulated. Hardware components can be provided virtually.

[0041] According to one aspect of the present invention, the subdivision rule is stored in a data memory and is present as a coding rule and / or is read from a hardware architecture. This has the advantage that the subdivision rule can be statically specified or can also be changed in the data memory. Furthermore, the subdivision rule can take the corresponding hardware architecture into account. If, for example, different encoders are provided for different bit lengths, the bit sequences can be subdivided such that the corresponding segments correspond to the respective encoders. The segments therefore have exactly the length provided by the respective encoder.

[0042] According to a further aspect of the present invention, all bit sequences have the same structure in their data format, the same segment lengths, and / or the same bit positions. This has the advantage that the individual segments can be fed to the respective encoders. For example, the first segment of each bit sequence is fed to the same encoder. Thus, figuratively speaking, the segments can be encoded column by column, with a specialized encoder for each column.

[0043] According to a further aspect of the present invention, the partial forward error correction has correction information which describes a target content of the segment for which the partial forward error correction was created. This has the advantage that the transmitted data can be corrected using this correction data, whereby an entire correction is not formed for each bit sequence, but rather individual partial forward error corrections are formed for the individual segments. All partial forward error corrections in their entirety describe all segments of all bit sequences and thus all payload data. The difference from the prior art here, however, is that a forward error correction is not formed for each bit sequence, but for all segments across all bit sequences. This makes it possible to use the same line encoder for each partial forward error correction that is used for the corresponding segments.

[0044] According to a further aspect of the present invention, the partial forward error correction has the same bit length as the segment over which it is created. This has the advantage that specialized line encoders can be maintained, thus creating maximum efficiency in that the corresponding column-wise line encoders are specialized precisely for the bit length they must then encode. This creates an efficient method with minimal technical complexity.

[0045] According to a further aspect of the present invention, a set of partial forward error corrections describes all the payload data to be transmitted in a correctable manner. This has the advantage that all the payload data being transmitted can be corrected for errors, but this can be done on a segment-by-segment basis, so that the proposed method is more fine-grained than the prior art.

[0046] According to a further aspect of the present invention, the segment encoders each generate at least part of a line code. This has the advantage that the outputs of the segment encoders can be combined to provide the line codes to be transmitted. According to a further aspect of the present invention, the entirety of the segment encoders encodes 112-bit bit sequences into 128-bit words. This has the advantage of creating a particularly efficient line code.

[0047] According to a further aspect of the present invention, the partial forward error correction line codes are appended to the segment line codes during transmission. This has the advantage that all data to be transmitted is line-coded, thus allowing the line to be operated deterministically, and the advantages of line coding can be utilized for all data, not just the payload data itself.

[0048] According to a further aspect of the present invention, the bit position is specified as an offset or as a bit index in the bit sequence. This has the advantage that different addressing types can be used, and the index is based on an order of the respective segments, which can then be advantageously specified using known methods.

[0049] According to a further aspect of the present invention, the payload data is present as a serial data stream. This has the advantage that, theoretically, any amount of payload data can be transmitted, which is then divided into bit sequences of equal length.

[0050] According to a further aspect of the present invention, the method steps are performed in the described order and / or iteratively. This has the advantage that the coding order is reversed. According to the invention, forward error correction is performed first, followed by line coding. This does not preclude the possibility that individual method steps may need to be performed multiple times. This may be the case, for example, when multiple bit sequences are present and these must be segmented.

[0051] The object is also achieved by a system arrangement for calculating a forward error correction with a reduced number of gates in FEC encoders, comprising a decomposition unit configured to decompose a data word into a sequence of data subwords according to a provided data structure; a further decomposition unit configured to decompose further data words into data subwords of the data structure, wherein each position of the data subwords within the sequence is assigned a position index; a grouping unit configured to concatenate all data subwords with the same position index to form a data subword block; and a calculation unit configured to calculate a data subword block forward error correction over each data subword block.

[0052] The present invention is also directed to a system arrangement or a method which receives the data and then decodes it and reads out both the forward error correction and the payload data.

[0053] The problem is also solved by a computer program product with control commands which implement the proposed method or operate the proposed device.

[0054] According to the invention, it is particularly advantageous that the method can be used to operate the proposed devices and units. Furthermore, the proposed devices and units are suitable for implementing the method according to the invention. Thus, each device implements structural features suitable for executing the corresponding method. However, the structural features can also be configured as method steps. The proposed method also provides steps for implementing the function of the structural features. Furthermore, physical components can also be provided virtually or in a virtualized form.

[0055] Further advantages, features and details of the invention will become apparent from the following description, in which aspects of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. Likewise, the features mentioned above and those further explained here can each be used individually or in groups in any combination. Parts or components with similar functions or that are identical are sometimes provided with the same reference numerals. The terms “left”, “right”, “top” and “bottom” used in the description of the exemplary embodiments refer to the drawings in an orientation with normally legible figure designations or normally legible reference numerals.The embodiments shown and described are not intended to be exhaustive, but rather are exemplary in nature to illustrate the invention. The detailed description is intended to inform those skilled in the art; therefore, known circuits, structures, and methods are not shown or explained in detail in order not to obscure the understanding of the present description. The figures show:

[0056] Figure 1: several examples of a process flow with serial coding and

[0057] Calculation of a forward error correction according to the state of the art;

[0058] Figure 2: an optimized process flow with forward error correction and serial coding according to one aspect of the present invention;

[0059] Figure 3: encoding of payload data and calculating a

[0060] State-of-the-art forward error correction;

[0061] Figure 4: a method for improving forward error correction in serial

[0062] Coding in a data transmission in the vehicle according to the present invention;

[0063] Figure 5: a comparison of the coding according to the state of the art and the

[0064] A method for improving forward error correction according to one aspect of the present invention;

[0065] Figure 6: a diagram showing the required number of gates per bit length of

[0066] Forward error corrections clarified;

[0067] Figure 7A: encoding payload data into a line code according to one aspect of the present invention;

[0068] Figure 7B: the proposed system arrangement to improve the

[0069] Forward error correction in serial coding in a vehicle data transmission according to one aspect of the present invention;

[0070] Figure 8A: an aspect of the method for improving forward error correction according to an aspect of the present invention on the transmitter side;

[0071] Figure 8B: a method for improving forward error correction on

[0072] Receiver side according to an aspect of the present invention; and Figure 9: a flowchart of a method for improving forward error correction in serial coding during data transmission according to an aspect of the present invention.

[0073] Some of the figures present parameters which are familiar to the person skilled in the art in their English terminology and which are used as parameters and therefore cannot be translated.

[0074] Figure 1 shows three exemplary embodiments of how forward error correction is performed according to conventional methods. On the left, an exemplary embodiment is shown that first performs serial encoding of the payload data and then generates a forward error correction code (FEC). The serially encoded data is transmitted, and subsequently, the forward error correction is encoded and then appended to the encoded payload data. Thus, according to this prior art example, the forward error correction is generated over an entire data word, which then must be encoded again and is appended. Encoding is therefore not performed over the individual segments, but over the entire bit sequence.

[0075] In the middle, another prior art embodiment is shown, in which the line-encoding step of the forward error correction is omitted and unencoded parity information is appended. This has the disadvantage that the last data part, i.e., the parity information, is not line-encoded and is therefore highly error-prone.

[0076] On the right, an example is shown which, unlike the example in the middle, omits the loopback of the parity information for serial encoding. This results in the same disadvantages as the example in the middle.

[0077] Data transmission solutions place ever stricter demands on error-free performance / fault tolerance, which require a fine tuning between serial coding and forward error correction (FEC) as data rates continue to increase.

[0078] The current state of the art (Ethernet / DisplayPort) processes the data stream in the following order: 1. The input data is encoded in the first step using serial coding (8b10b, 64b66b, 128b132b, etc.). For larger codings from 64b66b upwards, this is primarily achieved by scrambling using LFSR.

[0079] 2. The serially coded stream is now additionally protected against bit errors using FEC (Forward Error Correction) coding. A complete FEC coding (FEC coding word) contains both the input data on a symbol basis and also the so-called parity symbols. For these applications, the input data is passed through the FEC untouched. This means that it always corresponds to the original serial code. The following additional procedures are now available: a. The parity symbols are now also serially coded afterwards (e.g. 8b10b) in order to meet the requirements for serial transmission (run length, DC balance, etc.). This additional post-coding of the parity symbols requires an additional encoder in hardware. b. Instead of the aforementioned subsequent serial coding of the parity symbols, there are also solutions with feedback of the parity symbols to step 1.).With a serial encoder, it is possible to control the DC balance based on the selection of a positive or negative symbol. However, this is associated with a corresponding dead time (depending on the size of the serial encoding and the FEC encoder). This can, for example, lead to a significant deviation in the temporary DC balance. c. The parity symbols are sent untreated directly to the serial link (e.g., DisplayPort 2.0). However, this is very imprecise because the parity symbols are generated depending on the input data. Here, one relies on the parity symbols being DC-balanced on average.

[0080] All of the methods mentioned (ac) have the disadvantage that they require large resources (e.g., two serial encoders) or result in insufficiently precise serial coding (e.g., DC balancing, run length, spectrum). In particular, inaccurate control over the serial coding, in combination with the transmission channel, can lead to the data stream not being able to be reconstructed error-free at the receiver end (CDR samples incorrectly). These effects are mitigated when operating with FEC (since this corrects bit / symbol errors), which unnecessarily deprives the FEC coding of its correction margin for further necessary error correction for errors caused by signal integrity or, for example, external influences. Based on the size of the overhead (2t see Figure 3), a Reed Solomon FEC can only correct t symbol errors in symbols.

[0081] Figure 2, on the other hand, shows the method according to the invention, in which forward error corrections are generated via the payload data, which are then also encoded with the payload data. The advantage here is that both the payload data and the forward error correction are line-coded and thus error-robust. This figure also shows that the difference from the prior art is that the forward error corrections are generated directly on the payload data and not on the line-coded payload data. This then enables all data to be transmitted in line-coded form, which in turn results in increased error robustness.

[0082] The procedure proposed below to improve the problem mentioned applies to all conceivable ECC / FEC codings and is not only applicable to Reed Solomon codes.

[0083] The presented method changes the order of serial coding and FEC:

[0084] 1. In the first step, the input data is protected using FEC or several individual FEC units with smaller symbol widths (6-12 bits). This also results in a total overhead of 2t.

[0085] The use of multiple FEC sub-codings is expressly preferred here, as this brings further positive properties (explained below).

[0086] 2. Subsequently, the respective current FEC output symbol(s) (not to be confused with the entire FEC coding word n) is encoded using block code in such a way that all desired properties of DC balance, run length, frequency spectrum, etc. are maintained.

[0087] In the case of multiple FEC coders in step 1, exactly the same number of block coders is used. This means that on the receiving side, a bit error on the link that destroys an entire data symbol of the serial code results in only a single FEC symbol error.

[0088] Figure 3 shows a flowchart according to the prior art, wherein the input data is line-coded, and then a forward error correction is generated. This forward error correction is appended to the present right-hand side, as shown at the very bottom. Thus, first the data word above is line-coded, and then a non-line-coded forward error correction is appended. This now presents a problem, since the forward error correction does not have the desired properties necessary for robust data transmission. Disadvantages arise because the data is not DC (digital current) balanced, meaning that a favorable parity is not set. Furthermore, clock recovery errors can occur with a non-line-coded transmission.In general, line coding is advantageous in that it allows an average value of the analog signals to be measured, and then it can be determined which actual signals are above this average value and which are below it. It is desirable that the number of analog signals above the average value, i.e., digital "1s," be equal to the number of analog signals below the average value, i.e., digital "0s." This allows for optimized signal modeling. This is not possible in Figure 3, since the forward error correction code is not line-coded.

[0089] Figure 4 shows the inventive method and transmission over a lossy channel. Here, every channel is potentially lossy, and it is particularly advantageous that forward error coding occurs first upon data input, followed by the entire serial coding. On the receiver side, the method is implemented in reverse analogue, and serial decoding occurs first, restoring not only the payload data but also the forward error correction.

[0090] Figure 5 shows an upper exemplary embodiment of a method according to the prior art, wherein in a first method step, an output data word or a bit sequence is line-coded from the first to the second line. This results in a code that is longer than the output bit sequence, which is also referred to herein as overhead. In a subsequent method step, a forward error correction code is generated from the second line to the third line and appended to the line coding. As can now be seen, the first part on the left of the data to be transmitted is line-coded, and the second part, namely the forward error correction, is not line-coded. This entails problems, since the advantages of line coding must be foregone for the appendix on the right. This is disadvantageous.

[0091] In the exemplary embodiment in the middle of the present figure, the output word ABC is again shown at the top. The bit sequence therefore consists of the segments A, B and C. In this case, these are 11 bits, 6 bits and 7 bits long. According to the invention, it is not the entire data word, i.e. the entire bit sequence, that is, is protected in its entirety, i.e. provided with a forward error correction code, but rather the individual segments are protected. This is shown in the second line by the fact that the corresponding forward error correction code is shown after each segment A, B and C. In a subsequent method step, line coding is applied in the third line, or the data from the second line is completely line-coded, which results in a line code in the third line. This can now be transmitted, and it is clear that all of the data is line-coded and that the forward error correction code is also line-coded.Thus, the advantages of line coding apply to all data to be transmitted.

[0092] The exemplary embodiment at the very bottom of Figure 5 shows the method steps according to the invention, although further sub-steps are possible. The different bit sequences are shown, with the payload data now divided into bit sequences of equal length. The entire payload data is thus divided into four bit sequences, all of the same length. These four bit sequences are in turn divided into segments of equal length. Figuratively speaking, individual bit sequences are arranged horizontally, and these bit sequences are arranged one below the other, so that each row reflects a bit sequence. As can also be seen, the bit sequences are each divided into three segments of equal length. This results in a matrix-like arrangement of the payload data with bit sequences per row and segments per column.

[0093] Now, instead of performing line coding as is provided for in the prior art, a partial forward error correction is calculated for each column, i.e., for all segments at the same bit position, according to the subdivision rule specified in the above method step. As can be seen in the first row of the second rectangle, a partial forward error correction is drawn at the top, which is referred to as FEC overhead in this figure. The segmented bit sequences are now available according to the subdivision rule, and the partial forward error corrections for all segments at the same bit position are available across all bit sequences.

[0094] A segment encoder is then applied to all segments with the same bit position to generate segment line codes across all segments for each bit position and each bit sequence. In a further or the same method step, the same segment encoder is applied to the respective partial forward error correction (FEC) code, resulting in a single line code that includes the segment line codes and the partial forward error correction (FEC) codes. As can now be seen below in Figure 5, all data has been line-coded, and in particular, the FEC code has also been line-coded. This data can now be advantageously transmitted.

[0095] Figure 6 shows, in a diagram on the y-axis, the number of gates required to create a forward error correction code as a function of the bit length to be encoded on the x-axis. As can be seen, this is an exponential growth, and from a bit length of 10-12 bits, the growth of the gates, i.e. the number of gates required for forward error correction, increases above average. Thus, according to the invention, it is particularly advantageous to perform forward error correction for each segment, as this avoids having to take the entire data word, i.e. the entire bit length, into account. If the entire bit length had to be taken into account for forward error correction, the bit length would typically be beyond the critical 12 bits. The number of gates required in the forward error correction encoder would increase in an unfavorable manner.This illustrates the advantageous technical effect of the present invention, which first forms segments over the bit sequence and then calculates the forward error correction on the segments.

[0096] At this point, reference is again made to the subdivision rule according to Figure 5, which stipulates that a segment can have 11 bits, 6 bits or 7 bits.

[0097] By using multiple FEC encoders / decoders with smaller FEC symbol sizes, both the number of required gates and the maximum operating frequency for a given process node F are reduced. m ax larger (shorter carry chains, more parallelism).

[0098] Figure 6 shows the relationship between the FEC symbol size in bits and the required implementation. This refers to a hardware implementation of a Reed Solomon FEC. The number of gates is normalized (to 12 bit symbol size) so that a direct comparison can be made. The exponential relationship between symbol size in bits and implementation in gates can be seen in the graph. The same symbol widths do not always have to be used for the respective small FEC sub-coders. Large serial codes can also consist of several different sub-codes (simplest example 8b10b which can be constructed from 3b4b and 5b6b), as suggested with the use for FEC. In the case of the present invention or ADXpress (registered trademark), this is achieved using a total of 11 coders with four basic types: 6b8b, 7b8b, 11b12b and 11b13b.The FEC symbol width used for each sub-encoding is determined by the data word width of the respective serial encoder. For example, for 6b8b, an FEC with a symbol width of 6 bits is used.

[0099] The complete structure for the transmitter data path of the present invention, or ADXpress (registered trademark), is shown in one aspect in Figure 8A. The data path in the receiver is constructed in a correspondingly inverse manner (see also Figure 8B).

[0100] Figure 7A shows a line coding system or a line coding device with multiple line coding units, which, for example, map 11 bits to 12 bits, 11 bits to 13 bits, or 11 bits to 12 bits. This corresponds to the sequence in Figure 7 from right to left and illustrates that the input data word, i.e., the bit sequence at the top, is divided into individual segments, and then the individual segments are line-coded. The calculation of the forward error correction is not yet taken into account in Figure 7A, so the system arrangement according to Figure 7A can serve as the starting system arrangement for the present invention.

[0101] Figure 7A above shows any 112-bit bit sequence being segmented into 11, 6, or 7 bits. The coding units are then addressed in parallel, converting the bits into subsymbols optimized for disparity. For example, 11 bits are encoded to 12 bits, or 11 bits to 13 bits.

[0102] In Figure 7A, a coding unit from the second subset, labeled 11B12B, is shown in the center of the far left side. This unit provides a subsymbol with any sign, i.e., with any disparity.

[0103] To compensate for this disparity, the coded unit 11B13B is connected downstream in parallel with the bit sequence. This means that a data stream is formed that converts the most significant bits of twice 11 into two subsymbols: firstly, the 11-bit data segment is formed into a 12-bit subsymbol with any sign, i.e., disparity, using 11B12B, and secondly, the data segment of 11 bits is encoded into 13 bits using the coding unit 11B13B. In the figure below the coding units, the second coding unit from the left, 11B13B, is a coding unit of the first subset. This unit has an inverter and a multiplexer. The first 13 bits are therefore present as a data stream that is divided in such a way that it is inverted once with respect to the sign, i.e., the disparity, and once remains unchanged. Further down it is indicated that under feedback of disparity the positive or negative, i.e.i.e., the original or inverted data stream is used, which compensates for the sign from the leftmost coding unit. The first multiplexer on the left thus receives two data streams, each representing the subsymbol: one with the conventional sign, as output from the 11-bit 13-bit coding unit, and one with an inverted sign or inverted disparity.

[0104] Based on the feedback from the unit at the very top, the disparity resulting from the leftmost encoder 11 B12B is determined, and thus the multiplexer, at the very bottom left, compensates for or minimizes the disparity of the subsymbol of the leftmost encoder 11 B12B. This is carried out in parallel in such a way that the coding units from the second subset are followed by coding units from the first subset, which minimize or eliminate the disparity. Finally, the overall symbol is output at the very bottom right. This overall symbol has 128 bits and is made up of the subsymbols, as inserted into the bold line below using the slanted arrows. Thus, the subsymbols whose disparity is optimized or minimized are present on this output line, and these subsymbols form the overall symbol, which can then be output and transmitted.

[0105] According to one aspect of the present invention, a 112-bit data word with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) is encoded into a 128-bit symbol. The overhead resulting from the encoding is thus 14.2%.

[0106] The maximum run length occurring in the symbol, as well as in any sequencing of any symbols, is 8 equal bits.

[0107] The maximum disparity in the long mean is 0. The disparity in a symbol is less than 9.

[0108] The complexity of the logic is minimal, comparable to 10 8B / 10B encoders (with the well-known disadvantage of the large overhead).

[0109] This is achieved by the use, or parallel use, of several “small” encoders whose characteristics regarding disparity and run length are optimally matched to one another.

[0110] The encoders 11 B12B, 7B8B and 6B8B all generate symbols with a guaranteed maximum run length of 6, even with arbitrary sequencing of the (partial) symbols.

[0111] According to one aspect of the present invention, the encoder (11 B13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the sequencing (Fig. 2) of the (11 B13B) with the other encoders, a maximum run length of 8 can be created in the symbol.

[0112] See encoder properties as follows:

[0113] 11B13B: 11 bits of data are mapped to 2048 13-bit symbols. The symbols can be transmitted inverted or non-inverted.

[0114] Disparity:

[0115] +3... +9 or controllable -3... -9

[0116] Run length in word: 7

[0117] Running length at the edge: 5.

[0118] 11B13B: 11 bits of data are mapped to 2048 13-bit symbols. The symbols can be transmitted inverted or non-inverted.

[0119] Disparity: +3... +9 or controllable -3... -9

[0120] Run length in word: 7

[0121] Running length at the edge: 5

[0122] 11B12B: 11 bits of data are mapped to 2048 12-bit symbols. The symbols are transmitted uninverted.

[0123] Disparity: -2, -1 , 0, 1 , 2

[0124] Running length in the word: 6 Running length in the margin: 3

[0125] 7B8B: 7-bit data is mapped to 128 8-bit symbols. The symbols are transmitted uninverted.

[0126] Disparity: -2, -1 , 0, 1 , 2 Run length in word: 6 Run length at edge: 3

[0127] 6B8B: 6-bit data is mapped to 64 8-bit symbols. The symbols are transmitted uninverted.

[0128] Disparity: 0

[0129] Run length in word: 6

[0130] Running length at the edge: 3

[0131] With the four 11 B13B encoders, a disparity of at least +-12 can be controllably generated to compensate for the uncontrollable disparity of a maximum of +-12 (6 x +-2) of the 11 B12B and 7B8B encoders, so that a balanced disparity can be reliably achieved regardless of the data to be transmitted.

[0132] To further reduce the complexity of the hardware, according to one aspect of the present invention, four small encoders (11B13B) are used, the disparity of which can be controlled with respect to sign (+-).

[0133] According to one aspect of the present invention, symbol disparity is controlled by each encoder calculating the parity of "its" subsymbol. This is done with little effort, since the subsymbol has only a few bits.

[0134] For four of the eleven encoders, the sign of the disparity of the subsymbol can be actively controlled by inverting the generated subsymbol. The encoders (11B13B) have the special feature that their symbols generate a symbol with positive disparity (+3... +9) for all input data. Inverting the subsymbol produces a symbol with negative disparity (-3... -9).

[0135] This allows the disparity (-2, -1, 0, 1, 2) of the subsymbols of the other encoders (11B12B and 7B8B) to be compensated. The 6B8B encoder generates symbols whose disparity is always 0. Then, all (sub)parities of the encoders (11B12B and 7B8B) are added, and the result determines how many inverted and non-inverted symbols of the encoder (11B13B) are used.

[0136] The minimum (smallest) disparity of the encoder is 11B13B +-3. Thus, in total, these four encoders can reliably compensate for a disparity of +-12 (4*+-3) per symbol.

[0137] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, each with a maximum disparity of +-2. Thus, in the extreme case, these six encoders produce a disparity of exactly +-12 (2*+-6). This can be reliably compensated by the 11B13B encoders.

[0138] According to one aspect of the present invention, the method achieves the same quality as an 8B10B code but with half the overhead (loss due to coding).

[0139] The implementation of the encoding and decoding hardware requires only minimal resources (logic) due to the use of several small encoders instead of one large one.

[0140] The encoding can typically be done entirely in one clock cycle of the parallel data path (no pipelining necessary).

[0141] The control of the disparity of the 128-bit symbol can be realized with (very) little logic, and can be realized entirely within one clock of the data path (slowly), instead of calculating the disparity by counting the one and zero bits in the serial data stream with the very fast serial clock.

[0142] Due to the deterministic disparity and run length, further scrambling is not necessary, thus enabling fast synchronization to the data stream on the receiver side (no scrambler synchronization required).

[0143] This is very useful, among other things, for power-save modes in which the link can be disabled for energy-saving purposes and enabled again when needed. Fast synchronization between transmitter and receiver is essential for this. According to one aspect of the present invention, a 112-bit data word with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) is encoded into a 128-bit symbol. The overhead resulting from the encoding is thus 14.2%.

[0144] The maximum run length occurring in the symbol, as well as in any sequencing of any symbols, is 8 equal bits.

[0145] The maximum disparity in the long mean is 0. The disparity in a symbol is less than 9.

[0146] The complexity of the logic is minimal, comparable to 10 8B / 10B encoders (with the well-known disadvantage of the large overhead).

[0147] This is achieved by the use, or parallel use, of several “small” encoders whose characteristics regarding disparity and run length are optimally matched to one another.

[0148] The encoders 11 B12B, 7B8B and 6B8B all generate symbols with a guaranteed maximum run length of 6, even with arbitrary sequencing of the (partial) symbols.

[0149] According to one aspect of the present invention, the encoder (11 B13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the sequencing (Fig. 2) of the (11 B13B) with the other encoders, a maximum run length of 8 can be created in the symbol.

[0150] See encoder properties as follows:

[0151] To further reduce the complexity of the hardware, four small encoders (11B13B) are used, whose disparity can be controlled with respect to sign (+-).

[0152] According to one aspect of the present invention, symbol disparity is controlled by each encoder calculating the parity of "its" subsymbol. This is done with little effort, since the subsymbol has only a few bits.

[0153] For four of the eleven encoders, the sign of the disparity of the subsymbol can be actively controlled by inverting the generated subsymbol. The encoders (11B13B) have the special feature that their symbols generate a symbol with positive disparity (+3... +9) for all input data. Inverting the subsymbol produces a symbol with negative disparity (-3... -9).

[0154] This allows the disparity (-2, -1, 0, 1, 2) of the subsymbols of the other encoders (11B12B and 7B8B) to be compensated. The 6B8B encoder generates symbols whose disparity is always 0. Then, all (sub)parities of the encoders (11B12B and 7B8B) are added, and the result determines how many inverted and non-inverted symbols of the encoder (11B13B) are used.

[0155] The minimum (smallest) disparity of the encoder is 11B13B +-3. Thus, in total, these four encoders can reliably compensate for a disparity of +-12 (4*+-3) per symbol.

[0156] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, each with a maximum disparity of +-2. Thus, in the extreme case, these six encoders produce a disparity of exactly +-12 (2*+-6). This can be reliably compensated by the 11B13B encoders.

[0157] The method achieves the same quality as an 8B10B code but with half the overhead (loss due to coding).

[0158] The implementation of the encoding and decoding hardware requires only minimal resources (logic) due to the use of several small encoders instead of one large one.

[0159] The encoding can typically be done entirely in one clock cycle of the parallel data path (no pipelining necessary).

[0160] The control of the disparity of the 128-bit symbol can be realized with (very) little logic, and can be realized entirely within one clock of the data path (slowly), instead of calculating the disparity by counting the one and zero bits in the serial data stream with the very fast serial clock.

[0161] Due to the deterministic disparity and run length, further scrambling is not necessary, allowing for fast synchronization to the data stream on the receiver side (no scrambler synchronization required). This is very useful, among other things, for power-save modes in which the link can be shut down for energy-saving purposes and re-enabled when needed. Fast synchronization between transmitter and receiver is essential for this.

[0162] Figure 7B now shows the adapted system arrangement from Figure 7A, with corresponding partial forward error correction encoders now shown. These are referred to here as FEC blocks. This figure shows that segments are first formed from the bit sequences, which corresponds to the upper arrows pointing downwards from the payload data. This is where the partial forward error corrections are generated and then fed into the coding units, as already shown in Figure 7A. The line coding units are referred to here as line coders and encode both the segments of the bit sequences and the partial forward error corrections. The parity can also be adjusted in optional process steps. The line-coded data is then output at the bottom and transmitted to the right via a potentially error-prone communication channel to a receiver (not shown here).

[0163] Figure 8A shows the inventive method for improving forward error correction and, in particular, shows the method steps performed on the transmitter side. The arrows at the bottom of this Figure 8A correspond to the arrow at the top of the subsequent Figure 8B. The data is thus input according to Figure 8A, and then the partial forward error correction is calculated. As can be seen above, all segments have the same bit length. This means that the first column contains 11 bits, the second column contains 11 bits, and the last column contains 6 bits.

[0164] A partial forward error correction is then generated across all segments of the same bit sequence, which has the same bit length as the corresponding segments. This results in the data with a parity symbol. In a final process step, serial line coding takes place, which, for example, maps 11 bits to 12 bits, or 11 bits to 13 bits, or 6 bits to 8 bits. This data can now be transmitted over the potentially interference-prone channel. This results in a transmission as shown in Figure 8A below or in the present Figure 8B above.

[0165] Figure 8B shows the process on the receiver side and corresponds to the process in Figure 8A in reverse. As also shown in Figure 8B, it is recognized that bit errors may be present, which, however, can be handled particularly advantageously at the segment level. The bit errors therefore do not occur in the entire bit sequence, but only in individual segments and can therefore be handled advantageously. This leads to the corrected data, as shown below in Figure 8B, and thus the 112 bits are recovered, as they served as the output in Figure 8A.

[0166] Figure 9 shows a flowchart of a method for calculating a forward error correction with a reduced number of gates in FEC encoders, comprising decomposing 100 a data word into a sequence of data subwords according to a provided data structure; decomposing 101 further data words into data subwords of the data structure, wherein each position of the data subwords within the sequence is assigned a position index; concatenating 102 all data subwords with the same position index to form a data subword block; and calculating 103 a data subword block forward error correction over each data subword block.

[0167] All segment line codes and all partial forward error correction line codes are also transmitted. In this final step, all generated segment line codes and partial forward error correction line codes are transmitted. These transmitted codes contain the information for error detection and correction for the corresponding segments and partial forward error corrections. The described method enables improved forward error correction during serial coding and data transmission in the vehicle. By dividing the payload data into segments and applying specific coding methods to these segments, effective error detection and correction at the segment level is achieved.

[0168] By iteratively creating a partial forward error correction for all segments with the same bit position and applying a segment encoder to each segment, targeted error correction for the transmitted data is enabled. The partial forward error correction line codes contain the necessary information to detect and correct errors, while the segment line codes represent the structure and content of the segments and also contribute to error detection and correction.

[0169] By transmitting all generated segment line codes and

[0170] Partial forward error correction line codes allow the receiver to analyze the received data accordingly and detect and correct errors to ensure reliable and accurate transmission of the payload data in the vehicle.

[0171] The described method thus provides improved forward error correction, which is particularly important in demanding environments such as vehicles, where interference and signal loss can occur. It contributes to ensuring reliable and high-quality data transmission, which is of great importance for various automotive applications, such as autonomous driving, vehicle safety systems, and infotainment applications.

[0172] The invention makes it possible to maintain all desired properties and requirements for serial coding at all times while ensuring efficient operation of an FEC. By deliberately positioning the serial encoder after the FEC units, the physical behavior on the link can always be deterministically controlled (not the case with scramblers as serial coding).

[0173] In addition, the selection of the FEC symbol size based on the data word size of the respective serial sub-encoder always ensures that bit errors always propagate to a minimum (a defective line code symbol then only generates one defective FEC symbol).

[0174] Furthermore, the use of multiple FEC sub-encoders creates a very efficient form of interleaving. This is possible without the laborious manual interleaving of symbols, which would always require data (increasing latency and buffering). This also makes it possible to correct burst errors, such as 112 / 128 bit errors, at once.

[0175] Only the schematic structure in Figures 7A, 7B and 8A, 8B clearly shows that this is the case: 128 bit errors in this case result in only a single symbol error in the respective FEC sub-coder. With conventional single-FEC coding, a burst error of the same length (128 erroneous bits in a row) would generate several symbol errors in succession. Depending on the selected coding, this can lead to the FEC word (all symbols of an FEC cycle) no longer being decodable (thus making correction impossible). This is usually achieved by interleaving symbols of one FEC cycle with those of one or more subsequent FEC cycles.However, this is only possible with the use of buffers on the transmit and receive sides. This allows the data to be interleaved at the transmitter and then converted back into the original continuous FEC symbol data stream of the individual FEC cycles at the receiver using the inverse operation. Using multiple small FEC encoders eliminates the need for interleaving and thus the buffers required for interleaving (although only to a certain extent; a burst error of more than 128 consecutive bits mentioned in the example results in more than one symbol being corrupted per individual FEC cycle).

[0176] The number of symbols a particular FEC sub-encoder can repair (t) depends on the overhead 2t (see Figure 2). This must be selected accordingly for the desired application. The case shown in Figure 8A with one symbol error per FEC sub-encoder is already reached at t=1 (i.e., two parity symbols overhead). It should also be noted that the burst error can also occur without any restrictions in the range of parity symbols.

Claims

Patent claims 1. A method for calculating a forward error correction with a reduced number of gates in FEC encoders, comprising: - decomposing (100) a data word into a sequence of data subwords according to a provided data structure; - decomposing (101) further data words into data subwords of the data structure, wherein each position of the data subwords within the sequence is assigned a position index; - concatenating (102) all data subwords with the same position index to form a data subword block; and - calculating (103) a data subword block forward error correction over each data subword block.

2. Method according to claim 1, characterized in that a line code segment is generated for each data subword block and / or each data subword block forward error correction.

3. Method according to claim 1 or 2, characterized in that a forward error correction for a data block is composed of several partial forward error corrections of the data subword blocks.

4. Method according to one of the preceding claims, characterized in that the data structure is read out and a FEC partial encoder is selected depending on the respective bit lengths of the data subwords.

5. Method according to one of the preceding claims, characterized in that the number of gates of the FEC partial encoders is selected as a function of a bit length of the data subwords.

6. Method according to one of the preceding claims, characterized in that the number of all gates of all encoders is selected such that an iterative execution of the method results in a linear increase in the number of gates with respect to increasing data word lengths.

7. Method according to one of the preceding claims, characterized in that each data word has 112 bits.

8. Method according to one of the preceding claims, characterized in that the bit length of the data subword block forward error correction is selected such that it corresponds to the bit length of the data subwords.

9. Method according to one of the preceding claims, characterized in that the data subword block forward error correction and the data subword block on the basis of which the data subword block forward error correction is calculated are line-coded by means of the same line encoder.

10. Method according to one of the preceding claims, characterized in that the data structure is selected as a function of the bit length of the data words.

11. Method according to one of the preceding claims, characterized in that serial line coding is carried out after calculating the data subword block forward error correction.

12. Method according to one of the preceding claims, characterized in that the method steps are carried out in a virtualized manner and information about the underlying encoders and / or gates is generated.

13. System arrangement for calculating a forward error correction with a reduced number of gates in FEC encoders, comprising: - a decomposition unit configured to decompose (100) a data word into a sequence of data subwords according to a provided data structure; - a further decomposition unit configured to decompose (101) further data words into data subwords of the data structure, wherein each position of the data subwords within the sequence is assigned a position index; - a grouping unit configured to concatenate (102) all data subwords of the same position index into a data subword block; and - a calculation unit arranged to calculate (103) a data subword block forward error correction over each data subword block.

14. A computer program product comprising instructions which, when the program is executed by at least one computer, cause the computer to carry out the steps of the method according to any one of claims 1 to 12.

15. A computer-readable storage medium comprising instructions which, when executed by at least one computer, cause the computer to carry out the steps of the method according to any one of claims 1 to 12.

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