A method for operating at least one CMOS transistor

Abstract

The invention provides a method for operating at least one CMOS transistor at a low temperature, the at least one CMOS transistor produced using at least one process selected from a planar bulk CMOS process, a fin field effect transistor (FinFET) process, and a combination thereof, the method comprising setting the at least one CMOS transistor in a low-temperature drive mode comprising determining for the at least one CMOS transistor its threshold voltage as a function of its operating temperature range and for an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature in the operating temperature range for the at least one CMOS transistor, in particular a desired operating temperature below 218K, more in particular at a cryogenic temperature, determining a resulting forward bulk biasing (FBB) voltage, and applying the resulting forward bulk biasing voltage to the at least one CMOS transistor.

Description

[0001] A METHOD FOR OPERATING AT LEAST ONE CMOS TRANSISTOR

[0002] Field of the invention

[0003] The invention relates to a semiconductor devices adapted for rectifying, amplifying, oscillating or switching, in particular to a method for operating at least one CMOS transistor, a CMOS transistor, a circuit comprising the at least one CMOS transistor, and a method for operating the circuit comprising the at least one CMOS transistor.

[0004] Background of the invention

[0005] Electronic circuits or devices fabricated using the CMOS technology are in some applications required to operate at low temperatures, in particular at cryogenic temperature. These devices can be used e.g., in space applications or quantum computers, which require high-performance cryogenic electronics, but are also severely power constrained. For examples, quantum computers are limited by the cooling power of dilution refrigerators, which is only < 1 W at the 4K stage and < 1 mW at the 100 mK stage.

[0006] A drawback when cooling down a CMOS transistor is the increase in its threshold voltage (Vth). In operation, this means for instance that a higher voltage is required to turn on the device to conduct an electric current. This increase in threshold voltage can so far only be circumvented by complex circuit techniques and may still impair the performance of the electronic circuit.

[0007] Reducing this threshold voltage is possible using cryogenic aware doping. However, this doping is often still optimized for room-temperature electronics. Additionally, changing the doping would still not allow for wide temperature applications. An alternative solution is the back-biasing in FD-SOI technologies, which has been shown to drastically improve performance. In this respect, reference is made to H. Bohuslavskyi, S. Barraud, V. Barral, M. Cass' e, L. Le Guevel, L. Hutin, B. Bertrand, A. Crippa, X. Jehl, G. Pillonnet et al., “Cryogenic characterization of 28- nm FD-SOI ring oscillators with energy efficiency optimization,” IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3682-3688, 2018. A large downside of this technique though, is that the body-factor in FD-SOI technologies is lower than in bulk CMOS. For example, in A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T.-J. K. Liu, “Forward body biasing as a bulk-si emos technology scaling strategy,” IEEE Transactions on Electron Devices, vol. 55, no. 10, pp. 2657-2664, 2008, the body factor can be 0.085 V / V, while for bulk it is 0.25 V / V. A quick calculation with this factor in FDSOI shows that 0.18 / 0.085 ~ 2.1 V may be required to compensate for the increase in the threshold voltage at cryogenic temperatures. This means that the required applied voltages drastically exceed the typical supply rails of 1 V. The consequence is that when avoiding reliability issues that could arise when generating high voltages on chip, all back-bias voltages have to be generated off-chip. If several different voltages are required for different parts of a system, this would necessitate an increase in the number of pads. Thus, if a large threshold shift is desired whilst keeping the bias voltages within the supply rails, a higher body-factor would be needed.

[0008] Summary of the invention

[0009] It is an aspect of the invention to provide a CMOS transistor and circuit, which preferably further at least partly obviates one or more of above-described drawbacks.

[0010] There is provide a method for operating at least one CMOS transistor at a low temperature, the at least one CMOS transistor produced using at least one process selected from a planar bulk CMOS process, a fin field effect transistor (FinFET) process, and a combination thereof, the method comprising setting the at least one CMOS transistor in a low-temperature drive mode comprising determining for the at least one CMOS transistor its threshold voltage as a function of its operating temperature range and for an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature in the operating temperature range for the at least one CMOS transistor, in particular a desired operating temperature below 218K, more in particular at a cryogenic temperature, determining a resulting forward bulk biasing (FBB) voltage, and applying the resulting forward bulk biasing voltage to the at least one CMOS transistor. There is further provided a CMOS transistor produced using at least one process selected from a planar bulk CMOS procedure, a fin field effect transistor (FinFET) procedure, and a combination thereof, said CMOS transistor comprising a low- temperature drive mode, in particular a drive mode at a low temperature below 218K, more in particular a cryogenic drive mode, said drive mode adapted for supplying a forward bulk bias voltage to the CMOS transistor for setting a desired threshold voltage of the CMOS transistor at the desired operating temperature below 218K, in particular at a cryogenic temperature.

[0011] There is further provided a semiconductor circuit comprising a series of these CMOS transistors.

[0012] There is further provided computer program product which, when executed on a data processing device, preforms retrieving for said one or more CMOS transistor its threshold voltage as a function of an operating temperature range including a temperature in the cryogenic temperature range and of an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature for said CMOS transistor; calculating a resulting forward bulk biasing (FBB) voltage using the function, and providing as output the resulting forward bulk biasing voltage.

[0013] There is further provided a CMOS transistor driver for driving at least one CMOS transistor, comprising computer program product which, when executed on a the CMOS transistor driver, performs retrieving for said one or more CMOS transistor its threshold voltage as a function of an operating temperature range including a temperature in the cryogenic temperature range and of an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature for said CMOS transistor; calculating a resulting forward bulk biasing (FBB) voltage using the function, and providing as output the resulting forward bulk biasing voltage.

[0014] This invention as claimed proposes an effective scheme to reduce the threshold voltage at low temperatures, in particular at cryogenic temperatures. In this way circuit techniques and circuit topologies requiring the standard threshold voltage available at room temperature can be adopted. Furthermore, being able to tune the threshold voltage of individual devices individually enables novel techniques and circuits.

[0015] The resulting forward bulk biasing (FBB) voltage is determined. In an embodiment, the FBB is calculated, or predicted from a predetermined relation. The relation of function can be a generalised relation or function, averaging a series of CMOS transistors, for instance on one single chip. In another embodiment, the relation or function is determined for each CMOS transistor individually.

[0016] In bulk CMOS, applying large bulk voltages at room temperatures would turn on the diodes in the bulk. This would lead to massive unwanted currents leaking into the bulk. When cooling down electronics, the diode turn-on voltage starts increasing above the supply rails. The question that arises, will use of forward back-biasing in bulk CMOS at low, in particular cryogenic temperatures, enable low-power and high- performance design, while staying within the supply rails?

[0017] In general, Complementary Metal-Oxide-Semiconductor (CMOS) is a type of metal-oxide-semiconductor device fabrication, like for instance a field-effect transistor (MOSFET) fabrication process, that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication. Furthermore, driver circuits for quantum devices can be made using CMOS devices or CMOS production methods.

[0018] Bulk CMOS in general refers to a chip (integrates circuit) built on a standard silicon wafer. In contrast to bulk CMOS, the “Fully Depleted Silicon on Insulator” (FD-SOI) production method and devices uses “ Silicon on Insulator (SOI of Sol) wafers that incorporate thin insulating layer within the substrate. The insulating layer is often referred to as “ buried oxide”.

[0019] A Fin Field-Effect Transistor (FinFET) is a multigate device and yet another CMOS technology. In general, it is a MOSFET (Metal-Oxide-Semiconductor Field- Effect Transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source / drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal-oxide-semiconductor) technology.

[0020] FinFET in particular relates to a type of non-planar transistor, or "3D" transistor. It is the basis for modern nano-electronic semiconductor device fabrication.

[0021] Planar bulk CMOS in general refers to a circuit build on a semiconductor wafer.

[0022] In general, the current device and circuit(s) operate(s) or is / are designed to operate at a low temperature. In the current application, “low temperature” is defined as a temperature of below -55°C (218K).

[0023] In physics, cryogenics relates to the production and behaviour of materials at very low temperatures. The 13th IIR International Congress of Refrigeration (held in Washington DC in 1971) a universal definition of "cryogenics" and "cryogenic" was set by accepting a threshold of 120 K (or -153 °C) to distinguish these terms from the conventional “refrigeration”. The U.S. National Institute of Standards and Technology considers the field of cryogenics to involve temperatures below 120K. In particular embodiments, reference is made to circuits operating at cryogenic temperature.

[0024] In some applications, even lower temperatures are required. For instance, this low cryogenic operation is below 10 K. In particular, low cryogenic is below 4.2 K.

[0025] In an embodiment, the forward-bulk-biasing voltage is extended well beyond what possible at room temperature. In an embodiment, the forward bulk biasing voltage was extended up to the supply. In particular, it was not extended further because 1) going too further will increase the leakage dramatically and impede the circuit functionality 2) using only supply within the supply rails helps generate those voltages on chip.

[0026] In an embodiment, the CMOS transistor is provided on a chip. In an embodiment the CMOS transistor is part of an integrated circuit on a chip. This may for instance be based upon Germanium, silicon, gallium-arsenide or diamond.

[0027] The driver in many instances is integrated on the chip (on-chip) of integrated circuit mentioned above. However, in for instance temperature and / or power sensitive embodiments, the driver is separate from the chip, allowing it to be provided outside a low-temperature environment of the chip. The driver may be of relatively simple design, applying one forward bulk bias voltage to a series of CMOS transistors. In an alternative embodiment, the driver can apply individual forward bulk bias voltages to various CMOS transistors.

[0028] In an embodiment, the driver can be provided outside the low-temperature environment of the device or circuit.

[0029] In the current application, usually the term forward bulk biasing or forward body biasing, in short FBB, is used. In some instances, the (shorthand) wording “ back biasing” or “body biasing” is used for the same feature.

[0030] Detailed description of the invention

[0031] Below, some detailed embodiments of the current invention are elucidated.

[0032] In an embodiment, the forward bulk biasing (FBB) voltage is at least as much as the turn-on voltage of the bulk-source diode at room temperature, in particular at least 0.5 Volt. In an embodiment in which the CMOS transistor is substantially from silicon, it is at least 0.6 Volt for a silicon diode.

[0033] In an embodiment, the forward bulk biasing (FBB) voltage is applied to a substrate contact near the CMOS transistor. In particular the substrate contact is at a distance of between 0.1-5 micron. In an embodiment, the substrate contact is at a distance of 0.5-2 micron, specifically in the order of 1 micron.

[0034] In an embodiment, the CMOS transistor is provided on a chip, and the forward bulk biasing (FBB) voltage is applied to the CMOS transistor via a driver from outside the chip. In an embodiment, the driver is provided at a low temperature in the order of the temperature of the CMOS transistor, in particular within 10K of the temperature of the CMOS transistor.

[0035] In an embodiment, the CMOS transistor is provided on a chip, and the forward bulk biasing (FBB) voltage is applied to the CMOS transistor via a driver on the chip.

[0036] In an embodiment, the CMOS transistor is embedded within a well with a doping type that is opposite to the doping type of its substrate. In a particular embodiment the CMOS transistor sharing its well with at least one other transistor. More in particular, it is a PMOS transistor in an N-well and / or a NMOS transistor implemented in an P- well. In an embodiment, the wells are separated via a deep-N-well.

[0037] The CMOS transistor can be a PMOS transistor. In another embodiment, the CMOS transistor is an NMOS transistor. It was found that PMOS is in particular suited for application of forward bulk bias voltage. PMOS has an available separate well to apply forward body bias voltage.

[0038] In an embodiment, the CMOS transistor is part of an amplifier.

[0039] In an embodiment of the CMOS transistor it is further functionally coupled to a driver, the driver comprising a temperature input functionally coupled to the CMOS transistor and the driver adapted for setting a forward bulk bias voltage as a function of the temperature input. In an embodiment of the CMOS transistor it is further functionally coupled to a driver, the driver comprising a temperature input functionally coupled to the CMOS transistor and a set threshold voltage for the CMOS transistor, the driver adapted for calculating a forward bulk bias voltage as a function of the temperature input and the set threshold voltage, and for setting the calculated forward bulk bias voltage to the CMOS transistor.

[0040] In an embodiment of the semiconductor circuit, the CMOS transistor is a diode- connected transistor.

[0041] In an embodiment of the semiconductor circuit, the circuit is part of an analog circuit.

[0042] In an embodiment of the semiconductor circuit the CMOS transistor is part of a switch, in particular a switch selected from a NMOS switch, a PMOS switch, a passgate, and a combination thereof.

[0043] In an embodiment of the semiconductor circuit, the forward body biasing voltage is supplied via a digital-to-analog converter (DAC), in particular the DAC comprising a resistive DAC, in particular a series of forward body biasing voltages are supplied via the digital-to-analog converter (DAC), in particular the DAC comprising the resistive DAC.

[0044] In an embodiment of the semiconductor circuit it is part of an inverter amplifier, in particular a floating inverter amplifier (FIA).

[0045] In an embodiment of the semiconductor circuit it is part of the floating inverter amplifier (FIA) adapted for driving an Analog-to-Digital converter (ADC) and used to sample the input voltage for further digitization by the ADC.

[0046] In an embodiment of the semiconductor circuit the ADC is a time-interleaved ADC and the circuit is adapted to switch between each slice of the ADC by switching cascode transistors. In an embodiment of the semiconductor circuit the drain and sources of the cascode transistors are shielded with metal shields above the cascode gates to minimize the crosstalk between different ADC slices.

[0047] In an embodiment of the semiconductor circuit the ADC is a SAR ADC, in particular a time-interleaved SAR ADC.

[0048] In an embodiment of the semiconductor circuit the circuit is part of a Dynamic ADC driver adapted for operating at a low temperature, in particular at a cryogenic temperature.

[0049] In an embodiment of the semiconductor circuit at least part of the CMOS transistors are PMOS transistors, and wherein the bulk terminals of at least part of the PMOS transistors are connected to the ground terminal.

[0050] In an embodiment of the semiconductor circuit at least part of the CMOS transistors are NMOS transistors, and wherein the bulk terminal of at least part of the NMOS transistors are connected to the supply (Vdd).

[0051] In an embodiment of the semiconductor circuit at least part of the CMOS transistors are NMOS transistors, and wherein at least part of the NMOS transistors of the circuit comprises a said low-temperature drive mode, and wherein each low temperature drive mode is functionally coupled to a driver for setting an individual forward bulk bias voltage for the respective NMOS transistors.

[0052] In an embodiment of the semiconductor circuit it comprises a PMOS or NMOS differential transistor pair in which the forward bulk bias is applied to the differential pair to trim out the differential transistor pair offset.

[0053] In an embodiment of the semiconductor circuit it comprises a series of said CMOS transistors wherein at least part of said CMOS transistors are functionally equally sized and provided in an array of said equally-sized CMOS transistors with the bulk terminals of substantially all CMOS transistors in said array comprising said low temperature drive mode for applying a forward bulk bias voltages selected to minimize a mismatch in output current of the substantially all CMOS transistors in said array, in particular the array forming part of a DAC selected from a current DAC, a capacitive DAC, and a combination thereof. In the capacitive DAC, an array of transistors is provided to implement a capactive DAC by using their gate capacitance.

[0054] There is further provided a quantum computing device comprising one or more of the current CMOS transistors. In an embodiment, the quantum computing device comprises a wide-band analogue to digital converter (ADC) comprising an ADC driver, comprising at least one of the current CMOS transistors.

[0055] The terms “upstream” and “downstream” relate to an arrangement of items or features relative to the propagation of a signal, wherein relative to a first position within a path of a signal, a second position in the path of the signal beam of light closer to the source of the signal is “upstream”, and a third position within the path of the signal further away from the source of the signal is “downstream”.

[0056] The term “substantially” herein, such as in “substantially all emission” or in “substantially consists”, will be understood by the person skilled in the art. The term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Hence, in embodiments the adjective substantially may also be removed. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, even more especially 99.5% or higher, including 100%. The term “comprise” includes also embodiments wherein the term “comprises” means “consists of’.

[0057] The term "functionally" will be understood by, and be clear to, a person skilled in the art. The term “substantially” as well as “functionally” may also include embodiments with “entirely”, “completely”, “all”, etc. Hence, in embodiments the adjective functionally may also be removed. When used, for instance in “functionally parallel”, a skilled person will understand that the adjective “functionally” includes the term substantially as explained above. Functionally in particular is to be understood to include a configuration of features that allows these features to function as if the adjective “functionally” was not present. The term “functionally” is intended to cover variations in the feature to which it refers, and which variations are such that in the functional use of the feature, possibly in combination with other features it relates to in the invention, that combination of features is able to operate or function. For instance, if an antenna is functionally coupled or functionally connected to a communication device, received electromagnetic signals that are receives by the antenna can be used by the communication device. The word “functionally” as for instance used in “functionally parallel” is used to cover exactly parallel, but also the embodiments that are covered by the word “substantially” explained above. For instance, “functionally parallel” relates to embodiments that in operation function as if the parts are for instance parallel. This covers embodiments for which it is clear to a skilled person that it operates within its intended field of use as if it were parallel.

[0058] Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

[0059] The devices or apparatus herein are amongst others described during operation. As will be clear to the person skilled in the art, the invention is not limited to methods of operation or devices in operation.

[0060] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "to comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device or apparatus claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0061] The invention further applies to an apparatus or device comprising one or more of the characterising features described in the description and / or shown in the attached drawings. The invention further pertains to a method or process comprising one or more of the characterising features described in the description and / or shown in the attached drawings.

[0062] The various aspects discussed in this patent can be combined in order to provide additional advantages. Furthermore, some of the features can form the basis for one or more divisional applications. Brief description of the drawings

[0063] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

[0064] Figure 1 shows DC Id / Vg measurements of both an NMOS and PMOS LVT 2pm / 40 nm device at Vds = 1.1 V transistor, where indicated lines shows 300K, other indicated lines are at 4.2K, The line Vbb=0 is without back-biasing and other indicated line has Vbb = 1.1 V. The lines in between have back-biasing voltages that increases in steps of 0.1 V;

[0065] Figure 2 shows the resistances of an SVT (left) and LVT (right) pass-gate, with the indicated lines shows 300K, the other indicated lines are at 4.2K, The line indicated Vbb=0 is without back-biasing and the other indicated line has Vbb = 1.1 V, and the lines in between have back-biasing voltages that increases in steps of 0.1 V;

[0066] Figure 3 shows a sketch of NMOS in DNW with resistances and diodes considered here, in the 40 nm bulk process adopted here;

[0067] Figure 4 shows a proposal for an inverter-based amplifier, where the core differential amplifier uses the same set of amplifying inverters (M1-M4) for driving two ADC slices;

[0068] Figure 5 illustrates the inverter transconductance (gm= gm,N + gm,p, with gm,N / p the transconductance of the individual transistors) derived from measured Id (Vd=550 mV) of individual devices, showing a) Transconductance (gm) of an inverter amplifier and of its individual PMOS and NMOS. The data is derived from measured Id of individual NMOS / PMOS with L=100 nm, W=1.2 / 2.4 pm and 6 fingers, and b) Transconductance of an inverter based differential pair;

[0069] Figure 6 (Left) Threshold voltage at 4.2K and 300K of both an NMOS and PMOS LVT 2pm / 40 nm device at Vds = 50 mV when applying forward back biasing, the dashed line indicates the 300 K threshold without forward back biasing, and (Right) the extracted body factor;

[0070] Figure 7 measurement results of a standard drive-1 LVT inverter ring oscillator, with frequency measurements in figure 7a, and figure 7b showing both the dynamic and static power consumed by the ring oscillators, and in figure 7c and 7d the increased power which also increases the EPT, with all data for a ring oscillator consisting of 1025 drive 1 LVT inverters, indicated lines show 300K, the other lines are at 4.2K, lines indicated no bb are without forward back biasing, and the lines / w bb are with forward back biasing to the opposite supply. The lines in between have back- biasing voltages that increases in steps of 0.1 V;

[0071] Figure 8 a) Pass-gate, b) RT Monte Carlo simulation of pass-gate resistance at VCM = 550 mV, 104 samples, cryogenic behavior only modeled by Vth increase.;

[0072] Figure 9 Inverter-amplifier a) DC-coupled, b) AC-coupled, c) DC-coupled with forward body bias voltage;

[0073] Figure 10 Acquisition front-end block diagram with a ADC core with its two time-interleaved slices and a driving FIA;

[0074] Figure 11 shows a timing diagram with interleaving of the shared inverters is implemented by a separate set of cascodes (M5 / 6,A / B-M7 / 8,A / B) and pass-gate reset switches (SW+ / -,A / B) for each of the two slices (A, B) of figure 4;

[0075] Figure 12 shows a cascode layout a) standard, b) proposed layout with improved isolation by increasing the diffusion contact-to-gate distance of the cascode transistors to allow for metal shielding above the gate;

[0076] Figure 13 shows a well layout in the amplifier to identify possible sources of leakage;

[0077] Figure 14 shows an example of a DAC which is used to generate forward bodybias voltages, uses a simple resistive ladder between ground and Vdd, which is tapped by a set of switches addressed by binary decoders;

[0078] Figure 15 illustrated how the master pulse generator can shared between both slices to avoid the additional calibration necessary to generate the control pulses via separate blocks, with a) Master pulse generator b) RT simulation of pulse-width control;

[0079] Figure 16 (a) Drawing of the cross-section of a back-biased inverter in a triplewell process, the well-to-well diodes are drawn open, whilst the drain- / source-to-well diodes are drawn solid, and (b) a schematic representation of the same inverter, and (c) the magnitude of the NMOS bulk current of all 289 ring oscillators together with the colors both magnitude and sign, and (d) The magnitude of the PMOS bulk currents of all 289 ring oscillators together, the colors both magnitude and sign.

[0080] The drawings are not necessarily on scale.

[0081] Description of preferred embodiments The threshold voltage (Vth) of a MOS transistor is a fundamental device parameter that has a crucial impact on the electrical performance of the device. It approximately indicates the gate-source voltage (VGS) to be applied to an NMOS transistor beyond which the transistor conducts a significant drain-source current (figure 1). Figure 1 is a set of graphs with DC Id / Vg measurements of both an NMOS and PMOS LVT 2 um / 40 nm device at Vds = 1.1 V. Indicated lines show 300K, the other lines are at 4.2K. The lines with Vb=0.0 are without back-biasing and the line with Vbb = 1.1 V has forward back biasing. Note that the nominal supply voltage of the CMOS process in this example is Vdd=l.l V. The lines in between have back- biasing voltages that increases in steps of 0.1 V. Furthermore, note that in this respect SVT and LVT stand for two different flavours, standard threshold voltage and low threshold voltage.

[0082] The graphs illustrate the effect of applying a forward bulk bias or FBB at cryogenic temperature, showing that, although there is an inherent in crease of the threshold voltage at cryogenic temperature, FBB allows to reduce the threshold voltage back to its value at room temperature (for intermediate FBB voltage values) and even below its room-temperature value when extending FBB up to the process nominal supply voltage.

[0083] Similarly, for a PMOS, the threshold voltage indicates the gate-source voltage (VGS) to be applied to the PMOS transistor below which the transistor conducts a significant drain-source current. In the following, we always refer to the NMOS transistor to ease the explanation, but all can be applied dually to a PMOS. In several circuits, the VGS must be significantly larger than Vth to turn the transistor on. However, the maximum VGS that can be applied may be limited by the combination of specific voltages applied to the terminal of the transistor, e.g., at its source, and the maximum voltage available in the circuit, typically the supply voltage.

[0084] When cooling down a MOS transistor to very low temperature, its threshold voltage considerably increases, typically by 100-200 mV for modern nanometre CMOS technologies when operating below 100 K, as shown in figure 1 and figure 6 (below). The increase in Vth combined with a maximum available voltage in a given circuit or technology (which limits the maximum gate voltage VG) limits the maximum achievable overdrive voltage Vos-Vth. For instance, a pass-gate circuit (figure 2) is often used to implement a low-impedance switch and, at room temperature, is typically able to operate for any voltage between the supply rail, as shown in figure 2. In figure 2, two graphs are plotted, showing the resistances of an SVT (left) and LVT (right) pass-gate. Indicated lines shows 300K (i.e. room temperature or RT), the other lines are at 4.2K. The line Vbb=0.0 is without back-biasing and the line with Vbb = 1.1 V is with forward back biasing. The lines in between have back-biasing voltages that increases in steps of 0.1 V. However, when the threshold voltage of the PMOS or NMOS increases, for instance because of cryogenic operation, the pass-gate may show excessive resistance for mid-rail voltages (figure 2), because of the limited conductance of both NMOS and PMOS for mid-supply voltages due to the low |VGS- Vth|.

[0085] Figure 3 depicts a schematic representation of the wells in a typical bulk CMOS process, indicating the parasitic diodes and parasitic resistors present in a device. These elements are used as equivalent circuit components indicating specific physical effects and are used for theoretical calculation purposes only.

[0086] Figure 4 shows an inverter-based amplifier with cascode sampling and a floating supply driving a 2x interleaved ADC. In this other example, the inverter-based amplifier shown in figure 4 can easily operate at room temperature, (figure 5a) but may fail to operate for increased threshold voltages (figure 5a), due to the low overdrive voltages since:

[0087] In particular, Figure 5 illustrates a) Measured gm, as well as sum of gm without shift and with shift for NMOS and PMOS as well as b) differential transconductance of a pair of inverters, showing recovery of the linear region with shifted Vth. A solution would be to break the supply constraint by independently AC coupling the amplifier input voltage to the NMOS and PMOS gate and independently choosing the gate bias voltage for each transistor. However, this would put a lower limit to the transistor bandwidth, require additional bulky passive components for the biasing, and add additional parasitics at the input that may limit the amplifier performance.

[0088] To counteract the threshold voltage increase, the use of FD-SOI CMOS processes has been proposed where the availability of a back-gate connection enables to electrically tune the threshold voltage. However, in order to counteract a significant increase in the threshold voltage, such as the one happening for cryogenic operation, the back-gate voltage in typical FD-SOI processes can be as high as a few Volt, even exceeding the nominal supply of the process. This is due to the low body effect coefficient C, (with a typical value in FD-SOI of 0.085 V / V):

[0089] The low effect of the back-gate voltage on the threshold voltage of an FD-SOI MOS is due to the relatively low capacitance between the back-gate terminal and the MOS channel.

[0090] The need for a very large voltage either requires complex circuits to generate such voltages, or requires that such voltages are provided externally to the chip. As externally providing a large number of back-gate biasing voltages is unpractical due to the large number of I / O interconnects, typically a single back-gate voltage is provided for all the NMOS in the circuit (and one for the PMOS). This prevents individually tuning the threshold voltage of each device in the circuit.

[0091] However, the problem of the increased threshold voltage persists for non-FD- SOI CMOS technologies, such as bulk CMOS. In bulk CMOS, body biasing can be used to tune the threshold voltage. For instance, by increasing the potential of the bulk node with respect to the source potential (forward body biasing, FBB), the threshold can be decreased. However, the maximum Vssthat can be practically applied is limited by turning on of the body-source (BS) PN diode, as shown in figure 3. When the BS diode turns on, a significant leakage current appears, strongly impacting the circuit functionality.

[0092] Forward body biasing (FBB) can be applied at cryogenic temperature by extending the available body-biasing range. This is allowed by the fact that the BS PN diode requires a much higher turn-on voltage at cryogenic temperature than at room temperature. Typically, the BS diode starts conducting at approximately 0.7 V at room temperature while it starts conducting only above approximately 1 V at temperatures below 100 K. Combined with the typically large (-0.25) body effect coefficient in bulk CMOS, a significant reduction of the threshold voltage can be achieved while still using body voltages well within the circuit nominal supply, e.g., as shown in figure 6. This allows to easily tune the threshold voltage of each transistor in a circuit, eventually generating the body bias voltages in the circuit itself. In the following, we will discuss the application of this technique to a number of circuits.

[0093] Switches

[0094] Cryogenic-aware FBB can be successfully applied to MOS switches. These can be individual NMOS or PMOS transistors, but also pass-gates, for which it solves the pass-gate cryogenic limitations. The problem arises due to the steeper subthreshold slope and higher threshold voltage. These result in an increase in resistance of several orders of magnitude for switching voltages around mid-rail, which makes those switches not usable at cryogenic temperatures. The back-biasing reduces the threshold enough to pull the resistance back down.

[0095] Some experimental demonstrations are shown in figure 2, references above. It is clear that with the use of back-biasing, for different flavours of the devices including both standard-threshold-voltage (SVT) ad low-threshold-voltage (LVT) devices, the resistance can be brought back to levels similar to 300 K. This means that with the help of back-biasing, pass-gates are viable again. The figure also shows that the curves at 4.2 K are shifted to the right compared to 300K. This confirms that the NMOS threshold is less affected by cooling down than that of the PMOS.

[0096] Digital Circuits

[0097] Digital circuits can also greatly benefit from cryogenic-aware FBB, as demonstrated in the following by analysing the behaviour of 40-nm-CMOS ring oscillators, as an example of a typical digital circuit.

[0098] A big advantage of cryogenic operation is the reduction in leakage power, due to the steep subthreshold slope. By combining this with cryogenic-aware FBB, this gives an opportunity to reduce the dynamic power, by reducing both the threshold and supply voltage, without significant increases in leakage. As the threshold voltage increases at cryogenic temperatures, lowering this using back-biasing is crucial.

[0099] A second improvement at cryogenic temperature is the speed-up compared to room temperature, caused by the increase in mobility. Experimental work shows that more mature technologies are not limited by the threshold and thus achieve >1.6x speed-up when cooled down. We expect that shifting the threshold down will allow the same speed-up in threshold-limited technologies, such as modern nanometre CMOS technologies. Figure 6 shows two graphs, with the left plot showing a threshold voltage at 4.2K and 300K of both an NMOS and PMOS LVT transistors with 2pm width and 40 nm length at Vds = 50 mV when applying back-biasing. The dashed line indicates the 300 K threshold without back-biasing. (Right) The body effect coefficient C, factor extracted from the data in the left plot.

[0100] To see if the expectations hold, the measurement results of a standard drive- 1 LVT inverter ring oscillator are presented in figure 7. Indicated lines shows back- biasing to the opposite supply (Vbn = Vdd, Vbp = Vss). However, it is important to note that in those plots the supply is now being swept to study the performance of the digital circuit as a function of the supply voltage in order to find the best region of operation for a given application, as typically done in digital circuits

[0101] Figure 7 shows data of the frequency (a), total, static and dynamic power (b), energy per transition (c), and energy delay product (d). All data is for a ring oscillator consisting of 1025 drive 1 LVT inverters. The indicated lines shows 300K, the other lines are at 4.2K. Other indicated lines with “no bb” are without back-biasing and the lines “ / w bb”with back-bias to the opposite supply. The lines in between have back- biasing voltages that increases in steps of 0.1 V.

[0102] The frequency measurements in figure 7a show a speed-up of 1.16x when cooling down, which increases to 1.87x when applying back-biasing. This aligns with the expectations based on the increase of mobility and changes in threshold voltage with and without FBB. What is also clear from this plot is that the steeper subthreshold slope increases the minimum supply voltage at which the oscillators still work.

[0103] Figure 7b shows both the dynamic and static power consumed by the ring oscillators. There are two interesting findings here: First, the large reduction in static power, which increase significantly with back-biasing; second, the increase in power consumption of the fully back-biased line above Vdd = 0.8V. As the increased power also increases Energy-per-Transition (EPT) and Energy-Delay-Product (EDP) in figure 7c and 7d, it does not cause a speed-up and is likely caused by an increase in the short circuit current.

[0104] Next, figure 7c shows that the EPT does not benefit from back-biasing. Without the short circuit current, it is limited by CV2. Back-biasing increases the frequency, causing the lowest EDP in figure 7d to lower from 10.1 fl ps without back-biasing to 7.7 fl ps with back-biasing. This is similar to what can be achieved in 28-nm FD-SOI, but in that case only with back-bias voltages exceeding 4 V.

[0105] Another interesting thing to note in figure 7d is the difference in back-biasing above and below Vaa = 0.9V. Above 0.9 V, back-biasing increases the EDP. However, below 0.9 V, back-biasing lowers the EDP. This is mainly attributed to the optimal Vaa point shifting to lower Vaa for increasing back-bias.

[0106] Thus, for low-power digital design, we propose to lower the supply and apply full back-biasing to the opposite supply. Compared to nominal cryogenic operation, this gives an EPT reduction of 4.24x and an EDP reduction of 2.33x, while only reducing the speed by 5.6x. The largest gain is for high-performance designs, where an increase in frequency of 1.62x is obtained with an EDP comparable to RT.

[0107] Inverter-based amplifiers

[0108] The inverter amplifier, see figure 4, is a core building block of many efficient amplifier architectures, thanks to its power efficiency obtained by current reuse and the beneficial scaling with technology. At RT, this amplifier is also moderately linear when biased mid-rail and used in a differential configuration. This is illustrated in figure 5, where we show the inverter transconductance (gm=gm,N+gm,p, with gm,N / p the transconductance of the individual transistors) derived from measured Id (at constant mid-supply drain voltage) of individual devices. A smooth transition with little curvature can be observed at the mid-rail point. This breaks down at cryogenic temperatures, where due to the increased threshold voltage, a significant dip in the transconductance (gm) is observed. To avoid this dip and recover linear behaviour, the 4.2K characteristic needs to be shifted by 100 / 140mV for NMOS / PMOS, see figure 5. We can observe similar linearity if comparing a differential amplifier constructed from the gm characteristic at RT and the shifted characteristic at cryogenic temperatures.

[0109] For implementing this shift, we could use a bias-T, i.e., a device with 2 inputs and one output, to apply bias voltages V b,i / 2 at the gate of the NMOS and the PMOS transistors. One input lets only low frequency components pass through, the other input only the high frequency component. In this case, it would be used to apply the gate bias voltage via the low-frequency input and the signal via the high-frequency input, so that bias can be set independent of the input signal, and also different for each transistor (using 2 bias-T). However the amplifier bandwidth would be reduced around DC by the bias-T high-pass characteristic and the signal would suffer attenuation due to the parasitic behaviour of the passive network. Alternatively, FBB can shift the transfer characteristics by shifting Vth without significantly altering the transistor characteristics. This allows recovering the linearity without introducing any additional components into the signal path and / or limiting the input bandwidth.

[0110] The design can use back-biasing for all core transistors to enhance operation at cryogenic temperatures. Most importantly, the input transistors M1-M4 need to be back-biased at cryogenic temperatures if using DC coupling, as discussed above. By biasing the body of the input transistors separately (Vbb,n+ / - and Vbb,p+ / -), we also allow for input offset cancellation. To get a reliable pass-gate operation, the complementary transistors in SW+ / .,A / B need to be back-biased, as discussed above. And finally, back- bias can be also applied to the cascode transistors M5,A / B-S,A / B for additional swing, avoiding the cascode transistors driving the input towards triode. In RT simulation, we were able to adjust for a 120mV increase in Vth and recover the target driver linearity of >50dB.

[0111] Other circuits

[0112] Cryogenic-aware FBB can be applied in several more circuits. Some examples are listed below:

[0113] • FBB can be individually applied to the devices in a differential pair to reduce its offset. The large compensation range offered by cryogenic-aware FBB can be used to compensate for any practical offset.

[0114] • Similar to the previous point, cryogenic-aware back-biasing can be used to compensate the mismatch of transistors, e.g., in circuits like so called “current mirrors”, and / or in so called “data converters”.

[0115] • Transistors in diode connection, e.g., as the one used as active loads in amplifiers: A full Vth+Vod needs to be applied for a diode-connected transistor. A PMOS diode in a typical 40-nm process with Vod=200 mV uses 700 mV of voltage headroom, leaving little space for other circuitry or signal swing for a 1.1-V supply. With FBB, regular stacking like a RT is possible in amplifiers at cryogenic temperature. An example for this is a mirror load in an amplifier, where, for instance, FBB enables cascodes to fit into a nominal supply voltage. In the following, a circuit and some components are presented.

[0116] A floating inverter amplifier (FIA) can perform high-linearity amplification and sampling while driving a 2 / time-interleaved (TI) SAR ADC operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuoustime input signal by windowed integration, thus avoiding the traditional sample-and- hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behaviour of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analysed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR=38.7 dB (38.2 dB), SFDR>50 dB (>50 dB), and FOMW=25.4 fl / conv-step (31.3 fl / conv-step) with Nyquist-rate input at 1.0 GS / s (0.9 GS / s) at 4.2 K (RT), respectively.

[0117] Quantum computers promise significant speed advantages for many applications that are excessively demanding for classical computers. To achieve such a speed-up, the number of quantum bits (qubits) used to store quantum information in such machines must scale up by orders of magnitude from the currently available 100s. However, due to the fragile nature of the qubits, the most promising quantum computing platforms must operate at cryogenic temperatures <4.2 K, posing significant challenges to the realization of largescale quantum computers. Crucial to obtain this goal is an electronic interface for the quantum processor located close to the cryogenic quantum substrate, or even on the same chip, hence, also operating at cryogenic temperatures. Out of the many candidates, here we target semiconductor spin-based quantum computers due to their inherent compatibility with CMOS fabrication and good scaling properties.

[0118] In particular for the compact cryogenic readout of spin qubits, a cryogenic wideband ADC is required to digitize the frequency multiplexed channels in a reflectometry readout scheme. The power dissipation of such circuitry is strictly constrained by the limited cooling power available in deep-cryogenic environments. Prior works only focused on the power efficiency of the ADC itself, while either neglecting the ADC driver or just using traditional power-hungry settling drivers. This is a substantial shortcoming as these settling drivers can require a power budget even larger than the ADC itself.

[0119] The presented driver and ADC combination achieves high linearity with more than 50 dB SFDR and also a competitive F0MW=31.3 / 25.4 fl / conv-step with Nyquist-rate input at 0.9 / 1.0 GS / s at RT / 4.2 K. These advances are enabled, in addition to the cryogenic-aware FBB, by the use of cascode switching, the adoption of a floating supply, and the use of accurate pulse-width timing calibration.

[0120] VBB is the voltage applied via the body contact, i.e the forward body bias voltage as in Fig. 3. In the 40 nm bulk process adopted here, C, varies between ~ 0.1 to ~ 0.35 at 4.2 K when the body-bias is swept from 0 to 1.1 V with an average of ~ 0.25 V / V, which is higher than in common FDSOI technologies with, for example, 0.085 V / V. The body contact has been used at RT both as a tuning knob for mitigating mismatch, or as additional input. For 40-nm CMOS, a 5 pm><0.2 pm P+ / Nwell diode conducts ~1 nA when forward biased with the full nominal supply voltage (1.1 V) at 4.2 K, more than 5 orders of magnitude less than at RT. For more sensitive applications, the diode leakage can be decreased by applying a lower FBB, since the leakage decreases by ~ 10x for a 100 mV decrease in VBB. With a full FBB VBB - VS =Vdd=l.l V, the threshold voltage can be shifted by >200 mV in the adopted technology. Combined with the available threshold flavors, this offers a wide range of viable threshold values.

[0121] Two examples of circuits enabled by cryogenic-aware FBB and their limitations are analysed below. For the analysis, we use data measured at RT and 4.2 K from a characterization chip. Both circuits will be used in the driver illustrated below.

[0122] A pass gate (Fig. 8a) can be easily designed to switch midrail voltages at room temperature, as shown by the limited spread in the Monte Carlo (MC) simulation of its mid-rail (550 mV) on-resistance (Fig. 8b), considering the Vth increase of 110 / 180 mV in NMOS / PMOS measured at cryogenic temperatures in triode for 40 nm devices. Applying FBB can bring the Vth back to its RT value, or even below, thus reducing the on-resistance. At mid-rail, the switch will also benefit from the generally increased mobility at cryogenic temperatures, allowing for smaller sizing than possible at RT. Although the increase in subthreshold leakage associated with a lower threshold may be a concern, this effect is contained by the steeper subthreshold slope at cryogenic temperature, increasing by about 3x. This allows to reduce the transistor threshold voltage even below RT values without deteriorating leakage performance.

[0123] The inverter amplifier, see Fig. 9a), is a core building block of many efficient amplifier architectures, thanks to its power efficiency obtained by current reuse and the beneficial scaling with technology. At RT, this amplifier is also moderately linear when biased at mid-rail and used in a differential configuration. This is illustrated in Fig. 5, where we show the inverter transconductance (gm= gm,N + gm,p, with gm,N / p the transconductance of the individual transistors) derived from measured Id (Vd=550 mV) of individual devices. A sizeable linear region can be observed in the transconductance of an inverter-based pseudo-differential pair Fig. 5b) at the mid-rail point. This breaks down at cryogenic temperatures, where, due to the increased threshold voltage, a significant dip in the gm is observed, corresponding to a limited linearity. To avoid this dip and recover the linear behaviour, the 4.2 K characteristic needs to be shifted by 100 / 140 mV for NMOS / PMOS, see Fig. 5. We can now observe similar linearity if comparing the transconductance of the differential pair in Fig. 5b).

[0124] For implementing this shift, a bias-T as shown in Fig. 9b can be used and applying bias voltages vb,i / 2, but the amplifier bandwidth would be reduced around DC by the bias-T high-pass characteristic and the signal would suffer attenuation due to the parasitic behaviour of the passive network. FBB can shift the transfer characteristics by shifting Vth without significantly altering the transistor characteristics. This allows recovering the linearity without introducing any additional components into the signal path and / or limiting the input bandwidth.

[0125] Applying FBB via the bulk contact may be potentially limited by the high substrate resistance at cryogenic temperature, as indicated by typical N-well resistances up to a few GQ / n at 4.2 K. If such large bulk resistance (RB in Fig. 3) would be effectively present, the applied bias Vbb would only set the DC operating point, around which capacitively coupled excitations could alter the bulk potential, causing unexpected effects. For instance, the capacitive coupling via the drain-bulk diode (DD) could lower the output resistance due to modulation of the bulk potential. If floating the bulk terminal, the size of this effect is about 8% in RT simulation. The influence of the gate in this context is largely reduced due to shielding by the channel. To mitigate the effects of the unknown substrate resistance, substrate contacts can be placed near the active devices. In the current design, a distance in the order of 1 pm was chosen.

[0126] The application of body-bias is restricted by the available process. It is for instance applicable to planar bulk technologies with a triple-well option.

[0127] If circuits employing FBB must operate both at RT and cryogenic temperatures, measures must be taken to ensure correct operation, especially when using high FBB values. For instance, to avoid excessive diode leakage at RT, the body potential must be switched depending on the operating temperature, or DACs adjusting the body-bias are required. This is not an issue in the target application in quantum-computer interfaces, which always operate at cryogenic temperatures. If using a triple-well layout for minimizing leakage paths when employing FBB, additional area might be necessary due to the design rules of such processes. Especially the distance of a deep- N-well (DNW) to an N-well (NW) of different potential typically carries a significant distance requirement. The additional area also may cause increased parasitic capacitance due to necessary routing between now spaced transistors, which may be critical for parasitic-sensitive scenarios like the input of a latching comparator. To avoid this space constraint, the PMOS can be placed in the DNW surrounding the NMOS P-well (PW). While reducing the required extra area to a minimum, this leads to some additional leakage via the P-well / N-well diode if the PMOS transistors inside the DNW are also using FBB. Additionally, this would also imply using the same body-bias for all PMOS transistors sharing the DNW.

[0128] The acquisition front-end in Fig. 10 comprises the ADC core with its two time- interleaved slices and the driving FIA. The front-end operates in three phases on each slice in alternation, see Fig. 11 : First, during TR, the slice is reset and its input settled to VCM. Second, during TS, the differential input signal Vin is amplified via windowed integration on the top-plate of the ADC sampling capacitor, VA / B,+ / -. Finally, during Tconv, the amplified signal is converted by the slice to the output word. The slices are 7-bit loop-unrolled SAR ADCs with foreground calibration for the comparator offset. The slices’ design changed in the timing circuitry necessary to integrate the amplifier and a slightly increased capacitive DAC (CDAC) to retain the input voltage range of 600 mVpp,d after adding the amplifier parasitics. In an optional bypass-mode, the FIA is disabled and the input is directly sampled on the DAC topplates by clock-boosted sampling transistors. Our target front-end specification required >50dB SFDR, >38dB SNDR when operating at a conversion rate of >lGS / s. As the ADC slices meet these specifications, the following sections focus on the driver design.

[0129] The core differential amplifier, see Fig. 4, uses the same set of amplifying inverters (M1-M4) for driving both ADC slices.

[0130] The inverters are designed to deliver an output current signal for windowed integration, M1-M4 are chosen with a length of 100 nm to increase the intrinsic gain of the amplifying transistors, approximating an integrating behavior.

[0131] Interleaving of the shared inverters is implemented by a separate set of cascodes (M5 / 6,A / B-M7 / 8,A / B) and pass-gate reset switches (SW+ / -,A / B) for each of the two slices (A, B). First, during TR, see Fig. 11, SW+ / -,A / B, controlled by RA / B, reset the output of the amplifier to VCM. In case of a metastability event causing the previous ADC slice conversion time (Tconv) to extend up to TR, the data out bits are latched in their incomplete state and the CD AC undergoes a forced reset to avoid propagating the error. Then, during TS, the cascodes connecting to the target slice are turned on using the SA / B signal and the input signal is integrated on the cap-DAC topplate. This windowed-integration operation during TS dictates the circuit transfer function, which can be approximated as:

[0132] |H(f)| = gm.TS.CDAC.sinc(7tTSf) (2) where gm is the differential-inverter transconductance, and CDAC is the load capacitance of the inverter-based amplifier. In addition to the limited intrinsic gain of the devices, deviations from this “sinc”-shape are caused by the stray capacitance at the drain of the input transistors. The duration of RA / B and SA / B can be configured in the timing generator. SA / B is shorter than 400 ps, leading to an output attenuation below 7% for a 0.5 GHz input compared to the DC gain. At the end of TS, the slice conversion Tconv and supply reset supply-R are triggered. During supply-R, the amplifier’s floating supply capacitor Csupply is reset via M9 / M10 to ground / Vdd, respectively. The process continues at the next clock edge with a reset on the other slice. The choice of a floating supply allows for the stable definition of the output common mode without using a power hungry full-rate common-mode feedback circuit. Since Csupply is disconnected from the ground / Vdd supply during TS, it acts as a floating battery-like supply. As the current is now sourced from this floating supply, the amplifier has (ideally) no common-mode drive capability, and can therefore not alter the output common mode that was reset to VCM during TR. VCM is nominally 550 mV, and amplifier performance is stable over a ±25 mV window in RT simulation. In practice, the amplifier is not fully floating due to the parasitic capacitance of Csupply and the core transistors towards the AC ground. The amplifiers commonmode specifications are especially important for the loop-unrolled ADC driven here, as the architecture has poor common-mode rejection caused by the common-mode dependence of the comparator offset. Also the floating supply reduces the common mode gain to 0.5 in RT simulation for a small power overhead, while it would equal the differential gain without any common-mode control. With a full-scale differential output signal, the amplifier produces a 4 mV common-mode signal in extracted RT simulations, resulting in negligible comparator offset variation. This common mode signal is caused by second order distortion in the signal inputs, that is cancelled in the differential signal domain. The Csupply is designed to be large (1.3 pF), compared to the load cap (113 fF), largely avoiding the degenerative effect of the floating supply to enable a larger gain. We did not target the narrow high-linearity condition outlined. In favor of robustness, as the achieved linearity is sufficient for the application. The cascode-sampling scheme used here replaces an otherwise needed sampling switch at the output, while also providing a small boosting of the inverter output impedance. The limitation in boosting is caused by the cascodes’ operation close to triode due to the full-swing SA / B control signals. A downside of implementing interleaving with the cascodes is the introduced inter-slide feed-through via CDS during SA / B onto the topplate of slice B / A. This feed-through happens during the sensitive conversion phase Tconv,B / A. To address this, different strategies can be employed: to cancel the feed- through, an additional pair of cross-coupled always off transistors could be employed as done for the switches but at the cost of significant additional capacitive load and layout complexity. The coupling capacitance was minimized by spacing the source and drain contacts apart, thus minimizing the coupling capacitance. Here, we pursue a third approach for isolation, by increasing the diffusion contact-to-gate distance of the cascode transistors to allow for metal shielding above the gate, see Fig. 12. In addition to implementing the interleaving, resetting the floating supply is integrated with the cascodes by turning the cascodes off during supply-R. This removes the need for additional switches at the source of the input transistors M1-M4, which can cause additional source degeneration. The design uses back-biasing for all core transistors to enhance operation at cryogenic temperatures. Most importantly, the input transistors M1-M4 need to be back-biased at cryogenic temperatures if using DC coupling. By biasing the body of the input transistors separately (Vbb,n+ / - and Vbb,p+ / -), input offset can be cancelled. An offset of 1 LSB to avoid significant SNDR degradation, which dictates the body -bias DAC resolution can be applied. For an expected gain of 7, an LSB of ~5 mV at the ADC input, a body-bias factor C, = 0.25, and a total DAC range of 1.1 V we require approximately 8b resolution to cover the expected mismatch range when applying the body-bias to one of the four input transistors M1-M4. To get a reliable pass-gate operation, the complementary transistors in SW+ / -,A / B need to be back-biased. Finally, forward back bias can also be applied to the cascode transistors M5,A / B-8,A / B for additional swing, avoiding the cascode transistors driving the input pairs towards triode. According to RT simulation, we would be able to adjust for the expected increase in Vth and recover the target driver linearity of >50 dB. FBB can cause leakage by forward-biasing the device diodes. To identify possible sources of leakage, we show a sketch of the amplifiers’ well layout in Fig. 13. The problematic diodes in this context are formed by the source / drain diffusion of transistors (labelled DS / D in Fig. 13). All well-to-well diodes (DDNW,1, DDNW,2 and DNW) are usually not forward biased for FBB within the supply rails. Among the DS / D diodes, the worst-case for leakage is found at the source of the cascodes M5,A / B-M8,A / B when a full nominal supply is applied as FBB. During reset, M1-M4 are in triode and the supply is reset to the nominal ground / Vdd rails. Hence, the forward voltage for the source-bulk diodes of the cascode is a full Vdd. This leads to an estimated leakage of 58 nA from the PMOS cascode onto a node in reset, causing only additional power dissipation at a magnitude that currently are negligible. All other diodes carry less FBB, specifically the ones connecting to the ADC top-plate, and are therefore not expected to contribute measurable effects.

[0133] The body-bias DAC uses a simple resistive ladder between ground and Vdd, which is tapped by a set of switches addressed by binary decoders, see Fig. 14. The small-size pass-gates implementing these switches must be operational for switching mid-rail voltages at cryogenic temperatures. To ensure that, in this prototype chip the switches themselves are also back biased by externally supplied voltages Vbb,n / p,ext. In a future iteration, these voltages can be generated with a set of onchip resistors, as the necessary body-bias for guaranteeing full functionality (0.4 V for NMOS, 0.7 V for PMOS) are easily switchable by switches without body-bias. The DAC also allows for using the external voltages Vbb,n / p,ext instead of the resistive ladder, as well as read- back of the control voltages to detect abnormalities via Vdebug, connected to a pad.

[0134] The timing-generation block, see Fig. 10, produces all pulses shown in Fig. 11 from the full-rate input clock. The output of the pseudo-differential clock receiver is divided and aligned on the negative clock edge, while the master pulse is initiated at each positive edge. The entire timing calibration block, except the clock divider, is implemented with open-loop delays and combinational logic. This saves power compared to using the high-frequency clock required to produce all the phases and fine-grain adjustments necessary here. N an embodiment, a DLL-based alternative would improve the robustness but also at the cost of increased power consumption and design complexity. Special care was therefore taken to make the delay-based logic robust to PVT variations by only using relative delays and carefully matching driving capabilities of parallel paths, thus achieving reliable operation from RT to 4.2 K.

[0135] The master pulse generator (Fig. 15) is shared between both slices to avoid the additional calibration necessary to generate the control pulses via separate blocks. The produced pulses are multiplexed in the timing generator, see Fig. 10. Both TR and TS are ideally kept short to allow more conversion time for the ADC, and are adjustable from 120 ps to 400 ps. To generate this range, three functions are used: a full delay step (AT ) defined by the combined delays of two inverter delays and a pass-gate, a half step (AThaif) corresponding to two inverter delays, and a 5b binary weighed capacitor array for fine steps. While the main effect of adjusting TS is varying the amplifier gain, the duration of TS also affects the inherent filtering introduced by the windowed integration. As the windowed integration corresponds to a sine response, this could allow, for example, adjustment of the notch to reject a spurious out-of-band tone like mixer LO feed-through.

[0136] In a further embodiment, the following setup was used. A chip was designed in a 40-nm LP triple-well technology. The chip contains two back-biased structures to be characterized. One comprised of various individual transistors, the other containing 289 different ring-oscillators.

[0137] All transistors are here individually selectable on the gate, but tied together on the drain, source and bulk. Everything is measured using SMU channels. The drain and source nodes use a Kelvin connection to negate IR drop in the wires. The gates are selected using a thick-oxide switch driven by a thick-oxide shift register to avoid the pass-gate problem. To obtain the pass-gate resistance, the NMOS and PMOS smallsignal resistances are measured separately. This is done by applying VD = VCM + AV and VS = VCM - AV , for AV = 5m V and keeping the gate fully turned on. These can then be added in parallel to give the resulting pass-gate resistance.

[0138] The ring oscillators are used to investigate the effect of back-biasing on digital circuits. Each ring oscillator consists of 1025 inverters. To disable them, the loop can be opened using a thick-oxide switch. For the ring oscillators, the output frequency is measured with a spectrum analyzer, while simultaneously measuring the currents into the supplies and forward back-bias nodes using SMU channels. These are then used to obtain the energy per transition (EPT) and the energy delay product (EDP).

[0139] DC measurements are validated first on transistor level.

[0140] The Id / Vg curves of an NMOS and PMOS device are shown in figure 1. Both devices are LVT to lower the threshold, and have a W / L of 2pm / 40nm. The shown curves are extracted at Vds = 1.1 V, but the thresholds are extracted at Vds = 50 mV using the maximum gm method. As expected, in figure 6a, we can see a clear increase in threshold when cooling down, which can be more than cancelled by applying back- biasing. However, this is a lot better for NMOS than PMOS. This due to the PMOS having a larger Vth shift. The body-factor only depends on Vb and doping, but not on temperature and is thus roughly constant. Additionally in figure 1, we can see the steeper subthreshold slope that limits the leakage even at full forward back-bias and the larger maximum current at high Vgs caused by the higher mobility.

[0141] An embodiment is a pass-gate. A problem arises due to the steeper subthreshold slope and higher threshold voltage. These result in an increase in resistance of several orders of magnitude at mid-rail. The forward back biasing was found to reduce the threshold enough to pull the resistance back down. The measurement results are shown in figure 2, showing the resistances of an SVT (left) and LVT (right) pass-gate. It is clear that with the use of back-biasing, both for SVT and LVT devices the resistance can be brought back to levels similar to 300K. This means that with the use of back biasing, pass-gates are viable again. The figure also shows that the curves at 4.2K are shifted to the right compared to 300K. This again confirms that the NMOS threshold is less effected by cooling down than that of the PMOS. A further embodiment is a ring oscillators, as an indicator of cryogenic digital circuits. A big advantage here is the reduction in leakage power due to the steep subthreshold slope. This also gives us an opportunity to reduce the dynamic power, by reducing both the threshold and supply voltage, without significant increases in leakage. As our threshold voltage sadly increases at a cryogenic temperature range, back-biasing is crucial. A second improvement at cryogenic temperatures is the speedup compared to RT, caused by the increase in mobility. The work shows that shifting the threshold down will allow the same speed-up in threshold limited technologies, such as this one. To verify this, the measurement results of a standard drive 1 LVT inverter ring oscillator are presented in figure 7. The other indicate line again shows back-biasing to the opposite supply (Vbn = Vdd, Vbp = Vss). However, it is important to note that the supply is now being swept. The frequency measurements in figure 7a show a speed-up of 1.16* when cooling down, which increases to 1.87x when applying back-biasing. What is also clear from this plot is that the steeper subthreshold slope increases the minimum supply voltage at which the oscillators still work. Figure 7b shows both the dynamic and static power consumed by the ring oscillators. There are two interesting findings here. First, the large reduction in static power, that does increase significantly with back-biasing. Second, the increase in power consumption of the fully back-biased line above Vdd = 0.8 V. As it also shows as an increase of the EPT and EDP in figures 7c and 7d, it does not cause a speed-up and is likely caused by an increase in the short circuit current. Next, figure 7c shows that the EPT does not benefit from back-biasing. This makes sense as without short circuit current, it is limited by CV2. Forward back-biasing does however increase the frequency, causing the lowest EDP in figure 7d to lower from 10.1 fl ps without back-biasing to 7.7 fl ps with back-biasing. Interesting to note in figure 7d is the difference of forward back biasing above and below Vdd = 0.9 V. Above 0.9 V, forward back biasing increases the EDP. However, below 0.9 V, forward back-biasing lowers the EDP. This is mainly attributed to the optimal Vdd point shifting to lower Vdd for increasing forward back- bias. Thus for lower-power digital design we propose, lowering the supply (to 0.725 V) and apply full back-biasing to the opposite supply.

[0142] Compared to nominal (Vdd = 1.1 V) cryogenic operation this gives an EPT reduction of 4.24* and an EDP reduction of 2.33 x, whilst only reducing speed by 5.6*. The biggest gain though is for high-performance design where an increase in frequency of 1.62x is obtained with an EDP comparable to RT.

[0143] To verify the bulk diode leakage, the results in figure 16c and 16d show the bulk current measurements of all ring oscillators. A cross section of a back-biased inverter is shown in figure 16a, with a simplified schematic in figure 16b. Bulk leakage is clearly not a problem. Even at full supply and forward back bias, the bulk currents of 289 ring oscillators is 12.5 lower than the dynamic power of a single ring oscillator. At lower supplies it will be even less problematic, due to the exponential dependence on the bias-voltages. Next, we identify the solid black diodes as dominant. If the well- to-well diode between Vbn and Vbp were dominant, both leakage currents would be similar. However, dividing by the total widths, the leakage is 64.1 pA / pm for NMOS and 1.32 nA / pm for PMOS, a factor of roughly 20 times. Finally, it is interesting that the leakage changes sign for forward back-bias voltages around half supply and also seems to be dependent on the opposite forward back-bias voltage. This might point to an offset current, probably caused by the gate leakage of the following stage. Changing the threshold with forward back bias, will affect this gate current.

[0144] Forward back-biasing can be done in bulk CMOS to the opposite supplies, without causing excessive leakage. Doing so causes the threshold voltage to shift back more than it increases from cooling down and enough to re-enable the use of passgates. In ring oscillators it can be used to either increase speed 1.62x or reduce the EPT and EDP by 4.24x and 2.32x respectively. This technique is also interesting in analogue design, where the trade-off between speed and power and the re-enabling of pass-gates is just as valuable. But on top of that this technique re-enables certain topologies, for examples those using diode connected transistors. Finally, it might enhance some techniques such as a wider range of dynamic forward back biasing and threshold calibration.

[0145] It will also be clear that the above description and drawings are included to illustrate some embodiments of the invention, and not to limit the scope of protection. Starting from this disclosure, many more embodiments will be evident to a skilled person. These embodiments are within the scope of protection and the essence of this invention and are obvious combinations of prior art techniques and the disclosure of this patent.

Claims

Claims1. A method for operating at least one CMOS transistor at a cryogenic temperature, the at least one CMOS transistor produced using at least one process selected from a planar bulk CMOS process, a fin field effect transistor (FinFET) process, and a combination thereof, the method comprising setting the at least one CMOS transistor in a low-temperature drive mode comprising determining for the at least one CMOS transistor its threshold voltage as a function of its operating temperature range and for an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature in the operating temperature range for the at least one CMOS transistor, in particular a desired operating temperature below 218K, more in particular at a cryogenic temperature, determining a resulting forward bulk biasing (FBB) voltage, and applying the resulting forward bulk biasing voltage to the at least one CMOS transistor, wherein the forward bulk biasing (FBB) voltage is at least as much as the turn-on voltage of the bulk-source diode at room temperature, in particular at least 0.5 Volt.

2. The method of claim 1, wherein the forward bulk biasing (FBB) voltage is at least at least 0.6 Volt for a silicon diode.

3. The method of claim 1 or 2, wherein forward bulk biasing (FBB) voltage is applied to a substrate contact near the CMOS transistor, in particular at a distance of between 0.1-5 micron, more in particular a distance of 0.5-2 micron, specifically in the order of 1 micron.

4. The method of any one of the preceding claims, wherein the CMOS transistor is provided on a chip, and the forward bulk biasing (FBB) voltage is applied to the CMOS transistor via a driver from outside the chip, in particular said driver is provided at a low temperature in the order of the temperature of the CMOStransistor, in particular within 10K of the temperature of the CMOS transistor.

5. The method of any one of the preceding claims 1-3, wherein the CMOS transistor is provided on a chip, and the forward bulk biasing (FBB) voltage is applied to the CMOS transistor via a driver on the chip.

6. The method of any one of the preceding claims, wherein the CMOS transistor is embedded within a well with a doping type that is opposite to the doping type of its substrate, in particular the CMOS transistor sharing its well with at least one other transistor, in particular a PMOS transistor in an N-well and / or a NMOS transistor implemented in a P-well, more in particular wherein wells are separated via a deep- N-well.

7. The method of any one of the preceding claims, wherein the CMOS transistor is an PMOS transistor.

8. The method of any one of the preceding claims, wherein the CMOS transistor is part of an amplifier.

9. A CMOS transistor produced using at least one process selected from a planar bulk CMOS procedure, a fin field effect transistor (FinFET) procedure, and a combination thereof, said CMOS transistor comprising a low-temperature drive mode, in particular a drive mode at a low temperature below 218K, more in particular a cryogenic drive mode, said drive mode adapted for supplying a forward bulk bias (FBB) voltage to the CMOS transistor for setting a desired threshold voltage of CMOS transistor at de desired operating temperature below 218K, in particular at a cryogenic temperature, wherein the forward bulk biasing (FBB) voltage is at least as much as the turn-on voltage of the bulk-source diode at room temperature, in particular at least 0.5 Volt.

10. The CMOS transistor according to claim 9, further functionally coupled to a driver, the driver comprising a temperature input functionally coupled to the CMOS transistor and a set threshold voltage for the CMOS transistor, the driver adaptedfor calculating a forward bulk bias voltage as a function of the temperature input and the set threshold voltage, and for setting the calculated forward bulk bias voltage to the CMOS transistor.

11. The CMOS transistor of any one of claims 9-10, wherein said CMOS transistor is a diode-connected transistor.

12. A semiconductor circuit comprising a series of CMOS transistors according to any one of the preceding claims 9-11.

13. The semiconductor circuit of claim 12, wherein the circuit is part of an analog circuit.

14. The semiconductor circuit of claim 12, wherein the CMOS transistor is part of a switch, in particular a switch selected from a NMOS switch, a PMOS switch, a passgate, and a combination thereof.

15. The semiconductor circuit of claim 12, wherein the forward body biasing voltage is supplied via a digital-to-analog converter (DAC), in particular the DAC comprising a resistive DAC, in particular a series of forward body biasing voltages are supplied via the digital-to-analog converter (DAC), in particular the DAC comprising the resistive DAC.

16. The semiconductor circuit of claim 12, wherein the circuit is part of an inverter amplifier, in particular a floating inverter amplifier (FIA).

17. The semiconductor circuit of claim 16, wherein the circuit is part of the floating inverter amplifier (FIA) adapted for driving an Analog-to-Digital converter (ADC) and used to sample the input voltage for further digitization by the ADC.

18. The semiconductor circuit of claim 17, wherein the ADC is a time-interleaved ADC and the circuit is adapted to switch between each slice of the ADC byswitching cascode transistors.

19. The semiconductor circuit of claim 18, where the drain and sources of the cascode transistors are shielded with metal shields above the cascode gates to minimize the crosstalk between different ADC slices.

20. The semiconductor circuit of claim 18 or 19, wherein the ADC is a SAR ADC, in particular a time-interleaved SAR ADC.

21. The semiconductor circuit of claim 12, wherein the circuit is part of a Dynamic ADC driver adapted for operating at a low temperature, in particular a cryogenic temperature.

22. The semiconductor circuit of claim 12, wherein at least part of the CMOS transistors are PMOS transistors, and wherein the bulk terminals of at least part of the PMOS transistors are connected to the ground terminal.

23. The semiconductor circuit of claim 12, wherein at least part of the CMOS transistors are NMOS transistors, and wherein the bulk terminal of at least part of the NMOS transistors are connected to the supply (Vaa).

24. The semiconductor circuit of claim 12, wherein at least part of the CMOS transistors are NMOS transistors, and wherein at least part of the NMOS transistors of the circuit comprises a said low-temperature drive mode, and wherein each low temperature drive mode is functionally coupled to a driver for setting an individual forward bulk bias voltage for the respective NMOS transistors.

25. The semiconductor circuit of claim 12, comprising a PMOS or NMOS differential transistor pair in which the forward bulk bias is applied to the differential pair to trim out the differential transistor pair offset.

26. The semiconductor circuit of claim 12, comprising a series of said CMOS transistors wherein at least part of said CMOS transistors are functionally equallysized and provided in an array of said equally-sized CMOS transistors with the bulk terminals of substantially all CMOS transistors in said array comprising said low temperature drive mode for applying a forward bulk bias voltages selected to minimize a mismatch in output current of the substantially all CMOS transistors in said array, in particular the array forming part of a DAC selected from a current DAC, a capacitive DAC, and a combination thereof.

27. A quantum computing device comprising one or more CMOS transistors according to any one of the claims 12-26.

28. The quantum computing device of claim 27, comprising a wide-band analog-to- digital converter (ADC) comprising an ADC driver, comprising at least one of the CMOS transistors according to any one of the claims 12-26.

29. A computer program product which, when executed on a data processing device, preforms retrieving for said one or more CMOS transistor its threshold voltage as a function of an operating temperature range including a temperature in the cryogenic temperature range and of an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature for said CMOS transistor; calculating a resulting forward bulk biasing (FBB) voltage using the function, and providing as output the resulting forward bulk biasing voltage.-o-o-o-o-o-

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