Process for fabricating a strained layer

Abstract

The present description relates to a process for fabricating a strained metal or semiconductor or insulator layer comprising a step in which the metal or semiconductor or insulator layer (11) is transferred from a first carrier substrate (10) to a second carrier substrate (20), the carrier substrates (10, 20) having different coefficients of thermal expansion, the transfer step being carried out at high temperature. After removal of the first carrier substrate (10), the obtained structure is cooled, whereby a tensilely or compressively strained metal or semiconductor or insulator layer (11) is obtained.

Description

DESCRIPTION TITLE: Process for manufacturing a constrained layer This application is based on, and claims priority from, French patent application number FR 23 / 08447 filed on August 3, 2023, entitled “Process for manufacturing a constrained layer”, which is considered to be an integral part of this description within the limits provided by law. Technical field

[0001] This description relates generally to the manufacture of strained layers. Such strained layers are particularly interesting for structures used in microelectronics, and in particular for SSOI (“Strained Silicon On Insulator”) type structures. Prior art

[0002] Silicon-on-insulator (SOI) substrates consist of a semiconductor substrate covered by a thin oxide layer and a silicon layer. These structures are particularly attractive because they avoid the use of a bulk substrate and also allow for increased component integration density.

[0003] The realization of a constrained layer within these structures is of great interest for many applications.

[0004] For example, the realization of SSOI makes it possible to increase the performance of microprocessors [Huang et al. “Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding”, 2001 Symposium on VLSI Technology, 2001. Digest of Technical Papers, 57-58, 2001; Mazurier et al. “High performance and low variability fully-depleted strained-SOI MOSFETs”, 2010 IEEE International SOI Conference (SOI), 1-2, 2010].

[0005] Germanium film stressing also makes it possible to produce optical devices by obtaining a direct gap in the Germanium [Gassenq et al. “1.9% Bi-Axial Tensile Strain in Thick Germanium Suspended Membranes Fabricated in Optical Germanium-on-Insulator Substrates for Laser Applications”, Applied Physics letters 107, 19, 2015, 191904].

[0006] Generally, to fabricate a strained layer, an epitaxial growth step is implemented. This type of growth allows to play on the mismatches of lattice parameter. However, inevitably dislocations and other crystal defects appear in the strained layers. Thus, it is difficult in an SSOI structure to obtain less than 10 5 dislocation / cm 2 .

[0007] Alternatively, in order to better control the stresses in the SSOI structure, it is possible to manufacture these structures by implementing hot bonding [Abadie et al. “Germanium Thin Film Manufacturing Using Covalent Bonding Process”, Semiconductor Science and Technology 37, 4, 2022, 045012] or by bonding under imposed curvature, as described in patent EP1570509 B1. These different bonding techniques make it possible to impose stresses in the structure while avoiding the appearance of crystalline defects.

[0008] However, after hot bonding, the bonded structure must resist returning to room temperature despite the differences in the coefficient of expansion of the bonded materials. However, as the bonded materials have thick thicknesses (typically greater than 100 pm), the stored elastic energy reaches significant values, which can induce defects or rupture of the structure. glued. It is therefore necessary to limit the temperature of hot gluing, which limits the accessible level of constraints. Summary of the invention

[0009] There is a need to obtain a method for manufacturing layers stressed in tension or compression, the resulting stressed layers having to have a high level of stress (in particular greater than 200 MPa, preferably greater than 700 MPa or even greater than 1000 MPa) and a low rate of crystalline defects, or even no crystalline defects.

[0010] This aim is achieved by a method for manufacturing a constrained layer comprising the following steps: a) Providing, on the one hand, a first elementary structure comprising a first support substrate made of a first material whose thickness is for example greater than 100 pm, preferably greater than 500 pm, for example greater than 700 pm, covered by a metallic or semiconducting or insulating layer having a thickness of less than 10 pm, made of a material different from the first material, and on the other hand, a second elementary structure comprising a second support substrate whose thickness is for example greater than 100 pm, preferably greater than 500 pm, for example greater than 700 pm,the first support substrate and the second support substrate being chosen so that the coefficient of thermal expansion of the first support substrate is different from the coefficient of thermal expansion of the second support substrate and so that the coefficient of thermal expansion of the first support substrate and the coefficient of thermal expansion of the second support substrate induce a desired level of stress in the metallic or semiconducting or insulating layer during step c), b) Transferring the metallic or semiconducting layer or, insulating layer on the second elementary structure by assembling the first elementary structure and the second elementary structure by bonding at a bonding temperature Te such that Tc>70°C, whereby a bonded structure is obtained in which the metal or semiconductor or insulating layer is constrained to a first stress level, then by removing the first support substrate at a temperature Tt such that Tc-50°C < Tt < Tc+50°C and such that Tt>70°C, between bonding and removal of the first support substrate, the temperature of the bonded structure being maintained at a temperature both greater than 70°C and not varying by more than 50°C relative to the bonding temperature, so that the metal or semiconductor or insulating layer, once transferred, is constrained with the first stress level on the second support substrate, c) Cooling the assembly obtained,whereby a metallic or semiconducting or insulating layer is obtained, stressed in tension or compression at the desired stress level.

[0011] The desired stress level is equal to the first stress level if the material of the useful layer is the same as that of the second support substrate. If the material of the useful layer and the material of the second support substrate are different, the stress of the useful layer will be modified according to the difference in GTE between the two materials.

[0012] The invention differs fundamentally from the prior art by the hot implementation of all the transfer steps, that is to say that not only is the step of bonding the elementary structures carried out hot but also the step of removing the first support substrate. By hot, we mean a temperature above 70°C.

[0013] Furthermore, between the bonding of the two elementary structures and the removal of the first support substrate, the temperature of the bonded structure is maintained at a temperature Tt such that Tc-50°C < Tt < Tc+50°C and such that Tt>70°C. In other words, the bonded structure is always at a temperature above 70°C.

[0014] As the layer has a low thickness (less than 10 pm), during heating, a strong stress appears in the layer but not or relatively little in the first support substrate because the latter is much thicker. The stored elastic energy will then be low enough to avoid any rupture or generation of defects in the support substrate.

[0015] Furthermore, as the layer has a low thickness (less than 10 pm), during cooling, a high stress appears in the layer but not or relatively little in the second support substrate because the latter is much thicker. The stored elastic energy will then be low enough to avoid any rupture or generation of defects in the support substrate.

[0016] This produces an assembly comprising the second support substrate, free from practically any stress, covered by the metallic or semiconducting or insulating layer within which the internal stresses are relatively homogeneous and higher than those initially present in the same layer on the first support before heating.

[0017] In step c), the temperature Tt may be identical to the bonding temperature Te or close to the bonding temperature Te. By close, it is meant that it does not vary by more than 50°C, or even not more than 20°C, relative to the bonding temperature and, preferably, that it does not vary by more than 10°C relative to the bonding temperature. The temperature will be chosen according to the layer that we wish to stress and so as not to harm the transfer step.

[0018] The bonding is carried out hot (Tc>70°C) and the temperature of the bonded structure is maintained within a temperature range whose extreme values ​​do not vary by more than 50°C, or even 20°C and preferably 10°C, compared to the bonding temperature.

[0019] The smaller the temperature difference, the more the GTEs of the two substrates can be different and the greater the constraint obtained will be.

[0020] Advantageously, the metallic or semiconducting or insulating layer is a semiconducting layer, preferably made of silicon.

[0021] The first structure may comprise one or more additional layers positioned above and / or below the metallic or semiconducting or insulating layer.

[0022] The second structure may comprise one or more additional layers positioned on the second support substrate.

[0023] The presence of these additional layers can facilitate hot bonding and / or protect the metallic, semiconducting or insulating layer.

[0024] The additional layers may be selected, for example, from oxide layers, nitride layers and layers of amorphous semiconductor material.

[0025] Advantageously, the first elementary structure comprises the first support substrate, the metallic or semiconducting or insulating layer and a first layer of amorphous semiconductor material and / or the second elementary structure comprises the second support substrate and a second layer of amorphous semiconductor material. According to this advantageous embodiment, during step b), the first layer of amorphous semiconductor material is bonded with the second layer of amorphous semiconductor material.

[0026] Advantageously, the first support substrate and the second support substrate are chosen from germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa and diamond substrates. The support substrates are chosen according to the layer to be transferred.

[0027] According to a first advantageous embodiment variant, the first support substrate is made of sapphire and the second support substrate is made of silica.

[0028] According to a second embodiment, the first support substrate is made of copper and the second support substrate is made of silica.

[0029] These first two variants are interesting for putting tension on a layer, for example a silicon layer.

[0030] According to a third advantageous embodiment, the first support substrate is made of silicon and the second support substrate is made of copper.

[0031] Advantageously, when assembling the first elementary structure with the second elementary structure, a so-called curved bond can be carried out to adapt the level of stress.

[0032] Advantageously, several iterations of steps b) and c) will be carried out so as to increase the stresses within the layer. Preferably, according to this advantageous variant, the method comprises, after step c), the following steps: d) bonding the metallic or semiconducting or insulating layer to a third support substrate, preferably identical to the first support substrate, e) removing the second support substrate, f) transferring the metallic or semiconducting or insulating layer onto a fourth support substrate, preferably identical to the second support substrate, by implementing step b), g) cooling the assembly obtained in step f).

[0033] Advantageously, the metallic or semiconducting or insulating layer is a semiconducting layer and the method comprises a subsequent step, after step c) or after step g), during which said layer is transferred onto a semiconducting substrate covered by an oxide layer whereby a structure on insulator is formed (an SSOI if the layer of interest is made of silicon). Brief description of the drawings

[0034] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

[0035] Figure 1A, Figure 1B and Figure 1C schematically represent different steps of a method of manufacturing a constrained layer according to a first particular embodiment of the invention;

[0036] Figure 2A, Figure 2B and Figure 2C schematically represent different steps of a method of manufacturing a constrained layer according to another particular embodiment of the invention;

[0037] Figure 3A, Figure 3B and Figure 3C schematically represent different steps of a method of manufacturing an elementary structure comprising a layer to be stressed according to a particular embodiment of the invention;

[0038] Figure 4A, Figure 4B, Figure 4C and Figure 4D schematically represent different steps of a method of manufacturing an elementary structure comprising a layer to be stressed according to another particular embodiment of the invention; and

[0039] Figure 5 represents, schematically and in section, an SSOI structure comprising a constrained layer according to a particular embodiment of the invention.

[0040] For reasons of clarity of the figures, the different elements are not represented on a uniform scale. Description of the embodiments

[0041] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0042] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed.

[0043] In the following description, when reference is made to relative position qualifiers, such as the terms "on", "under", etc., reference is made unless otherwise specified to the orientation of the figures.

[0044] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0045] We will now describe in more detail the process of manufacturing a strained metallic or semiconducting or insulating layer, firstly with reference to Figures 1A to 1C and to Figures 2A at 2C. The layer can be stressed in tension or compression depending on the use of the stressed layer.

[0046] The method for manufacturing the strained metallic or semiconducting or insulating layer comprises a step during which the metallic or semiconducting or insulating layer 11 is transferred from a first support substrate 10 to a second support substrate 20, the support substrates 10, 20 having different thermal expansion coefficients. The bonding and transfer step is carried out hot. After removal of the first support substrate, the structure obtained is cooled, whereby a metallic or semiconducting or insulating layer 11 strained in tension or compression is obtained.

[0047] More particularly, the method comprises the following steps: a) providing, on the one hand, a first elementary structure SI comprising a first support substrate 10 covered by a metallic or semiconducting or insulating layer 11 having a thickness of less than 10 μm, and on the other hand, a second elementary structure S2 comprising a second support substrate 20, the coefficient of thermal expansion of the first support substrate 10 being different from the coefficient of thermal expansion of the second support substrate 20 (figures 1A and 2A), b) transferring the metallic or semiconducting or insulating layer 11 from the first support substrate 10 onto the second support substrate 20: - by assembling the first elementary structure SI and the second elementary structure S2 by bonding at a bonding temperature Te such that Tc> 70°C (figures 1B and 2B), whereby a bonded structure is obtained, then - by removing the first support substrate 10 at a temperature Tt such that Tt > 70°C and such that Tc-50°C < Tt < Tc+50°C, and preferably Tc-20°C < Tt < Tc+20°C, and more preferably Tc-10°C < Tt < Tc+10°C (figures IC and 2C), between the bonding and the removal of the first support substrate, the temperature of the bonded structure always being at a temperature above 70°C and at a temperature not varying by more than 50°C, preferably not varying by more than 20°C and preferably not varying by more than 10°C relative to the bonding temperature, c) cooling the assembly obtained in step b), whereby a metallic or semiconducting or insulating layer 11 stressed in tension or compression is obtained.

[0048] The layer 11 to be stressed may be a metal layer, a semiconductor layer or an insulating layer. An insulating layer is understood to mean an electrically insulating layer. Preferably, it is a semiconductor layer and, even more preferably, it is a semiconductor layer made of silicon or SiGe. The semiconductor layer may be an amorphous layer or a crystalline layer (preferably monocrystalline). The insulating layer may be silica.

[0049] The layer 11 to be stressed has a thickness of less than 10 μm, preferably less than 2 μm. The thickness of the layer may be less than 500 nm, or even less than 200 nm. Preferably, the thickness of the layer 11 is greater than 5 nm and even more preferably greater than 10 nm. Depending on its thickness, this layer may also be called a film.

[0050] The coefficient of thermal expansion (GTE) of the first support substrate 10 is different from the coefficient of thermal expansion of the second support substrate 20. The substrates are chosen according to the desired stress (tension or compression) and the nature of the layer to be stressed.

[0051] The material of the first support substrate 10 is different from the material of the layer 11. Thus, the coefficient of thermal expansion of the first support substrate 10 is different from the coefficient of thermal expansion of the layer 11. The difference in GTE between the material of the layer 11 and the material of the first support substrate 10 will induce, during the temperature rise, before bonding, either compression or tensioning of the layer 11. The layer is then in a first level of stress. By appropriately choosing the material of the second support substrate, it will be possible to accentuate this tensioning or compression or not to obtain the desired level of stress in the layer 11 at the end of the process.

[0052] The thermal expansion coefficients of the support substrates 10, 20 may be greater or less than the thermal expansion coefficient of the layer 11 to be stressed. Preferably, the thermal expansion coefficient of one of the support substrates 10, 20 is greater than that of the layer 11 to be stressed and the thermal expansion coefficient of the other support substrate 10, 20 is less than that of the layer 11 to be stressed.

[0053] The support substrates 10, 20 are chosen from germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa and diamond substrates.

[0054] For example, to tension a layer 11, by a silicon layer, the first support substrate 10 and the second support substrate 20 can be chosen from one of the following pairs: - a first support substrate 10 made of sapphire and a second support substrate 20 made of silica, - a first support substrate 10 made of copper and a second support substrate 20 made of silica.

[0055] For example, silica has a GTE of about 0.5 ppm which varies little with temperature.

[0056] On the contrary, silicon has a GTE which typically varies between 2 ppm at room temperature (i.e. at a temperature between 20 and 25°C) and 4 ppm around 450°C.

[0057] Copper has a GTE that typically ranges from 16 ppm at room temperature to 20 ppm around 450°C.

[0058] Sapphire has a GTE that typically ranges from 6.5 ppm at room temperature to 7.5 ppm around 450°C.

[0059] Thus, when the first structure SI is heated during step b), the support substrate 10 made of copper or sapphire expands more than the silicon, leading to an expansion of the silicon layer 11. The expanded silicon layer 11 is assembled hot with the second support substrate 20 made of silica which hardly expands. The first support substrate 10 is removed hot. When the temperature drops again, the support substrate 10 made of silica hardly contracts and a silicon layer 11, which tends to contract, sees its tension further increased.

[0060] If the first support substrate were not removed before cooling, the assembly formed by the assembly of the first elementary structure and the second elementary structure would break due to the internal stress generated by the difference in thermal expansion coefficient between the two support substrates.

[0061] The first structure SI may consist of the first support substrate 10 covered by the layer to be stressed 11.

[0062] According to an advantageous embodiment variant, the first structure SI further comprises a first layer 13 of material capable of facilitating or enabling hot bonding. The first layer 13 can also advantageously protect layer 10 during bonding and transfer. This layer can in particular be made of amorphous semiconductor material such as amorphous silicon (figure 1A).

[0063] According to a particular embodiment variant, the first structure SI further comprises an oxide layer 12 positioned between the layer 11 to be stressed and the amorphous silicon layer 13 (figure 2A). In a generic manner, it is possible to have one or more multilayers above and / or below the layer 11.

[0064] The first structure SI may also comprise, between the first support substrate 10 and the layer to be constrained 11, a layer or a multilayer allowing detachment during step b), in particular in the case of laser lift-off (or LLO for "Laser Lift Off"). It may be a bilayer comprising a GaN layer and an oxide layer, for example, in the case of a first support substrate 10 made of sapphire. It may also be a SiO2 / AlN / SiO2 or SiO2 / TiN / SiO2 trilayer, for example, in the case of a first support substrate 10 made of silicon. It may also be a silicon layer or a silicon / oxide bilayer in the case of using the Smart Cut™ process to make the transfer. The fracture due to the Smart Cut™ process occurs in this silicon layer and not in layer 11. This silicon layer can be polycrystalline. Alternatively, the fracture can occur in layer 11.

[0065] As shown in Figures 3A to 3C and in Figures 4A to 4C, the first SI structure can be obtained by bonding, on the first support substrate 10 or where appropriate on the detachment layer or multilayer, an SOI substrate comprising a semiconductor substrate 14 covered by an oxide layer 12 and a semiconductor layer 11 then by removing the semiconductor substrate 14 and, optionally, the oxide layer 14. This allows you to obtain the structure which will be glued and heat transferred.

[0066] The second structure S2 may consist of the first support substrate 20.

[0067] According to an advantageous embodiment variant, the second structure S2 may consist of the second support substrate 20 covered by a second layer 21 of material capable of facilitating or enabling hot bonding. This layer may in particular be made of an amorphous semiconductor material such as amorphous silicon (figure 1A).

[0068] Preferably, the first layer of amorphous semiconductor material 13 and the second layer of amorphous semiconductor material 21 are made of silicon.

[0069] The first layer of amorphous semiconductor material 13 and the second layer of amorphous semiconductor material 21 may be formed, for example, by a chemical vapor deposition technique, in particular by low pressure chemical vapor deposition (LPCVD).

[0070] In step b), the layer to be stressed 11 is transferred from the first elementary structure SI to the second elementary structure S2. The transfer consists, firstly, of hot assembling the first elementary structure SI on the second elementary structure S2 in order to position the layer 11 on the second elementary structure S2, then of hot removing the first support substrate 10.

[0071] First, the two elementary structures SI and S2 are assembled by hot bonding. For example, the elementary structures SI and S2 are assembled by bringing the surfaces of the layers of amorphous semiconductor material 13, 21 into contact if they are present.

[0072] In order to facilitate bonding, the surfaces to be bonded can be previously subjected to various treatments, for example mechanical and / or chemical polishing, chemical treatment, UV / Ozone treatment, RIE (“Reactive Ion Etching”), plasma, or hydrogen annealing, etc.

[0073] Bonding can be carried out under ultra-high vacuum (or UHV for “Ultra High Vacuum” in English terms).

[0074] Preferably, the bonding is a SAB (“Surface Activated Bonding”) bonding. For this, the surfaces of the SI and S2 structures are ionically bombarded under ultra-high vacuum before being brought into contact.

[0075] In the case of SAB bonding and a second silica support substrate 20, a second layer 21 of amorphous silicon may be deposited beforehand on the second support substrate 20 in order to facilitate SAB bonding.

[0076] It is possible to cover the layer 11 to be stressed with an oxide layer and then with a layer 13 of amorphous silicon. The oxide layer prevents damage to the layer 11, and in particular the creation of an undesirable amorphous area on the surface, during the SAB process. The layer 13 of amorphous silicon facilitates SAB bonding.

[0077] Alternatively, the bonding is an ADB (Activated Diffusion Bonding) bond. A filler metal can be used to join the surfaces to be bonded. This can also be a layer of semiconductor such as silicon or germanium.

[0078] According to an alternative embodiment, the bonding may be a so-called curved bonding. The curvature of the layers of amorphous semiconductor material 13, 21 will be chosen so as to allow the transfer of the layer to be constrained 11 (metallic, semiconductor or insulating layer). The bonding will then be carried out hot and with a curvature.

[0079] To achieve a curved bond, before bringing the two amorphous layers 13, 21 into contact, a difference in the state of tangential stresses between the two faces to be joined is created. This difference can be obtained by bending each of the two elementary structures SI, S2 to be joined, for example by applying mechanical forces. For example, the use of electrostatic supports (“chucks”) having a curvature makes it possible to impose a curvature on SI and S2 when applying the electrostatic force. Advantageously, the structures SI, S2 are curved so that the two faces to be joined are complementary. For example, one of the faces can be concave and the other face can be convex.

[0080] The bonding of the amorphous layers 13, 21 is carried out at a so-called bonding temperature noted Te. The bonding temperature is determined according to the materials to be bonded. Advantageously, the temperature Te can be maintained after bonding for a period of between 1 min and 10 min. The bonding temperature Te is higher than the ambient temperature (TA) by at least 50°C, that is to say that for a typical ambient temperature of 20°C, the bonding temperature TC is higher than 70°C. Advantageously Tc>TA +380°C (in other words Te > 400°C if TA=20°C) or even Tc>TA+880°C (in other words Te > 900°C if TA=20°C).

[0081] During bonding, the elementary structures SI and S2 can each be held by electrostatic supports (“chucks”) which can be heated to the same or different temperatures.

[0082] According to a first embodiment variant, during bonding, the first elementary structure SI and the second elementary structure S2 are at identical temperatures.

[0083] According to another embodiment, during bonding, the first elementary structure SI and the second elementary structure S2 are at different temperatures. The bonding temperature Te is then considered to be the highest temperature.

[0084] After bonding, the first support substrate 10 is removed hot at a temperature Tt. The temperature Tt may be identical to the bonding temperature Te or close to the bonding temperature Te. Between transfer and bonding, the bonded structure remains close to Te.

[0085] By close is meant that it does not vary by more than 20°C and, preferably, does not vary by more than 10°C. In other words, step c) is carried out at a temperature Tt such that Te -20°C < Tt < Te + 20°C, and preferably, such that Te - 10°C < Tt < Te + 10°C.

[0086] Advantageously, the temperature Tt can be maintained for a period of between 1 min and 10 h.

[0087] Depending on the transfer technique used, part of the layer 11 may also be removed. This is particularly the case in a Smart Cut™ type process. The thickness removed nevertheless remains low compared to the thickness of the layer when it is bonded. In particular, less than 90% or more specifically less than 50% or less than 10% of the thickness of the layer is removed. In order not to change the thickness of the layer 11, it is possible to carry out the Smart Cut™ in a layer positioned under the layer 11.

[0088] In order to implement the Smart Cut™ type method, a step of implanting ionic species, such as hydrogen and / or helium, possibly associated with boron, is carried out in the layer 11 so as to form a weakening zone delimiting the part of the layer 11 to be transferred. The fracture of the first elementary structure SI takes place along the weakening zone, which makes it possible to detach the remainder of the elementary structure SI and transfer the thin layer 11. The implantation step is carried out before implementing step b).

[0089] According to another embodiment, the removal of the first support substrate 10 can be carried out by a laser detachment (LLO) process, for example by the Nanocleave™ process. In the case of a LLO laser detachment process, a layer or multilayer allowing detachment is positioned between the first support substrate 10 and the metallic or semiconducting or insulating layer 11.

[0090] Alternatively, the removal of the first support substrate 10 can be carried out by a method using a porous material (for example a porous SiOCH) or even a method using the fusion of a sacrificial layer with a mechanical separation (“slide off”).

[0091] In step c), the assembly obtained after the transfer of the metallic or semiconducting or insulating layer 11 is cooled. The assembly is preferably cooled to room temperature. Room temperature means a temperature between 20 and 25°C.

[0092] At the end of step c), an assembly is obtained comprising the second support substrate 20, possibly the amorphous layers 13, 21, potentially one or more additional layers necessary for the final structure and / or for the implementation of the method, and the metallic or semiconducting or insulating layer 11 stressed in tension or compression.

[0093] To increase the stresses within the layer, the method may further comprise, after step c), the following steps: d) Bonding the metallic or semiconducting or insulating layer 11 on a third substrate, preferably identical to the first substrate 10, e) Remove the second substrate 20, f) Cool the assembly obtained in step f).

[0094] Step d) is preferably carried out by direct bonding and, even more preferably, by SAB or ADB bonding.

[0095] Step f) allows the transfer of the metallic or semiconducting or insulating layer 11 by hot bonding and removal of the third substrate while hot.

[0096] At the end of step f), a metallic or semiconductor-conductive layer 11 is obtained having a stress rate greater than that obtained at the end of step b).

[0097] Thus, by repeating this sequence several times, it is possible to considerably increase the constraints within layer 11.

[0098] The number of iterations will be chosen according to the desired strain rate and thickness of the metallic, semiconducting, or insulating layer 11. Indeed, at each transfer step, part of the layer 11 can be removed. Advantageously, additional layers are cleverly placed to carry out the transfers.

[0099] This process makes it possible to obtain a layer, of silicon for example, stressed in tension or compression.

[0100] The layer obtained has a stress greater than 200MPa, preferably greater than 400MPa, even more preferably greater than 700MPa and even more preferably greater than 1GPa.

[0101] Such a layer is particularly interesting for applications in microelectronics, especially in the high frequency domain, the charge carriers then having greater mobility.

[0102] Thus, at the end of step c) or step g), the layer 11 stressed in tension or compression can advantageously be deposited on a substrate of interest. For example, in the case of a semiconductor layer 11, in particular made of silicon, this layer can be deposited on a substrate of interest comprising a silicon substrate 30 and an oxide layer 31 to form an SSOI substrate (figure 5).

[0103] The SSOI structure successively comprises a semiconductor substrate, an oxide layer and a semiconductor layer stressed in tension or compression, the semiconductor layer having a stress of more than 200 MPa, preferably more than 400 MPa, even more preferably more than 700 MPa and even more preferably more than 1000 MPa in absolute value. The semiconductor layer stressed in tension or compression is preferably defect-free.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0105] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

[0106] Illustrative and non-limiting examples of different particular embodiments

[0107] First example: fabrication of an SSOI using a Smart Cut™ step from a sapphire substrate and a silica substrate

[0108] In this first example, initially, an SOI substrate is bonded to a first sapphire support substrate by direct bonding.

[0109] The SOI substrate is a commercial SOI substrate formed by a 200 mm diameter and 725 pm thick silicon substrate covered by a 500 nm oxide and a 1000 nm silicon thin film.

[0110] The first sapphire support substrate is a 200 mm diameter and 725 pm thick substrate.

[0111] Before bonding, a nitrogen plasma treatment is carried out on the SOI substrate then ethalonamine (diluted to 10 -4 M) is added to this same substrate. After bonding, thermal annealing at 150°C is carried out (the maximum temperature, above which such a bond breaks, is approximately 200°C).

[0112] A lapping step is performed on the silicon substrate until the substrate thickness is reduced to approximately 50 pm. A chemical attack based on HF / HNO3 is used to remove the remaining part of the substrate. The concentration is for example 1% by volume of HF (50%) in HNO3 (70%). This step can be performed in a machine, for example in a machine that only processes one side such as a SEZ type machine. The oxide, which was used to stop the chemical attack, then undergoes chemical mechanical polishing (CMP) to reduce its thickness to 100 nm and reduce its roughness below 0.3 nm RMS to make it compatible with direct bonding.

[0113] A 30 nm layer of amorphous silicon is then deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C.

[0114] The silicon layer is implanted with a hydrogen dose of 8E 16 at / cm 2 at an energy of 76 keV.

[0115] At the same time, a second fused silica support substrate (plate) with a diameter of 200 mm and a thickness of 725 μm is polished by CMP to obtain a surface compatible with direct bonding. A 30 nm amorphous silicon layer identical to that of the first structure is deposited on the silica plate. The amorphous silicon layers are bonded to each other by SAB (Surface Advanced Bonding) at 400°C. For this, after placing under ultra-high vacuum (UHV or "High Ultra Vacuum") at 10 -8mbar, the surfaces to be bonded are subjected to an argon ion beam at 200 eV and 150 mA for 60 s. The substrates are then placed on electrostatic chucks preheated to 400°C. After a 5 min thermal stabilization, the two surfaces to be bonded are brought into contact. Bonding is then carried out without modification of the stress levels because the two substrates are at 400°C. The heat treatment is extended for 2 h to be able to implement the Smart Cut™ process. After Smart Cut™ separation, the first support with a part of the silicon film and the assembly formed by the silicon layer, the amorphous silicon layers and the second support substrate are cooled to room temperature (typically between 20 and 25°C). Approximately 800 nm of silicon is transferred from the sapphire substrate to the silica substrate.

[0116] Raising the temperature of the silicon layer bonded to the sapphire to 400°C allows it to be tensioned to +262 MPa.

[0117] After transfer to the silica substrate, there is no change in stress in the silicon layer because the silica is at the same temperature (here 400°C). After lowering the temperature to room temperature and separating the substrates, the silicon layer transferred to the silica sees its stress increase to +465 MPa.

[0118] The different steps previously described can be repeated to increase the stress in the silicon layer.

[0119] For this, the silicon layer of about 800nm ​​is polished by CMP to make it compatible with direct bonding and then the silica substrate covered with the silicon layer is cold bonded to a new sapphire plate. The thickness of the silicon layer is then about 700nm. The silica substrate is removed by lapping and chemical etching (hydrofluoric acid). The stress of the silicon layer transferred to the sapphire substrate is always +465 MPa.

[0120] The silicon layer is then transferred onto another hot silica substrate as before: a layer with a stress of 930 MPa and a thickness of 500 nm (having adapted the hydrogen implantation) is obtained. After a new CMP step, the silicon layer is ready for a third iteration. Its thickness is then 400 nm. We then obtain 200 nm of silicon with a stress of 1395 MPa and a thickness of 100 nm after a last CMP.

[0121] This 100 nm silicon layer can finally be transferred onto a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. An SSOI with a layer exhibiting a stress of approximately 1.4 GPa is obtained.

[0122] Second example: fabrication of an SSOI using a Smart Cut™ step from a copper substrate and a silica substrate

[0123] In this second example, initially, an SOI substrate is bonded to a first copper support substrate by direct bonding.

[0124] The SOI substrate is a commercial SOI substrate formed by a 200 mm diameter and 725 pm thick silicon support substrate covered by a 500 nm oxide and a 400 nm silicon thin film.

[0125] The first copper support substrate is a 200 mm diameter and 725 pm thick substrate.

[0126] The SOI substrate is bonded to the copper substrate by SAB. As before, the silicon substrate is subjected to a lapping step to reduce the thickness of the silicon substrate to about 50 pm, then a chemical etching based on HF / HNO3 (concentrations 1% by volume of HF (50%) in HNO3 (70%)) is carried out to remove this part of the silicon substrate. A CMP is carried out on the oxide which was used to stop the chemical etching. The oxide then regains a surface state compatible with direct bonding and a thickness of 50 nm. A 30 nm amorphous silicon layer is deposited on the oxide by LPCVD at 550°C. Finally, the silicon layer is implanted, for example, with a Helium-Hydrogen coimplantation (with energies and doses respectively of 38 keV / 1.3E16 at / cm 2 and 24 keV / 5.25E16 at / cm 2 ) .

[0127] In parallel, a second support substrate (plate) of fused silica with a diameter of 200 mm and a thickness of 725 μm is polished by CMP to obtain a surface compatible with direct bonding. A 30 nm layer of amorphous silicon is deposited on its surface.

[0128] The two amorphous silicon layers are bonded by SAB at 400°C. For this, as previously, the two surfaces to be bonded are placed under ultra-high vacuum at 10 -8 mbar and activated with an argon ion beam at 200 eV and 150 mA for 60 s. The plates are then placed on electrostatic chucks preheated to 400°C. After a 5 min thermal stabilization, the two plates are put in contact. Bonding is then carried out without changing the stress levels because both substrates are at 400°C. Thermal annealing is extended for 2 hours in order to implement the Smart Cut® process. A thickness of approximately 200 nm of silicon is thus transferred from the copper substrate to the silica substrate.

[0129] Before bonding, heating the silicon film bonded to the copper to 400°C puts the silicon film under tension at +1030 MPa. After transfer to the silica, there is no change in stress because the silica is also at 400°C. After separation of the two substrates, they are cooled to room temperature. The silicon layer transferred to the silica sees its stress increase to +1.23 GPa. We then obtain a stress of 1395 MPa and a thickness of 100 nm after a final CMP.

[0130] This 100 nm layer can then be transferred to a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. The final result is an SSOI structure comprising a silicon layer with stresses of approximately 1.4 GPa. In this example, there is no need to repeat the process steps to obtain an SSOI of more than 1.2 GPa.

[0131] Third example: manufacturing of an SSOI using a transfer step using a “Laser Lift OFF” (LLO) process from a sapphire substrate and a silica substrate

[0132] First, a commercial SOI substrate composed of a 100 nm silicon thin film on a 500 nm oxide is bonded onto a 200 mm diameter and 725 pm thick silicon substrate.

[0133] In a second step, a layer of GaN is successively deposited on a first sapphire support substrate. 100 nm thick by epitaxy and a 200 nm oxide layer on the GaN. A CMP is carried out on this oxide to make it compatible with direct bonding. After carrying out a nitrogen plasma treatment and adding ethanolamine (diluted to 10 -4 M), direct bonding of the SOI is carried out on the sapphire support substrate with a diameter of 200 mm and a thickness of 725 pm covered with GaN and oxide. After heat treatment at 150°C (the maximum temperature above which such bonding breaks is approximately 200°C), the silicon substrate is ground to leave only 50 pm and then this remaining thickness is removed by chemical attack based on HF / HNO3 (1% by volume of HF (50%) in HNO3 (70%)) in a machine (for example of the SEZ type). The oxide is also removed.

[0134] The second support substrate is a fused silica plate 200 mm in diameter and 725 μm thick. It is polished by CMP to obtain a surface compatible with direct bonding. A 30 nm amorphous silicon layer is deposited on it, produced by LPCVD at 550°C.

[0135] To transfer the layer to be stressed, SAB bonding is first carried out at 900°C. For this, the two plates are placed under ultra-high vacuum at 10 -8mbar. Each face is activated with an argon ion beam at 200 eV and 150 mA for 60 s. The plates are then placed on electrostatic supports ("chucks") preheated to 900 ° C. After a 5 min thermal stabilization, the two plates are brought into contact. Bonding is then carried out without modifying the stress levels because the two substrates are at 900 ° C. The resulting assembly is then transferred, while maintaining the temperature at 900 ° C, into a chamber allowing a transfer by a LLO ("laser lift off") technique to separate the GaN from the sapphire.

[0136] The 100nm silicon layer is thus transferred onto the silica.

[0137] Before bonding, as the silicon layer is bonded to the sapphire at a temperature of 900°C, it is under tension at +700 MPa. After transfer to the silica, there is no change in stress because the silica is also at 900°C. After separation of the substrates, both substrates are cooled to room temperature. The silicon layer transferred to the silica sees its stress increase to +1.24 GPa.

[0138] After chemical etching removal of the remaining GaN and silicon oxide with HF.

[0139] The 100 nm layer can then be transferred onto a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. An SSOI is obtained with a silicon layer strained to approximately 1.24 GPa.

Claims

CLAIMS 1. Method for manufacturing a constrained layer comprising the following steps: a) Providing, on the one hand, a first elementary structure (SI) comprising a first support substrate (10) made of a first material covered by a metallic or semiconducting or insulating layer (11), made of a material different from the first material, having a thickness of less than 10 pm, and on the other hand, a second elementary structure (S2) comprising a second support substrate (20),the first support substrate (10) and the second support substrate (20) being chosen so that the coefficient of thermal expansion of the first support substrate (10) is different from the coefficient of thermal expansion of the second support substrate (20) and that the coefficient of thermal expansion of the first support substrate (10) and the coefficient of thermal expansion of the second support substrate (20) induce a desired level of stress in the metallic or semiconducting or insulating layer (11) during step c), b) Transferring the metallic or semiconducting or insulating layer (11) onto the second elementary structure (S2) by assembling the first elementary structure (SI) and the second elementary structure (S2) by bonding at a bonding temperature Te such that Tc>70°C, whereby a bonded structure is obtained in which the metallic or semiconducting or insulating layer (11) is stressed at a first level of stress,then by removing the first support substrate (10) at a temperature Tt such that Tc-50°C < Tt < Tc+50°C, between the bonding and the removal of the first support substrate (10), the temperature of the bonded structure being maintained at a temperature both greater than 70°C and not varying by more than 50°C relative to the bonding temperature, so that the, metallic or semiconducting or insulating layer (11), once transferred, is constrained to the first stress level on the second support substrate (20), c) Cooling the assembly obtained, whereby a metallic or semiconducting or insulating layer (11) is obtained, constrained in tension or compression to the desired stress level.

2. Method according to claim 1, characterized in that the metallic or semiconducting or insulating layer (11) is a semiconducting layer, preferably made of silicon.

3. Method according to one of claims 1 and 2, characterized in that the first support substrate (10) and the second support substrate (20) are chosen from substrates made of germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa and diamond.

4. Method according to any one of the preceding claims, characterized in that the first elementary structure (SI) comprises one or more additional layers which can be positioned above and / or below the metallic or semiconducting or insulating layer (11) and / or in that the second elementary structure (S2) comprises one or more additional layers positioned on the second support substrate (20).

5. Method according to any one of the preceding claims, characterized in that the first elementary structure (SI) comprises the first support substrate (10), the metallic or semiconducting or insulating layer (11) and a first layer of amorphous semiconductor material (13) and / or in that the second elementary structure (S2) comprises the second support substrate (20) and a second layer of amorphous semiconductor material (21).

6. Method according to any one of claims 1 to 5, characterized in that the first support substrate (10) is made of sapphire and the second support substrate (20) is made of silica.

7. Method according to any one of claims 1 and 5, characterized in that the first support substrate (10) is made of copper and the second support substrate (20) is made of silica.

8. Method according to any one of claims 1 to 5, characterized in that the first support substrate (10) is made of silicon and the second support substrate (20) is made of copper.

9. Method according to any one of the preceding claims, characterized in that the temperatures Te and Tt are identical.

10. Method according to any one of the preceding claims, characterized in that during the assembly of the first elementary structure (SI) with the second elementary structure (S2), a difference in state of tangential stresses exists between the first layer of amorphous semiconductor material (13) and the second layer of amorphous semiconductor material (21).

11. Method according to any one of the preceding claims, characterized in that the method comprises, after step c), the following steps: d) Bonding the metallic or semiconducting or insulating layer (11) to a third support substrate, preferably identical to the first support substrate (10), e) Removing the second support substrate (20), f) Transferring the metallic or semiconducting or insulating layer (11) to a fourth support substrate, preferably identical to the second support substrate (20), implementing step b), g) Cool the assembly obtained in step f).

12. Method according to any one of the preceding claims, characterized in that the metallic or semiconducting or insulating layer (11) is a semiconducting layer and in that the method comprises a subsequent step, after step c) or after step g), during which said layer (11) is transferred onto a semiconducting substrate (30) covered by an oxide layer (31) whereby a structure on an insulator is formed.

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