Cabac inter / intra shared models
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- INTERDIGITAL CE PATENT HOLDINGS SAS
- Filing Date
- 2024-07-17
- Publication Date
- 2026-06-10
Smart Images

Figure EP2024070301_13022025_PF_FP_ABST
Abstract
Description
[0001] CABAC INTER / INTRA SHARED MODELS
[0002] CROSS REFERENCE TO RELATED APPLICATION
[0003] This application claims the benefit of European Serial Nos. 23306338.7 filed August 4, 2023, 23306645.5 filed September 29, 2023, 23306991 .3 filed November 17, 2023, which is incorporated by reference herein in its entirety.
[0004] TECHNICAL FIELD
[0005] At least one of the present embodiments generally relates to a method or an apparatus for video encoding or decoding, compression or decompression.
[0006] BACKGROUND
[0007] To achieve high compression efficiency, image and video coding schemes usually employ prediction, including motion vector prediction, and transform to leverage spatial and temporal redundancy in the video content. Generally, intra or inter prediction is used to exploit the intra or inter frame correlation, then the differences between the original image and the predicted image, often denoted as prediction errors or prediction residuals, are transformed, quantized, and entropy coded. To reconstruct the video, the compressed data are decoded by inverse processes corresponding to the entropy coding, quantization, transform, and prediction.
[0008] SUMMARY
[0009] At least one of the present embodiments generally relates to a method or an apparatus for video encoding or decoding, and more particularly, to a method or an apparatus for coding or decoding using regressive-based affine bi-prediction weights.
[0010] According to a first aspect, there is provided a method. The method comprises steps for coding binary symbols obtained from residual coefficients of video blocks coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, encoding the video block using said CABAC models.
[0011] According to a second aspect, there is provided another method. The method comprises steps for decoding binary symbols obtained from residual coefficients of video blocks coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, decoding the video block using said CABAC models. According to another aspect, there is provided an apparatus. The apparatus comprises a processor. The processor can be configured to encode a block of a video or decode video data by executing any of the aforementioned methods.
[0012] According to another general aspect of at least one embodiment, there is provided a device comprising an apparatus according to any of the decoding embodiments; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, or (iii) a display configured to display an output representative of a video block.
[0013] According to another general aspect of at least one embodiment, there is provided a non-transitory computer readable medium containing data content generated according to any of the described encoding embodiments or variants.
[0014] According to another general aspect of at least one embodiment, there is provided a signal comprising video data generated according to any of the described encoding embodiments or variants.
[0015] According to another general aspect of at least one embodiment, video data or a bitstream is formatted to include data content generated according to any of the described encoding embodiments or variants.
[0016] According to another general aspect of at least one embodiment, there is provided a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out any of the described decoding embodiments or variants.
[0017] These and other aspects, features and advantages of the general aspects will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
[0018] BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 illustrates an entropy coding overview.
[0020] Figure 2 illustrates parameter initialization.
[0021] Figure 3 illustrates an example of a flowchart for decoding a bin.
[0022] Figure 4 illustrates CABAC carry over for intra slices.
[0023] Figure 5 illustrates an embodiment of a first method under the described aspects. Figure 6 illustrates an embodiment of a second method under the described aspects.
[0024] Figure 7 illustrates one embodiment of an apparatus under the described aspects.
[0025] Figure 8 illustrates a standard, generic, video compression scheme.
[0026] Figure 9 illustrates a standard, generic, video decompression scheme.
[0027] Figure 10 illustrates a processor-based system for encoding / decoding under the general described aspects.
[0028] DETAILED DESCRIPTION
[0029] The embodiments described here are in the field of video compression and generally relate to video compression and video encoding and decoding more specifically aims at improving compression efficiency compared to existing video coding systems.
[0030] To achieve high compression efficiency, image and video coding schemes usually employ block-based prediction, including motion vector prediction, and transform to leverage spatial and temporal redundancy in the video content. Generally, intra or inter prediction is used to exploit the intra or inter frame correlation, then the differences between the original block and the predicted block, often denoted as prediction errors or prediction residuals, are transformed, quantized, and entropy coded. To reconstruct the video, the compressed data are decoded by inverse processes corresponding to the entropy coding, quantization, transform, and prediction.
[0031] In the HEVC (High Efficiency Video Coding) video compression standard, motion compensated temporal prediction is employed to exploit the redundancy that exists between successive pictures of a video.
[0032] To do so, a motion vector is associated to each prediction unit (PU), which is introduced now. Each CTU (Coding Tree Unit) is represented by a Coding Tree in the compressed domain. This is a quad-tree division of the CTU, where each leaf is called a Coding Unit (CU).
[0033] Each CU is then given some Intra or Inter prediction parameters (Prediction Info). To do so, it is spatially partitioned into one or more Prediction Units (PUs), each PU being assigned some prediction information. The Intra or Inter coding mode is assigned on the CU level. Exactly one Motion Vector is assigned to each PU in HEVC. This motion vector is used for motion compensated temporal prediction of the considered PU.
[0034] In the Versatile Video Codec (WC) developed by the JVET (Joint Video Exploration Team) group, a CU is no more divided into PU or TU, and some motion data is directly assigned to each CU. In this new codec design, a CU can be divided into sub-CU with a motion vector computed for each sub-CU.
[0035] Entropy Coding Overview
[0036] In current video codec, a large part of the signaling is done using an entropy coding of the values to transmit. Especially, using CABAC, only binary values are encoded and generic values should first undergo a binarization process. For each individual bin to encode, a context is also attached so that the probability of each bin to encode is updated after each encoding / decoding. The speed at which the probability is updated is a parameter of the model. Another parameter is the initial probability used by the model.
[0037] In next generation video codecs, the entropy coding is summed up in Figure 1. For each bin, the context is selected. Each context contains the following information:
[0038] 1 . Current probability. In recent codecs like HEVC and WC, 2 probabilities are maintained pO and p1.
[0039] 2. The windows size(s), corresponding to the update speed of the probability. Typically, the probability is updated following: p’= w * b + (1- w) *p, where p is the previous probability, p’ the updated probability, b the current bin encoded / decoded and w the window size. In recent codec, 2 probabilities are updated, using 2 different window sizes, wO and w1 . Each bin is then encoded / decoded by considering the simple mean of the two probabilities pO and p1 .
[0040] 3. The initial probability. Typically, pO and p1 are initialized using the same initial probability.
[0041] The parameters for a given context (initial probability, windows sizes) depend on external parameters, such as the type of slice to encode intra, biprediction, unidirection (I, B or P) and / or the quantization parameter qp
[0042] Each context uses fixed (between encoder and decoder) parameters, and these parameters are decided per context. At the beginning of each slice, the parameters are initialized by computing an initial probability and getting a window size, both based on slice type, as depicted in Figure 2.
[0043] Moreover, a flag called sh_cabac_init_flag is signaled in the slice header for non intra slice which allows to switch the parameters to use for initialization: when the flag is true for a B slice, P slice parameters set are used, and the other way around.
[0044] In the WC, CABAC contains the following major changes compared to the design in HEVC: Core CABAC engine, separate residual coding structure for transform block and transform skip block, and context modeling for transform coefficients.
[0045] The CABAC engine in HEVC uses a table-based probability transition process between 64 different representative probability states. In HEVC, the range ivICurrRange representing the state of the coding engine is quantized to a set of 4 values prior to the calculation of the new interval range. The HEVC state transition can be implemented using a table containing all 64x4 8-bit pre-computed values to approximate the values of ivICurrRange * pLPS( pStateldx ), where pLPS is the probability of the least probable symbol (LPS) and pStateldx is the index of the current state. Also, a decode decision can be implemented using the pre-computed LUT. First ivILpsRange is obtained using the LUT as shown in Equation (3-47). Then, ivILpsRange is used to update ivICurrRange and calculate the output binVal. ivILpsRange = rangeTabLps[ pStateldx ][ qRangeldx ]
[0046] (3-1)
[0047] In VVC, the probability is linearly expressed by the probability index pStateldx. Therefore, all the calculation can be done with equations without LUT operation. To improve the accuracy of probability estimation, a multi-hypothesis probability update model is applied. The pStateldx used in the interval subdivision in the binary arithmetic coder is a combination of two probabilities pStateldxO and pStateldxl . The two probabilities are associated with each context model and are updated independently with different adaptation rates. The adaptation rates of pStateldxO and pStateldxl for each context model are pre-trained based on the statistics of the associated bins. Since the adoption of JVET-Z0135, the probability estimate pStateldx is the average of the estimates from the two hypotheses.
[0048] Figure 3 shows the flowchart for decoding a single binary decision in VVC.
[0049] As done in HEVC, WC CABAC also has a QP dependent initialization process invoked at the beginning of each slice. Given the initial value of luma QP for the slice, the initial probability state of a context model, denoted as preCtxState, is derived as follows m = slopeldx x 5 - 45 (3-2) n = (offsetldx « 3) +7 (3-3) preCtxState = Clip3(1 , 127, ((m x (QP - 32)) » 4) + n) (3-
[0050] 4) where slopeldx and offsetldx are restricted to 3 bits, and total initialization values are represented by 6-bit precision. The probability state preCtxState represents the probability in the linear domain directly. Hence, preCtxState only needs proper shifting operations before input to arithmetic coding engine, and the logarithmic to linear domain mapping as well as the 256-byte table is saved. pStateldxO = preCtxState « 3 (3-5) pStateldxl = preCtxState « 7 (3-6)
[0051] Entropy Coding with Extended Precision
[0052] The intermediate precision used in the arithmetic coding engine is increased, including three elements. First, the precisions for two probability states are both increased to 15 bits, in comparison to 10 bits and 14 bits in WC. Second, the LPS range update process is modified as below, if q >= 16384 q = 215
[0053] RLPS = ((range where range is a 9-bit variable representing the width of the current interval, q is a 15-bit variable representing the probability state of the current context model, and RLPS is the updated range for LPS. This operation can also be realized by looking up a 512x256-entry in 9-bit look-up table. Third, at the encoder side, the 256-entry lookup table used for bits estimation in VTM is extended to 512 entries. Slice-type-based window size
[0054] Since statistics are different with different slice types, it is beneficial to have a context probability state updated at a rate that is optimal under the given slice type. Therefore, for each context model, three window sizes are pre-defined for I-, B-, and P-slices, respectively, as the initialization parameters.
[0055] The context initialization parameters and window sizes are retrained.
[0056] Adaptive update rates, weighted average and state carry-over
[0057] While the update rules for the two probability states pStateldxO and pStateldxl stay the same, encoding of the n-th bit of a context is performed using probability states pStateldxO’ and pStateldxT, which are obtained from pStateldxO and pStateldxl using window sizes which depend on the (n-1 )-th bin: pStateldxO’ (n) = (1-wO’(b_(n-1)))*pStateldxO(n-1) + w0’(b_(n-1))*b_(n-1) (3-53) pStateldxT(n) = (1 -w1’(b_(n-1 )))*pStateldx1 (n-1 ) + w1’(b_(n-1 ))*b_(n-1 ) (3-
[0058] 54)
[0059] Furthermore, the probability state used for coding is a weighted average of pStateldxO’ and pStateldxT (instead of a simple average as before): pStateldx = alpha*pStateldxO’ + (1-alpha)*pStateldxT, (3-55) where the parameter alpha is obtained from a LUT and depends on the context and on the slice type.
[0060] Finally, the initial state of some B or P-slices are inherited from previous slices instead of being re-initialized at each slice: more precisely, the two final states of each B-slice (or P-slice) are stored and used to initialize the next B-slice (or P-slice) in the same intra-period sharing the same temporal level and qp.
[0061] In current codec design, CABAC parameters are initialized for each context depending only on the slice type and qp. However, some syntax elements may exhibit different statistics depending, for example, on the prediction mode of the current block (CU). For example, residual coefficients in inter slices of type B are all coded using the same CABAC models; however, residual coefficients of CU-s using intra prediction should have statistics more similar to those of residual coefficients of intra slices (type I).
[0062] Furthermore, CABAC state carry-over is currently not applied to intra slices. It is generally proposed by the described embodiments, in certain situations, to use inter CABAC models in intra slices or intra CABAC models in inter slices. Furthermore, it is proposed to extend the carry over mechanism to intra slices.
[0063] Several aspects are proposed:
[0064] In at least one embodiment, use intra CABAC models to code residual coding information of intra predicted CU (Coding Unit) in inter slices.
[0065] In a variant, also use intra CABAC models to code syntax elements proper to intra predicted CU in inter slices.
[0066] In at least one further embodiment, use inter CABAC models to code residual coefficients of IBC (Intra Block Copy) or IBC-CIIP (where CIIP stands for Combined Inter and Intra Prediction) or IntraTMP (Intra Template Matching Prediction) or CCCM (Cross-Component Convolutional Model) / CCLM (Cross-Component Linear Model) predicted CU in intra slices.
[0067] In at least one further embodiment, use the same CABAC models to code block vectors of IBC predicted CU in inter and intra slices.
[0068] In at least one further embodiment, carry over CABAC state from l-slices to I- slices; possibly combine with at least one of aspects described in the above embodiments.
[0069] In at least one further embodiment, carry over CABAC state related to intra CU to Inter slice for elements related to intra coded CU.
[0070] The following embodiments and variants refer generically to “residual coding information” (or “block vector information”). This may include some or all the bins used to encode residual coefficients (SigFlag, ParFlag, GtxFIag) and / or the position of significant coefficients (SigGroup, lastX, lastY, CbfFlag, QtCbfFlag).
[0071] Some of the above mentioned bins are coded using separate CABAC contexts depending on some encoding choices: for example, specific context are employed to encode SigFlag, ParFlag, GtxFIag if the current block uses Transform Skip (TS) feature; other contexts are employed if the current block employs Low-Frequency Non- Separable Transform (LFNST) feature. These context may or may not be impacted by the proposed method.
[0072] In a variant, some or all contexts employed to encode block-specific feature flags (for example the flag for Transform Skip or MTS mode) are also impacted by the proposed method. Use of intra CABAC models in inter slices
[0073] In current codec design, residual coding information of inter-predicted slices (B- and P-type) are binarized, then the binary symbols are entropy-coded using CABAC models of inter slices. However, the residual coefficients of intra-coded coding units are more similar to residual coefficients of intra slices than to typical inter residuals.
[0074] It is proposed that some or all the binary symbols related to residual coding of intra-predicted coding units in inter slices are coded using CABAC models of intra slices instead, i.e. have a separate model from the same syntax elements used to encode residuals of inter coded CU. These bins may include those obtained from residual coefficients (like S ig Flag , ParFlag, GtxFIag, LastX, LastY) and / or those that carry an information about the transformation applied to a Transform Unit (like the flag for Multi Transform Selection or MTS, the flag for Low Frequency Non-Separable Transform or LFNST, etc.).
[0075] In a variant, it is proposed that, if a CU in an inter slice is coded via intra prediction, then syntax elements which are proper to intra coded CU (e.g. Decoder Intra Mode Derivation, or DIMD, flag, Most Probable Mode, or MPM, flag, intra prediction direction index etc.) are also similarly coded using CABAC models of intra slices.
[0076] In a variant, if a CU in an inter slice is coded via intra prediction, then it is proposed that mode flags which are signaled both in inter CU and intra CU (e.g. jointCbCr) are similarly coded using CABAC models of intra slices instead.
[0077] In a variant of any or all of the previous ones, instead of using CABAC intra models, new CABAC contexts are created for intra-related syntax elements in intrapredicted CU of inter slices. These new contexts can be either shared by all the B- slices, or specific contexts can be defined for B-slices where the B / P switch feature is applied.
[0078] Use of inter CABAC models in intra slices
[0079] In the way as the previous section, the residual coefficients of IBC or IntraTMP or IBC-CIIP or CCCM / CCLM predicted coding units are more similar to those of inter slices than to typical intra residuals. It is proposed that some or all the binary symbols related to residual coding of IBC or IntraTMP or I BC-CI IP or CCCM / CCLM predicted coding units in intra slices are coded using CABAC models of inter slices instead, i.e., new contexts are used in intra slices for block mode IBC or intraTMP. These bins may include those obtained from residual coefficients (like S ig Flag , ParFlag, GtxFIag, LastX, LastY) and / or those that carry any information about the transformation applied to a Transform Unit (like flags for MTS, LFNST etc.).
[0080] In a variant, instead of using CABAC models of B-slices, the encoder can signal to use CABAC models of P-slices. The choice of switching to P-slice models can be signaled at the beginning of each slice via a flag, similar to the currently used B / P switch mechanism.
[0081] In a variant, instead of using CABAC inter models, new CABAC contexts are created for syntax elements related to residual coefficients in IBC or IntraTMP or I BC- CI IP predicted CU of intra slices.
[0082] In a variant, the described algorithm is only applied to a subset of the proposed prediction modes (IBC, IntraTMP, I BC-CI IP, CCCM, CCLM).
[0083] CABAC coding of IBC block vectors
[0084] In the same spirit as the previous sections, the coding of block vectors (bv) information is addressed next. The current codec design prescribes coding all motion vector differences (mvd) and block vector differences (bvd) in inter slices with the same CABAC models and logic, while all block vectors in intra slices (namely, those defined by IBC predicted CU) are coded using a different model.
[0085] However, block vectors of IBC predicted CU in inter slices are more similar to other mv defined by IBC predicted CU (namely, in intra slices) than to typical inter prediction motion vectors.
[0086] It is proposed that all block vectors difference defined by IBC predicted CU (regardless of the slice type) use the same CABAC models (for example, those currently used in intra slices), while other motion vectors in inter slices use distinct models.
[0087] In another variant, not only the context for IBC bvd coding is separated from usual mvd of inter block, but the coding process is also adapted to the characteristics of the bvd in IBC mode. Indeed, the maximum mvd length for normal inter block is for typically set to 2A15 so the maximum number of bits is 15+2 (2 bits for fractional mvd). In the case of IBC, the area reachable by a block is much smaller, typically 2 CTU, typically 2*256 pixels, so the maximum number of bits to represent a bvd of IBC is 9+2. The Rice Golomb code to encode a mvd is then adapted to stop at the maximum number of bits for an IBC bvd.
[0088] CABAC state carry over for intra slices
[0089] In the current codec design, CABAC state carry over is only implemented for inter slices. It is proposed that this mechanism is extended to intra slices. In order for Instantaneous Decoding Refresh (IDR) pictures to be independently decodable, no carry over should be performed onto those frames. The main idea is to carry over the states for syntax element of intra slices which are relevant in an inter slice, for example the syntax associated with the intra coded blocks, especially the residuals coefficients coding.
[0090] Figure 4 depicts the base proposed carry over scheme for intra slices. Solid boxes indicate syntax elements whose related CABAC contexts should be initialized with inter parameters according to previous embodiments, and dashed boxes indicate those syntax elements initialized with intra parameters.
[0091] In a variant, carry over is performed from an intra slice to a subsequent intra slice which is not an IDR.
[0092] In a variant, carry over is performed from an intra slice to a subsequent intra slice which is not an IDR, or to the following inter slice. In the latter case, only CABAC states for syntax elements with a shared inter / intra model as defined in Section 4.1 , 4.2 and / or 4.3 are reported. In a variant, for a given inter slice, the intra slice from which the CABAC carry over is performed is an intra reference picture for that slice.
[0093] In a variant, carry over is also performed from an inter slice of highest temporal level BO to a subsequent intra slice. In this case, only CABAC states for syntax elements with a shared inter / intra model as defined in Section 4.1 , 4.2 and / or 4.3 are reported.
[0094] In a variant, carry over is also performed from an intra (or inter) slice to a subsequent inter (or intra) slice, where the QP differences between these two slices below a predefined threshold. In this case, only CABAC states for syntax elements with a shared inter / intra model as defined in the previous three sections are reported.
[0095] One embodiment of a method 500 under the general aspects described here is shown in Figure 5. The method commences at start block 501 and control proceeds to block 510 for coding binary symbols obtained from residual coefficients of video blocks coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode. Control proceeds from block 510 to block 520 for encoding the video block using said CABAC models.
[0096] One embodiment of a method 600 under the general aspects described here is shown in Figure 6. The method commences at start block 601 and control proceeds to block 610 for decoding binary symbols obtained from residual coefficients of video blocks coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode. Control proceeds from block 610 to block 620 for decoding the video block using said CABAC models.
[0097] Figure 7 shows one embodiment of an apparatus 700 for encoding, decoding, compressing or decompressing video data using coding of intra geometric partition mode with template matching. The apparatus comprises Processor 710 and can be interconnected to a memory 720 through at least one port. Both Processor 710 and memory 720 can also have one or more additional interconnections to external connections.
[0098] Processor 710 is also configured to either insert or receive information in a bitstream and, either compressing, encoding, or decoding using any of the described aspects.
[0099] The embodiments described here include a variety of aspects, including tools, features, embodiments, models, approaches, etc. Many of these aspects are described with specificity and, at least to show the individual characteristics, are often described in a manner that may sound limiting. However, this is for purposes of clarity in description, and does not limit the application or scope of those aspects. Indeed, all of the different aspects can be combined and interchanged to provide further aspects. Moreover, the aspects can be combined and interchanged with aspects described in earlier filings as well.
[0100] The aspects described and contemplated in this application can be implemented in many different forms. Figures 8, 9, and 10 provide some embodiments, but other embodiments are contemplated and the discussion of Figures 8, 9, and 10 does not limit the breadth of the implementations. At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting a bitstream generated or encoded. These and other aspects can be implemented as a method, an apparatus, a computer readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the methods described, and / or a computer readable storage medium having stored thereon a bitstream generated according to any of the methods described.
[0101] In the present application, the terms “reconstructed” and “decoded” may be used interchangeably, the terms “pixel” and “sample” may be used interchangeably, the terms “image,” “picture” and “frame” may be used interchangeably. Usually, but not necessarily, the term “reconstructed” is used at the encoder side while “decoded” is used at the decoder side.
[0102] Various methods are described herein, and each of the methods comprises one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and / or use of specific steps and / or actions may be modified or combined.
[0103] Various methods and other aspects described in this application can be used to modify modules, for example, the intra prediction, entropy coding, and / or decoding modules (160, 260, 145, 230), of a video encoder 100 and decoder 200 as shown in Figure 8 and Figure 9. Moreover, the present aspects are not limited to WC or HEVC, and can be applied, for example, to other standards and recommendations, whether pre-existing or future-developed, and extensions of any such standards and recommendations (including WC and HEVC). Unless indicated otherwise, or technically precluded, the aspects described in this application can be used individually or in combination.
[0104] Various numeric values are used in the present application. The specific values are for example purposes and the aspects described are not limited to these specific values.
[0105] Figure 8 illustrates an encoder 100. Variations of this encoder 100 are contemplated, but the encoder 100 is described below for purposes of clarity without describing all expected variations.
[0106] Before being encoded, the video sequence may go through pre-encoding processing (101), for example, applying a color transform to the input color picture (e.g., conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to get a signal distribution more resilient to compression (for instance using a histogram equalization of one of the color components). Metadata can be associated with the pre-processing and attached to the bitstream.
[0107] In the encoder 100, a picture is encoded by the encoder elements as described below. The picture to be encoded is partitioned (102) and processed in units of, for example, CUs. Each unit is encoded using, for example, either an intra or inter mode. When a unit is encoded in an intra mode, it performs intra prediction (160). In an inter mode, motion estimation (175) and compensation (170) are performed. The encoder decides (105) which one of the intra mode or inter mode to use for encoding the unit, and indicates the intra / inter decision by, for example, a prediction mode flag. Prediction residuals are calculated, for example, by subtracting (110) the predicted block from the original image block.
[0108] The prediction residuals are then transformed (125) and quantized (130). The quantized transform coefficients, as well as motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. The encoder can skip the transform and apply quantization directly to the non-transformed residual signal. The encoder can bypass both transform and quantization, i.e., the residual is coded directly without the application of the transform or quantization processes.
[0109] The encoder decodes an encoded block to provide a reference for further predictions. The quantized transform coefficients are de-quantized (140) and inverse transformed (150) to decode prediction residuals. Combining (155) the decoded prediction residuals and the predicted block, an image block is reconstructed. In-loop filters (165) are applied to the reconstructed picture to perform, for example, deblocking / SAO (Sample Adaptive Offset) filtering to reduce encoding artifacts. The filtered image is stored at a reference picture buffer (180).
[0110] Figure 9 illustrates a block diagram of a video decoder 200. In the decoder 200, a bitstream is decoded by the decoder elements as described below. Video decoder 200 generally performs a decoding pass reciprocal to the encoding pass as described in Figure 8. The encoder 100 also generally performs video decoding as part of encoding video data.
[0111] In particular, the input of the decoder includes a video bitstream, which can be generated by video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors, and other coded information. The picture partition information indicates how the picture is partitioned. The decoder may therefore divide (235) the picture according to the decoded picture partitioning information. The transform coefficients are de-quantized (240) and inverse transformed (250) to decode the prediction residuals. Combining (255) the decoded prediction residuals and the predicted block, an image block is reconstructed. The predicted block can be obtained (270) from intra prediction (260) or motion- compensated prediction (i.e. , inter prediction) (275). In-loop filters (265) are applied to the reconstructed image. The filtered image is stored at a reference picture buffer (280).
[0112] The decoded picture can further go through post-decoding processing (285), for example, an inverse color transform (e.g. conversion from YcbCr 4:2:0 to RGB 4:4:4) or an inverse remapping performing the inverse of the remapping process performed in the pre-encoding processing (101). The post-decoding processing can use metadata derived in the pre-encoding processing and signaled in the bitstream.
[0113] Figure 10 illustrates a block diagram of an example of a system in which various aspects and embodiments are implemented. System 1000 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances, and servers. Elements of system 1000, singly or in combination, can be embodied in a single integrated circuit (IC), multiple ICs, and / or discrete components. For example, in at least one embodiment, the processing and encoder / decoder elements of system 1000 are distributed across multiple ICs and / or discrete components. In various embodiments, the system 1000 is communicatively coupled to one or more other systems, or other electronic devices, via, for example, a communications bus or through dedicated input and / or output ports. In various embodiments, the system 1000 is configured to implement one or more of the aspects described in this document.
[0114] The system 1000 includes at least one processor 1010 configured to execute instructions loaded therein for implementing, for example, the various aspects described in this document. Processor 1010 can include embedded memory, input output interface, and various other circuitries as known in the art. The system 1000 includes at least one memory 1020 (e.g., a volatile memory device, and / or a nonvolatile memory device). System 1000 includes a storage device 1040, which can include non-volatile memory and / or volatile memory, including, but not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, magnetic disk drive, and / or optical disk drive. The storage device 1040 can include an internal storage device, an attached storage device (including detachable and non-detachable storage devices), and / or a network accessible storage device, as non-limiting examples.
[0115] System 1000 includes an encoder / decoder module 1030 configured, for example, to process data to provide an encoded video or decoded video, and the encoder / decoder module 1030 can include its own processor and memory. The encoder / decoder module 1030 represents module(s) that can be included in a device to perform the encoding and / or decoding functions. As is known, a device can include one or both of the encoding and decoding modules. Additionally, encoder / decoder module 1030 can be implemented as a separate element of system 1000 or can be incorporated within processor 1010 as a combination of hardware and software as known to those skilled in the art.
[0116] Program code to be loaded onto processor 1010 or encoder / decoder 1030 to perform the various aspects described in this document can be stored in storage device 1040 and subsequently loaded onto memory 1020 for execution by processor 1010. In accordance with various embodiments, one or more of processor 1010, memory 1020, storage device 1040, and encoder / decoder module 1030 can store one or more of various items during the performance of the processes described in this document. Such stored items can include, but are not limited to, the input video, the decoded video or portions of the decoded video, the bitstream, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.
[0117] In some embodiments, memory inside of the processor 1010 and / or the encoder / decoder module 1030 is used to store instructions and to provide working memory for processing that is needed during encoding or decoding. In other embodiments, however, a memory external to the processing device (for example, the processing device can be either the processor 1010 or the encoder / decoder module 1030) is used for one or more of these functions. The external memory can be the memory 1020 and / or the storage device 1040, for example, a dynamic volatile memory and / or a non-volatile flash memory. In several embodiments, an external non-volatile flash memory is used to store the operating system of, for example, a television. In at least one embodiment, a fast external dynamic volatile memory such as a RAM is used as working memory for video coding and decoding operations, such as for MPEG-2 (MPEG refers to the Moving Picture Experts Group, MPEG-2 is also referred to as ISO / IEC 13818, and 13818-1 is also known as H.222, and 13818-2 is also known as H.262), HEVC (HEVC refers to High Efficiency Video Coding, also known as H.265 and MPEG-H Part 2), or VVC (Versatile Video Coding, a new standard being developed by JVET, the Joint Video Experts Team).
[0118] The input to the elements of system 1000 can be provided through various input devices as indicated in block 1130. Such input devices include, but are not limited to, (i) a radio frequency (RF) portion that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a Component (COMP) input terminal (or a set of COMP input terminals), (iii) a Universal Serial Bus (USB) input terminal, and / or (iv) a High Definition Multimedia Interface (HDMI) input terminal. Other examples, not shown in Figure 10, include composite video.
[0119] In various embodiments, the input devices of block 1130 have associated respective input processing elements as known in the art. For example, the RF portion can be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) downconverting the selected signal, (iii) band-limiting again to a narrower band of frequencies to select (for example) a signal frequency band which can be referred to as a channel in certain embodiments, (iv) demodulating the downconverted and bandlimited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets. The RF portion of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band-limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers. The RF portion can include a tuner that performs various of these functions, including, for example, downconverting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband. In one set-top box embodiment, the RF portion and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, downconverting, and filtering again to a desired frequency band. Various embodiments rearrange the order of the above-described (and other) elements, remove some of these elements, and / or add other elements performing similar or different functions. Adding elements can include inserting elements in between existing elements, such as, for example, inserting amplifiers and an analog-to-digital converter. In various embodiments, the RF portion includes an antenna.
[0120] Additionally, the USB and / or HDMI terminals can include respective interface processors for connecting system 1000 to other electronic devices across USB and / or HDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, can be implemented, for example, within a separate input processing IC or within processor 1010 as necessary. Similarly, aspects of USB or HDMI interface processing can be implemented within separate interface les or within processor 1010 as necessary. The demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, processor 1010, and encoder / decoder 1030 operating in combination with the memory and storage elements to process the datastream as necessary for presentation on an output device.
[0121] Various elements of system 1000 can be provided within an integrated housing, Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangement, for example, an internal bus as known in the art, including the Inter-IC (I2C) bus, wiring, and printed circuit boards.
[0122] The system 1000 includes communication interface 1050 that enables communication with other devices via communication channel 1060. The communication interface 1050 can include, but is not limited to, a transceiver configured to transmit and to receive data over communication channel 1060. The communication interface 1050 can include, but is not limited to, a modem or network card and the communication channel 1060 can be implemented, for example, within a wired and / or a wireless medium.
[0123] Data is streamed, or otherwise provided, to the system 1000, in various embodiments, using a wireless network such as a Wi-Fi network, for example IEEE 802.11 (IEEE refers to the Institute of Electrical and Electronics Engineers). The WiFi signal of these embodiments is received over the communications channel 1060 and the communications interface 1050 which are adapted for Wi-Fi communications. The communications channel 1060 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 1000 using a set-top box that delivers the data over the HDMI connection of the input block 1130. Still other embodiments provide streamed data to the system 1000 using the RF connection of the input block 1130. As indicated above, various embodiments provide data in a nonstreaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network.
[0124] The system 1000 can provide an output signal to various output devices, including a display 1100, speakers 1110, and other peripheral devices 1120. The display 1100 of various embodiments includes one or more of, for example, a touchscreen display, an organic light-emitting diode (OLED) display, a curved display, and / or a foldable display. The display 1100 can be for a television, a tablet, a laptop, a cell phone (mobile phone), or another device. The display 1100 can also be integrated with other components (for example, as in a smart phone), or separate (for example, an external monitor for a laptop). The other peripheral devices 1120 include, in various examples of embodiments, one or more of a stand-alone digital video disc (or digital versatile disc) (DVR, for both terms), a disk player, a stereo system, and / or a lighting system. Various embodiments use one or more peripheral devices 1120 that provide a function based on the output of the system 1000. For example, a disk player performs the function of playing the output of the system 1000.
[0125] In various embodiments, control signals are communicated between the system 1000 and the display 1100, speakers 1110, or other peripheral devices 1120 using signaling such as AV.Link, Consumer Electronics Control (CEC), or other communications protocols that enable device-to-device control with or without user intervention. The output devices can be communicatively coupled to system 1000 via dedicated connections through respective interfaces 1070, 1080, and 1090. Alternatively, the output devices can be connected to system 1000 using the communications channel 1060 via the communications interface 1050. The display 1100 and speakers 1110 can be integrated in a single unit with the other components of system 1000 in an electronic device such as, for example, a television. In various embodiments, the display interface 1070 includes a display driver, such as, for example, a timing controller (T Con) chip. The display 1100 and speaker 1110 can alternatively be separate from one or more of the other components, for example, if the RF portion of input 1130 is part of a separate set-top box. In various embodiments in which the display 1100 and speakers 1110 are external components, the output signal can be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs.
[0126] The embodiments can be carried out by computer software implemented by the processor 1010 or by hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments can be implemented by one or more integrated circuits. The memory 1020 can be of any type appropriate to the technical environment and can be implemented using any appropriate data storage technology, such as optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory, as non-limiting examples. The processor 1010 can be of any type appropriate to the technical environment, and can encompass one or more of microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as nonlimiting examples.
[0127] Various implementations involve decoding. “Decoding”, as used in this application, can encompass all or part of the processes performed, for example, on a received encoded sequence to produce a final output suitable for display. In various embodiments, such processes include one or more of the processes typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transformation, and differential decoding. In various embodiments, such processes also, or alternatively, include processes performed by a decoder of various implementations described in this application.
[0128] As further examples, in one embodiment “decoding” refers only to entropy decoding, in another embodiment “decoding” refers only to differential decoding, and in another embodiment “decoding” refers to a combination of entropy decoding and differential decoding. Whether the phrase “decoding process” is intended to refer specifically to a subset of operations or generally to the broader decoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.
[0129] Various implementations involve encoding. In an analogous way to the above discussion about “decoding”, “encoding” as used in this application can encompass all or part of the processes performed, for example, on an input video sequence to produce an encoded bitstream. In various embodiments, such processes include one or more of the processes typically performed by an encoder, for example, partitioning, differential encoding, transformation, quantization, and entropy encoding. In various embodiments, such processes also, or alternatively, include processes performed by an encoder of various implementations described in this application.
[0130] As further examples, in one embodiment “encoding” refers only to entropy encoding, in another embodiment “encoding” refers only to differential encoding, and in another embodiment “encoding” refers to a combination of differential encoding and entropy encoding. Whether the phrase “encoding process” is intended to refer specifically to a subset of operations or generally to the broader encoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.
[0131] Note that the syntax elements as used herein are descriptive terms. As such, they do not preclude the use of other syntax element names.
[0132] When a figure is presented as a flow diagram, it should be understood that it also provides a block diagram of a corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow diagram of a corresponding method / process.
[0133] Various embodiments may refer to parametric models or rate distortion optimization. In particular, during the encoding process, the balance or trade-off between the rate and distortion is usually considered, often given the constraints of computational complexity. It can be measured through a Rate Distortion Optimization (RDO) metric, or through Least Mean Square (LMS), Mean of Absolute Errors (MAE), or other such measurements. Rate distortion optimization is usually formulated as minimizing a rate distortion function, which is a weighted sum of the rate and of the distortion. There are different approaches to solve the rate distortion optimization problem. For example, the approaches may be based on an extensive testing of all encoding options, including all considered modes or coding parameters values, with a complete evaluation of their coding cost and related distortion of the reconstructed signal after coding and decoding. Faster approaches may also be used, to save encoding complexity, in particular with computation of an approximated distortion based on the prediction or the prediction residual signal, not the reconstructed one. Mix of these two approaches can also be used, such as by using an approximated distortion for only some of the possible encoding options, and a complete distortion for other encoding options. Other approaches only evaluate a subset of the possible encoding options. More generally, many approaches employ any of a variety of techniques to perform the optimization, but the optimization is not necessarily a complete evaluation of both the coding cost and related distortion.
[0134] The implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program). An apparatus can be implemented in, for example, appropriate hardware, software, and firmware. The methods can be implemented in, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable / personal digital assistants (“PDAs”), and other devices that facilitate communication of information between end-users.
[0135] Reference to “one embodiment” or “an embodiment” or “one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” or “in one implementation” or “in an implementation”, as well any other variations, appearing in various places throughout this application are not necessarily all referring to the same embodiment.
[0136] Additionally, this application may refer to “determining” various pieces of information. Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, or retrieving the information from memory.
[0137] Further, this application may refer to “accessing” various pieces of information. Accessing the information can include one or more of, for example, receiving the information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.
[0138] Additionally, this application may refer to “receiving” various pieces of information. Receiving is, as with “accessing”, intended to be a broad term. Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory). Further, “receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information.
[0139] It is to be appreciated that the use of any of the following “ / ”, “and / or”, and “at least one of”, for example, in the cases of “A / B”, “A and / or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are listed.
[0140] Also, as used herein, the word “signal” refers to, among other things, indicating something to a corresponding decoder. For example, in certain embodiments the encoder signals a particular one of a plurality of transforms, coding modes or flags. In this way, in an embodiment the same transform, parameter, or mode is used at both the encoder side and the decoder side. Thus, for example, an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as others, then signaling can be used without transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter. By avoiding transmission of any actual functions, a bit savings is realized in various embodiments. It is to be appreciated that signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word “signal”, the word “signal” can also be used herein as a noun.
[0141] As will be evident to one of ordinary skill in the art, implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted. The information can include, for example, instructions for performing a method, or data produced by one of the described implementations. For example, a signal can be formatted to carry the bitstream of a described embodiment. Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting can include, for example, encoding a data stream and modulating a carrier with the encoded data stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium.
[0142] The preceding sections describe a number of embodiments, across various claim categories and types. Features of these embodiments can be provided alone or in any combination. Further, embodiments can include one or more of the following features, devices, or aspects, alone or in any combination, across various claim categories and types:
[0143] At least one embodiment comprises encoding or decoding a video block by using bi-prediction with spatially varying weights per sample based on a template of samples around the video block.
[0144] At least one embodiment comprises the above embodiment using regression to derive weights for the bi-prediction.
[0145] At least one embodiment further comprises determining of weighting parameters based on minimizing a distance between reconstructed samples of the template and prediction samples of the template.
[0146] At least one embodiment further comprises the above embodiments wherein a weight for a sample is rounded, clipped, limited in range, or set to a specified value based on position or weight value.
[0147] At least one embodiment further comprises the above embodiments wherein determination of weighting parameters is done using regression in merge mode only.
[0148] At least one embodiment comprises the above embodiments wherein a template comprises a plurality of samples neighboring the video block, the plurality of samples taken from along a top row or a left row or both. At least one embodiment comprises any encoding or decoding operation based on the above operations.
[0149] At least one embodiment comprises performing encoding or decoding with the aforementioned methods on a sub-block.
[0150] At least one embodiment comprises a bitstream or signal that includes one or more of the described syntax elements, or variations thereof.
[0151] At least one embodiment comprises a bitstream or signal that includes syntax conveying information generated according to any of the embodiments described.
[0152] At least one embodiment comprises creating and / or transmitting and / or receiving and / or decoding according to any of the embodiments described.
[0153] At least one embodiment comprises a method, process, apparatus, medium storing instructions, medium storing data, or signal according to any of the embodiments described.
[0154] At least one embodiment comprises inserting in the signaling syntax elements that enable the decoder to determine decoding information in a manner corresponding to that used by an encoder.
[0155] At least one embodiment comprises creating and / or transmitting and / or receiving and / or decoding a bitstream or signal that includes one or more of the described syntax elements, or variations thereof.
[0156] At least one embodiment comprises a TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) according to any of the embodiments described.
[0157] At least one embodiment comprises a TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) determination according to any of the embodiments described, and that displays (e.g., using a monitor, screen, or other type of display) a resulting image.
[0158] At least one embodiment comprises a TV, set-top box, cell phone, tablet, or other electronic device that selects, bandlimits, or tunes (e.g., using a tuner) a channel to receive a signal including an encoded image, and performs transform method(s) according to any of the embodiments described.
[0159] At least one embodiment comprises a TV, set-top box, cell phone, tablet, or other electronic device that receives (e.g., using an antenna) a signal over the air that includes an encoded image, and performs transform method(s).
Claims
CLAIMS1. A method, comprising: coding binary symbols obtained from residual coefficients of a video block coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, encoding the video block using said CABAC models.
2. An apparatus, comprising: a memory, and a processor, configured to: code binary symbols obtained from residual coefficients of a video block coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, encode the video block using said CABAC models.
3. A method, comprising: decoding binary symbols obtained from residual coefficients of a video block coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, decoding the video block using said CABAC models.
4. An apparatus, comprising: a memory, and a processor, configured to: decode binary symbols obtained from residual coefficients of a video block coded in a first mode but in slices of a second mode using CABAC models of slices of the first mode; and, decode the video block using said CABAC models.
5. The method of any one of Claim 1 or 3, or the apparatus of any one of Claim 2 or 4, wherein the first mode is inter coded and the second mode is intra coded.
6. The method of any one of Claim 1 or 3, or the apparatus of any one of Claim 2 or 4, wherein the first mode is intra coded and the second mode is inter coded.
7. The method of any one of Claim 1 , 3, 5 or 6, or the apparatus of any one of Claim 2, 4, 5 or 6, further comprising coding block vector differences defined by IBC predicted coding units using the same CABAC models and using other models for motion vectors in inter slices.
8. The method of any one of Claim 1 , 3, 5, 6, or 7, or the apparatus of any one of Claim 2, 4, 5, 6, or 7, wherein the first mode used to code the video block is Combined Inter and Intra Prediction (CIIP).
9. The method of any one of Claim 1 , 3, 5, 6, or 7, or the apparatus of any one of Claim 2, 4, 5, 6, or 7, wherein CABAC context are created for syntax elements related to residual coefficients in IBC or in IntraTMP predicted blocks of intra slices.
10. The method of any one of Claim 1 , 3, or 5 through 9, or the apparatus of any one of Claim 2, 4, or 5 through 9, wherein states of syntax elements of intra coded slices in an inter coded slice are carried over for use in a subsequent inter coded slice.
11. The method or the apparatus of Claim 10, wherein carry over is performed from an intra slice to a subsequent intra slice which is not an I DR, or to the following inter slice.
12. A device comprising: an apparatus according to Claim 4; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, and (iii) a display configured to display an output representative of a video block.
13. A non-transitory computer readable medium containing data content generated according to the method of any one of claims 1 , or 5 through 11 , or by the apparatus of any one of claims 2, or 5 through 11 , for playback using a processor. n14. A signal comprising video data generated according to the method of any one of claims 1 , or 5 through 11 , or by the apparatus of any one of claims 2, or 5 through 11 , for playback using a processor.
15. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method of any one of claims 1 , 3, or 5 through 11 .