Digital circuit, method of storing parameters, and method of outputting parameters

Abstract

A digital circuit according of the invention is a digital circuit provided in a semiconductor device to control analog elements. The digital circuit includes a digital communication circuit, a random access memory, a temporary parameter store, and an output circuit. The digital communication circuit receives a control message including a command and data in one communication transaction. The random access memory stores a look-up table. The look-up table has an address and a data set corresponding to the address. The data set includes a plurality of analog-element control parameters. The temporary parameter store temporarily stores the data received by the digital communication circuit in the communication transaction. The temporary parameter store prepares a data set to be stored to one address of the look-up table. The output circuit outputs a setting-parameter.

Description

[DESCRIPTION][Title of Invention]DIGITAL CIRCUIT, METHOD OF STORING PARAMETERS, AND METHOD OF OUTPUTTING PARAMETERS[Technical Field]

[0001] The present invention relates to a digital circuit, a method of storing parameters, and a method of outputting parameters.[Background Art]

[0002] In order to increase a capacity of wireless communication, a frequency band being used is becoming wider and is becoming higher in frequency. Particularly, development of wireless communication devices using a millimeter waveband is progressing rapidly. For example, use of millimeter-wave wireless communication devices has been studied as mobile communication networks, a small cell linked to mobile communication networks, wireless access networks of wireless Internet service providers (WISPs), or as wireless backhaul links such as wireless base stations, radio repeater stations, or public wireless LAN communication access points.

[0003] Non-Patent Literature 1 and 2 disclose a phased array antenna module for millimeterwave wireless communication as a millimeter-wave wireless communication device. This phased array antenna module has a beamformer integrated circuit (IC) with a lookup table. Non-Patent Literature 2 discloses a look-up table that can select 32 beams by referring to addresses corresponding to data in the look-up table.Such a look-up table is stored in, for example, a static random access memory (SRAM) constituting the beamformer IC.[Citation List][Patent Literature]

[0004] [Non-Patent Literature 1]Bodhisatwa Sadhu et al. “The More (Antennas), the Merrier: A Survey of Silicon-Based mm-Wave Phased Arrays Using Multi-IC Scaling,” IEEE Microwave Magazine, pp. 32- 50, No. 12, 2019[Non-Patent Literature 2]Alberto Valdes-Garcia et al., “A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications,” IEEE J. Solid-State Circuits, Vol. 45, No. 12, pp. 2757-2773, Dec. 2010.[Summary of Invention] [Technical Problem]

[0005] Non-Patent Literature 1 discloses various phased array antennas. The phased array antenna of Non-Patent Literature 1 has a plurality of antenna elements such as 64 or 256. An SRAM provided in a digital control unit is utilized as a look-up table and stores a beam table formed of a plurality of sets of phase setting values of phase shifters and gain setting values of variable gain amplifiers. Further, in Non-Patent Literature 1, phase shifter settings and variable gain amplifier settings are adjusted to change phases and intensities of signals supplied to the plurality of antenna elements. Therefore, a beam oriented in an arbitrary direction can be generated and intensity tapering can be realized.

[0006] Non-Patent Literature 2 discloses a specific example of the phased array antenna. In the configuration of the phased array antenna, a phase shifter setting is 6 bits width, and a variable gain amplifier setting is 4 bits width.In such a phased array antenna, if the number of items of beam patterns stored in a beam table is increased, or if the number of bits of a gain setting value of the variable gain amplifier or a phase setting value of the phase shifter is increased, there is a problem that an SRAM area increases, thereby increasing costs of the IC chip.

[0007] The present invention has been made in consideration of such circumstances, and an objective of the present invention is to reduce an SRAM area to reduce costs of the IC chip even if the number of bits used for analog-element control is increased or the number of items of control set values is increased.

[0008] A digital circuit according of one aspect of the invention is a digital circuit provided in a semiconductor device to control analog elements. The digital circuit includes a digital communication circuit, a random access memory, a temporary parameter store, and an output circuit. The digital communication circuit receives a control message including a command and data in one communication transaction. The random access memory stores a look-up table. The look-up table has an address and a data set corresponding to the address. The data set includes a plurality of analog-element control parameters. The temporary parameter store temporarily stores the data received by the digital communication circuit in the communication transaction and / or prepares a data set to be stored to one address of the look-up table. The output circuit outputs a settingparameter.

[0009] In the digital circuit according of one aspect of the invention, the semiconductor device may be a beamformer. The analog-element control parameters include a first parameter and a second parameter. One of the first parameter and the second parameter may be a gain setting value. The other of the first parameter and the second parameter may be a phase setting value. One of the analog elements may be a variable gain amplifier controlled by using the gain setting value. Another of the analog elements may be a phase shifter controlled by using the phase setting value.

[0010] The digital circuit according of one aspect of the invention may further include a first circuit, a second circuit, and a third circuit. The first circuit may receive a first- parameter writing command and may store the first parameter in the temporary parameter store in accordance with the first-parameter writing command. The second circuit may receive a second-parameter writing command and may store the second parameter in the temporary parameter store in accordance with the second-parameter writing command. The third circuit may receive a look-up-table writing command. The look-up-table writing command may specify a to-be-written address. The third circuit may write the first parameter and the second parameter into the to-be-written address of the look-up table in accordance with the look-up-table writing command.

[0011] The digital circuit according of one aspect of the invention may further include a first circuit, a fourth circuit, and a fifth circuit. The first circuit may receive a first-parameter wnting command and may store the first parameter in the temporary parameter store in accordance with the first-parameter writing command. The fourth circuit may receive a look-up-table-writing-address specifying command and may store a to-be-written address in the temporary parameter store in accordance with the look-up-table-writing- address specifying command. The fifth circuit may receive a second-parameter writing command and may write the first parameter and the second parameter into the to-be- written address of the look-up table in accordance with the second-parameter writing command.

[0012] The digital circuit according of one aspect of the invention may further include a sixth circuit, and a seventh circuit. The sixth circuit may receive a first-parameter-reading- address specifying command, may read out the first parameter from an address that the first parameter to be read-out in accordance with the first-parameter-reading-address specifying command, and may store the first parameter in the temporary parameter store in accordance with the first-parameter-reading-address specifying command. The seventh circuit may receive a second-parameter-reading-address-specifying-and- parameter-outputting command, may read out the second parameter from an address that the second parameter to be read-out in accordance with the second-parameter- readmg-address-specifying-and-parameter-outputting command, and may output the first parameter stored in the temporary parameter store and the second parameter read from the address that the second parameter to be read-out to the analog elements in accordance with the second-parameter-reading-address-specifying-and-parameter- outputting command.

[0013] A method of storing parameters of one aspect of the invention is a method for controlling analog elements in a look-up table stored in a random access memory provided in a semiconductor device. The parameter storing method includes a first step, a second step, and a third step. The first step is to send first communication transaction including a first parameter and a first command to the semiconductor device. In the first step, the first command is to instruct the semiconductor device to store the firstparameter in a temporary parameter store. The second step is to send second communication transaction including second data and a second command to the semiconductor device. The third step is to send third communication transaction including third data and a third command to the semiconductor device. In the third step, the third command is to instruct the semiconductor device to write the first parameter specified in the first step and a second parameter specified in the second step or the third step into the to-be-written address of the look-up table specified in the second step or the third step. In the parameter storing method, the first to third steps are carried out by sending communication transaction including a command and fixed bit width data to the semiconductor device.

[0014] In the parameter storing method of one aspect of the invention, the second data may be include the second parameter. The second command may instruct the semiconductor device to store the second parameter in the temporary parameter store. The third data may include a to-be-written address of the look-up table. The third command may instruct the semiconductor device to write the first parameter and the second parameter into the to-be-written address of the look-up table.

[0015] In the parameter storing method of one aspect of the invention, the second step may send a to-be-written address of the look-up table and a second command to the semiconductor device, by sending one or more communication transactions including a command and data. The second command may instruct the semiconductor device to store the to-be-written address in the temporary parameter store. The third data may include the second parameter. The third command may instruct the semiconductor device to wnte the first parameter and the second parameter into the to-be-written address of the look-up-table.

[0016] A method of outputting parameters of one aspect of the invention is a method for reading out a plurality of parameters and outputting the plurality of the parameters to analog elements. The plurality of the parameters are stored in a look-up table stored in a random access memory provided in a semiconductor device. The parameter outputting method includes a first step and a second step. The first step is to send firstcommunication transaction including a to-be-read-out-first-parameter address of the look-up table and a first command to a semiconductor device. In the first step, the first command is to instruct the semiconductor device to store a first parameter read out from the to-be-read-out-first-parameter address of the look-up table to a temporary parameter store. The second step is to send second communication transaction including a to-be- read-out-second-parameter address of the look-up table and a second command to a semiconductor device. In the second step, the second command is to instruct the semiconductor device to read out a second parameter from the to-be-read-out-second- parameter address of the look-up table and to output the first parameter and the second parameter to the analog elements. In the parameter outputting method, the first and second steps are carried out by sending communication transaction including a command and fixed bit width data to the semiconductor device.[Advantageous Effects of Invention]

[0017] According to the above-described aspect of the present invention, even if the number of bits used for analog-element control is increased or the number of items of control set values is increased, an SRAM area can be reduced, thereby reducing costs of the IC chip.[Brief Description of Drawings]

[0018] [FIG. 1]FIG. 1 is a system configuration diagram showing a configuration of a phased array antenna module according to a first embodiment of the present invention.[FIG. 2]FIG. 2 is a configuration diagram showing a configuration of a beamformer IC and connection between the beamformer IC and an antenna element according to the first embodiment of the present invention.[FIG. 3]FIG. 3 is a diagram schematically showing a step of specifying a to-be-read-out address of a look-up table to output a first parameter and a second parameter to an analog element in the beamformer IC according to the first embodiment of the present invention.[FIG. 4]FIG. 4 is a diagram schematically showing a step of storing the first parameter in a temporary parameter store in the beamformer 1C according to the first embodiment of the present invention.[FIG. 5]FIG. 5 is a diagram schematically showing a step of storing the second parameter in a temporary parameter store after the first parameter is stored in the temporary parameter store in the beamformer IC according to the first embodiment of the present invention. [FIG. 6]FIG. 6 is a diagram schematically showing a step of specifying a to-be-written address of the look-up table and specifying writing after the first parameter and the second parameter are stored in the temporary parameter stores in the beamformer IC according to the first embodiment of the present invention.[FIG. 7]FIG. 7 is a diagram schematically showing a step of storing a to-be-written address of a look-up table in a temporary parameter store after a first parameter is stored in a temporary parameter store in a beamformer IC according to a second embodiment of the present invention.[FIG. 8]FIG. 8 is a diagram schematically showing a step of specifying a second parameter and specifying writing after the first parameter and the to-be-written address of the look-up table are stored in the temporary parameter stores in the beamformer IC according to the second embodiment of the present invention.[FIG. 9]FIG. 9 is a diagram schematically showing a step of specifying a to-be-read-out-first- parameter address of a look-up table and storing a read first parameter in a temporary parameter store in a beamformer IC according to a third embodiment of the present invention.[FIG. 10]FIG. 10 is a diagram schematically showing a step of specifying a to-be-read-out- second-parameter address of the look-up table and outputting the first parameter and a second parameter to an analog element after the read first parameter is stored in thetemporary parameter store in the beamformer IC according to the third embodiment of the present invention.[FIG. 11]FIG. 11 is a table showing a configuration and an area in design of an SRAM having an integrated look-up table according to example 1 of the present invention.[FIG. 12]FIG. 12 is a table showing a configuration and an area in design of an SRAM having an integrated look-up table according to example 2 of the present invention.[FIG. 13]FIG. 13 is a table showing a configuration and an area in design of an SRAM having an integrated look-up table according to comparative example 1.[FIG. 14]FIG. 14 is a table showing configurations and areas in design of two SRAMs having two look-up tables according to comparative example 2.[FIG. 15]FIG. 15 is a table showing configurations and areas in design of two SRAMs having two look-up tables according to comparative example 3.[Description of Embodiments]

[0019] <First embodimentA phased array antenna module 1 according to a first embodiment of the present invention will be described with reference to the drawings.The phased array antenna module 1 is an example of a wireless communication device using a millimeter waveband and is an example of a module including a beamformer IC. The phased array antenna module 1 includes, for example, a plurality of integrated circuits (ICs) mounted on one surface of a circuit board such as a known printed circuit board, and an antenna array mounted on the other surface of the circuit board. The plurality of ICs and the antenna array constituting the phased array antenna module 1 are formed by using known materials and using known methods. Also, an electrical connection structure between the plurality of ICs and an electrical connection structure between the ICs and the antenna array are not particularly limited. A know n connection structure is employed as the electrical connection structure.

[0020] <Phased array antenna module 1>FIG. 1 is a system configuration diagram showing a configuration of the phased array antenna module 1.The phased array antenna module 1 includes eight beamformer ICs 10A, 10B, IOC, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer ICs lOA to 10H), an antenna array 20, a frequency conversion IC 30, and an RF signal coupler / splitter 40.

[0021] The phased array antenna module 1 is connected to a control device 50 via an RF signal line 51, a control line 52 and a power line 53. An RF signal is transmitted and received between the control device 50 and the phased array antenna module 1 via the RF signal line 51. The RF signal may be an IF signal with an intermediate frequency. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0022] The frequency conversion IC 30 is an IC that performs frequency conversion between the RF signal with an IF signal frequency and the RF signal with a frequency transmitted and received between the beamformer ICs 10A to 10H and the antenna array 20 when the RF signal transmitted and received via the RF signal line 51 is an IF signal.

[0023] The RF signal coupler / splitter 40 splits the RF signal output from the frequency conversion IC 30 to the beamformer ICs 10A to 10H. Also, the RF signal coupler / splitter 40 couples the RF signals received by the beamformer ICs 10A to 10H and inputs them to the frequency conversion IC 30.

[0024] <Beamformer ICs lOA to 10H>FIG. 2 is a configuration diagram showing a configuration of one of the beamformer ICs 10A to 10H and connection between one beamformer IC and an antenna element 21.The eight beamformer ICs 10A to 10H have the same configuration as each other. Therefore, in the following description, one of the beamformer ICs 10A to 10H, that is, a beamformer 1C 10, may be described. Description of the other seven beamformer ICs may be omitted.

[0025] The beamformer IC 10 includes 16 RF front ends 5A to 5P and a beamformer IC control circuit 6. The beamformer IC control circuit 6 is a digital circuit. This digital circuit mediates transmission and reception of communication messages related to control of the 16 RF front ends 5 A to 5P. Further, the digital circuit controls a plurality of analog elements not included in the 16 RF front ends 5 A to 5P in the beamformer IC 10. The 16 RF front ends 5 A to 5P have the same configuration as each other.Therefore, in the following description, one of the 16 RF front ends 5 A to 5P, that is, an RF front end 5, may be described. Description of the other 15 RF front ends may be omitted.The beamformer IC 10 is an example of a “semiconductor device” and a “beamformer.”

[0026] <Antenna element 21 >In one beamformer IC 10 shown in FIG. 2, the 16 RF front ends 5A to 5P are connected to 16 antenna elements 21A to 21P so that one antenna element 21 and one RF front end 5 have a one-to-one correspondence.The 16 antenna elements 21A to 21P have the same or similar configurations.Therefore, in the following description, one of the 16 antenna elements 21A to 21P, that is, the antenna element 21, may be described. Description of the other 15 antenna elements may be omitted. The antenna elements 21 A to 2 IP may have the same configuration as each other. Or, the antenna elements 21A to 21P may have slightly different configurations between a configuration of the antenna element for horizontally -polarized waves and a configuration of the antenna element for vertically- polarized waves.

[0027] <Overall antenna array 20>In one beamformer IC 10, the 16 RF front ends 5 A to 5P are connected to the 16 antenna elements 21 A to 21P to have a one-to-one correspondence. Thus, in the entirephased array antenna module 1 having the eight beamformer ICs 1OA to 10H, a total of 128 of the antenna elements 21 are connected to the 16 RF front ends 5 A to 5P in each of the eight beamformer ICs 10A to 10H.

[0028] <Control of antenna array 20 by beamformer ICs 10A to 10H>The 128 antenna elements 21 constituting the antenna array 20 are divided into 64 antenna elements 21 for transmitting and receiving horizontally-polarized radio waves and 64 antenna elements 21 for transmitting and receiving vertically-polarized radio waves.

[0029] The eight beamformer ICs 10A to 10H control transmission and reception of horizontally-polarized radio waves in the 64 antenna elements 21, and control transmission and reception of the vertically-polarized radio waves in the 64 antenna elements 21.For each of the horizontally -polarized radio waves and the vertically-polarized radio waves, the beamformer ICs 10A to 10H set a gain and a phase of each of the 64 antenna elements so that directions of combined radio waves transmitted or received from the 64 antenna elements 21 are in a predetermined direction.

[0030] <RF front end 5>Next, a configuration of one RF front end 5 will be described with reference to FIGS. 2 to 6.FIGS. 3 to 6 are diagrams for schematically showing each step related to an operation of the RF front end 5.The RF front end 5 includes a digital circuit 11, an analog circuit 12, and a static random access memory (SRAM) 13. In FIGS. 3 to 6, a first register 14 A, a second register 14B, one WEN line 15, eight address lines 16, five first data lines 17A, seven second data lines 17B, five gain setting lines 18A, seven phase setting lines 18B, five first register lines 19A, and seven second register lines 19B, which are included in the digital circuit 11, are shown in detail for explanation of the present embodiment.

[0031] Here, the digital circuit 11 including the SRAM 13, the first register 14 A, and the second register 14B is an example of “a digital circuit provided in a semiconductor device to control the plurality of antenna elements 21”.The digital circuit 11 includes a circuit that receives control messages each including a command and data in one communication transaction. The digital circuit 11 includes a circuit that is an example of a “digital communication circuit”.The SRAM 13 is a circuit that stores a look-up table. The SRAM 13 is an example of a “random access memory”.Each of the first register 14A and the second register 14B is a circuit that temporarily stores data received by the digital circuit 11 in a communication transaction and prepares a data set to be stored in one address of the look-up table. Each of the first register 14A and the second register 14B is an example of a “temporary parameter store”.The analog circuit 12 is a circuit that adjusts a gain and a phase of an RF signal according to setting-parameters and outputs the result to the antenna element 21. The analog circuit 12 includes a variable gain amplifier and a phase shifter. The gain setting terminals 12A includes five terminals and is connected to a variable gain amplifier. The phase setting terminals 12B includes seven terminals and is connected to a phase shifter. The RF front end 5 includes an output circuit that outputs the setting-parameters to the analog circuit 12.

[0032] The number of address lines 16 is eight as described above. Therefore, an address is 8 bits in one RF front end 5. Here, data transmitted through the address lines 16 is address data.Similarly, the number of each of the first data lines 17A, the gam setting lines 18 A, and the first register lines 19A is five. Therefore, 5-bit data transmission can be performed through the first data lines 17A, the gain setting lines 18A, and the first register lines 19A in one RF front end 5.

[0033] Similarly, the number of each of the second data lines 17B, the phase setting lines 18B, and the second register lines 19B is seven. Therefore, 7-bit data transmission can beperformed through the second data lines 17B, the phase setting lines 18B, and the second register lines 19B in one RF front end 5.

[0034] <Digital circuit 11>The digital circuit 11 performs transmission and reception of communication messages related to control between the control device 50 and the digital circuit 11 via the control line 52 and the beamformer IC control circuit 6. Also, the digital circuit 11 is controlled by the beamformer IC control circuit 6. The digital circuit 11 is a circuit that controls the RF front ends 5 on the basis of transmission and reception of communication messages or on the basis of the control from the beamformer IC control circuit 6. The digital circuit 11 includes the SRAM 13, the first register 14A, and the second register 14B. The digital circuit 11 is a circuit that writes data to the SRAM 13 and reads data from the SRAM 13 to control the analog circuit 12.In more detail for explanation of the present embodiment, FIGS. 3 to 6 show the first register 14A, the second register 14B, connection lines between the first register 14A and the SRAM 13, connection lines between the second register 14B and the SRAM 13, connection lines between the first register 14A and the gain setting terminals 12A of the analog circuit 12, connection lines between the SRAM 13 and the gain setting terminals 12A of the analog circuit 12, connection lines between the second register 14B and the phase setting terminals 12B of the analog circuit 12, and connection lines between the SRAM 13 and the phase setting terminals 12B of the analog circuit 12.In the configuration of the digital circuit 11 shown in FIGS. 3 to 6, not only the first register 14A, the second register 14B, and the above-described connection lines, but also one WEN circuit terminal 11W, five first data circuit terminals 11 A, seven second data circuit terminals 1 IB, and eight address circuit terminals 1 IC are shown as circuits constituting the digital circuit 11.

[0035] In FIGS. 3 to 6, the first register 14A and the second register 14B are shown to be circuits different from the digital circuit 11. In practice, the first register 14A and the second register 14B constitute a part of the digital circuit 11.

[0036] Communication performed in the first embodiment will be described.In the first embodiment, transmission and reception of communication messages related to control are performed by parallel communication. The present invention is not limited to the parallel communication. Serial communication such as SP1 and 12C may be performed. A single communication transaction of the communication messages includes commands, data, and additional information. The communication transaction has a fixed bit length. The commands are each a register address when instructing to write to or read from the register. Alternatively, the command is a numerical value that denotes an operation instruction to the beamformer IC 10 or the RF front end 5. The command and data have fixed lengths. In the first embodiment, the command is 8 bits and the data is 8 bits.

[0037] The digital circuit 11 sets the SRAM 13 to a write mode or a read mode using the WEN line 15.The digital circuit 11 sets write addresses or read addresses with respect to the SRAM 13 using the address lines 16. The digital circuit 11 directly sets write data in the SRAM 13. Alternatively, the digital circuit 11 sets write data in the SRAM 13 via the first register 14 A and the second register 14B. When write data is set with respect to the SRAM 13, the first register 14A and the second register 14B can hold the write data for a required period.

[0038] <Analog circuit 12>The analog circuit 12 is a circuit that causes the antenna element 21 connected to the RF front end 5 to transmit radio waves and receives radio waves from the antenna element 21.The analog circuit 12 sets a gain of a variable gain amplifier using a 5 -bit gam setting value output from the digital circuit 11 as an input value. Also, the analog circuit 12 sets a phase of a phase shifter using a 7-bit phase setting value output from the digital circuit 11 as an input value.The analog circuit 12 is an example of an “analog element”.The analog circuit 12 is an example of a phase shifter that is controlled using the phase setting value.Also, the analog circuit 12 is an example of a variable gain amplifier that is controlled using the gain setting value.

[0039] <SRAM 13>The SRAM 13 includes one WEN terminal 13W, eight address terminals 13C, and 12 data terminals. In the present embodiment, the 12 data terminals are classified into two groups of five first data terminals 13A and seven second data terminals 13B.In the present embodiment, an SRAM is used as a memory circuit that stores the lookup table, but other memory circuits may be used in place of the SRAM 13 as long as they are readable and writable semiconductor memories. For example, it is possible to use a register, a dynamic random access memory (DRAM), a flash memory, or the like.

[0040] <Look-up table>The look-up table is data stored in the SRAM 13. The look-up table has data including gain setting values and phase setting values indexed by addresses. In the data, the addresses, the gain setting values, and the phase setting values are associated with each other. In other words, in data forming the look-up table, one address, one gain setting value, and one phase setting value form one set, that is, one data set. The look-up table is formed of a plurality of data sets.

[0041] In other words, the look-up table includes an address and a data set corresponding to the address and containing a plurality of analog-element control parameters. The plurality of analog-element control parameters include a first parameter and a second parameter. Each of the gain setting value and the phase setting value is an example of an “analogelement control parameter”. Also, the gain setting value is an example of the “first parameter”. The phase setting value is an example of the “second parameter”.Further, when the gain setting value is the “second parameter,” the phase setting value is the “first parameter”.

[0042] As shown in FIG. 2, the beamformer IC 10 includes the 16 RF front ends 5, and appropriately sets the gain setting value to the variable gain amplifier and the phasesetting value to the phase shifter in each of the RF front ends 5. Therefore, beamforming is performed.In order to form one beam pattern of horizontally-polarized combined radio waves, 64 data sets are required. Here, one data set is formed of the gain setting value and the phase setting value.Similarly, in order to form one beam pattern of vertically-polarized combined radio waves, 64 data sets are required. Here, one data set is formed of the gain setting value and the phase setting value.In order to prepare beam paterns of 256 types of combined radio waves for each of the horizontally -polarized wave and the vertically-polarized wave, it is necessary to prepare 256 data sets in each RF front end 5.

[0043] In each beamformer IC 10, a total of 4,096 data sets are stored in the look-up table.Also, in the phased array antenna module 1, a total of 32,768 data sets are stored in the look-up table.If 2,048 types of beam paterns are to be prepared, each RF front end 5 stores 2,048 data sets in the look-up table, each beamformer IC 10 stores 32,768 data sets in the look-up table, and the phased array antenna module 1 stores 262,144 data sets in the look-up table.

[0044] When transmission and reception are atempted with an N-th beam patern in a beamforming operation of the phased array antenna module 1, each RF front end 5 specifies an address corresponding to “N”. Therefore, a data set corresponding to the N-th beam pattern is read from the look-up table of the SRAM 13. Accordingly, a gain seting value is set in the variable gam amplifier, and a phase seting value is set in the phase shifter.

[0045] <Writing data to look-up table>At the time of starting use of the phased array antenna module 1 or when setting of the phased array antenna module 1 is changed, data sets are stored in the look-up table of the SRAM 13. Specifically, data sets, which are pairs of the gain seting values and the phase seting values on beam paterns of the required number of items, are sequentiallywritten to the look-up table and the data sets are stored. Therefore, a beam table is formed.In the phased array antenna module 1 according to the first embodiment of the present invention, data sets of 256 items are written to each of the 128 RF front ends 5. Therefore, 32,768 times of write operations are performed according to the procedure described below.

[0046] <Write operation for look-up table>First, a write operation for the look-up table according to the first embodiment of the present invention will be described. The write operation of the look-up table has first to third steps.

[0047] <First step>In the first step, the control device 50 transmits a communication message (first write communication message) to the RF front end 5 via the control line 52 in one communication transaction. The communication message in the first step includes additional information. The additional information includes selection information of the beamformer IC 10 to be written this time and selection information of the RF front end 5 to be written this time. In the communication message, a first-parameter writing command has been set as a command. Further, a gain setting value serving as the first parameter has been set as data having a fixed bit length or a part thereof.

[0048] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the first-parameter writing command has been received and causes a first circuit to store the received first parameter, which is the 5-bit gain setting value, in the 5-bit first register 14A. This state is shown in FIG. 4.

[0049] <Second step>Next, in the second step, the control device 50 transmits a communication message (second write communication message) to the RF front end 5 via the control line 52 inone communication transaction. In the communication message in the second step, a second-parameter writing command has been set as a command. Further, a phase setting value serving as the second parameter has been set as data having a fixed bit length or a part thereof.

[0050] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the second-parameter writing command has been received and causes a second circuit to store the received second parameter, which is the 7-bit phase setting value, in the 7-bit second register 14B. This state is shown in FIG. 5. The first register 14A holds the 5- bit gain setting value.

[0051] <Third step>Next, in the third step, the control device 50 transmits a communication message (third write communication message) to the RF front end 5 via the control line 52 in one communication transaction. In the communication message in the third step, a look-uptable writing command that specifies a to-be-written address has been set as a command. Further, to-be-written addresses of the look-up table to which the first parameter specified in the first step and the second parameter specified in the second step are to be written have been set as data having a fixed bit length or a part thereof.

[0052] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself the RF front end 5 accepts that the look-up-table writing command specifying the to-be-written address has been received, and causes a third circuit to set the received 8-bit to-be-written address to the address lines 16. Further, the RF front end 5 instructs writing to the SRAM 13 through the WEN line 15. This state is shown in FIG. 6.

[0053] In the state shown in FIG. 6, the first register 14A holds the 5-bit gain setting value.The second register 14B holds the 7-bit phase setting value. A to-be-written address hasbeen specified on the address line 16. In this state, the WEN line 15 is specified to write. Therefore, one set of the gain setting value and the phase setting value is written to the address specified in the SRAM 13.A preparation of a beam table is completed by performing a series of procedures from the first step to the third step described above 32,768 times for one phased array antenna module 1.

[0054] <Beamforming procedure according to first embodimentA beamforming procedure according to the first embodiment of the present invention will be described with reference to FIG. 3. A case in which transmission and reception are performed by setting the N-th beam pattern in the phased array antenna module 1 by the beamforming will be described below.

[0055] First, the control device 50 transmits a communication message (beamforming communication message) to the RF front end 5 via the control line 52 in one communication transaction. In the communication message, a command for instructing switching to the N-th beam pattern has been set as a command by the control device 50. Further, a beam selection parameter specifying N or indirectly specifying N has been set as data having a fixed bit length or a part thereof.

[0056] Here, in the beamforming, the same N number is specified to a plurality of RF front ends 5. Therefore, in the additional information included in the communication message, it is preferable to be able to specify a broadcast transmission mode that specifies all the beamformer ICs 10 and all the RF front ends 5 as destinations. Also, it is more preferable to be able to specify the broadcast transmission mode selected by polarized waves, such as targeting only the RF front ends 5 connected to the antenna elements 21 for horizontally -polarized waves and excluding the RF front ends 5 connected to the antenna elements 21 for vertically-polarized waves, or conversely, targeting only the RF front ends 5 connected to the antenna elements 21 for vertically - polarized waves and excluding the RF front ends 5 connected to the antenna elements 21 for horizontally -polarized waves.

[0057] In the SRAM 13, when the WEN line 15 is in a state of specifying reading and the address lines 16 are in a state in which a to-be-read-out address has been specified thereon, the SRAM 13 outputs a gam setting value serving as the first parameter and a phase setting value serving as the second parameter, which are data set stored at the address, to the data terminal 13A and the data terminal 13B, respectively.

[0058] The first parameter and the second parameter are transmitted to the analog circuit 12 by an output circuit including a strobe circuit (not shown), and the gain setting value is set in the variable gain amplifier and the phase setting value is set in the phase shifter. As a result, an appropriate phase difference is set for each of electromagnetic waves emitted from the antenna elements 21 or received by the antenna elements 21, and a beam pattern having a desired beam direction, half-power beamwidth, and side lobe shape can be realized.

[0059] According to the present embodiment, the integrated look-up table can be employed as a beam table by the look-up table writing method using the temporary parameter store. It is possible to reduce an area of the SRAM 13 to reduce costs of the IC chip while realizing precise beamforming control.

[0060] <Second embodimentA phased array antenna module according to a second embodiment of the present invention will be described with reference to the drawings.The second embodiment differs from the first embodiment in that the number of items of the beam table stored in the integrated look-up table is increased to 2,048 items. Therefore, the number of address lines 16 for specifying write addresses or read addresses in an SRAM 13 is eleven. Also, the second embodiment differs from the first embodiment in that an RF front end 5 includes a third register 14C serving as a temporary parameter store.

[0061] The phased array antenna module according to the second embodiment of the present invention requires 11 bits for specifying addresses of the SRAM. Therefore, all the 2,048 items cannot be written or read in the circuit and procedures exemplified in thefirst embodiment. Therefore, in the second embodiment, the third register 14C serving as a temporary' parameter store is used for specifying addresses in the SRAM 13, as shown in FIGS. 7 and 8.

[0062] <Write operation for look-up table>First, a write operation for a look-up table according to the second embodiment of the present invention will be described. The write operation of the look-up table has first to third steps.

[0063] <First step>In the first step, a control device 50 transmits a communication message (first write communication message) to the RF front end 5 via a control line 52 in one communication transaction. The communication message in the first step includes additional information. The additional information includes selection information of a beamformer IC 10 to be written this time and selection information of the RF front end 5 to be written this time. In the communication message, a first-parameter writing command has been set as a command. Further, a gain setting value serving as a first parameter has been set as data having a fixed bit length or a part thereof.

[0064] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the first-parameter writing command has been received and causes a first circuit to store the received first parameter, which is a 5 -bit gain setting value, in a 5 -bit first register 14A. This first step is the same as the first step of the wnte operation to the look-up table according to the first embodiment described above, and this state is like the state shown in FIG. 4.

[0065] <Second step>Next, the second step will be explained.As the second step, a first method and a second method can be stated.

[0066] <First Method of second Step>In the first method of the second step, the control device 50 sets a first look-up-table- wnting-address specifying command in the command. Further, the control device 50 sets a part of a to-be-written address, for example, MSB 3 bits, to data having a fixed bit length or a part thereof. The control device 50 transmits a communication message (third write communication message) to the RF front end 5 via the control line 52 in one communication transaction.

[0067] Following the above, the control device 50 sets a second look-up-table-writing-address specifying command in the command. Further, the control device 50 sets the remaining part of the to-be-written address, for example, LSB 8 bits, to data having a fixed bit length or a part thereof. The control device 50 transmits a communication message (fourth write communication message) to the RF front end 5 via the control line 52 in one communication transaction.

[0068] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the first and second look-up-table-writing-address specifying commands have been received, and causes a fourth circuit to set a to-be-written address of 11 bits in total, that has been received in twice, to the address lines 16. This state is shown in FIG. 7. The first register 14A holds the 5-bit gain setting value.

[0069] <Second method of second Step>In the second method of the second step, the RF front end 5 has determined a part of the to-be-written address prior to the first step. As one of the methods, the control device 50 sets a first look-up-table-writing-address specifying command in the command in advance, and furthermore, sets a part of the to-be-written address, for example, MSB 3 bits, to data having a fixed bit length or a part thereof. The control device 50 transmits a communication message (third write communication message) to the RF front end 5 via the control line 52 in one communication transaction.

[0070] Also, a method of providing a circuit that determines a part of the to-be-written address, for example, MSB 3 bits, can be considered on the basis of certain conditions such as horizontally -polarized waves or vertically-polarized waves, transmission or reception, or environmental temperature. It can also be said that this is a method of using the look-up table of 2,048 items by dividing them into eight banks of 256 items. In the second method of the second step, in a state in which a part of the to-be-written address has been determined, the control device 50 sets the second look-up-table-writing- address specifying command in the command, and furthermore, sets the remaining part of the to-be-written address to data having a fixed bit length or a part thereof. The control device 50 transmits a communication message (fourth write communication message) to the RF front end 5 via the control line 52 in one communication transaction.

[0071] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the second look-up-table-writing-address specifying command has been received, and causes the fourth circuit to set a to-be-written address of 11 bits in total to the address lines 16. Similarly to the first method, this state is shown in FIG. 7. The first register 14A holds the 5-bit gain setting value.

[0072] <Third step>Next, in the third step, the control device 50 transmits a communication message (fifth write communication message) to the RF front end 5 via the control line 52 in one communication transaction. In the communication message of the third step, a look-uptable writing command that specifies a second parameter has been set as a command. Further, a phase setting value serving as the second parameter has been set as data having a fixed bit length or a part thereof.

[0073] The RF front end 5 receives the communication message.The RF front end 5 ascertains a destination specified in the additional information. If the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts thatthe look-up-table writing command specifying the second parameter has been received, and causes a fifth circuit to output the received second parameter, which is the 7-bit phase setting value, to the SRAM 13 via a 7-bit second register 14B and instruct writing to the SRAM 13 through the WEN line 15.Alternatively, if the destination specified in the additional information is ascertained and the destination corresponds to the RF front end 5 itself, the RF front end 5 accepts that the look-up-table writing command specifying the second parameter has been received, and causes the fifth circuit to directly output the received second parameter, which is the 7-bit phase setting value, to the SRAM 13 and instruct writing to the SRAM 13 through the WEN line 15.This state is shown in FIG. 8.

[0074] The first register 14A holds the 5-bit gain setting value. The third register 14C holds the 11 -bit to-be-written address. The 7-bit phase setting value is held by the second register 14B or output directly to the SRAM 13. In this state, the WEN line 15 is in a state of instructing writing. Therefore, one set of the gain setting value and the phase setting value is written to the address specified in the SRAM 13.A preparation of a beam table is completed by performing a series of procedures from the first step to the third step described above 262,144 times for one phased array antenna module.

[0075] <Beamforming procedure according to second embodimentA beamforming procedure according to the second embodiment of the present invention is substantially the same as the beamforming procedure according to the first embodiment. However, the second embodiment differs from the first embodiment in that, two communication transactions are used, or a bank switching circuit that predetermines a part of the to-be-written address, for example, MSB 3 bits, is used on the basis of certain conditions in specifying a to-be-read-out address on the address lines 16.

[0076] In the second embodiment of the present invention, the gain setting value is 5 bits and the phase setting value is 7 bits, and thereby precise beamforming can be realized.Further, a large number of beam paterns as many as 2,048 items can be stored in the look-up table.According to the present embodiment, the integrated look-up table can be employed as a beam table by the look-up table writing method in which the third register 14C is used as a temporary' parameter store, and it is possible to reduce an area of the SRAM 13 and reduce costs of the IC chip while realizing precise beamforming control and storing a large number of beam paterns.

[0077] <Third embodimentA phased array antenna module according to a third embodiment of the present invention will be described with reference to the drawings.As shown in FIGS. 9 and 10, the third embodiment differs from the first embodiment in that a temporary parameter store is also placed in an output circuit, and a to-be-read-out address of a first parameter and a to-be-read-out address of a second parameter can be specified independently of each other. In other words, the third embodiment differs from the first embodiment in that the RF front end 5 includes a fourth register 14D serving as a temporary parameter store. Particularly, the configuration show n in FIGS. 9 and 10, the gain setting terminals 12A of the analog circuit 12 are connected to the SRAM 13 via the fourth register 14D. In other words, FIGS. 9 and 10 show connection lines between the SRAM 13 and the fourth register 14D and connection lines between the fourth register 14D and the gain seting terminals 12A of the analog circuit 12.

[0078] <Write operation for look-up table>Since a write operation for a look-up table in the third embodiment is the same as that in the first embodiment, description thereof will be omited.

[0079] <Beamforming procedure according to third embodiment?*A beamforming procedure according to the third embodiment of the present invention will be described with reference to FIG. 9. A case in which transmission and reception are performed by selecting the N-th first parameter and the M-th second parameter and seting beam paterns thereof in the phased array antenna module by the beamforming will be described below.

[0080] <First step>First, a control device 50 transmits a communication message (second beamforming communication message) to the RF front end 5 via a control line 52 in one communication transaction. In the communication message of a first step, a command instructing to store the first parameter read from the to-be-read-out-first-parameter address to the fourth register 14D has been set as a command by the control device 50. Further, a first parameter selection parameter specifying N or indirectly specifying N has been set as data having a fixed bit length or a part thereof.

[0081] Here, in beamforming, the same number of N is specified to a plurality of RF front ends 5. Therefore, in additional information included in the communication message, it is preferable to be able to specify a broadcast transmission mode that specifies all beamformer ICs 10 and all the RF front ends 5 as destinations.Also, it is more preferable to be able to specify the broadcast transmission mode selected by polarized waves, such as targeting only the RF front ends 5 connected to antenna elements 21 for horizontally-polarized waves and excluding the RF front ends 5 connected to the antenna elements 21 for vertically-polarized waves, or conversely, targeting only the RF front ends 5 connected to the antenna elements 21 for vertically- polarized waves and excluding the RF front ends 5 connected to the antenna elements 21 for horizontally -polarized waves.

[0082] In an SRAM 13, when a WEN line 15 is in a state of specifying reading and address lines 16 are in a state in which a to-be-read-out address has been specified thereon, the SRAM 13 outputs a gam setting value serving as the first parameter and a phase setting value serving as the second parameter, which are N-th data set stored at the address, to a data terminal 13A and a data terminal 13B, respectively.A state at this time is shown in FIG. 9. At this stage, unlike the first embodiment, the output circuit including a strobe circuit (not shown ) does not yet transmit these set values to an analog circuit 12. The fourth register 14D holds the gain setting value, which is the N-th first parameter.

[0083] <Second step>Next, in a second step, the control device 50 transmits a communication message (third beamforming communication message) to the RF front end 5 via the control line 52 in one communication transaction. In the communication message in the second step, a command instructing to output the second parameter read from a to-be-read-out-second- parameter address and the first parameter that has been read in the first step and stored in the fourth register 14D to the analog circuit has been set as a command. Further, a second parameter selection parameter specifying M of the look-up table or indirectly specifying M has been set as data having a fixed bit length or a part thereof.

[0084] In the SRAM 13, when the WEN line 15 is in a state of specify ing reading and the address lines 16 are in a state in which a to-be-read-out address has been specified thereon, the SRAM 13 outputs a gain setting value serving as the first parameter and a phase setting value serving as the second parameter, which are M-th data set stored at the address, to the data terminal 13A and the data terminal 13B, respectively.

[0085] The output circuit including the strobe circuit (not shown) outputs the N-th gain setting value held in the fourth register 14D as the gain setting value serving as the first parameter and the M-th phase setting value read from the SRAM 13 as the phase setting value serving as the second parameter to the analog circuit 12. This state is shown in FIG. 10.

[0086] These first parameter and second parameter are transmitted to the analog circuit 12 by the output circuit including the strobe circuit (not shown), and the gain setting value is set in a variable gam amplifier and the phase setting value is set in a phase shifter. As a result, an appropriate phase difference is set for each of electromagnetic waves emitted from the antenna elements 21 or received by the antenna elements 21, and a beam pattern having a desired beam direction, half-power beamwidth, and side lobe shape can be realized.

[0087] According to the present embodiment, precise beamforming can be realized by employing the integrated look-up table. The first parameter and the second parametercan be separately selected from the look-up table, and a degree of freedom in setting the beam pattern can be improved while reducing an area of the SRAM 13 to reduce costs of the 1C chip.

[0088] While preferred embodiments of the present invention have been described and illustrated above, it should be understood that these are exemplary of the present invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the present invention is not to be considered as being limited by the foregoing description and is only limited by the scope of the claims.[Examples]

[0089] Next, examples and comparative examples of the present invention will be described with reference to FIGS. 11 to 15, and effects obtained by the present invention will be described.FIG. 11 is a table showing a configuration and a relative area in a design example of an SRAM for an integrated look-up table according to the first embodiment described above.FIG. 12 is a table showing a configuration and a relative area in a design example of an SRAM for an integrated look-up table according to the second embodiment described above.FIG. 13 is a table showing a configuration and a relative area in a design example of an SRAM for an integrated look-up table according to comparative example 1.FIG. 14 is a table showing configurations and relative areas in design examples of two SRAMs for look-up tables according to comparative example 2.FIG. 15 is a table showing configurations and relative areas in design examples of two SRAMs for look-up tables according to comparative example 3.

[0090] <Example 1>In example 1, an SRAM that reads and writes data in 12 bits is used. Here, 12 bits correspond to a total number of bits of a gain setting value with a data width of 5 bitsand a phase setting value with a data width of 7 bits. An integrated look-up table of the SRAM according to example 1 was designed to be able to store data of 256 items. Generally, SRAM designs for ASICs are provided by semiconductor device manufacturers or IP vendors using a Memory Compiler software. Otherwise, the SRAM design could be prepared in any suitable manner, such as via the open source projects of Google Sky Water SKY130PDK, OpenRAM, OpenROAD and OpenLane. In example 1, the relative area of a designed SRAM per RF front end was 129 % compared with the comparative example 1. The designed SRAM area depends on used PDK and process node, therefore relative areas are shown from FIG. 11 to FIG. 15 for comparison purpose.

[0091] <Example 2>In Example 2, an SRAM was designed by the same method as in example 1.In the Example 2, an SRAM that reads and writes data in 12 bits is used. Here, 12 bits correspond to a total number of bits of a gain setting value with a data width of 5 bits and a phase setting value with a data width of 7 bits. An integrated look-up table of the SRAM according to example 2 was designed to be able to store data of 2,048 items. In example 2, the relative area of a designed SRAM per RF front end was 664 % compared with the comparative example 1.

[0092] Comparative example 1>In an integrated look-up table of an SRAM according to comparative example 1, a communication message with a fixed bit length is written to the SRAM using 8-bit data. Therefore, in comparative example 1, a total of bit numbers used for a gain setting value and bit numbers used for a phase setting value is limited to 8 bits, and thus a control resolution of analog elements is insufficient and precise beamforming cannot be realized.For comparison purpose, the area of a designed SRAM per RF front end in comparative example 1 is treated as 100 %.

[0093] Comparative example 2>A look-up table in comparative example 2 is an example of a look-up table divided into two. A gain look-up table serves as a first look-up table of an SRAM. The gain lookup table can store 256 items of gam setting values with a data width of 5 bits. A phase look-up table serves as a second look-up table of the SRAM. The phase look-up table can store 256 items of phase setting values with a data width of 7 bits.

[0094] As a result of designing the SRAM by the same method as in example 1, in comparison with the comparative example 1, the relative area of the first look-up table was 79 %. The relative area of the second look-up table was 93 %. The relative area of SRAM per RF front end in total was 172 %.In comparative example 2, since it is possible to specify separate to-be-read-out addresses of the first look-up table and the second look-up table, the N-th first parameter and the M-th second parameter can be combined to control analog elements and form a beam pattern.

[0095] Comparative example 3>A look-up table in comparative example 3 is an example of a look-up table divided into two. A gain look-up table serves as a first look-up table of an SRAM. The gain lookup table can store 2,048 items of gain setting values with a data width of 5 bits. A phase look-up table serves as a second look-up table of the SRAM. The phase look-up table can store 2,048 items of phase setting values with a data width of 7 bits.

[0096] As a result of designing the SRAM by the same method as in example 1, in comparison with the comparative example 1, the relative area of the first look-up table was 355 %. The relative area of the second look-up table was 441 %. The relative area of SRAM per RF front end in total was 795 %.In comparative example 3, since it is possible to specify separate to-be-read-out addresses of the first look-up table and the second look-up table, the N-th first parameter and the M-th second parameter can be combined to control analog elements and form a beam pattern.

[0097] Comparison between example 1 and comparative example 1>In example 1, the gain setting value is 5 bits and the phase setting value is 7 bits. In comparative example 1, the gain setting value and the phase setting value are limited to 8 bits in total. Compared to comparative example 1, according to example 1, more precise beamforming could be achieved.

[0098] <Comparison between example 1 and comparative example 2>Example 1 has used the integrated look-up table. Therefore, the relative area of SRAM per RF front end could be reduced to 129 % of comparative example 1.An area ratio of the relative area 129 % of example 1 to the total relative area 172 % of comparative example 2 was 75.0 %. That is, an effect of reducing the area by 25.0 percentage points could be obtained.

[0099] <Comparison between example 2 and comparative example 3>Example 2 has used the integrated look-up table. Therefore, the relative area of SRAM per RF front end could be reduced to 664 % of comparative example 1.An area ratio of the relative area 664 % of example 2 to the total relative area 795 % of comparative example 3 was 83.5 %. That is, an effect of reducing the area by 16.5 percentage points could be obtained.[Reference Signs List]

[0100] I Phased array antenna module5, 5A to 5P RF front end6 Beamformer IC control circuit10, lOA to 10H Beamformer IC (semiconductor device, beamformer)I I Digital circuit11 A First data circuit terminal1 IB Second data circuit terminal11C Address circuit terminal11 W WEN circuit terminal12 Analog circuit (analog element)13 SRAM13 A First data terminalA Data terminal B Second data terminal B Data terminal C Address terminal W WEN terminal A First register B Second register C Third register D Fourth register WEN line Address line A First data line B Second data line A Gain setting line B Phase setting line A First register line B Second register line Antenna array , 21A to 21P Antenna element RF signal coupler / splitter Control device RF Signal line Control line Power line

Claims

[CLAIMS]

1. A digital circuit provided in a semiconductor device to control analog elements, the digital circuit comprising: a digital communication circuit that receives a control message including a command and data in one communication transaction; a random access memory that stores a look-up table, the look-up table having an address and a data set corresponding to the address, the data set including a plurality of analogelement control parameters; a temporary parameter store that temporarily stores the data received by the digital communication circuit in the communication transaction, the temporary parameter store preparing a data set to be stored to one address of the look-up table; and an output circuit that outputs a setting-parameter.

2. The digital circuit according to claim 1 , wherein the semiconductor device is a beamformer, the analog-element control parameters include a first parameter and a second parameter, one of the first parameter and the second parameter is a gain setting value, the other of the first parameter and the second parameter is a phase setting value, one of the analog elements is a variable gain amplifier controlled by using the gain setting value, and another of the analog elements is a phase shifter controlled by using the phase setting value.

3. The digital circuit according to claim 2, further comprising: a first circuit that receives a first-parameter writing command and stores the first parameter in the temporary parameter store in accordance with the first-parameter writing command; a second circuit that receives a second-parameter writing command and stores the second parameter in the temporary parameter store in accordance with the second- parameter writing command; anda third circuit that receives a look-up-table writing command, the look-up-table writing command being to specify a to-be-written address, the third circuit writing the first parameter and the second parameter into the to-be-written address of the look-up table in accordance with the look-up-table writing command.

4. The digital circuit according to claim 2, further comprising: a first circuit that receives a first-parameter writing command and stores the first parameter in the temporary parameter store in accordance with the first-parameter writing command; a fourth circuit that receives a look-up-table-writing-address specifying command and stores a to-be-written address in the temporary parameter store in accordance with the look-up-table-writing-address specifying command; and a fifth circuit that receives a second-parameter writing command and writes the first parameter and the second parameter into the to-be-written address of the look-up table in accordance with the second-parameter writing command.

5. The digital circuit according to claim 2, further comprising: a sixth circuit that receives a first-parameter-reading-address specifying command, reads out the first parameter from an address that the first parameter to be read-out in accordance with the first-parameter-reading-address specifying command, and stores the first parameter in the temporary parameter store in accordance with the first- parameter-reading-address specifying command; and a seventh circuit that receives a second-parameter-reading-address-specifying-and- parameter-outputting command, reads out the second parameter from an address that the second parameter to be read-out in accordance with the second-parameter-reading- address-specifying-and-parameter-outputting command, and outputs the first parameter stored in the temporary parameter store and the second parameter read from the address that the second parameter to be read-out to the analog elements in accordance with the second-parameter-reading-address-specifying-and-parameter-outputting command.

6. A method of storing parameters for controlling analog elements in a look-up table stored in a random access memory provided in a semiconductor device, the method comprising: a first step of sending first communication transaction including a first parameter and a first command to the semiconductor device, the first command being to instruct the semiconductor device to store the first parameter in a temporary parameter store; a second step of sending second communication transaction including second data and a second command to the semiconductor device; and a third step of sending third communication transaction including third data and a third command to the semiconductor device, the third command being to instruct the semiconductor device to write the first parameter specified in the first step and a second parameter specified in the second step or the third step into the to-be-written address of the look-up table specified in the second step or the third step, wherein the first to third steps are carried out by sending communication transaction including a command and fixed bit width data to the semiconductor device.

7. The method according to claim 6, wherein the second data includes the second parameter, the second command is to instruct the semiconductor device to store the second parameter in the temporary parameter store, the third data includes a to-be-written address of the look-up table, and the third command is to instruct the semiconductor device to write the first parameter and the second parameter into the to-be-written address of the look-up table.

8. The method according to claim 6, wherein the second step is to send a to-be-written address of the look-up table and a second command to the semiconductor device, by sending one or more communication transactions including a command and data, the second command being to instruct the semiconductor device to store the to-be-written address in the temporary parameter store, the third data includes the second parameter, andthe third command is to instruct the semiconductor device to write the first parameter and the second parameter into the to-be-written address of the look-up-table.

9. A method of reading out a plurality of parameters and outputting the plurality of the parameters to analog elements, the plurality of the parameters being stored in a look-up table stored in a random access memory provided in a semiconductor device, the method comprising: a first step of sending first communication transaction including a to-be-read-out-first- parameter address of the look-up table and a first command to a semiconductor device, the first command being to instruct the semiconductor device to store a first parameter read out from the to-be-read-out-first-parameter address of the look-up table to a temporary parameter store; and a second step of sending second communication transaction including a to-be-read-out- second-parameter address of the look-up table and a second command to a semiconductor device, the second command being to instruct the semiconductor device to read out a second parameter from the to-be-read-out-second-parameter address of the look-up table and to output the first parameter and the second parameter to the analog elements, wherein the first and second steps are carried out by sending communication transaction including a command and fixed bit width data to the semiconductor device.

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