Apparatuses and methods for controlled waveshaping

Abstract

In certain examples, methods and circuit-based apparatuses are directed to use of logic circuitry to selectively engage (e.g., activating and / or deactivating) a plurality of resonant-isolated DC-DC converter cells ("converter cells"). The selective engagement of respective ones of the converter cells is to effect a combining of output signals from the converter cells to generate an aggregate (e.g., high-voltage) output signal having a waveform shape that is customized based on the selective engagement. In a more specific example, due to the inherent fast response of the converter cells, nanosecond level pulsing and customized high voltage waveshaping is achieved by controlling the precision timing, on the order of nanoseconds, of turning on or off the DC-DC converter cells and the voltage of each converter cell.

Description

APPARATUSES AND METHODS FOR CONTROLLED WAVESHAPINGBACKGROUND

[0001] Aspects of the present disclosure are related generally to the field of power conversion for delivering power at relatively high voltages to loads. As examples of loads in such contexts, many existing and new7applications operate based on high-voltage power sources from which an input voltage may be as high as or in excess of 1 kV (kiloVolt). For many applications, high-voltage power converters would ideally deliver power in the range of tens of kV (e g., 10-100 kV). Exemplary high-voltage applications in this context include, among others, those in the medical, environmental, security, aerospace fields, and semiconductor industry7.

[0002] Using plasma processing in the semiconductor manufacturing industry as one such technology type, it has been appreciated that advancements in this industry have resulted in demands to synthesize specially tailored voltage waveforms that exhibit (a) very7fast rise and fall times (e.g., 10s of ns); (b) very7high peak voltages (e.g., 10s of kV); and (c) customized (or arbitrary yet controllable) waveform shapes, such as a voltage ramp up or down at constant controllable slopes. In semiconductor manufacturing, for example, such unique voltage w aveforms enable direct control of ion energy^ distribution functions (IEDF) at a substrate during plasma processing. Goals for pulse generators producing these waveforms include high efficiency to minimize cooling requirements and electricity costs, and compact form factor to reduce storage requirements of the power equipment. Meeting these stringent needs and goals often results in solutions that sacrifice one or more performance measures, yielding systems having large size, significant cooling requirements due to low- efficiency, or both.

[0003] The above issues as well as others have presented challenges to power conversion for semiconductor plasma processing and a variety of other applications.SUMMARY OF VARIOUS ASPECTS AND EXAMPLES

[0004] Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure. For example, some of these disclosed aspects are directed to methods and devices that use or leverage from a stacked arrangement of resonant-isolated DC-DC converter cells (“converter cells”) having respective output terminals cooperativelyconfigured to combine, at an output terminal, output signals respectively produced by the converter cells to produce an aggregate output signal and through their control at high- precision (e.g., nanosecond timings), generating a customized waveform shape in the aggregate output signal.

[0005] In certain specific examples involving methods and / or apparatuses, aspects of the present disclosure involve a plurality of resonant-isolated converter cells and logic circuitry to control the converter cells. The converter cells may have respective output terminals cooperatively configured to combine, at an output terminal, output signals respectively produced by the converter cells. The logic circuitry’ (e.g., programmable or fixed logic circuitry such as programmable logic devices (PLDs) or microcomputer circuitry) is to control the converter cells by selectively engaging (e.g., activating and / or deactivating), respective ones of the converter cells to generate an output signal having a waveform shape that is customized based on such selective engagement.

[0006] In related methods according to the present-disclosure, specific implementations include selective engagement (including at least one of activating and deactivating), via logic circuitry, of respective ones of a plurality of resonant-isolated DC-DC converter cells, and combining output signals from respective output terminals of the converter cells to generate an output signal having a waveform shape that is customized based on the selective engagement.

[0007] More specific example aspects, according to the present disclosure, may build on the above exemplary methods and / or apparatuses. In one such example aspect, a set of time- coordinated gate drive signals are provided or generated to control input ports of the converter cells, including setting or adjusting timing and signal level of each of the time- coordinated gate drive signals for the selective engagement to adjust each respective output voltage generated by each of the converter cells, wherein the step of combining output signals is in response to the selective engagement. Consistent with another such example aspect, the logic circuitry is to effect the activation and deactivation via input signals, to be provided to the converter cells by controlled timings, on an order of nanoseconds, used in effecting the activation and deactivation of the converter cells and by respective voltages of each of the converter cells, wherein altering the timings of the input signals causes one or more changes in the waveform shape. Further, in yet another example aspect, the waveform shape is controlled according to timing control (e.g., with precision on the order of nanoseconds or tens of nanoseconds) for which activation of one or more of the converter cells are delayed to realize a desired form of the waveform shape.

[0008] In certain other examples that may also build on the above-discussed aspects, methods and apparatus are directed to controlling generation of the waveform shape, via the selective activation and deactivation, to realize design specifications including one or a combination of two or more of the following: (a) fast and / or fall times on the order of nanoseconds; (b) high peak voltages on the order of kV; and (c) the waveform shape being controllable by at least one of a voltage ramp up at constant controllable slopes or voltage ramp down at constant controllable slopes.

[0009] Other example aspects may also build on the above-discussed aspects. One such aspect is the activation and / or deactivation of the converter cells being controlled by the logic circuitry based on stored or configured information useful to realize the shape of the desired pulse waveform and its characteristics, wherein the stored or configured information is provided by at least one of: storage settings; configured logic circuitry; and feedback signals obtained or determined during operation of the apparatus. Another such aspect involves the converter cells and the logic circuitry being cooperatively configured and selectively engaged to generate a pulsed waveform having a tailored bias voltage, with a positive short pulse followed by a negative linear ramp. In specific examples, the tailored pulsed voltage waveform is provided to a load in semiconductor processing to result in a desired narrow' ion energy distribution in the plasma chamber. In this context, the pulsed voltage waveform is characterized, for example, by a maximum pulse voltage, rise and / or fall times, voltage and / or current ramps. According to example embodiments of the present disclosure, tailored pulsed voltage waveforms have been generated with maximum pulse voltages in a range from 10 kV up to a several kV, rise times in a range of 10 nanoseconds (ns) up to 100 ns, and negative linear ramps lasting up to several microseconds (psec).

[0010] Yet other example aspects, which may also build on the above-discussed aspects, involve inverter circuitry and isolation circuitry', including transformers, in one or more of the converter cells. The inverter circuitry includes control gates for which respective gate-control signals are generated. The output of the inverters connects to the primary of the transformer. The secondary of the transformer feeds rectifier stages. The combination of the inverter stage, transformer stage and rectifier stage is a single DC-DC convert cell. The logic circuitry' is to control generation of the w aveform signal for the respective ones of the converter cells by at least one of increasing or decreasing, relative to steady state, a frequency of the gate-control signals or pulse width of the gate-control signals to drive the inverter circuitry.[001 : ] Other example aspects involve mitigation or elimination of signal overshoot in the output signal at the output terminal of the converter cells. One or more of the convertercells includes inverter circuitry having control gates to receive respective gate-control signals, and the logic circuitry generates the waveform shape by producing the respective gate-control signals at an initial higher switching frequency for operating the converter cells (relative to a frequency used in steady state operation) to mitigate or eliminate such signal overshoot in the output signal at the output terminal. In a related aspect, the mitigation or elimination of the overshoot is realized by starting the switching frequency of the gate signals of the inverter at a relatively high frequency and then reducing this frequency to reduce overshoot (optionally, without thereafter further adjusting one or more switching frequencies used to operate the converter cells). In certain related examples (standing alone or in combination with the above related aspect), the proper timing and / or sequencing of the gate signals across different converter cells is also used to reduce overshoot of the combined output voltage signal (i.e. at the output of the overall stack).

[0012] Another example aspect according to the present disclosure uses a stack of the converter cells with multiple DC rails, isolated from one another by one or more voltageisolation barriers, to provide operating power at different voltage levels to respective ones of the cells. The cells have respective input ports referenced to the different voltage levels.

[0013] In further specific examples related to the above methodology' and devices, the one of more of the converter cells includes an inversion stage, an isolation stage, and a rectification stage. Design choices for inversion and rectification stages include the topology of the cell, selection of active power devices with appropriate voltage and current ratings, and the tuning of component values. Example circuits for the inversion stage may include circuits having resonant switched-mode push-pull topologies, which can allow adjustment of output voltage by phase-shifting constituent inverters.

[0014] In yet further specific examples, the present disclosure is directed to systems and methods for generating nanosecond-scale high-voltage pulses having customized (sometimes referred to as arbitrary) and controlled waveform shapes, fast rise and / or fall times, and in some instances, an inherently small volume and mass. In related example embodiments, customized and controllable high output voltages are produced by stacking the outputs of a group of highly miniaturized, optimized, and isolated individual resonant DC-DC converter cells in series and connecting the resulting stacked output across the desired load. The output voltage can be implemented in various ways, such as the sum of the individual output voltages of each cell or as an aggregation of certain (or all) the individual output voltages of each cell as may be derived for different purposes (e.g., realizing a capped voltage and / or current level). The input of the DC-DC converters is a DC voltage rail that may be providedby a front-end AC / DC converter, another DC-DC converter, or some other source of DC voltage.[001.5] In some example system-type embodiments, the present disclosure is directed to a system including a load with a plurality of converter cells (e.g., each as exemplified herein as including inverter, isolation and rectifier stages) configured with their respective outputs being combined, at an output terminal, and with logic circuitry is to control the converter cells by selectively engaging respective ones of the converter cells to generate an output signal that has a waveform shape which is customized for the load according to such selective engagement via control signals used drive gates of FETs of cell's inverter.

[0016] In some examples, the present disclosure is directed to apparatuses and methods involving control of such a system (e.g., as described immediately above) by implementing a feedforward mode and / or a feedback mode for controlling the respective outputs of the converter cells. The feedback mode may be implemented by monitoring levels at outputs of the converter cells (e.g., via the controller and / or related circuitry depicted by the block at the bottom of FIG. 1) for finely adjusting the operations of the converter cells. For example, such systems may be used to selectively engage converter cells based on operating zones in a current- voltage space in a feedforward mode, and with the system then using closed-loop feedback to adjust frequency, duty cycle, and phase-shift to arrive at the desired output voltage. As more-specific example implementations, the feedforward mode and / or feedback mode may be realized in various ways including, for instance, via the related circuitry of FIG. 1 implemented as threshold-level comparators, power-related parameter (e.g., voltage and / or current) measurement circuits to monitor the outputs of the converter cells and / or the aggregated or combined output in combination with data pre-stored in a look-up table or by algorithm-executing data-processing computing circuitry to assess current and / or past measurements to leam and / or predict what parameters to set for the converter cells (and which or how many the converter cells to engage), for ensuing signal generation, in an initial course mode and / or for subsequent fine tuning.

[0017] In some example embodiments, multiple DC-DC converter stacks may be connected in parallel to provide higher current levels to the load. Each stack is optimized to supply up to a certain amount of current at high efficiency. For a specified output current requirement, stacks can be added in parallel as needed to meet the load requirements, with each stack providing up to its rated current. In certain example circuits according to the present disclosure, the stacks are substantially identical such the current is sharedsubstantially equally among them to avoid efficiency degradation, overloading, overheating, or all of the above.

[0018] In some embodiments, multiple DC-DC converter cells may be connected in series or parallel to achieve fast transient response for the output waveform, and / or DC-DC converter cells may be designed to have substantially identical characteristics, including output voltage / power, switching frequency, transient response, and voltage isolation requirement. In other embodiments, DC-DC converter cells can be designed differently within a stack to have different output voltages / power, different switching frequencies, different transient responses, different voltage isolation requirements, etc. Also, due to the isolated nature of the DC-DC cells in the type of system show n in FIG. 1, each cell can be connected to provide a voltage waveform that can be positive or negative with respect to a reference node in the system. It is noted that at the bottom of FIG. 1, an arrow is shown pointing into the controller block to represent such logic circuitry retrieving, optionally, data from external circuitry (e.g., databases stored in a memory circuit such as the above-disclosed look-up table, and / or configuration parameters for executing the above-disclosed algorithm). The arrow in FIG. 1 is shown partially in dashed lines, as with other figures herein, with the dashed lines indicated that the illustrated aspect(s) is optional for the depicted non-limiting example.

[0019] The DC-DC converters in example embodiments of the present disclosure may be tuned to realize soft switching (e.g., zero-voltage switching) of the active power devices to minimize switching losses and maintain high efficiency. The resonant DC-DC converter cells are able to leverage high switching frequency (in different examples, from Is to 10s of MHz, from 10s to 100s of MHz, and in ranges that extend below and beyond such ranges) of the power devices and thus significantly reduce the size requirements for the internal energy storage devices, including capacitors, inductors, and transformers. The switching frequency of the DC-DC converters can furthermore be adjusted to meet specific rise or fall time targets, or to adjust the converter’s output voltage.

[0020] The DC-DC converter cells can be designed to process bidirectional energy flow such that energy stored in the output can be recycled back to the input when driving capacitive loads.

[0021] In some embodiments, the system output waveforms can be configured as unipolar, and in other embodiments, the system output waveforms can be configured as bipolar. When driving capacitive loads, bipolar pulses centered at zero require half of theenergy compared to unipolar pulses to achieve the same peak-to-peak voltage across the capacitive load.[00221 In some embodiments, the DC rail providing the inputs to the DC-DC converters may be a fixed DC voltage rail common to all converters. In other embodiments, the input voltage rail may be an adjustable DC voltage that is common to all converters. In other embodiments, the input voltage rail to each converter may be distinct from that of other converters and may be fixed or adjustable.

[0023] in some embodiments, selective engagement of the converter cells involves selectively activating, selectively deactivating and / or selectively setting or adjusting timing and coordination of the converter cells by way of the gate control signals driving the inverters. With such selectively activating and / or deactivating, each DC-DC converter can be optionally turned on or off, and this can be used as part of one example approach for coarsely varying the output voltage level in discrete steps. For a given required output voltage, the higher the number of DC-DC cells stacked in series, the smaller the discrete steps can be, and the less need there is for finer output voltage control. A primary advantage of on / off control in this context is the ability of the pulse generation system to step from low voltage levels (e.g., 10s of V) to much higher voltage levels (e.g., 10s of kV), or vice versa, at very fast time scales (e.g., 10s of ns) than would otherwise be possible with other approaches for output voltage control. Furthermore, the individual on and / or off (sometimes “on / off’) control of each converter in a given group of series-stacked converters can also be timed such that one or more converters are delayed with respect to the others to realize a desired output voltage waveform shape.

[1124] In certain examples, multiple DC-DC converter cells can be turned on or off at a controlled sequence during control set point change to minimize output waveform overshoot or undershoot (the set point being the point at which the electrical circuit, or cell, is activated or de-activated). Such multiple DC-DC converter cells can also operate at a synchronous switching frequency but having different phases to achieve output ripple cancellation.

[0025] In some embodiments, the DC-DC converter cells may include push-pull resonant power inverter stages, and adjustment of output voltage of one or more DC-DC converters may be achieved by phase shifting the two push-pull branches within the inverter stage. In certain example circuits according to the present disclosure, the range over which phase shifting is utilized is limited to providing only small adjustments in output voltage so that the DC-DC conversion efficiency is not impacted.

[0026] In some embodiments, additional switching stages such as a half-bridge, a fullbridge, a pull-down switch, or a pull-up switch can be cascaded after the output of each individual DC-DC converter cell or multiple DC-DC converter cells to further improve the transient response (e g., rise time, fall time, etc.) of the output waveform.

[0027] Example embodiments of the present disclosure may include a measurement and controls module that is responsible for (a) relaying signals from various sensors within the system, such as output voltage, output current, individual stack current, to name a few; (b) processing the received signals; and (c) providing appropriate commands to the DC-DC converters and the output switching stages. The control module may also contain information on the shape of the desired pulse waveform and its characteristics.

[0028] In some embodiments, a method for controlling the system includes receiving output voltage and corresponding output current set points, identifying an operating region or “zone” within the current-voltage space, and adjusting the DC-DC converter cell configurations according to a preassigned configuration for each region. Such configurations may include a number of enabled DC-DC cells connected in series, a number of enabled cells connected in parallel, operating frequency, input voltage, duty cycle, and / or phase-shift within individual DC-DC cells. The preassigned configurations may be stored in appropriate memory locations within the system controller, such as using lookup tables, or other means.

[0029] In some embodiments, the set points may be provided to the system controller via analog voltage signals fed to the system, with digital signals represented by a number of bits being transmitted to the controller via serial communication including RS232, RS485, or others, parallel communication, ethemet, universal asynchronous receiver-transmitter (UART), etc., or as values encoded in the form of pulse width modulation.

[0030] In some embodiments, once the DC-DC cell configuration is determined based on the operating region within the current-voltage space, the system may transition to a closed-loop control mode, wherein the operating frequency, input voltage, or both, are dynamically adjusted to achieve a desired output voltage or current.[003 i ] In other embodiments, once the DC-DC cell configuration is determined based on the operating region within the current-voltage space, the operating frequency for the DC- DC cells may be determined via a simple or adaptive feedforward scheme wherein the frequency is selected based upon a preassigned frequency table. Such a table may include operating frequency or input voltage at various combinations of desired output voltage and corresponding current set points.|O032] In some embodiments, a single frequency table may be preassigned for all regions within the current-voltage space. In other embodiments, a unique preassigned frequency table may be used for each region within the current-voltage operating space. The one or more frequency tables may be pre-populated during system characterization by manual entry, automated population via one or more scripts while training the system on a target load, or by other means.

[0033] In other embodiments, a method for controlling the system includes receiving output voltage and corresponding output current set points, determining the number of stacks to be enabled, dynamically incrementing or decrementing the number of DC-DC cells connected in series such that the measured output voltage is within a threshold of the desired output voltage, and dynamically adjusting the operating frequency, duty cycle, and / or phaseshift within individual DC-DC cells.

[0034] In the above and / or other embodiments, the system may be operated to produce repetitive pulses. A method for controlling such a system may include initially, for a given pulse, selecting the DC-DC cell configurations, including operating region, frequency, duty cycle, among others, based on the last known configuration from the preceding pulse. The system may then transition to closed-loop mode where the operating frequency and region may be adjusted such that the output converges to the desired operating point.

[0035] In some embodiments, a method for controlling rise times, fall times, overshoot, or combinations thereof, of the output waveform may include frequency ramping, whereby the operating frequency is smoothly adjusted to achieve a desired transient behavior. Further, some embodiments may utilize frequency stepping, such as within a pulse, to adjust the output voltage level smoothly, and certain example embodiments of the present disclosure may be suitable for a range of applications, including plasma processing in semiconductor manufacturing. Advanced plasma etching systems, for example, require a tailored bias voltage waveform with a positive short pulse followed by a negative linear ramp. This type of bias voltage waveform can provide narrower ion energy distributions (e.g.. as may be compared to a more-conventional sinusoidal waveform), with maximum pulse voltages reaching 10s of kV, rise times of <100 ns, and / or negative linear ramps lasting several ps. Certain specific example embodiments of the present disclosure may also provide the capability of adjusting the voltage levels, pulse widths, as well as ramp times, to accommodate a wide range of semiconductor etching recipes.

[0036] In yet further aspects which may be used alone and / or in combination with the above types of example power converters, the present disclosure is directed to an transformercore that includes: a primary winding and one or more secondary windings shaped to mitigate or minimize eddy current losses, and a multilayer printed circuit board (PCB) including a plurality of layers securing traces for the primary winding and a plurality' of layers securing traces for the secondary winding, and including vias through certain of the traces to minimize winding losses and to facilitate thermal conductivity, wherein the PCB. the primary winding and the secondary winding are cooperatively stacked, vertically among certain of the plurality of layers of the PCB, to facilitate magnetic coupling between the primary winding and the secondary winding.

[0037] The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. It should be appreciated that such embodiments (and related aspects) may be combined unless indicated otherwise. The figures and detailed description that follow' also exemplify the above and various other aspects and embodiments.BRIEF DESCRIPTION OF FIGURES

[0038] Various example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, each in accordance with the present disclosure, in which:

[0039] FIG. 1 is a block diagram of a system, according to an example embodiment of the present disclosure, capable of generating nanosecond high voltage pulses w ith customized (arbitrary) waveform shapes. The diagram illustrates a power stage block comprising DC-DC converter blocks forming multiple stacks, optional switching stages cascaded with the DC- DC blocks, and a controller (and related circuity) block;

[0040] FIGs. 2A-2D are a series of schematic diagrams of example implementations of a switching stage. FIG. 2A is an example implementation using a pull-up switch that may be used to achieve fast output voltage charging across a load;[0041 j FIG. 2B is an example implementation of the switching stage using a pull-down switch that may be used to achieve fast output voltage discharging within a series stack and / or across a load;

[0042] FIG. 2C is an example implementation of the switching stage using a half-bridge structure with both a pull-up switch and a pull-down switch that may be used to achieve fast output voltage charging or discharging within a series stack and / or across a load;

[0043] FIG. 2D is an example implementation of the switching stage using a full-bridge structure with pull-up switches and pull-down switches, that may be used to achieve both fastoutput voltage charging or discharging, as well as voltage polarity within a series stack and / or across a load;

[0044] FIG. 3 shows a flow diagram illustrating one method of controlling the system to achieve a desired output voltage pulse waveform;

[0045] FIG. 4 shows a plot illustrating an example in which current-voltage space is divided into regions or zones;

[0046] FIG. 5 shows a plot of an example in which the current-voltage space is divided into regions or zones that are not necessarily rectangular; 0047 ] FIG. 6 shows a flow diagram illustrating a method of controlling the system byenabling DC-DC cells based on the operating zone in the current-voltage space in feedforward mode, and using closed-loop feedback to adjust frequency, duty cycle, and phase-shift to arrive at the desired output voltage;

[0048] FIG. 7 shows a flow diagram illustrating a method of controlling the system of FIG. 1;

[0049] FIG. 8 shows a flow' diagram illustrating another method of controlling the system of FIG. 1 with feedback;

[0050] FIG. 9 shows a flow diagram illustrating a method for controlling the system when a desired pulse is repeated in time;[005 s ] FIG. 10 shows a schematic diagram of an example load with a substantially capacitive component that can be driven using the type of system shown in FIG. 1. This load is ty pically seen in semiconductor processing bias power source applications. The example simulated system uses this load model in the presented voltage waveform example plots;

[0052] FIG. 11 is a plot of example output voltages of the system as a function of time; this plot demonstrates an example of the capability of the system to generate high-voltage pulse waveforms with nanosecond rise and fall times, and with adjustable pulse widths;

[0053] FIG. 12 is a plot of example output voltages of the system as a function of time; this plot demonstrates an example of the capability of the system to generate high-voltage pulse w aveforms with nanosecond rise and fall times, and with adjustable slopes during the fall time, as is commonly required in some semiconductor processing applications;

[0054] FIGs. 13A-13C show scope shots illustrating adjustability of rise or fall time slopes between consecutive pulses by timing the turn-on and turn-off of cells in a prescribed sequence;(0055 J FIGs. 14A-14B show scope shots illustrating adjustability of pulse peak voltage levels by timing the tum-on and turn-off of cells in a prescribed sequence to obtain customized voltage waveforms;

[0056] FIG. 15 is a plot of example output voltages of the system as a function of time; this plot demonstrates an example of the capability of the system to generate high-voltage pulse waveforms with nanosecond rise and fall times, and with adjustable inflection points (the starting points of the controlled-slope duration of the waveform), as is commonly required in some semiconductor processing applications;

[0057] FIG. 16 is a plot of various example output voltages of the system as a function of time; this plot demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series-stacks in parallel) on the overall waveform shape of an example pulse. In this example, 16 cells were series-stacked, and a number of these stacks were paralleled to get to the desired total number of cells;

[0058] FIG. 17 is a plot of various example output voltages of the system as a function of time; this plot demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series-stacks in parallel) on the achievable rise times of an example pulse. The plots zooms in around the vicinity of the rising edges for additional clarity. In this example, 16 cells were series-stacked, and a number of these stacks were paralleled to get to the desired total number of cells;

[0059] FIG. 18 is a plot of various example output voltages of the system as a function of time; this plot demonstrates the effect of changing the total number of DC-DC converter cells (e.g., by adding more series-stacks in parallel) on the achievable fall times of an example pulse. The plot zooms in around the vicinity of the falling edges for additional clarity. In this example, 16 cells were series-stacked, and a number of these stacks were paralleled to get to the desired total number of cells;

[0060] FIG. 19 is a plot of rise time, fall time, and estimated bill-of-materials (BOM) cost of the power stage as a function of the total number of DC-DC converter cells used. In this example, 16 cells were series-stacked, and a number of these stacks were paralleled to get to the total number of cells shown on the x-axis;

[0061] FIGs. 20A-20B show scope shots depicting example pulse fall time adjustment by ramping the operating frequency;

[0062] FIG. 21 show a scope shot illustrating the use of frequency stepping for smooth voltage level adjustments within a pulse;(0063 J FIGs. 22A-22B show scope shots illustrating the use of frequency adjustment within a pulse to correct for input voltage rail variation effects using feedforward;

[0064] FIG. 23 is a schematic diagram of one of many approaches for implementing a converter cell and with a control block driving the converter cell by using gate-control signals to engage an inverter;

[0065] FIG. 24 shows a control block (e g., logic circuitry) sending control signals to selectively engage certain cells in and among a stacked arrangement of converter cells to control output overshoot in the output signal of the converter cells;

[0066] FIGs. 25 A, 25B and 25C show alternative block diagrams for respective approaches to provide power to a stacked arrangement of converter cells, with FIG. 25A having input signals to the converter cells referenced commonly to a single pair of power rails, and FIG. 25B and FIG. 25C having different configurations, each with input signals to certain of the converter cells referenced to different sets of power rails;

[0067] FIG. 26A and FIG. 26B are diagrams showing respective cross-sectional views for corresponding planar transformers, either of which is applicable to a transformer-based implementation of one or more of the converter cells show n in FIG. 1, with FIG. 26A indicating there are vias dispersed throughout the planar windings (e.g., improving thermal issues) on different layers, and FIG. 26B showing normal planar windings;

[0068] FIG. 27 is an exploded view' of a PCB planar transformer which may be used with one or more of the converter cells depicted for the system of FIG. 1.

[0069] While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary', the intention is to cover all modifications, equivalents, and alternatives falling w ithin the scope of the disclosure including aspects defined in the claims. In addition, the term "example" as used throughout this application is only by way of illustration, and not limitation.DETAILED DESCRIPTION

[0070] Aspects of the present disclosure are believed to be applicable to a variety of different ty pes of apparatuses, systems and methods involving devices characterized at least in part by generating nanosecond-scale high-voltage pulses having customized waveform shapes (e.g., including closely around the vicinity of one or more peaks and / or fast rise and fall times). Aspects of the present disclosure have been found to be particularly beneficial for delivering power to equipment used in plasma processing in the semiconductor manufacturing industry'. While the present disclosure is not necessarily limited to such aspects and / or specifically in the field of plasma processing, an understanding of specific examples in the following description may be understood from discussion in such specific contexts.

[0071] Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination. 0072] Exemplary aspects of the present disclosure are related to power supplies and / or power conversion methods and circuit-based apparatuses involving use of logic circuitry to selectively engage (e.g., activating and / or deactivating) a plurality' of resonant-isolated DC- DC converter cells. The selective engagement of respective ones of the converter cells is to effect a combining of output signals from the converter cells to generate an aggregate (e.g., high-voltage) output signal having a waveform shape that is customized based on the selective engagement. In a more specific example, due to the inherent fast response of the converter cells, nanosecond level pulsing and customized high voltage waveshaping is achieved by controlling the timing of turning on or off the DC-DC converter cells and the voltage of each converter cell. In certain specific example embodiments the selective engagement includes operating at least a subset of the converter cells via a frequency set of one or more sufficiently-high switching frequencies in a range of high frequencies (e.g., fromabout 1 MHz to 100 MHz) over at least several cycles of the frequency set to manipulate the waveform shape in a fractional portion (e.g., in individual portions corresponding to a small percentage of a full cycle, such as significantly less than a quarter or an eighth) of the output signal at the output terminal of the converter cells.

[0073] Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No. 63 / 518,883 filed on August 11, 2023, to which priority is claimed. To the extent permitted, such subject matter is incorporated by reference in its entirety generally and to the extent that further aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarify.

[0074] According to certain more specific examples, the present disclosure is directed to a method, and alternatively a device, involving the ability to produce accurately controlled pulsed voltage waveforms having unique and challenging characteristics, such as in modem industrial applications where this is an ever-increasing need. These characteristics include waveforms of pulsed nature involving rise and fall times in the nanosecond timescale, with high voltages in the tens of kilovolts, and with the ability to control other voltage waveform features such as slope, pulse width, and pulse repetition rates. Embodiments described herein provide a customized waveform high voltage pulse generation system that satisfies such requirements in various applications, including plasma processing in semiconductor manufacturing.

[0075] In such plasma processing applications, for example, plasma etching provides the advantage of anisotropic etching due to energetic ion bombardment of the substrate, making it conducive for etching small and high aspect ratio features in wafer processing. In many plasma etching systems, a sinusoidal bias voltage supply is used to control the ion energy. Because of the time-vary ing nature of a sinusoidal waveform, ion fluxes impinging on a wafer substrate typically have bimodal and wide ion energy distribution functions (IEDF). This is not optimal when smaller and higher aspect ratio etching features are demanded for the most advanced semiconductor technology, which require very narrow IEDF. A tailored bias voltage waveform wi th a positive short pulse followed by a negative linear ramp can provide narrower ion energy distributions compared to the conventional sinusoidal waveform. Depending on specific types of plasma etching applications, the optimal maximum pulse voltage might be >10 kV with a rise time of <100 nanoseconds, and a negative linear ramp lasting several microseconds. It is also desired for a plasma etching tool to have the capability of adjusting the voltage levels, pulse widths, as well as negative ramptimes, to accommodate a wide range of etching recipes. For these reasons, having a pulse generation system with such capability enables accurate control over the shape of the IEDF at the surface of a substrate, thereby pennitting precise control of the features on that substrate.

[0076] FIG. 1 is a block diagram of a type of system, according to an example of the present disclosure, for high-voltage nanosecond pulsing and customized waveform generation comprising two stages: a power stage and a controller stage (in some instances a controller and measurement stage). Another important aspect in the operation of a pulse generator system, according to the present disclosure, is its ability to: (a) generate the required high voltages; (b) rapidly adjust the output voltage level from very low / high voltages to very high / low voltages; and (c) modify the output voltage level with time precisely according to a prescribed pattern, such as a ramp waveform, a sawtooth waveform, a triangle waveform, and / or otherwise.

[0077] As illustrated in FIG. 1, the power stage comprises a modular array of isolated DC-DC converters. These converters in the array are fed from a DC voltage source (e.g., a front-end AC / DC converter, another DC-DC converter, or other source) and act as power building blocks to realize a desired output voltage and current in a specific application. In certain example circuits also according to the present disclosure, the converters are identical in terms of component and architecture, or alternatively the converters are designed differently in these regards (within the array), for example, with different output voltages / pow-er, different switching frequencies, different transient responses, and / or different isolation requirements. A plurality of converters may be stacked in series to realize a higher desired output voltage or speed up the transient response of the output waveform. Each converter is optimized to produce an output voltage Vcdi and an output current Iceii therefore, when AT of these converters are connected in series, the resulting voltage produced across the series stack is MVceii. Similarly, multiple stacks may be connected in parallel to provide a desired output current that is higher than the rated current of an individual converter stack. Specifically, when N converter stacks are connected in parallel, the resulting cunent provided to the load is NIcdi. In this manner therefore, a suitable combination of M N converters can be selected to meet a target load voltage, current, or rise time. In certain example circuits according to the present disclosure, the stacks are designed (and optionally may be substantially identical) such that they can share current equally among them as much as practicably possible. In certain other example circuits according to the present disclosure, the stacks are not substantially identical and the system still functions correctly; however, it may be helpful to mitigate thermal issues (e.g., vias in traces, vias in the PCB, heat sinks, and / ormore conventional cooling mechanisms such as fans). Such thermal issues ensue as stacks conducting higher currents relative to other stacks may become overloaded, resulting in efficiency degradation, overheating, or both.

[0078] In certain examples, a controller block (as at the bottom of FIG. 1 (e.g., optionally including related circuitry such as measurement circuitry, sensors, comparators, and / or CPU-based circuits) is used to selectively engage (e.g., activate) the DC-DC cells to cause the outputs of the cells to be combined in series. This in-series arrangement may correspond to a series stack of certain of the converter cells such as, but not necessarily limited to, a series stack with a broad range of converter cells such as including 2-3 converter cells at the lower end and up to 30 or more converter cells at the upper end.

[0079] In conjunction with the appropriate selection of M and N, the design choices for the individual DC-DC converter cells are of equal importance. Each cell includes an inversion stage, isolation stage, and a rectification stage. Design choices for inversion and rectification stages include the topology of the cell, selection of active power devices with appropriate voltage and current ratings, and the tuning of component values. Example circuits for the inversion stage may include resonant switched-mode push-pull topologies, which can allow adjustment of output voltage by phase-shifting constituent inverters. These may include push-pull variants of resonant class D, class E, class F, or 2 topologies, among others. In certain applications, for optimal efficiency and mitigating losses, switched-mode designs utilizing zero-voltage switching (ZVS) of the active devices may be used. Additionally, in certain designs high-switching frequencies (e.g., Is to 10s of MHz, or Is to 100s of MHz and beyond) are used to minimize energy storage, volume, and weight requirements. Non-push- pull switched-mode resonant variants may also be used if inverter phase-shifting within a DC-DC converter cell need not be used for output voltage control. For rectification, similar resonant topologies may be used whereby the rectifying components may consist of semiconductor switches or diodes.

[0080] Power stage isolation between inverter and rectifier stages may be achieved using a separate standalone transformer with appropriate voltage standoff rating across the primary - to-secondary windings. In other example implementations, the transformer primary and secondary windings are integrated into the inverter and rectifier stages, respectively. Adequate voltage isolation between the windings may be provided by controlling the spacing between primary and secondary windings, introducing one or more high-voltage standoff materials between windings (e.g., polyimide films, coatings, etc.), or both. As one of many examples in this context, reference may be made to U.S. Pat. No. 11,228,252, which disclosesa planar-PCB transformer as an isolation stage between inverter circuitry and DC-DC rectifier circuitry. with Figs. 1, 2A, 2B, 4A-4C, exemplifying a planar PCB transformer that provides the inductive isolation in each of several stacked DC-DC converters.

[0081] The inverter and rectifier stages may be designed so as to allow bidirectional flow of energy to and from the load. This may be useful in cases such as when the load consists of an energy storage element (e g., when it is a substantially capacitive load). The power stage can channel the stored energy' back to the input by receiving appropriate control signals to reverse the energy flow. In applications requiring repeated charging and discharging of a capacitive load, for example, the energy that is redirected back to the input prevents it from being lost and dissipated as heat, thereby improving system efficiency and reducing the need for additional thermal management.

[0082] The power stage may optionally also comprise an additional switching stage (e.g., half-bridge, full-bridge, a pull-down switch, a pull-up switch, etc.) connected across the output of each DC-DC converter as shown in FIG. 1, where each of these switches is rated up to the maximum expected voltage at the converter output. Alternatively, or additionally, specific example embodiments according to the present disclosure have a single or multiple switching stages connected across multiple DC-DC converter cells, or the output of the system (i.e. across the load), where each of these switches is rated up to the maximum expected voltage at according nodes. In these and other embodiments disclosed herein according to the present disclosure, the additional switching stages may be incorporated to further improve the rise time and / or fall time of the output waveform. FIGs. 2A-2D illustrate schematic diagrams of example embodiments of such switching stages, including the ability for achieving a voltage pull-up using a series semiconductor switch (FIG. 2A), a voltage pulldown using a shunt semiconductor switch (FIG. 2B), both pull-up as well as pull-down using a half-bridge arrangement of sw itches (FIG. 2C), and all of the above with the ability' to swap output voltage polarities using a full-bridge arrangement (FIG. 2D). As one of many examples of a switching stage / supply in this context, reference may be made to U.S. Pat. No. 1 1,978,611 (e.g., passim and disclosing with Fig. 2 a switching-mode supply with a controller that generates drive-control signals to engage high-power (FET) switching components). It is to be understood that these are only example embodiments of the switching stage and should not be regarded as limiting. As such, those skilled in the art will appreciate that other implementations are possible, such as using multiple switches instead of a single switch, among other possibilities.

[0083] Due to the isolated nature of the DC-DC cells in the type of system shown in FIG. 1, the system can be configured to provide an output voltage waveform that can be positive or negative with respect to a reference node within the system. Therefore, the system can also be configured to provide an output voltage waveform that can be unipolar or bipolar. It is to be noted that when the system is driving a capacitive load, bipolar pulses centered at zero require half of the energy compared to unipolar pulses to achieve the same pulse voltage differentially across the capacitor.

[0084] A controller block as show n at the bottom of FIG. 1 is normally required to achieve the control objectives of the system and ensure correct and safe operation of all system parts including the power stage. Specifically, this stage obtains various measurements from the power stage as appropriate, processes these measurements, and provides the necessary' control signals to the power stage to achieve the desired output w aveform shape and voltage level.

[0085] This stage may comprise measurements and control signals present at either side of the isolation barrier of the power stage. For these signals, various ways can be used for the signals to cross the isolation barrier. These include, but are not limited to, using galvanic isolation such as transformers, capacitive isolation, or optical isolation. Such schemes are applicable to both analog and digital measurement and control signals.

[0086] Various control methods may be suitable for the high-voltage customized pulse generation system of the type disclosed with FIG. 1. In various examples, multiple means of voltage, current, and / or power control are optionally implemented. Enabling and disabling the inverter stage of individual DC-DC converter cells allows for rapid changes in voltage, power, and / or current. Having a system made up of many series / parallel strings of cells allow s for relatively fine control of the output w hile allowing each cell to operate close to its optimal conversion efficiency. Enabling and disabling DC-DC cells (sequentially and / or selectively) in this manner can be beneficial when relying on a variable input DC bus voltage which may have limited control bandwidth and / or transient response.

[0087] Frequency can be used as a method of controlling the output of the system due to the resonant nature of the DC-DC cells. Changing the fundamental DC-DC conversion frequency can be used to adjust voltage, current, and power. Frequency can also be adjusted to optimize transient response and achieve a desired wave shape when moving from one operating point to another. Frequency can be adjusted as a method of optimizing conversion efficiency or minimizing losses in various components within the power stage.

[0088] For inverters using a complimentary “push-pull” design, the gating signals of a single cell, generally operating at a relative phase of 180 degrees, can be phase shifted to control the amplitude of the voltage signal driving the rectifier portion of the cell. This phase control can thus allow the voltage, current, and / or power contribution of individual inverters to be adjusted. In certain examples, also according to the present disclosure, the range over which phase shifting the gating signals is utilized is limited to provide only small adjustments (e.g., less than P%, where P is greater than 0 and less than 5, 10 or 15) in output voltage so that the DC-DC conversion efficiency is not adversely impacted. The phase of each DC-DC cell can also be coordinated with respect to each other DC-DC cell to reduce or substantially cancel the voltage and / or current ripple experienced by the load and / or allow for reduced output filtering and better dynamic response.

[0089] Gating duty7cycle of the inverters can be used to optimize cell conversion efficiency. Dynamic adjustment during operating point changes can be used to adjust transient response.

[0090] The input DC voltage to the resonant DC-DC converter cells can be adjusted to control the output voltage of the unit to achieve a specific voltage target or optimize performance of a specific operating point. While a single variable DC bus feeding all DC-DC converter cells is possible, sub-groups of cells, such as series and / or parallel strings, and even individual DC-DC cells can have their own variable DC voltage rail to add tunability and flexibility to the system. Examples of this approach are disclosed in connection with FIGs. 25B and 25C.10091] Feedback can be based on measured voltage, current, and power, including derivatives of these signals and calculated load impedance. In instances where repeated or pulsed output signals are required, the system can “learn” from the previous pulse(s) and adjust for the next pulse by measuring and analyzing the telemetry data at discrete times during a pulse. The control parameters can thus be adjusted by defining a trajectory7in an adaptive feedforward scheme rather than simply as a result of pure feedback. The power supply can optionally store these control parameters in system memory. Various sets of control parameters may be obtained by training the system on a range of loads and stored in appropriate memory within the system, such as lookup tables (LUT) or other means. Similarly, such control parameter sets may be transferred to system memory from an external device (e.g., a computer) based on prior knowledge and characterization of the system. FIG. 3 depicts a flow diagram of an example control strategy7as described above to achieve a desired output waveform.

[0092] In many examples according to the present disclosure, the operating output voltage-current space may be divided into regions or zones (e.g., as in FIGs. 4 and 5), where different sets of control parameters, such as number of DC-DC cells to be enabled in series or parallel, can be preassigned for each region. In certain example embodiments of the present disclosure, the operating current-voltage space is divided into rectangular regions. Such division may, for example, allow for simple selection of number of series or parallel DC-DC cells to enable: if more voltage is desired for the same output current, more cells can be enabled in series; if more current is desired for the same output voltage, more cells can be enabled in parallel, as shown in Table 1. as provided below:Table 1

[0088] While FIG. 4 shows such regions being rectangular, in other cases need not be necessarily rectangular. It may be desirable to assign the enabling of series or parallel DC-DC cells, for example, based on output voltage, current, power, efficiency, losses, or any combinations thereof, resulting in many possible shapes for the regions, including irregular ones. An example is illustrated in FIG. 5, which shows a combination of rectangular (at low voltages / currents) and non-rectangular regions. Whereas in these examples each region corresponds to an assignment of enabled series or parallel cells, it may also correspond to other control parameter choices, including operating frequency, duty ratio, input voltage, or phase-shifts within DC-DC cells.

[0089] Various example methods for controlling the system by utilizing these regions are given. FIG. 6 shows a flow diagram describing one such method. The first step involves the controller receiving a desired output voltage set point and a desired output current set point (which may be derived, for example, from the desired output voltage and a loadimpedance value). Based on these desired set points, the system then determines the operating region and retrieves the preassigned number of series and parallel enabled DC-DC cells (e.g., stored in system memory) in feedforward mode. The system then enables these cells at an initial operating frequency that can be predefined distinctly for each region, or identically for all regions. The system may then enter a closed-loop mode where one or more of the: cell switching frequency, duty cycle, or phase-shift, is dynamically adjusted such that the output voltage converges to the desired set point. For example, in many applications according to the present disclosure, it has been discovered that in certain examples, the output voltage can be caused to converge to the desired set point by entering the closed-loop mode in conjunction with dynamically adjusting the cell switching frequency.

[0090] FIG. 7 shows another example method for the system of FIG. 1, wherein parallel stacks can be set based on corresponding output current set point. The method of FIG. 7 uses a coarse closed-loop voltage feedback to set the number of series enabled cells, and another closed-loop feedback for fine control of particular output signal parameters. The coarse closed-loop voltage feedback is run first, wherein the selective engagement of the cells includes discrete enabling and disabling of DC-DC cells to coarsely achieve an output voltage that is within some predefined threshold t) from a given desired output voltage set point. Once that is achieved, the system may enter a closed-loop mode with the system controlling (e.g., by adjustments and / or re-settings) of particular signal parameters such as frequency, duty cycle, and / or phase-shift, to achieve a relatively finer output voltage control as compared to the threshold 3.

[0091] Another control method example applicable to the system of FIG. 1 is shown in FIG. 8, and this involves input voltage variation and feedback control. More specifically, Error! Reference source not found, shows a block diagram illustrating a method of controlling such a system by using coarse closed-loop voltage feedback for the selective engagement setting the number of series enabled cells, and another closed-loop feedback for fine control by adjusting the DC voltage rail at the input of the cells. In other words, in addition to a closed-loop mode for coarse control by enabling / disabling cells, fine control adjustment may be achieved by adjusting the input DC voltage to the converter cells. Depending on the speed with which input voltage can be varied, this approach of FIG. 8 may be beneficial when output voltage convergence to the desired set point is allowed to happen at a slower time scale than would be possible with a closed-loop based on cell switching frequency, such as within several pulse cycles.

[0092] In many cases, it may be required to generate a pulse voltage waveform that repeats in time at some repetition rate. Some applications may dictate narrow pulse widths (e.g., Is or 10s of ps) that can make settling to the desired voltage set point difficult to achieve on the first pulse. Such cases may utilize control methods better suited for pulsed applications that allow the system to “learn’7from previous pulses, and can thus allow the system to reuse the system configuration from previous pulses. The system may then operate starting with those system parameters and then adjusting cell parameters such as cell switching frequency (or duty cycle, or phase shift, or combinations thereof) until the desired output voltage is reached or cell parameters exceed predetermined bounds. In that case, the system may adjust the number of enabled cells and repeat adjustment of cell parameters. This process may repeat until the desired output voltage is achieved. FIG. 9 shows an example of one such control method, wherein at the start of a new pulse the controller retrieves from a memory database (e.g., in the controller of FIG. 1): the desired voltage(s) and corresponding current set points, and other system configuration parameters (for supplying power to the load), at the end of the last pulse. This data retrieval, in various example embodiments, may include a specified ones (or a number of) of enabled series and parallel DC-DC cells, operating frequency, duty cycle, phase-shift, and / or other control parameter(s) as may be appropriate (exemplary ones of such control parameter(s) are disclosed throughout the present disclosure).

[0093] It is to be understood that the disclosed subject matter is not limited in its application to the implementation details and to the arrangements of the components set forth in the description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways.

[0094] To demonstrate the utility of the type of system shown in FIG. 1, an example system is designed and simulated for a typical semiconductor processing bias load model. One such circuit model that is commonly used in semiconductor bias applications is shown in FIG. 10. The components can take on a wide range of values; Table 2 below shows the selected component values of the load circuit model in the simulations described hereafter. Experimental examples, according to the present disclosure, demonstrate how the system can be used to synthesize the desired bias voltage waveforms with adj ustable waveform parameters, including on-time, falling slope, and inflection point. Such examples also show how rise and fall times change as the total number of DC-DC converter cells in the system is scaled.Table 2

[0095] With reference to Table 2,refers to the number of 16-cell stacks that are connected in parallel. For example, to achieve a total of 128 cells in the system, 8 of the 16- cell stacks would be connected in parallel so / would be assigned the value of 8, and so on.

[0096] According to various examples of the present disclosure, output waveforms can be adjusted, for example, by way of a controller (aka logic circuitry) as discussed supra. FIG. 11 shows an example of the output voltage waveforms having different pulse widths (i. e. , on-time). The pulse on-time can be adjusted arbitrarily. In this example, the pulse width was adjusted by adjusting the timing and number of enabled DC-DC cells.

[0097] FIG. 12 shows an example of the output voltage waveforms with different falling slopes during the portion of the waveform after completing the prescribed on-time.Controllability of the rising or falling slope of the voltage during such portions of the waveform is highly desirable in some applications, such as in some semiconductor manufacturing processes. In the system disclosed herein, the slope can be adjusted in real time by controlling the output voltage to track a sequence of control set points. Multiple control means can be used to achieve this, as described earlier; in this simulation example, the waveforms with the different slopes were generated by simulating the system in an openloop configuration and by controlling the number of enabled DC-DC cells over time.

[0098] FIG. 15 shows an example of another simulated demonstration wherein the output voltage waveforms show different inflection points, which are the instants marking the start of the controlled-slope portion of the waveform described earlier. The inflection point can be adjusted by controlling output voltage during the fall time. In this illustration, inflection point 1 appears as an undulating plot beginning just before 0.5 ps (microseconds) before merging with the delayed inflection point (inflection point 2).

[0099] It can be concluded from these demonstrations (FIG. 15 among others disclosed herein) that the system is indeed capable of adjusting specific aspects of the waveform shape and is able to adapt the output voltage at tens of nanosecond timescales.

[0100] Another important aspect for certain examples of the present disclosure is the scalability to a higher number of stacked converters. As disclosed herein, the example stacked converter arrangements may be widely varied by the scalability of the architecture. In experimental efforts leading to the present disclosure, modifications of simulation examples demonstrate tradeoffs in scaling to a higher total number of converters while using the same DC-DC cell design. Exemplary systems herein, include examples based on successful experimental and / or proof-of-concept efforts (simulations and / or prototype-like embodiments) in support of the present disclosure, are used with a relatively large range for total number of DC-DC cells (e.g., 360 total cells, in some specific instances with on the order of a hundred or hundreds of cells such as between 128 and 1024 total cells), and the pulse rise time is measured (going from 5% to 95% and 10% to 90%) and the fall time (ranging from 5% to 95%). FIG. 1 shows the overall shapes of the voltage waveforms for the selected number of DC-DC cells. It is noted, that the plot lines on the right of FIG. 16 are depicted in the same order as in the legend, from top to bottom. It can be seen that a higher number of cells can generally result in faster rise and fall times. FIG. 17 provides a zoomedin view in the vicinity of the pulse rising edges. It is noted, that the vertical plot lines of FIG. 17 are depicted in the same order as in the legend, if viewing the plot lines from right to left. FIG. 18 provides a zoomed-in view in the vicinity' of the pulse falling edges. It is noted, that the plot lines on the right of FIG. 18 are depicted in the same order as in the legend, from top to bottom. In all the aforementioned examples, 16 DC-DC cells were stacked in series, and several of these stacks were paralleled to achieve the indicated total number of cells. The extent to which more cells in the system affect the rise and fall times of a given output voltage pulse depends upon the exact implementation of the system, including the switching stage(s) shown in FIG. 1.

[0101] An estimate of the cost of the bill of materials (BOM) is also calculable for each choice of number of DC-DC cells. In one such example estimate, the results shown in FIG. 19 indicate that increasing the total number of converters in the system results in a linear increase in the cost of the BOM. The results also show an appreciable reduction in rise and fall times of the output voltage pulse as the number of cells is increased to about 384. Beyond that number, however, increasing the number of cells provides diminishing returns due to rapidly increasing BOM cost and no significant reduction in rise or fall times. Note thatanother benefit of increasing the number of cells not conveyed in FIG. 19 is the reduction in discrete step size in output voltage (e.g., as a percentage of total output voltage) as a result of enabling or disabling individual converters.

[0102] Accordingly and based at least in part from the example simulated demonstrations, there generally is an optimal total number of cells to be used for a given cell design and a given output waveform requirement.

[0103] According to certain specific example embodiments also according to the present disclosure, FIG. 23 is a schematic diagram of one of many approaches for implementing a converter cell (including an inversion stage, an isolation stage, and a rectification stage. FIG. 23 also shows timing diagrams, at the lower portion of the illustration, related to optional uses of a control block (e.g., logic circuitry) driving the converter cell by sending gate-control signals to engage an inverter and with the gate-control signals (or simply “gate signals'’) being manipulated to minimize drain voltage during transients and / or for fast rise times in the output signal at the output terminal of the converter cells.

[0104] For a more general context, the control block may include or refer to logic circuitry cooperatively arranged with a plurality of resonant-isolated DC-DC converter cells in an apparatus having respective output terminals of the converter cells configured to combine (or aggregate), at an output terminal, output signals respectively produced by the converter cells. The logic circuitry is used to selectively engage respective ones of the converter cells (e.g., selectively activating and / or deactivating) the converter cells to generate an output signal having a waveform shape that is customized based on the selective engagement. In more specific examples, the control block and related timing diagrams of FIG. 23 may be used to illustrate how transient portions of the pulse waveform may be readily and efficiently controlled in a form that more closely follows a desired waveform shape. As examples, such desired waveform shape and related control are discussed hereinabove in connection with FIGs. 6-9. 11, 13A-13C and 20A-20B.

[0105] In certain other examples according to the present disclosure, the gate signals (FIG 23, to the right of the controller), can be generated and / or manipulated (e.g., adjusted) by the controller, as well as intervening circuitry or components (not shown) to affect one or more of the following aspects: the switching behavior, both in switch stresses and output performance (rise time, overshoot, etc.) in terms of operating frequencies, frequency modulation, and duty’ control. Certain of these converter examples, according to the present disclosure, are designed to operate where frequency has an inverse relationship with output voltage and current capability7. The open loop rise time also depends on frequency, owing tothe presence of tuned reactive elements in the DC-DC cell design. In this common case, faster rise times can be achieved by operating at a lower frequency during the initial rise. Likewise, slower response and reduced overshoot can be achieved by operating at a higher initial frequency.

[0106] In such examples that use inverters based on a Class E design in which the drain nodes (DI and D2 of the respective FETs shown in FIG. 23) are unclamped, precise control over the gate drive signals may be important, for example, to mitigate or prevent occurrences of overvoltage and / or to limit power loss. According to one aspect of the present disclosure, the controller generates the gate drive signals for gates G1 and G2 of FIG. 23 to reduce the initial voltage spike on the drain. In one more specific example, this is achieved by setting the first gate pulse width to around half the later value (in different more-specific examples, “around half’ is within 5-10%, 10-15%, and in some instances within 20-25%). This is because there is no initial input inductor Lf current or load current, so fewer volt-seconds are required to reach the steady state turn off condition. The same principle can be applied to adjust subsequent gate pulses to track transient inverter and load conditions.

[0107] The timing diagrams of the gate drive signals are illustrated at the lower portion of FIG. 23. With reference to the example schematic at the top of FIG. 23, the horizontal axis shows relative timing for the control voltages presented to the gates (G1 and G2) and the corresponding drain voltages (DI and D2), with the left side of the timing diagram showing the such pulse-width manipulated control signals for effecting low drain voltage (e.g., represented at the bottom of the timeline of FIG. 23).

[0108] According to another optional aspect of the present disclosure, the controller generates the gate drive signals to control the signal transition timing (e.g.. faster rise time) at the output of the converter cell (Vo+ and Vo- of FIG. 23). Generally, duty cycle of gate drive signals in such FET-based circuitry is constrained by efficiency interests for a given operating frequency and load. However, where efficiency is not as important as rise time or other behavior, or for certain tunings and operating conditions, duty cycle can be varied to shape the output. In this case, the typical process is to increase the duty cycle to force the inverter to generate higher peak drain voltages (thus hard switching) or to overcome the distortion from a low impedance load. The same timing diagrams are used to represent the gate drive signals and the corresponding drain voltages (DI and D2) for effecting a faster rise time at the output of the converter cell.

[0109] Accordingly and in view of the above, examples of the present disclosure are directed to effecting lower drain voltages in examples using such an inverter and controllingthe transition time at the output of the converter cell. In one such example, the converter cell is one of among a stack of DC-DC converter cells having respective outputs connected in series to provide an aggregated output voltage based on output voltage contributions from respective outputs of selected ones of the converter cells activated to generate an output voltage. Each converter cell, in such examples, includes inverter, isolation and rectifier circuitry. The inverter circuitry has gates to receive gate drive (control) signals from the controller, isolation circuitry (e.g., including transformers) to pass output signals from the inverter circuitry to the rectifier circuitry which connects to an output terminal where activated ones of the converter cells effect respective contributions to provide a combined (or aggregated) output signal. A controller, in generating and / or controlling the gate drive signals of the FETs within the inverter, is used to control generation of the gate drive (control) signal for each of the selected ones of the converter cells to be activated by at least one of increasing or decreasing, relative to steady state: a frequency or pulse width of the gate drive (control) signal.

[0110] In more specific examples of this type, the controller is to control generation of the waveform signal: by producing the waveform signal at an initial lower frequency, relative to steady state, to realize faster rise times at the output of the inverter circuitry; by producing the waveform signal at an initial higher frequency, relative to steady state, to realize slower response and reduced overshoot at the output of the inverter circuitry; and / or by setting consecutive gate pulse widths of the waveform signal with an initial gate pulse width that is substantially reduced relative to an ensuing gate pulse width.

[0111] In other specific examples of this type (which may be implemented alone or with the above aspects), the initial gate pulse width is reduced by about one half, with a certain margin of error, of an ensuing gate pulse width, and in more specific examples w here the inverter circuitry has drain nodes (e.g., with the drain nodes being unclamped or otherwise), the controller is configured to control generation of the waveform signal by setting consecutive gate pulse widths to mitigate or reduce an initial voltage spike on the drain.

[0112] Other aspects of the present disclosure involve use of such a controller to control signal overshoot in the output signal provided by a stacked configured of such DC-DC converters. In addition to controlling such signal overshoot, this ty pe of selective engagement is optionally used to control rise time, shaping and efficiency (as disclosed here, for example, in connection with discussion of FIGs. 13A-13C and FIGs. 14A-14B). FIG. 24 shows a control block (e.g., logic circuitry) sending control signals to selectively engage certain cells in and among a stacked arrangement of converter cells to control output overshoot in theoutput signal at the output terminal of the converter cells. In this context, a purpose of a specific example system, in which the converter cells are configured and selectively engaged while arranged in series as stacked cells and / or in parallel branches, may be to configure the power cells to operate within the load range available through frequency control. However, the cells can also be used to control shaping of the transient response (outside of frequency controls) and optimize efficiency. This may be realized, for example, by staggering the turn on of different series cells which can reduce the overshoot to that of a single series cell (however, this increases rise time). Turning on additional cells or branches during the rise can provide additional cunent into the output capacitance and reduce the rise time, and can also be adjusted to have limited effect on overshoot. Turning off branches after the initial transient can shift the cell operating point to a more efficient one and reduce losses either for the system or even per cell.

[0113] Depending on the design of the DC-DC cell, enable lines may asynchronously modulate the gate drive signals to the inverter or be processed to internally control the turnon transient. The lines can also be modulated to mix with a common operating frequency with the enable frequency, or at a much lower frequency to effect PWM control. In certain example implementations this approach generally may not optimize an efficient control input but advantageously it provides some intermediate levels without involving phase shift. As the open loop response of the cells depends on operating frequency, enable control can be most effective when combined with suitable frequency selection. Additionally, the controller can use the frequency or open loop response information to adjust the enable sequence and timing.

[0114] According to further examples of the present disclosure, control of signal overshoot may be realized by using a controller to generate enable and / or disable signals for a circuit including a stack of DC-DC converter cells having respective outputs connected in series to provide an aggregated output voltage based on the respective outputs. The controller, including logic circuitry, is configured to mitigate or eliminate output overshoot in the aggregated output voltage by selectively activating certain of the selected cells in the stacked-cell DC-DC converter. In more specific embodiments, the controller is to: sequentially control the cells by at least one of selective enablement and disablement; selectively controlling activation of the cells to effect respective delays in contributions by the activated cells to the aggregated output voltage; or selectively control at least one of activation and deactivation of the cells by adjusting or modulating one or more frequencies of certain of the activated cells. In other specific examples and as indicated previously, themitigation or elimination of output overshoot in the aggregated output voltage: is at least predominantly realized starting certain sets of the gate drive signals with one or more higher initial switching frequencies and thereafter reducing the frequencies (optionally, without thereafter adjusting one or more frequencies); and / or is realized by selectively adjusting one or more voltage set points characterizing a subset of the cells or by selectively adjusting one or more output voltages generated by a subset of the cells.

[0115] Yet further aspects of the present disclosure include use of different power rails to reduce isolation barrier requirement on high-speed converters by reducing voltage stresses. FIGs. 25A-25C show alternative block diagrams for respective approaches to provide power to a stacked arrangement of converter cells, with each cell including an isolation stage as depicted within each cell. FIG. 25A shows one approach having input signals to the converter cells referenced commonly to a single pair of power rails, which does not necessarily advantage such reduction of the isolation barrier requirement. FIG. 25B, however, illustrates an alternative approach in which input signals to certain of the converter cells are referenced to different sets of power rails. In certain regards, FIG. 25B illustrates multi-stepping the levels provided by the power rails to which the respective converter cells are referenced.

[0116] More specifically, the power-rail configuration of FIG. 25 A may be considered more of a default serial connection of cells for higher output voltages, wherein the inputs remain in parallel while the outputs are connected in series. This approach has limited scaling for higher output voltages as the isolation barrier needs to be reliable up to the full pulsed output voltage. To satisfy the isolation barrier needs, thickness is increased, thereby reducing the magnetizing inductance of the transformer and increasing the leakage inductance (doubly reducing the coupling coefficient). Compared to the approach of FIG. 25B. this reduces the efficiency, power densify, and response speed of the DC-DC cell, as it needs to be designed around excessive parasitic elements. Also, the thicker isolation increases the cost.

[0117] The approach of FIG. 25B, as an alternative design, works around these issues by producing multiple high-voltage isolated DC rails to power the cell inputs. Therefore, while the outputs are still connected in series, the inputs can be referenced to intermediate voltages within the stack, and the isolation barrier stress is limited to a fraction of the total output voltage. In the example illustrated in FIG. 25B, by having four isolated input rails, the isolation barrier requirement is reduced by roughly a factor of eight. As the dielectric thickness does not always scale linearly with voltage, the required barrier thickness can be reduced by more than the voltage stress. This allows the use of more efficient, compact, and cost effective cells for the generation of the required output voltage. While a downside of thisapproach in certain implementations is that an additional isolated conversion step (and related conversion circuitry or one or more intermediate power supplies to provide the operating power at the different voltage levels as indicated in FIG. 25B) is used for one or more inputs to the cells, this type of converter has different requirements from the cell that can make it easier and / or more advantageous. For example, while in operation and powering a DC rail, control bandwidth is much less important, and energy storage can be connected to its output to provide the peak input power required by the load; therefore, in some cases operation only needs to deliver the average power requirement. In addition to a smaller transformer to support average rather than peak power requirements, the isolation barrier capacitance can be further reduced without directly trading off the cell speed (as would be the case with the single step approach of FIG. 25 A). This reduces the effective output load on the power supply, thereby reducing the rise time and stored energy.

[0118] The respective stacks of DC-DC cells in FIG. 25 A may be compared to those in FIG. 25B by way of the following more-specific example embodiments. With reference to the stack of DC-DC cells in FIG. 25A and viewing from the bottom cell to the top cell, the isolation voltages for the cells in this more-specific example are as follows: (l / 8)*Vout; (2 / 8)*Vout [= (l / 4)*Vout]; (3 / 8)*Vout; (4 / 8)*Vout [=(l / 2)*Vout]; (5 / 8)*Vout; (6 / 8)*Vout [=(3 / 4)*Vout]; (7 / 8)*Vout; and (8 / 8)*Vout [= Vout], respectively. With reference to the stack of cells in FIG. 25B for this more-specific example, for the rightmost group of eight DC-DC cells, each cell has an isolation voltage of (l / 8)*Vout. Each of the intermediate 4 DC-DC cells on the left of FIG. 25B has an isolation voltage as follows: starting from the bottom cell to the top as follows: (l / 8)*Vout; (3 / 8)* Vout; (5 / 8)* Vout; and (7 / 8)* Vout. respectively. In particular examples relating to the general configuration of FIG. 25B, if the output voltage is a pulsed DC voltage, the group of 4 cells need to withstand only purely DC voltage, while the group of 8 cells (in both drawings) need to withstand pulsed DC voltage.

[0119] In view of the above, aspects of the present disclosure are directed to various examples to reduce isolation barrier requirements on such high speed converters. In one such example, a power converter includes: a stack of DC-DC converter cells (‘'converter cells’’) having respective outputs connected in series to provide an aggregated output voltage based on the respective outputs, and multiple DC rails, isolated from one another by one or more voltage-isolation barriers, to provide operating power at different voltage levels to respective ones of the converter cells. With access to respective ones of the multiple DC rails, the converter cells have respective input ports referenced to the different voltage levels.

[0120] FIG. 25C is one or many alternative example multi-step configurations to that show n in FIG. 25B. The configuration of FIG. 25C shows DC-pulsed DC isolation stress reduced to !4 Vout with a separate DC-DC stage isolating up to % Vout.

[0121] In more specific examples: the multiple DC rails are to provide the operating power at high voltages (e.g.. for about a 10 kV output, the range might be about 1 kV to about 9 kV), respectively corresponding to the different voltage levels. In such specific examples, each of the one or more voltage-isolation barriers is capable of isolating voltage, associated with immediately adjacent ones of the multiple DC rails, at least in part as functions of material thickness and of a voltage differential, between the immediately adjacent ones of the multiple DC rails; and / or the one or more voltage-isolation barriers are to limit stress to a fraction of the aggregated output voltage, on the one or more voltage - isolation barriers of immediately adjacent ones of the multiple DC rails. In certain of these examples, each of the cells may include a transformer-based isolation stage, with a large difference of voltages on respective primary and secondary sides of the voltage-isolation barrier(s).

[0122] Accordingly, the foregoing discloses examples of different types of processes and apparatuses (e.g., systems, devices, etc.) using a stacked arrangement of converter cells to produce a custom waveform shape at an output signal corresponding to an aggregation of individual output signals from the respective converter cells. Via selective engagement of respective ones of the converter cells, output signals from the converter cells are combined to generate an aggregate (e.g., high-voltage) output signal having a waveform shape that is customized based on the selective engagement. Certain more specific examples leverage inherent fast response times of the converter cells, by using nanosecond level pulsing for precise control over the cells in order to tailor high-voltage waveshaping of the aggregate output signal as derived from the DC-DC converter cells.

[0123] Further aspects of the present disclosure are directed to example configurations for primary and secondary windings of a planar-type transformer-based isolation stage as part of a PCB (printed circuit board), for example, for integration with the circuitry of the inverter and rectification stages of a converter cell. As example embodiments of such a planar-type transformer-based isolation stage, FIG. 26A and FIG. 26B are diagrams showing respective cross-sectional views for corresponding planar transformers, either of which is applicable to a transformer-based implementation of one or more of the converter cells show n in FIG. 1, with FIG. 26A indicating there are vias dispersed throughout the planar windings (e.g., improving thermal issues) on different layers, and FIG. 26B showing normal planarwindings. FIG. 27 is an exploded view of a PCB planar transformer which may be used with one or more of the converter cells depicted for the system of FIG.1 (e.g., showing a PCB planar transformer having an architecture common to all such converter cells).

[0124] In the example configurations of FIGs. 26A, 26B and 27. a transformer is implemented with primary and secondary windings implemented using planar traces in PCB layers. These example configurations are not limited to being used with one or more of the circuits depicted for the system of FIG. 1, but they have been found to be beneficial in terms of small form factor (e.g., minimal PCB real estate), voltage isolation and other parameters advantaging operation of the system of FIG. 1.

[0125] In connection with each of the example configurations of FIGs. 26A-26B, the transformer has a primary winding and one or more secondary windings (e.g., both spiral windings), integrated with a multilayer PCB, with the windings shaped to minimize eddy current losses. The PCB has the layers implemented for securing traces for the primary windings and for the secondary windings, and includes vias through certain of the traces to minimize winding losses and to facilitate thermal conductivity. Further, the PCB, the primary winding and the secondary' winding are cooperatively stacked vertically to facilitate magnetic coupling between the primary winding and the secondary winding.

[0126] In more specific examples that build on the above examples, such configurations may be implemented for realizing advantages that depend on the specific design, PCB space constraints, and power and thermal requirements and / or constraints. In certain of these examples, a number (X) of layers secure traces for the primary' winding, and another number (Y) of layers secure traces for the secondary winding, wherein X and Y are integers. In each of the examples of FIG. 26A and FIG. 26B. X is 4 and Y is 2. The number and placement of the vias, being different in FIG. 26A and FIG. 26B, are defined in part by the traces for the primary' winding and by the traces for the secondary' w inding for the purposes of minimizing winding losses and to facilitate thermal conductivity'. The primary' and secondary windings may have corresponding portions therein with different widths at sections nearest one another to minimize eddy current losses, or may have corresponding portions at sections nearest one another, with gradually decreasing trace width towards a center of the 'indings, to minimize eddy current. Also, at least one of the primary and secondary windings may have a section with a trace having a narrower width nearer the center of the winding and nearer an outer edge of the winding, and wider traces nearer the middle of the winding. The primary and secondary windings may7also be cooperatively arranged with minimal overlap to minimize parasitic capacitance between the primary and secondary' windings. In different examples, theprimary and secondary windings may be spiral windings or other forms and shapes of windings (e g., square, rectangular windings and / or a combination of shapes such as spiral, square and / or rectangular).

[0127] In yet further examples in this context, the PCB includes: at least one insulating material between each set of traces that are cooperatively arranged to provide magnetic coupling; or multiple insulating material types to provide, respectively, at least two levels of isolation protection including a high-voltage isolation protection nearest the transformer and another isolation protection, wherein the high-voltage isolation protection is nearest the transformer than other ones of the insulating material types and is to provide an increased degree of voltage isolation protection than isolation protection provided by the other ones of the insulating material types.

[0128] In connection with certain of the specific examples of the present disclosure, the above-characterized figures and discussion are provided to help illustrate certain aspects (and advantages in some instances) which may be used in the manufacture of such structures and devices. For example, the flow diagrams of FIGs. 3, 6, 7, 8 and 9 are presented to exemplify methods and / or uses according to specific approaches involving operations of the system of FIG. 1 (e g., with each flow diagram depicting one or more blocks which may be used alone or in combination with other aspects depicted blocks in the flow diagram). As may be useful in certain implementations, such structures and devices may include the exemplary structures and devices described in connection with one or more related aspects (e.g., by modifying and / or combining with the examples of the present disclosure) as described in the abovereferenced patent documents (including the above-referenced U.S. Provisional Application and U.S. Patents Nos. 11,228,252 and 11.978.611). Each of these patent documents is incorporated by reference, to the extent permitted, in its entirety' for the specific subject generally discussed therein, for the specific subject matter discussed hereinabove, and to the extent that further aspects and examples (such as experimental and / or more-detailed embodiments) may be useful to supplement and / or clarify aspects of the present disclosure including example types of signals, circuits, loads and the like.

[0129] The skilled artisan would also recognize various terminology as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrate aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms which refer to circuits such as block, module, stack, device, system, unit, stage, controller, and / or other circuit-type depictions. Also, in connection with such descriptions, where appropriate incertain circuit polarity orientations the term "source7’ may refer to source and / or dram interchangeably in the case of a transistor structure. Such semiconductors, semiconductive materials (including portions of semiconductor structure), circuit elements and / or related circuitry may be used together with other aspects of the present disclosure to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It is also noted that terms to exemplify orientation, such as upper / lower, left / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented different from the orientation shown in the figures. Thus, such terms should not be construed in a limiting manner.

[0130] Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, methods as exemplified in the Figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps. Such modifications do not depart from the true spirit and scope of various aspects of the disclosure, including aspects set forth in the claims.

Claims

What is Claimed:

1. An apparatus comprising: a plurality of resonant-isolated DC-DC converter cells (“converter cells'’) having respective output terminals cooperatively configured to combine, at an output terminal, output signals respectively produced by the converter cells; and logic circuitry to control the converter cells by selectively engaging including at least one of activating and deactivating (“selective engagement”), respective ones of the converter cells to generate an output signal having a waveform shape that is customized based on the selective engagement.

2. The apparatus of claim 1, wherein the logic circuitry is to effect the activation and deactivation via input signals, to be provided to the converter cells by controlled timings, on an order of nanoseconds, used in effecting the activation and deactivation of the converter cells, wherein altering the timings of the input signals causes one or more changes in the waveform shape.

3. The apparatus of claim 1, wherein the waveform shape is controlled according to timing control for which activation of one or more of the converter cells, one or more delays are effected to realize a desired form of the waveform shape.

4. The apparatus of claim 1, wherein the waveform shape is controlled, via the selective activation and deactivation, to realize design specifications including one or a combination of two or more of the following: (a) fast and / or fall times on the order of nanoseconds; (b) high peak voltages on the order of kV; and (c) the waveform shape being controllable by at least one of a voltage ramp up at constant controllable slopes or voltage ramp down at constant controllable slopes.

5. The apparatus of claim 1, wherein the activation and deactivation is controlled by the logic circuitry based on stored or configured information useful to realize the shape of the desired pulse waveform and its characteristics, wherein the stored or configured information is provided by at least one of storage settings; configured logic circuitry: and feedback signals obtained or determined during operation of the apparatus.

6. The apparatus of claim 1. wherein the waveform shape is defined by pulses, ensuing from a combined set of the output signals driven by respective ones of the converter cells.

7. The apparatus of claim 1, wherein the waveform shape is susceptible to being changed via waveshape-defining control parameters including one or more of the following: voltage, current, power, a derivative of said voltage, said current, and said power, and load impedance.

8. The apparatus of claim 1, wherein the waveform shape is set or adjusted via feedback that is based on control parameters including one or more of the following: voltage, current, power, a derivative of said voltage, said current, and said power, and load impedance.

9. The apparatus of claim 1, further including measurement and control circuitry to realize one or a combination of two or more of the following: (a) signals being relayed from various sensors configured to monitor parameters derived from one or more of the converter cells and including at least one of: output voltage, output current, individual current from a stacked arrangement of the converter cells; (b) processing of signals derived from the monitor parameters derived from one or more of the converter cells; and (c) providing commands to the converter cells to cause the converter cells to effect certain operations of corresponding ones of the converter cells.

10. The apparatus of claim 1, wherein the converter cells and the logic circuitry are cooperatively configured to generate pulses for plasma processing in semiconductor manufacturing.

11. The apparatus of claim 1, wherein the converter cells and the logic circuitry are cooperatively configured to generate a pulsed waveform having a tailored bias voltage, with a positive short pulse followed by a negative linear ramp, with maximum pulse voltages in a range from 10 kV up to a several kV, rise times in a range of 10 ns up to 100 ns, and negative linear ramps lasting up to several psec.

12. The apparatus of claim 1, wherein the converter cells and the logic circuitry are cooperatively configured to generate the output signal having the waveform shape as anadjustable pulsed waveform for which a plurality of parameters, from among voltage levels, pulse widths and ramp times, are adjustable.

13. The apparatus of claim 1, wherein at least some of the converter cells are arranged in respective stacks to facilitate a fast time in transitioning to a peak voltage level, wherein the respective stacks are connected in parallel to provide increased current levels to a load driven by the output signal having the waveform shape that is customized based on the selective engagement.

14. The apparatus of claim 1, wherein the converter cells are arranged in stacks, wherein each stack is set, arranged in parallel, and / or optimized, to supply up to a certain amount of current to realize a degree of efficiency.

15. The apparatus of claim 1, wherein the converter cells are arranged in stacks, wherein each of the stacks has, and is to consume current according to, a common architecture, thereby avoiding one of a combination of two or more of degradation of efficiency, overloading, and overheating.

16. The apparatus of claim 1, wherein the selection engagement causes the outputs of the converter cells to be combined: in series corresponding to a series stack of certain of the converter cells; in parallel corresponding to a parallel arrangement of certain of the converter cells; or in series with certain of the converter cells in a series stack and in parallel with certain other of the converter cells corresponding to a parallel arrangement.

17. The apparatus of claim 1, wherein the selection engagement causes the outputs of the converter cells to be combined in series with certain of the converter cells in a series stack and in parallel with certain other of the converter cells corresponding to a parallel arrangement, wherein the respective output signals are combined at the output terminal to generate the customized waveform shape via a combined output signal having an output current and output voltage that are in accordance with a design limit or specified load requirement.

18. The apparatus of claim 1, wherein each of the converter cells have a common circuit architecture and operational characteristics including a plurality from among: output voltageor power, switching frequency, transient response, timing of selective activation, and voltage isolation requirement.

19. The apparatus of claim 1, wherein at least one of the converter cells is designed to have one or more different operational characteristics than another of the converter cells, and one or more different operational characteristics including at least one from among the following: different output voltage, different output power, different range of switching frequencies, different transient responses, and different voltage isolation.

20. The apparatus of claim 1, wherein at least one of the converter cells has a different circuit architecture than another of the converter cells.

21. The apparatus of claim 1, further including an inverter circuit and a rectifier circuit, wherein each of the converter cells implements isolation by integrating primary and secondary windings into the inverter and rectifier circuits.

22. The apparatus of claim 1 , further including switching circuitry coupled to one or more of the converter cells, wherein the converters cells are cascaded with the switching circuitry to affect corresponding ones of the respective output signals by one or a combination of the following operations: fast pull-up, ull-down, and polarity swapping.

23. The apparatus of claim 1, wherein the respective output terminals of the converter cells are configured to provide a unipolar or bipolar output voltage across a load that is predominantly capacitive.

24. The apparatus of claim 1 , wherein the output signal has a waveform shape that is customized to produce a shaped ion energy distribution at a surface of a substrate.

25. The apparatus of claim 1, wherein the output signal has a waveform shape that is customized to produce a shaped ion energy' distribution that is mono-energetic at a surface of a substrate.

26. The apparatus of claim 1. wherein the output signal has a waveform shape that is customized to produce a shaped ion energy distribution at a surface of a semiconductor wafer.

27. The apparatus of claim 1, further including an RF plasma source, wherein the output signal has a waveform shape that is customized to produce a shaped ion energy distribution defined at least in part by the RF plasma source.

28. The apparatus of claim 1, wherein the output signal has a waveform shape that is customized to produce a shaped ion energy distribution in which ions are produced with generation of a plasma and accelerated by the converter cells configured as a single power supply.

29. The apparatus of claim 1, wherein the logic circuitry is to control the converter cells by producing and manipulating gate drive signals, in terms of at least one of phase, timing and voltage level, for causing the generation of the output signal.

30. The apparatus of claim 1, wherein the converter cells are configured to provide at least one of: sourcing power to a load, and sinking power to a load.

31. The apparatus of claim 1 , further including an inverter circuit, a transformer, and a rectifier circuit including each of the converter cells, wherein the transformer includes: a primary winding and one or more secondary windings shaped to mitigate or minimize eddy current losses, and a multilayer printed circuit board (PCB) including a plurality of layers securing traces for the primary winding and a plurality of layers securing traces for the secondary' winding, and including vias through certain of the traces to minimize winding losses and to facilitate thermal conductivity, wherein the PCB, the primary winding and the secondary winding are cooperatively stacked, vertically among certain of the plurality of layers of the PCB with one or more isolation layers to isolate the secondary winding from the primary winding, to facilitate magnetic coupling between the primary winding and the secondary winding.

32. The apparatus of claim 1, wherein the logic circuitry is used to facilitate a coarse closed-loop voltage feedback involving certain of the converter cells, and another closed-loopfeedback for fine control of particular output signal parameters provided by selected ones of the converter cells.

33. The apparatus of claim 1, wherein one or more of the converter cells includes inverter circuitry having control gates to receive respective gate-control signals (in response to the logic circuitry), isolation circuitry, including transformers, and rectifier circuitry, wherein the logic circuitry is to control generation of the waveform signal for the respective ones of the converter cells by at least one of increasing or decreasing, relative to steady state, a frequency of the gate-control signals or pulse width of the gate-control signals.

34. The apparatus of claim 1, wherein the selective engagement further includes controlling at least one of the converter cells via coarse adjustment followed by fine adjustment, in addition to said at least one of activating and deactivating.

35. The apparatus of claim 1 , wherein at least one of the converter cells includes or is electrically coupled to a Class E amplifier.

36. The apparatus of claim 1, wherein one or more of the converter cells includes inverter circuitry having control gates to receive respective gate-control signals, wherein the logic circuitry is to generate the waveform shape by producing the output signal via an initial lower frequency of the gate-control signals, relative to a frequency used in steady state operation, to facilitate a fast or optimized transition time in the output signal reaching a peak.

37. The apparatus of claim 1, wherein one or more of the converter cells includes inverter circuitry having control gates to receive respective gate-control signals, wherein the logic circuitry is to generate the waveform shape by producing the respective gate-control signals by setting consecutive gate pulse widths in the respective gate-control signals via generation of an initial gate pulse width that is substantially reduced relative to an ensuing gate pulse width.

38. The apparatus of claim 37, wherein the initial gate pulse width is about one half, within a fifteen percent margin of error, of the ensuing gate pulse width.

39. The apparatus of claim 1. wherein one or more of the converter cells includes inverter circuitry having drain nodes and control gates to receive respective gate-control signals, wherein the logic circuitry is to generate the waveform shape by setting consecutive gate pulse widths to mitigate or reduce an initial voltage spike on one or more of the drain nodes.

40. The apparatus of claim 1, wherein one or more of the converter cells includes inverter circuitry having control gates to receive respective gate-control signals, wherein the logic circuitry is to generate the waveform shape by producing the respective gate-control signals at an initial higher frequency for operating the converter cells, relative to a frequency used in steady state operation, to mitigate or eliminate generating signal overshoot in the output signal.

41. The apparatus of claim 40, wherein the mitigation or elimination of the overshoot is at least predominantly realized without adjusting, after reducing the one or more switching frequencies from the initial higher frequency, one or more switching frequencies used to operate the converter cells.

42. The apparatus of claim 1, wherein the logic circuitry is to sequentially control the converter cells by at least one of selective enablement and selective disablement.

43. The apparatus of claim 1, wherein the logic circuitry is to control the converter cells by selectively controlling activation of the converter cells to effect respective delays in contributions by the activated converter cells to the output signals as combined at the output terminal.

44. The apparatus of claim 1 , wherein the logic circuitry is to selectively control at least one of the converter cells by adjusting or modulating one or more switching frequencies of said at least one of the converter cells.

45. The apparatus of claim 1, wherein the logic circuitry is to mitigate or eliminate output overshoot in the output signals as combined at the output terminal by selectively adjusting one or more voltage set points respectively characterizing one or more of the converter cells.

46. The apparatus of claim 1, wherein the logic circuitry is to mitigate or eliminate output overshoot in the output signals as combined at the output terminal by selectively adjusting one or more output voltages respectively generated by one or more of the converter cells.

47. A method comprising: selectively engaging including at least one of activating and deactivating (“selective engagement’1), via logic circuitry, respective ones of a plurality of resonant-isolated DC-DC converter cells (“converter cells'’); and combining output signals from respective output terminals of the converter cells to generate an output signal having a waveform shape that is customized based on the selective engagement.

48. The method of claim 47, further comprising providing a set of time-coordinated gate drive signals to control input ports of the converter cells, including setting or adjusting timing and signal level of each of the time-coordinated gate drive signals for the selective engagement to adjust each respective output voltage generated by each of the converter cells, wherein the step of combining output signals is in response to the selective engagement.

49. The method of claim 47, wherein the selective engagement includes operating at least a subset of the converter cells via a frequency set of one or more sufficiently -high switching frequencies in a frequency range from 1 MHz to 100 MHz, over at least several cycles of the frequency set to manipulate the waveform shape in a fractional portion of the output signal at the output terminal of the converter cells.

50. The method of claim 47, wherein the portion corresponds to a segment of the waveform shape immediately after the waveform shape reaches an upper or lower peak, selectively adjusting one or more output voltages respectively generated by one or more of the converter cells selectively adjusting one or more output voltages respectively generated by one or more of the converter cells.

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