Voltage converter with asymmetrical gate voltages

Abstract

Multiphase switching converter, the device comprising the following: a connection for an input voltage (Vin); a connection for a common reference voltage (Vcom), wherein the multiphase switching converter is supplied by a voltage difference between input voltage (Vin) and reference voltage (Vcom); Gate drive circuits that have a high-side gate voltage drive and a low-side gate voltage drive for each phase of the multiphase switching converter; an intermediate voltage (Vim), wherein the intermediate voltage (Vim) has an arbitrary intermediate voltage level between the input voltage (Vin) and the common reference voltage (Vcom), which, when enabled, is configured to allow the high-side gate voltage drivers to switch between the input voltage (Vin) and the intermediate voltage (Vim), and to allow the low-side gate voltage drivers to switch between the intermediate voltage (Vim) and the reference voltage (Vcom), thereby enabling reduced switching voltages by reducing gate voltages of the gate drive circuits (132, 134; 142, 144). where the intermediate voltage (Vim) is dynamically controlled to optimize the efficiency of the switching converter at different loads or output voltages; wherein the gate drive circuits (132, 134; 142, 144) share the same arbitrary intermediate voltage (Vim); Multiphase switches (112, 114) coupled to the gate drive circuits (132, 134; 142, 144); wherein the multiphase switching converter is able to make the gate voltage of the gate drive circuits (132, 134; 142, 144) and consequently the multiphase switch (112, 114) with lower switching voltages in order to provide lower switching losses and a higher switching converter efficiency for low and medium load currents.

Description

Area

[0001] The disclosure relates generally to variable step-down converters, voltage regulators and methods, and in particular to how the efficiency and response of the step-down converters and voltage regulators can be controlled, and a method for doing so. background

[0002] Step-down converters are switching voltage regulators that operate using a step-down technique to provide a voltage output lower than the input voltage. This is achieved by changing the circuit topology by switching semiconductor devices on and off. Signal switching is used to transfer energy to inductors. A low-pass filter scheme is employed to eliminate high-frequency harmonics, maintaining a relatively constant output voltage and reducing output ripple.

[0003] Step-down converters typically use a feedback circuit to regulate the output voltage in the presence of load changes. They are more efficient at the cost of additional components and complexity. Step-down converters can be manufactured very compactly. Therefore, they are frequently used in mobile devices, printed circuit boards, and also in integrated circuit assemblies.

[0004] An example of a well-known step-down converter circuit 500 is shown in a circuit block diagram in Fig. 5 shown. The circuit 500 comprises a pair of complementary switches SW1 and SW2, a pair of control switches SW11 and SW12, a pair of control switches SW21 and SW22 and phase control buffers 570 and 572.

[0005] The phase control signals Vc1 and Vc2 are complementary. Vc1 is coupled to the input of buffer 570, while Vc2 is coupled to the input of buffer 572. The P-type switch SW11 and the N-type switch SW12 form a complementary switch. Their input 540 is coupled to the output of 570. Their output 538 is coupled to the gate of the P-type switch SW1. The P-type switch SW21 and the N-type switch SW22 form a complementary switch. Their input 550 is coupled to the output of 572. Their output 548 is coupled to the gate of the N-type switch SW2. Switches SW1 and SW2 form a complementary switch with output 516. 516 is usually connected to an output inductor, and the output of the inductor is usually filtered by a capacitor.

[0006] In the conventional downward converter, as used in Fig. Figure 6 shows that, in order to control SW1, the drain of the P-type switch SW11 is connected to the voltage V IN coupled, while the source of the N-type switch SW12 is connected to the common ground V COM is connected. To control SW2, the drain of the P-type switch SW21 is connected to the voltage V. IN coupled, while the source of the N-type switch SW22 is connected to the common ground V COM is coupled. The voltage dynamic range of switches SW1 and SW2 ranges from V IN to V COM .

[0007] The main sources of power loss in a step-down converter are resistance losses, switching losses, and magnetic losses in the inductor connected to the output V. LX is coupled, and resistance losses in the inductor connected to the output V LX is coupled.

[0008] The resistance losses in SW1 and SW2 are approximately proportional to I 2R, where R is the resistance of SW1 and SW2 and I is the load current.

[0009] Switching losses are caused by switching SW1 and SW2. The gate capacitances of SW1 and SW2 are charged or discharged during switching. Charging a capacitor inevitably results in the loss of half the energy stored in the capacitor once it is fully charged. These losses are approximately proportional to CV. 2 , where C is the gate capacitance and V is the gate voltage.

[0010] At low output currents, switching losses and magnetic losses tend to dominate. As the switching frequency increases, the switching losses increase proportionally. In step-down converters designed for very high output currents, gate losses tend to dominate magnetic losses and ultimately limit the maximum efficiency that step-down converters can achieve.

[0011] Multiphase step-down converters use multiple phases to provide the output current. Each phase has its own inductor, and the inductor outputs are then short-circuited together at the filter capacitor. These circuits offer several advantages over a larger single-phase step-down converter. They typically respond faster with higher bandwidth and lower output impedance.

[0012] Many multi-phase step-down converters operate in two different modes: a low-current mode and a high-current mode. In the low-current mode, the step-down converter is often operated with fewer than the maximum number of phases. In this case, the remaining phases are only switched on once the load current has increased.

[0013] In the present disclosure, the step-down converter efficiencies for low-load and medium-load currents are further improved without affecting the high-load efficiency.

[0014] WO 2014 / 003967 A1 describes only a device comprising a low-side switch coupled to an output node and a first drive circuit operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Furthermore, US 2014 / 0306674 A1 describes only a load-and-discharge signal circuit comprising high-side transistors connected in series, low-side transistors connected in series, high-side drive circuits, low-side drive circuits, and a drive signal generation circuit. Additionally, US 2012 / 0007572 A1 describes only a voltage converter comprising a power switch with corresponding load-and-discharge control terminals and an output terminal coupled to a series of connected inductors and capacitors.US 7,679,218 B1 describes only a load compensation circuit for a circuit regulator that includes a comparator circuit and an adjustable voltage source. Furthermore, US 2008 / 0061757 A1 describes only that an output current of a fixed-frequency DC-DC converter is detected and that a voltage is created representing the load current. Additionally, US 2008 / 0209236 A1 describes only a voltage regulator configured to select a gate drive signal from a variety of input voltages and to use the selected gate drive signal to turn on a power transistor to produce a regulated voltage for the load. Summary

[0015] A primary purpose of this disclosure is to provide a switching converter.

[0016] Another object of the present invention is to provide a highly efficient voltage conversion circuit device with both asymmetric and symmetric gate voltages.

[0017] Another further objective of the present invention is to improve the efficiency of the different switching phases or different step-down converters on the same chip.

[0018] A switching converter is implemented in accordance with the objectives of this disclosure. The device comprises an intermediate voltage, gate voltage drive circuits that share the intermediate voltage, and polyphase switches connected to the gate voltage drive circuits. The switching converter is capable of making the gate voltage asymmetrical to provide lower switching losses and higher step-down converter efficiency for low and medium load currents. The intermediate voltage is capable of generating any intermediate voltage between the supply voltage and the common reference ground, which provides the asymmetrical gate voltage for the gate drive circuits.Gate drive circuits sharing the same intermediate voltage are able to reduce gate capacitance losses in polyphase switches by reducing their output gate voltage through the intermediate voltage. These gate drive circuits, sharing the same intermediate voltage, further comprise: at least two pairs of polyphase input signals as inputs; at least two pairs of complementary switch circuits connected to polyphase input signals to generate at least one pair of polyphase gate voltages for subsequent polyphase switches; at least one intermediate voltage connecting the two complementary switch circuits to break the gate voltage symmetry and reduce the dynamic range of the gate voltages; and a pair of complementary asymmetric phase signals formed by the outputs of two complementary switch circuits as the gate drive voltage.The multiphase input signals are capable of generating the sleep-mode phase when in phase (0°), the synchronous-mode phase when out of phase (180°), or other phase relationships. The intermediate voltage is capable of generating asymmetrical gate voltages in the subsequent complementary switching circuits, and the resulting gate voltages of any two pairs of complementary switching circuits are asymmetrical. The intermediate voltage is capable of reducing the gate switching voltage range, thereby decreasing the capacitive loss of the subsequent multiphase switches to improve the buck converter efficiency when the load is low or medium. For convenience, the intermediate voltage is chosen to be half the supply voltage, although any other intermediate voltage can be selected and shared by multiple phases or multiple buck converters.Gate drive circuits sharing the same intermediate voltage can be switched to regular mode, restoring the gate voltage range between the regular supply voltage and the common reference voltage to maintain the high efficiency of the buck converter for high load currents. Multiphase switches connected to asymmetric gate drive circuits are capable of generating multiphase switching signals for voltage switch circuits or buck converters. The multiphase switch unit further comprises a pair of complementary multiphase switches connected to outputs of the asymmetric gate drive circuits and an output signal at the common junction between the pair of complementary multiphase switch transistors.The pair of complementary multiphase switches is able to generate phase signals to the following multiphase inductors, filter capacitors and load resistors, with the efficiency loss of the switch being proportional to CV. 2 where C is the gate capacitance of switches, and V is the dynamic range of switching voltages. The pair of complementary polyphase switches coupled with the drive circuits for asymmetrical gate voltages has asymmetrical gate voltages that reduce the dynamic range V of switching voltages, making the efficiency loss of the switches proportional to CV. 2This reduces the power consumption and thereby achieves a higher step-down converter efficiency for low or medium load currents. The switching converter can operate in one of several configurations: only the low-load phases at low loads, only the high-load phase at high loads, or only the low-load phases at low loads and all phases at high loads, with the latter being preferred for optimized step-down converter efficiency. The switching converter can be implemented for all types of switching converters, not just step-down converters, and for different step-down converters on the same chip.

[0019] Also in accordance with the objects of this invention, a highly efficient voltage conversion circuit device is provided with both asymmetric and symmetric gate voltages, wherein the device comprises: an intermediate voltage generation circuit unit, gate voltage drive circuits connected to the intermediate voltage generation circuit unit, and multiphase switches connected to the drive circuits for asymmetric gate voltages, wherein the voltage conversion circuit device is capable of achieving the high conversion efficiency for low and medium load currents using asymmetric gate voltages and for high load currents using regular gate voltages.The intermediate voltage generation circuit unit is able to use the supply voltage to provide a stable intermediate voltage for the following connected drive circuits for asymmetrical gate voltages when the load current is low or medium, wherein the intermediate voltage generation circuit unit further comprises: a voltage reference circuit unit that provides the reference voltage for intermediate voltage generation, an active current pull-down circuit unit, a current pull-up supplied by a high-resistance resistor, and a charge storage capacitor.The voltage reference circuit unit is able to generate a reference voltage from the supply voltage through several resistors to provide the reference voltage for intermediate voltage generation when the load current is low or medium, and a regular voltage circuit device for the gate voltage drive circuits when the load current is high.The active current pull-down circuit is capable of reducing the charge stored in the charge storage capacitor and thereby decreasing the intermediate voltage generated by the intermediate voltage generation circuit, thus preventing the intermediate voltage from rising. The active current pull-down circuit further comprises an amplifier connected to the reference voltage generation circuit and an NMOS device, the gate of which is connected to the amplifier's output and drain to its input. The drain of the NMOS device is also connected to the charge storage capacitor and the pull-up resistor. The current pull-up, provided by a high-value resistor, charges the charge storage capacitor to prevent the intermediate voltage from dropping too low, thereby stabilizing the output intermediate voltage.The charge storage capacitor is capable of storing charges from the PMOS devices of the following gate voltage drive circuits and supplying charges to the NMOS devices of the following gate voltage drive circuits, providing a stable intermediate voltage for the asymmetric gate voltage control when the load current is low or medium. The charge storage capacitor provides an intermediate voltage for the asymmetric gate voltage control (AGVC) when the load current is low or medium, which is stabilized by the active current pull-down circuit and the pull-up circuit in the intermediate voltage generation circuit.

[0020] Also in accordance with the objectives of this disclosure, a method for improving the efficiency of different switching phases or different step-down converters on the same chip is implemented. The method includes: deciding whether to use an automatic asymmetric gate voltage control (AGVC) operating mode according to a programmable instruction; deciding whether to use AGVC based on the output load condition when the automatic AGVC operating mode is specified according to the programmable instruction; generating the asymmetric gate voltage by means of an intermediate voltage for the asymmetric gate voltage phase control units when AGVC is to be used and low output loads are encountered; bypassing intermediate voltage generation by means of a regular reference voltage for two pairs of complementary switching control units when AGVC is to be used and high output loads are encountered.An algorithm that detects outputs at loads and converts them into command signals for inputs of the gate voltage controller unit to adjust AGVC controls for multiphase switches for low, medium, or high load currents, and feeds the command signals back to the gate voltage controller unit to adjust AGVC controls for multiphase switches for low, medium, or high load currents. The method, wherein the decision to use AGVC is based on the output load state, is then able to automatically enable or disable AGVC control based on the output load state when the operating mode with automatic AGVC is set according to the programmable command. It further includes receiving the activation signal from the intermediate voltage generation circuit to activate the AGVC control, using the intermediate voltage for asymmetric gate voltage control.When the load current is low or medium, the AGVC is switched on, using intermediate voltages to generate asymmetrical gate voltage control signals to reduce switching losses and increase its operating efficiency. When the load current is low or medium, the AGVC is switched off, using regular reference voltages to generate symmetrical gate voltage control signals to reduce switching losses and increase its operating efficiency. The method, wherein the generation of the asymmetrical gate voltage by an intermediate voltage for the phase control units for asymmetrical gate voltage is possible when the AGVC is to be used and low output loads are encountered, is capable of providing asymmetrical gate voltages for complementary gate voltage drive circuits.to reduce their switching losses and increase their operating efficiency. It further comprises: generating the intermediate voltage by the intermediate voltage generation circuit, generating the asymmetrical gate voltage by two pairs of gate voltage drive circuits, using the generated intermediate voltage from the intermediate voltage generation circuit, and reducing switching losses and increasing operating efficiency by using asymmetrical gate voltages that are lower than normal gate voltages. The method, wherein an algorithm detects the outputs at loads and converts them into command signals for inputs of the gate voltage controller unit to adapt AGVC controls for multiphase switches for low, medium, or high load currents, is capable ofto dynamically automate AGVC controls based on the load condition. It further includes: detecting the output current or voltage from voltage switches or step-down converters and algorithms used to generate one or more command signals based on sampled currents or voltages to encode load condition information into the one or more command signals. The method, wherein the feedback of the command signals to the gate voltage controller unit to adapt AGVC controls for multiphase switches for low, medium, or high load currents, is able to use the load condition to automatically control the AGVC device. It further includes: feeding the generated command signal as the feedback control signal through the feedback loop into the input of the gate voltage controller unit to adapt AGVC controls for multiphase switches for low,to adapt to medium or high load currents.

[0021] Further advantages will be identified by experts in the field. Brief description of the drawings

[0022] The present disclosure and the corresponding advantages and features provided herein are best understood and appreciated by reviewing the following detailed description, which is provided in conjunction with the following drawings in which the same reference numerals correspond to the same elements, wherein: Fig. 1 is a schematic circuit diagram showing an example of an asymmetric gate voltage drive circuit for the step-down converter according to an embodiment of the disclosure; Fig. 2 is an efficiency diagram showing an example of an asymmetric gate voltage drive circuit for a low-efficiency step-down converter for low and medium output currents according to an embodiment of the disclosure; Fig. 3 is a schematic circuit diagram showing an example of an asymmetric gate voltage drive circuit for a step-down converter with the intermediate voltage generation circuit according to an embodiment of the disclosure; Fig. 4 is an efficiency diagram showing an example of an asymmetric gate voltage drive circuit for the step-down converter with the intermediate voltage generation circuit unit according to an embodiment of the disclosure; Fig. 5 is a circuit block diagram showing a state-of-the-art step-down converter; Fig. Figure 6 is a flowchart showing a method for using an asymmetric gate voltage drive circuit with the intermediate voltage generation circuit unit to improve the efficiency of the step-down converter for the low and medium output currents. Description

[0023] Fig. Figure 1 is a schematic circuit diagram illustrating an example of a drive circuit for asymmetrical gate voltages 100 for the step-down converter according to an embodiment of the invention. The device 100 comprises a complementary phase switch 110, the gate drive circuit 130, input signals, and output signals. The complementary phase switch 110 comprises an upper switch SW1, a lower switch SW2, an input 122, and a common circuit reference V. COMAt 124, the output 116 is from the upper switch SW1 and the lower switch SW2. The gate drive circuit 130 comprises an upper drive buffer 170, a lower drive buffer 172, an upper drive switch SW11, a lower drive switch SW12, an upper drive switch SW21, a lower drive switch SW22, and an input signal V. C1 and an input signal V C2 , an intermediate control voltage V IM , one input 136, one common circuit reference V COM At 146, an output 138 from the upper switch SW11 and the lower switch SW12, and an output 148 from the upper switch SW21 and the lower switch SW22. Input signals include a bias input V IN , a common circuit reference V COM , an input signal V C1 and an input signal V C2 and an intermediate control voltage V IM The output of the downward converter is V LX .

[0024] In the complementary phase switch 110, switches SW1 and SW2 form a complementary pair and are preferably coupled at node 116. The drain of SW1 is preferably biased with V IN coupled by 122. The source of SW2 is preferably connected to the common circuit reference V. COM coupled by 124. The switches can be implemented in any available technology, such as MOS, bipolar, or mixed technology. The output V LX is preferably coupled to node 116 with both the upper switch SW1 and the lower switch SW2.

[0025] In the gate drive circuit 130, the input signal V C1 preferably coupled to the input of buffer 170 and the input signal V C2The output of buffer 170 is preferably coupled to the input of buffer 172. The upper switch SW11 and the lower switch SW12 form a complementary switch by short-circuiting the gate at 140 and generating the output at 138. The upper switch SW21 and the lower switch SW22 form a complementary switch by short-circuiting the gate at 150 and generating the output at 148. The output of buffer 170 is preferably coupled to the gate input 140 of the complementary switch formed jointly by SW11 and SW12. The output of buffer 172 is preferably coupled to the gate input 150 of the complementary switch formed jointly by SW21 and SW22. The output of the complementary switch formed jointly by SW11 and SW12 is preferably coupled to the gate of SW1. The output of the complementary switch formed jointly by SW21 and SW22 is preferably coupled to the gate of SW2.The source of SW12 and the drain of SW21 are preferably coupled at 164. The intermediate voltage is preferably coupled via 164 to the complementary switch formed jointly by SW11 and SW12, and to the complementary switch formed jointly by SW21 and SW22. The drain of SW11 is preferably connected via 136 to the bias voltage V. IN The source of SW22 is preferably coupled by 146 with the common reference V. COM coupled.

[0026] Although the embodiment uses the modified gate drive circuit with only one phase output V LX To illustrate, it should be understood that in the present disclosure, multiple coupled coils with multiple phases of switches can be used.

[0027] In the preferred embodiment, the gate drivers are connected to an intermediate voltage V. IM operated. The P-type driver SW1 switches between the supply voltage VIN and the intermediate voltage V IM The N-type driver SW2 switches between the intermediate voltage V IM and the common reference voltage V COM um.

[0028] As one of many possibilities, V IM to half the supply voltage V IN be set. Half of the supply voltage V IN This is a suitable voltage. It can be easily generated by a regulator, a switched capacitor charge pump, or another switching converter. However, any other intermediate voltage can be used.

[0029] If one phase is operated with a lower switching voltage, the resistance of switches SW1 and SW2 increases. The associated power loss is I 2R is determined, where I is the current through the switch and R is the switch resistance. Thus, the power loss is proportional to the increase in resistance. As long as the device remains within its linear range, the increase in resistance will not be proportional to the decrease in voltage. Therefore, the increase in resistance losses will be small.

[0030] However, switching losses become proportional to CV. 2 reduced. Therefore, the reduction in switching losses is proportional to the square of the reduction in switching voltage. The overall effect is that the efficiency of the step-down converter is increased at low and medium output currents.

[0031] With reference to Fig. Figure 2 shows an exemplary diagram of the step-down converter efficiency improvement when applying the intermediate voltage in this disclosure. The efficiencies in synchronous and sleep modes are plotted against the load current when the intermediate voltage V is applied. IM is applied or not. In "sleep mode", this changes when the intermediate voltage V IM If no voltage is applied, the switch's operating dynamic range in this example is from 0 to 4 volts. Its efficiency 214 changes with the load current. However, if the proposed intermediate voltage V IM When applied, the switch's operating dynamic range changes within 2 volts in this example. Its efficiency 212 changes with the load current and is much better than that of 214. In the "synchronous mode," it then changes when the intermediate voltage V IMIf no voltage is applied, the switch's operating dynamic range in this example is from 0 to 4 volts. Its efficiency of 218 changes with the load current. However, if the proposed intermediate voltage V IM When applied, the switch's operating dynamic range changes within 2 volts in this example. Its efficiency 216 changes with the load current and is much better than that of 218. This justifies the use of the proposed intermediate voltage V for the efficiency. IM This disclosure has been significantly improved.

[0032] In the proposed embodiment, the efficiency is higher at high currents due to the higher gate voltage. The modified low-gate voltage configuration has a higher efficiency at medium and low load currents. Therefore, there is a significant advantage to operating low-load phases with the low-gate voltage circuit and high-load phases with the original circuit.

[0033] In the proposed embodiment, the step-down converter can be operated in one of several configurations to meet this requirement. One requirement is: only the low-load phases at low loads and only the high-load phases at high loads. Another requirement is: only the low-load phases at low loads and all phases at high loads. And other cases exist. It is evident that the phases used at low loads benefit from the proposed asymmetric gate voltage control. However, to achieve higher efficiency for phases used at high loads, the original circuit is switched on.

[0034] In the proposed embodiment, the step-down circuit can be designed to switch between two operating modes: low gate switching voltage and high gate switching voltage.

[0035] In the proposed embodiment, the intermediate voltage VIM They can be dynamically controlled to optimize efficiency at different loads or output voltages. For example, this can be achieved by lowering the intermediate voltage at high output voltages, where the P-type switch resistance of SW1 is more important than the N-type resistance of SW2.

[0036] In the preferred embodiment, the proposed disclosure includes all forms of switching converters, not just step-down converters.

[0037] In the preferred embodiment, the proposed intermediate voltage can be used jointly by several phases or several step-down converters.

[0038] In the preferred embodiment, the proposed disclosure also optimizes different step-down converters on the same chip. For example, some step-down converters are operated in standard mode to provide high currents, while other step-down converters would use the intermediate voltages to optimize efficiency at low loads.

[0039] With reference to Fig. Figure 3 shows an exemplary diagram of a drive circuit for asymmetrical gate voltages 300 for the step-down converter with the intermediate voltage generation circuit according to an embodiment of the disclosure. The device 300 comprises a complementary phase switch 310, the gate drive circuit 330, input signals, and an output signal V. LX and an exemplary drive circuit for asymmetrical gate voltages 381. The complementary phase switch 310 comprises an upper switch SW1, a lower switch SW2, an input VIN , a common circuit reference V COM , the output 316 from the upper switch SW1 and the lower switch SW2. The gate drive circuit 330 comprises an upper drive buffer 370, a lower drive buffer 372, an upper drive switch SW11, a lower drive switch SW12, an upper drive switch SW21, a lower drive switch SW22, and an input signal V C1 and an input signal V C2 , an intermediate control voltage V IM , an entrance V IN , a common circuit reference V COM , an output 338 from the upper switch SW11 and the lower switch SW12, an output 348 from the upper switch SW21 and the lower switch SW22. Input signals include a bias input V IN , a common circuit reference V COM , an input signal V C1 , an input signal V C2 and an intermediate control voltage V IMThe output of the downward converter is V LX The drive circuit for asymmetric gate voltages 381 includes a bias resistor R1, a reference resistor R2, a reference resistor R3, a capacitor C, an amplifier 378 and an N-type MOS transistor SW3.

[0040] In the complementary phase switch 310, switches SW1 and SW2 form a complementary pair and are preferably coupled at node 316. The drain of SW1 is preferably biased with the voltage V IN coupled. The source of SW2 is preferably coupled to the common circuit reference V. COM coupled. The switches can be implemented in any available technology, such as MOS, bipolar, or mixed technology. The output V LX is preferably coupled to both the upper switch SW1 and the lower switch SW2 at node 316.

[0041] In the gate drive circuit 330, the input signal is VC1 preferably coupled to the input of buffer 370 and the input signal V C2The output of buffer 370 is preferably coupled to the input of buffer 372. The upper switch SW11 and the lower switch SW12 form a complementary switch by short-circuiting the gate at 340 and generating the output at 338. The upper switch SW21 and the lower switch SW22 form a complementary switch by short-circuiting the gate at 350 and generating the output at 348. The output of buffer 370 is preferably coupled to the gate input 340 of the complementary switch formed jointly by SW11 and SW12. The output of buffer 372 is preferably coupled to the gate input 350 of the complementary switch formed jointly by SW21 and SW22. The output of the complementary switch formed jointly by SW11 and SW12 is preferably coupled to the gate of SW1. The output of the complementary switch formed jointly by SW21 and SW22 is preferably coupled to the gate of SW2.The source of SW12 and the drain of SW21 are preferably coupled at 364. The intermediate voltage is preferably coupled via 364 to the complementary switch formed jointly by SW11 and SW12, and to the complementary switch formed jointly by SW21 and SW22. The drain of SW11 is preferably connected via 336 to the bias voltage V. IN The source of SW22 is preferably coupled by 346 with the common reference V. COM coupled.

[0042] In the control circuit for asymmetrical gate voltages 381, the resistor R2 is preferably connected to V IN coupled, while resistor R3 is preferably coupled with V COMR2 and R3 are both preferably coupled to the negative input of amplifier 378. The bias resistor 366 is preferably coupled to the positive input of amplifier 378, the drain of PMOS device 376, and capacitor C. Both PMOS device 376 and capacitor C are preferably connected to the common reference V. COM coupled. The intermediate voltage V IM is generated at 390 and is preferably coupled to 364 of the gate control circuit 330.

[0043] In the preferred embodiment, the ground of the PMOS device SW21 and the supply of the NMOS device SW12 are both preferably at 390 with the intermediate voltage V IM coupled. They pump both charges into the intermediate supply. The capacitor can maintain the intermediate voltage V. IMWhen the PMOS device SW21 turns on, its gate goes low and SW21 injects charge into capacitor C. When the NMOS device SW12 turns on, its gate goes high and SW12 removes charge from capacitor C. In most common step-down converters, the PMOS device is significantly larger than the NMOS device. This means it injects more charge than the NMOS device removes. Over time, the total current into capacitor C becomes positive, and the intermediate voltage V IMThe current will tend to increase. Amplifier 378 controls a small active pull-down circuit consisting of an active NMOS device SW3. This circuit discharges the current and stabilizes the intermediate voltage VIM. A small pull-up current, supplied through a high-resistance resistor R1, stabilizes the voltage and prevents it from dropping too low. Due to the high resistance, the pull-up current is very small.

[0044] In the proposed embodiment, the asymmetric gate voltage driver circuit 381 has the advantage that it draws only the pull-up current directly from the supply. The remaining current used to generate the intermediate voltage is wasted charge from the PMOS gate driver itself. It is therefore very efficient.

[0045] With reference to Fig. Figure 4 shows an exemplary diagram illustrating the efficiency of the step-down converter with the intermediate voltage generation circuit according to one embodiment of the disclosure. Efficiency curve 412 is obtained when the drive circuit for asymmetric gate voltages is used in the step-down converter, while efficiency curve 414 is obtained when the drive circuit for asymmetric gate voltages is not used in the step-down converter. Obviously, due to the asymmetric gate voltage control in the present disclosure, the step-down converter efficiency 412 is much better than the efficiency 414.

[0046] In the proposed embodiment, the improved peak efficiency due to the asymmetric gate voltage control in this disclosure will actually be higher than in the original circuit, because there is no series impedance in the simulation data of Fig. 4 is included. These elements do not scale with the gate voltage. Thus, the improved circuit performs better than simply scaling the passband.

[0047] With reference to Fig.Figure 6 shows the flowchart of the asymmetric gate voltage control method for achieving higher efficiency for low and medium load currents from the proposed embodiment. It begins by setting an operating mode 610, receiving external commands in the form of signals. The command specifies whether automatic asymmetric gate voltage control (AGVC) should be used. As indicated by element 612, if automatic asymmetric gate voltage control (AGVC) is not used, the regular operating mode is preferred. The AGVC circuit is bypassed by 614 to set a switch control signal via 616. The step-down converter then operates in the regular state, and its output is preferably coupled to a step-down converter filter circuit 618 to produce the final output signal V. OUT to produce.

[0048] As specified by element 612, when automatic asymmetric gate voltage control (AGVC) is used, the procedure checks whether the output load current is low or medium, as specified by 620. If the load current is high, the regular operating mode is preferred. The AGVC circuit is bypassed by 622 to set the switch control signal by 626. However, if the load current is low or medium, the AGVC operating mode is preferred. It is implemented by an AGVC device 624. The system then proceeds to set the switch control signal by 626. The output of the step-down converter is preferably coupled to a step-down converter filter circuit 628 to determine the final output signal V. OUT to produce.

[0049] The above detailed description of the disclosure and the examples described therein are presented for illustrative and descriptive purposes. Although the principles of the disclosure above have been described in connection with a specific device, it is understood that this description is only exemplary and does not serve as a limitation of the scope of the disclosure.

Claims

[1] Multiphase switching converter, the apparatus comprising: a connection for an input voltage (Vin); a connection for a common reference voltage (Vcom), wherein the multiphase switching converter is supplied by a voltage difference between input voltage (Vin) and reference voltage (Vcom); Gate drive circuits that have a high-side gate voltage drive and a low-side gate voltage drive for each phase of the multiphase switching converter; an intermediate voltage (Vim), wherein the intermediate voltage (Vim) has an arbitrary intermediate voltage level between the input voltage (Vin) and the common reference voltage (Vcom), which, when enabled, is configured to allow the high-side gate voltage drivers to switch between the input voltage (Vin) and the intermediate voltage (Vim), and to allow the low-side gate voltage drivers to switch between the intermediate voltage (Vim) and the reference voltage (Vcom), thereby enabling reduced switching voltages by reducing gate voltages of the gate drive circuits (132, 134; 142, 144). where the intermediate voltage (Vim) is dynamically controlled to optimize the efficiency of the switching converter at different loads or output voltages; wherein the gate drive circuits (132, 134; 142, 144) share the same arbitrary intermediate voltage (Vim); Multiphase switches (112, 114) coupled to the gate drive circuits (132, 134; 142, 144); wherein the multiphase switching converter is able to make the gate voltage of the gate drive circuits (132, 134; 142, 144) and consequently the multiphase switch (112, 114) with lower switching voltages in order to provide lower switching losses and a higher switching converter efficiency for low and medium load currents. [2] Device according to claim 1, wherein the gate drive circuits (132, 134; 142, 144) which share the same intermediate voltage (Vim) are able to reduce gate capacitance losses in polyphase switches (112, 114) by reducing their output gate voltage by the intermediate voltage (Vim), wherein the gate drive circuits (132, 134; 142, 144) which share the same intermediate voltage (Vim) further comprise: at least two pairs of multiphase input signals (Vc1, Vc2) as inputs; at least two pairs of complementary switch circuits (132, 134; 142, 144) connected to polyphase input signals (Vc1, Vc2) to generate at least one pair of polyphase gate voltages for the following polyphase switches (112, 114); at least one intermediate voltage (Vim) connecting the two complementary switching circuits (132, 134; 142, 144) configured to introduce reduced and full gate voltages and to reduce the dynamic range of the gate voltages; and a pair of complementary phase signals with voltage that is reduced, formed by outputs of two complementary switching circuits as gate drive voltage. [3] Device according to claim 2, wherein the multiphase input signals (Vc1, Vc2) are able to generate the sleep mode phase when they are in phase (0°), to generate the synchronous mode phase when they are out of phase (180°), or to generate other phase relationships. [4] Device according to claim 2, wherein the intermediate voltage (Vim) is able to generate reduced gate voltages in the following complementary switch circuits, and the resulting gate voltages of each pair of complementary switch circuits become asymmetric. [5] Device according to claim 2, wherein the intermediate voltage (Vim) is able to reduce the switching voltage range of the gate and thereby reduce the capacitive loss of the subsequent multiphase switches (112, 114) in order to improve the step-down converter efficiency when the load is low or medium. [6] Device according to claim 2, wherein the intermediate voltage (Vim) is selected for convenience to be half the input voltage (Vin), although other intermediate voltages may be selected and may be used jointly by several phases or several step-down converters. [7] Device according to claim 1, wherein gate drive circuits (132, 134; 142, 144) sharing the same intermediate voltage (Vim) can be switched to regular mode, restoring the gate voltage range between the regular supply voltage and the common reference voltage to maintain the high efficiency of the step-down converter for high load currents. [8] Device according to claim 1, wherein multiphase switches (112, 114) connected to reduced gate voltage drive circuits (132, 134; 142, 144) are able to generate multiphase switching signals for voltage switch circuits or step-down converters, wherein the multiphase switch unit further comprises: a pair of complementary polyphase switches (112, 114) connected to outputs of the reduced gate voltage drive circuits (132, 134; 142, 144); and an output signal at the common junction point (116) between the pair of complementary multiphase switching transistors (112, 114). [9] Device according to claim 8, wherein the pair of complementary multiphase switches (112, 114) is able to generate phase signals for the following plurality of phase inductors, filter capacitors and load resistors, wherein the efficiency loss of the switch is proportional to CV 2is where C is the gate capacitance of switches, while V is the dynamic range of switching voltages. [10] Device according to claim 8, wherein the pair of complementary polyphase switches (112, 114) coupled to the reduced gate voltage drive circuits (132, 134; 142, 144) have reduced gate voltages which reduce the dynamic range V of switching voltages, the efficiency loss of the switches proportional to CV 2 reduce and thereby achieve a higher step-down converter efficiency for low or medium load currents. [11] Device according to claim 1, wherein the switching converter can be operated in one of several configurations: only the low-load phases at low loads and only the high-load phase at high loads, or only the low-load phases at low loads and all phases at high loads, the latter being preferred for an optimized step-down converter efficiency. [12] Device according to claim 1, wherein the switching converter can be implemented for all types of switching converters, not just for step-down converters and for different step-down converters on the same chip. [13] Highly efficient voltage conversion circuit device with both reduced and full gate voltages, wherein the full gate voltages oscillate between the input voltage (Vin) and the common reference voltage (Vcom), the device comprising: a connection for an input voltage (Vin); a connection for common reference voltage (Vcom), wherein the switching converter is supplied by a voltage difference between input voltage (Vin) and reference voltage (Vcom); an intermediate voltage generation circuit unit (381), wherein the intermediate voltage generation circuit unit (381) is configured to generate an intermediate voltage (Vim) having an arbitrary intermediate voltage level between the input voltage (Vin) and the common reference voltage (Vcom), providing symmetrical or asymmetrical supply voltages and symmetrical or asymmetrical gate voltages for gate drive circuits, wherein the intermediate voltage is dynamically controlled to optimize the efficiency of the switching converter at different loads or output voltages; wherein the gate drive circuits (332, 334; 342, 344) are connected to the intermediate voltage generation circuit unit (381); Multiphase switches (312, 314) connected to the drive circuits (332, 334; 342, 344) for asymmetric gate voltages; wherein the voltage conversion circuit device is able to achieve the high conversion efficiency for low and medium load currents using reduced gate voltages and for high load currents using the full gate voltages. [14] Device according to claim 13, wherein the intermediate voltage generation circuit unit (381) is able to use the supply voltage (Vin) to provide a stable intermediate voltage (Vim) for the following connected reduced gate voltage drive circuits (332, 334; 342, 344) when the load current is low or medium, wherein the intermediate voltage generation circuit unit (381) further comprises: a voltage reference circuit unit that provides the reference voltage (Vcom) for intermediate voltage generation; an active current pull-down circuit unit (378, 374); a current pull-up supplied by a high-resistance resistor (366); and a charge storage capacitor (376). [15] Device according to claim 14, wherein the voltage reference circuit unit is able to generate a reference voltage (Vcom) from the input voltage (Vin) through several resistors (388, 398) to provide the reference voltage (Vcom) for intermediate voltage generation when the load current is low or medium, and a regular voltage circuit device for the gate voltage drive circuits (332, 334, 342, 344) when the load current is high. [16] Device according to claim 14, wherein the active current pull-down circuit unit (378, 374) is able to reduce the charge storage in the charge storage capacitor (376) and thereby reduce the intermediate voltage generated by the intermediate voltage generation circuit unit (381) in order to prevent the intermediate voltage from increasing, wherein the active current pull-down circuit unit further comprises: an amplifier (378) connected to a reference voltage generation circuit; and an NMOS device (374) in which the gate is connected to the output of the amplifier and the drain is connected to the input of the amplifier; wherein the drain of the NMOS device (374) is also connected to the charge storage capacitor (376) and the pull-up resistor (366). [17] Device according to claim 14, wherein the current pull-up supplied by a high-resistance resistor (366) is able to charge the charge storage capacitor (376) to prevent the intermediate voltage (Vim) from dropping too much, thus stabilizing the output intermediate voltage. [18] Device according to claim 14, wherein the charge storage capacitor (376) is able to store charges from the PMOS devices of the following gate drive circuits (332, 334) and to supply charges to the NMOS devices (342, 344) of the following gate drive circuits and to provide a stable intermediate voltage (Vim) for the reduced gate voltage control when the load current is low or medium. [19] Device according to claim 14, wherein the charge storage capacitor (376) provides an intermediate voltage (Vim) for the reduced gate voltage control (AGVC) when the load current is low or medium, which is stabilized by the active current pull-down circuit unit and the pull-up circuit unit in the intermediate voltage generation circuit unit (381). [20] Method for improving the efficiency of different switching phases or different step-down converters on the same chip, the method comprising: Decide whether to use an automatic reduced gate voltage control (AGVC) operating mode according to a programmable instruction (610); Decide whether to use AGVC based on the initial load condition when the operating mode with automatic AGVC is set according to the programmable instruction (612); Generating the reduced gate voltage by means of an intermediate voltage (Vim) for reduced gate voltage phase control units, wherein high-side gate drives switch between an input voltage (Vin) and the intermediate voltage (Vim) and the low-side gate drives switch between the intermediate voltage (Vim) and a common reference voltage (Vcom), thereby enabling reduced switching voltages when AGVC is to be used and low output loads are encountered (624); Bypassing intermediate voltage generation by means of a regular reference voltage for two pairs of complementary switch control units when AGVC is to be used and high output loads are encountered (622); wherein an algorithm detects outputs at loads and converts them into command signals for inputs of the gate voltage controller unit to adapt AGVC controls for multiphase switches for low, medium or high load currents; and Feedback of the command signals to the gate voltage controller unit to adapt AGVC controls for multiphase switches for low, medium or high load currents. [21] Method according to claim 20, wherein the decision as to whether to use AGVC based on the initial load state, when the operating mode with automatic AGVC is set according to the programmable command, is able to automatically activate or deactivate the AGVC control based on the initial load state, wherein the method further comprises: Receiving the activation signal from the intermediate voltage generation circuit to activate the AGVC control, using the intermediate voltage (Vim) for reduced gate voltage control when the load current is low or medium; Turning on the AGVC, using intermediate voltages (Vim) to generate reduced gate voltage control signals to reduce switch loss and increase their operating efficiency when the workload current is low or medium; and switching off the AGVC, using regular reference voltages to generate full gate voltage control signals to reduce switch loss and increase their operating efficiency when the workload current is high. [22] The method of claim 20, wherein generating a reduced gate voltage by means of an intermediate voltage (Vim) for reduced gate voltage phase control units when AGVC is to be used and low output loads are encountered is able to provide reduced gate voltages for complementary gate voltage drive circuits in order to reduce their switching losses and increase their operating efficiency, wherein the method further comprises: Generating the intermediate voltage (Vim) by the intermediate voltage generation circuit; Generating the reduced gate voltage by two pairs of gate voltage drive circuits, using the generated intermediate voltage from the intermediate voltage generation circuit, and Reducing switching losses and increasing operational efficiency through reduced gate voltages that are lower than normal gate voltages. [23] Method according to claim 20, wherein an algorithm that detects outputs at loads and converts them into command signals for inputs of the gate voltage controller unit in order to adapt AGVC controls for multiphase switches for low, medium or high load currents is able to dynamically automate AGVC controls based on the load state, wherein the method further comprises: Detecting the output current or voltage from voltage switches or step-down converters; and algorithms used to generate one or more command signals based on sampled currents or voltages to encode load condition information in the one or more command signals. [24] Method according to claim 20, wherein the feedback of the command signals to the gate voltage controller unit, in order to adapt AGVC controls for multiphase switches for low, medium or high load currents, is able to use the load condition to automatically control the AGVC device, wherein the method further comprises: Feeding the generated command signal as the feedback control signal through the feedback loop into the input of the gate voltage controller unit to adapt AGVC controls for multiphase switches for low, medium or high load currents.

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