Display module and drive method therefor, and electronic device

Abstract

Embodiments of this application provide a display module and a driving method thereof, and an electronic device, and relate to the field of electronic technologies, to design a display module with low power consumption. During design of the display module, a driver circuit in the display module is set as including a first driver sub-circuit and a second driver sub-circuit that may implement independent driving. During partial display, gate start signals corresponding to the first driver sub-circuit and the second driver sub-circuit are independently input. For example, an active gate start signal is input to the first driver sub-circuit, and an inactive gate start signal is input to the second driver sub-circuit, to implement independent driving of the first driver sub-circuit and the second driver sub-circuit. On this basis, a clock signal corresponding to the first driver sub-circuit toggles at a normal frequency, and a clock signal corresponding to the second driver sub-circuit does not toggle or toggles at a reduced frequency, to implement different clock signal inputs, so as to reduce power consumption of the display module.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410726930.9, filed with the China National Intellectual Property Administration on June 5, 2024 and entitled "DISPLAY MODULE AND DRIVING METHOD THEREOF, AND ELECTRONIC DEVICE", which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] This application relates to the field of electronic technologies, and in particular, to a display module and a driving method thereof, and an electronic device.BACKGROUND

[0003] With diversification of forms and use scenarios of an electronic device, a size of a display module is gradually increased. However, the larger display module results in relative increased display power consumption, affecting an overall battery life of the electronic device. Therefore, a requirement of the display module for low power consumption becomes a new focus of design improvement in the display field.

[0004] In this case, how to design a display module with low power consumption is an urgent problem to be resolved by a person skilled in the art.SUMMARY

[0005] Embodiments of this application provide a display module and a driving method thereof, and an electronic device, to design a display module with low power consumption.

[0006] To achieve the foregoing objective, this application adopts the following technical solutions.

[0007] A first aspect of embodiments of this application provides a display module, where the display module includes a first driver circuit and a first display driver integrated circuit. The first driver circuit includes a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, where the plurality of cascaded first shift registers are configured to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are configured to output a gate scanning signal for controlling a second display partition. The first display driver integrated circuit includes a first gate start signal terminal and a second gate start signal terminal, where the first gate start signal terminal is coupled to an input terminal of a 1 st< -stage first shift register, and the second gate start signal terminal is coupled to an input terminal of a 1 st< -stage second shift register. The first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit.

[0008] According to the display module provided in embodiments of this application, the first driver circuit includes a first driver sub-circuit and a second driver sub-circuit. The first driver sub-circuit includes the plurality of cascaded first shift registers, and the second driver sub-circuit includes the plurality of cascaded second shift registers. The first driver sub-circuit is controlled by a first gate start signal terminal provided by the first gate start signal terminal in the first display driver integrated circuit, and the second driver sub-circuit is controlled by a second gate start signal terminal provided by the second gate start signal terminal in the first display driver integrated circuit, to implement independent partition control of the first driver sub-circuit and the second driver sub-circuit, so as to reduce power consumption of the display module. The first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit, so that signal terminals on two sides of the first display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0009] In a possible implementation, the first display driver integrated circuit further includes a first data signal terminal, the first data signal terminal is coupled to a data line, and the first data signal terminal is disposed between the first gate start signal terminal and the second gate start signal terminal. The first gate start signal terminal and the second gate start signal terminal that provide the first gate start signal and the second gate start signal are disposed on two sides of the first data signal terminal, so that signal terminals on the two sides of the first display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0010] In a possible implementation, the display module further includes a plurality of connection lines, and the plurality of connection lines and the data line are disposed on different layers; and the first gate start signal terminal and the input terminal of the 1 st< -stage first shift register are coupled through the connection line, and the second gate start signal terminal and the input terminal of the 1 st< -stage second shift register are coupled through the connection line. The connection line and the data line are disposed on different layers, so that difficulty of jumper wiring at an intersection of the connection line and the data line can be reduced, simplifying a preparation process.

[0011] In a possible implementation, the display module further includes a shield layer, and the shield layer is located between the data line and the plurality of connection lines. The shield layer is disposed between the data line and the connection line, to shield a signal of the data line, so as to reduce a coupling effect between the data line and the connection line, so as to reduce noise on the connection line.

[0012] In a possible implementation, in a thickness direction of the display module, the plurality of connection lines are disposed on a side that is of the data line and that faces the first display driver integrated circuit. The data line is usually disposed on a same layer as a source and a drain of a transistor in the pixel circuit. The connection line is disposed above the data line, so that a process modification can be reduced, and implementation difficulty can be reduced.

[0013] In a possible implementation, the first driver circuit is located on a first side of the display module, the first display driver integrated circuit is located on a second side of the display module, and the second side intersects the first side; the first gate start signal terminal is close to the first side relative to the second gate start signal terminal; and the connection line coupled to the second gate start signal terminal includes a first segment, a second segment, and a third segment; and the first segment is coupled to the second gate start signal terminal, the third segment is coupled to the input terminal of the 1 st< -stage second shift register, the second segment is connected between the first segment and the third segment, the second segment is disposed on a side that is of the first display driver integrated circuit and that is away from an edge of the display module, and the second segment intersects the data line. In an area on a side that is of the first display driver integrated circuit and that faces a pixel array, a wiring structure above the data line is simple. Therefore, the connection line is disposed in the area on the side that is of the first display driver integrated circuit and that faces the pixel array, so that process difficulty is low, and preparation costs are low.

[0014] In a possible implementation, the connection lines used for low-level active signal transmission are disposed adjacently, and the connection lines used for high-level active signal transmission are disposed adjacently. Signals at some gate start signal terminals are high-level turn-on signals, and signals at some gate start signal terminals are low-level turn-on signals. Therefore, the connection lines for low-level active signal transmission are disposed adjacently, and the connection lines for high-level active signal transmission are disposed adjacently, to avoid cross disposition, so as to reduce a spacing between the connection lines, and reduce layout occupation.

[0015] In a possible implementation, a spacing between adjacent connection lines is greater than or equal to ΔV / 0.5 µ m, and ΔV is an electric potential difference of signals on the adjacent connection lines. In this way, a requirement for weakening signal interference is met.

[0016] In a possible implementation, the display module further includes a second driver circuit, for example, the second driver circuit and the first driver circuit are located on a same side of the display module, the second driver circuit includes a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the first display driver integrated circuit further includes a third gate start signal terminal and a fourth gate start signal terminal, the third gate start signal terminal is coupled to an input terminal of a 1 st< -stage third shift register, and the fourth gate start signal terminal is coupled to an input terminal of a 1 st< -stage fourth shift register. A plurality of driver circuits that can implement partition control may be disposed in the display module, to further reduce power consumption of the display module.

[0017] In a possible implementation, at least one of the first gate start signal terminal, the second gate start signal terminal, the third gate start signal terminal, and the fourth gate start signal terminal is located on a different side of the first display driver integrated circuit. The display module may include a plurality of driver circuits, and a correspondence between the plurality of driver circuits and ports in the first display driver integrated circuit may be set in a diversified manner.

[0018] In a possible implementation, the display module further includes a second display driver integrated circuit, and the second display driver integrated circuit and the first display driver integrated circuit are disposed side by side. The display module may be a display module including a plurality of display driver integrated circuits, to meet a plurality of requirements.

[0019] In a possible implementation, the display module further includes a third driver circuit, the third driver circuit and the first driver circuit are located on different sides of the display module, the third driver circuit includes a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers, the plurality of cascaded fifth shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded sixth shift registers are configured to output a gate scanning signal for controlling the second display partition. Driver circuits may be disposed on a plurality of sides of the display module, to meet a large-screen driving requirement.

[0020] In a possible implementation, the second display driver integrated circuit includes a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled to an input terminal of a 1 st< -stage fifth shift register, and the sixth gate start signal terminal is coupled to an input terminal of a 1 st< -stage sixth shift register. Display driver integrated circuits at different locations may provide start signals for driver circuits located on different sides, to simplify a layout of the display module.

[0021] In a possible implementation, the fifth gate start signal terminal and the sixth gate start signal terminal are located on different sides of the second display driver integrated circuit. In this way, signal terminals at all locations of the second display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0022] In a possible implementation, the second display driver integrated circuit further includes a second data signal terminal, the second data signal terminal is coupled to the data line, and the second data signal terminal is disposed between the fifth gate start signal terminal and the sixth gate start signal terminal. In this way, signal terminals on two sides of the second display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0023] In a possible implementation, the display module further includes a fourth driver circuit, the fourth driver circuit and the third driver circuit are located on a same side of the display module, the fourth driver circuit includes a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers, the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the second display driver integrated circuit further includes a seventh gate start signal terminal and an eighth gate start signal terminal, the seventh gate start signal terminal is coupled to an input terminal of a 1 st< -stage seventh shift register, and the eighth gate start signal terminal is coupled to an input terminal of a 1 st< -stage eighth shift register. A plurality of driver circuits that implement partition control may be disposed in the display module, to further reduce power consumption of the display module.

[0024] In a possible implementation, at least one of the fifth gate start signal terminal, the sixth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal is located on a different side of the second display driver integrated circuit. Two sides of the display module may include a plurality of driver circuits, and a correspondence between the plurality of driver circuits and ports in the first display driver integrated circuit and the second display driver integrated circuit may be set in a diversified manner.

[0025] In a possible implementation, the first driver circuit and the third driver circuit are configured to transmit gate scanning signals of a same type. The first driver circuit and the third driver circuit may be configured to control transistors of a same type in the pixel circuit, and are applicable to a plurality of application scenarios.

[0026] In a possible implementation, the first driver circuit and the third driver circuit are configured to transmit gate scanning signals of different types. The first driver circuit and the third driver circuit may alternatively be configured to control transistors of a same type in the pixel circuit, and are applicable to a plurality of application scenarios.

[0027] In a possible implementation, the display module further includes a power supply voltage terminal, and the first shift register and the second shift register are coupled to the power supply voltage terminal. In this way, a structure of the display module can be simplified.

[0028] In a possible implementation, the first display driver integrated circuit further includes a clock signal terminal, and the first shift register and the second shift register are coupled to the clock signal terminal. In this way, a structure of the display module can be simplified.

[0029] A second aspect of embodiments of this application provides a display module, where the display module includes: a first driver circuit, including a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, where the plurality of cascaded first shift registers are configured to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are configured to output a gate scanning signal for controlling a second display partition; a second driver circuit, located on a different side of the display module from the first driver circuit, where the second driver circuit includes a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers are configured to output a gate scanning signal for controlling the second display partition; a first display driver integrated circuit, configured to: provide a first gate start signal for a 1 st< -stage first shift register, and provide a second gate start signal for a 1 st< -stage second shift register; and a second display driver integrated circuit, configured to: provide a third gate start signal for a 1 st< -stage third shift register, and provide a fourth gate start signal for a 1 st< -stage fourth shift register.

[0030] According to the display module provided in embodiments of this application, the first driver circuit includes the plurality of cascaded first shift registers and the plurality of cascaded second shift registers, and the first gate start signal and the second gate start signal that are provided by the first display driver integrated circuit respectively control the plurality of cascaded first shift registers and the plurality of cascaded second shift registers. The second driver circuit includes the plurality of cascaded third shift registers and the plurality of cascaded fourth shift registers. The fifth gate start signal and the sixth gate start signal that are provided by the second display driver integrated circuit respectively control the plurality of cascaded third shift registers and the plurality of cascaded fourth shift registers. In this way, the first driver circuit and the second driver circuit can implement independent partition control, and even each driver circuit in the display module can implement independent partition control. Power consumption of a plurality of driver circuits in the display module can be reduced, to greatly reduce power consumption of the display module.

[0031] In a possible implementation, the first display driver integrated circuit includes a first gate start signal terminal and a second gate start signal terminal, the first gate start signal terminal is coupled to an input terminal of the 1 st< -stage first shift register, the second gate start signal terminal is coupled to an input terminal of the 1 st< -stage second shift register, and the first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit. The first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit, so that signal terminals on two sides of the first display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0032] In a possible implementation, the second display driver integrated circuit includes a third gate start signal terminal and a fourth gate start signal terminal, the third gate start signal terminal is coupled to an input terminal of the 1 st< -stage third shift register, the fourth gate start signal terminal is coupled to an input terminal of the 1 st< -stage fourth shift register, and the third gate start signal terminal and the fourth gate start signal terminal are located on different sides of the second display driver integrated circuit. The third gate start signal terminal and the fourth gate start signal terminal are located on different sides of the second display driver integrated circuit, so that signal terminals on two sides of the second display driver integrated circuit can be utilized, and existing layout design of the display module is slightly modified, to reduce process implementation difficulty.

[0033] In a possible implementation, the display module further includes a third driver circuit, the third driver circuit and the first driver circuit are located on a same side of the display module, the third driver circuit includes a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers, the plurality of cascaded fifth shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded sixth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the first display driver integrated circuit is configured to: provide a fifth gate start signal for a 1 st< -stage fifth shift register, and provide a sixth gate start signal for a 1 st< -stage sixth shift register. A plurality of driver circuits that can implement partition control may be disposed in the display module, to further reduce power consumption of the display module.

[0034] In a possible implementation, the first display driver integrated circuit further includes a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled to an input terminal of the 1 st< -stage fifth shift register, and the sixth gate start signal terminal is coupled to an input terminal of the 1 st< -stage sixth shift register; and at least one of the first gate start signal terminal, the second gate start signal terminal, the fifth gate start signal terminal, and the sixth gate start signal terminal is located on a different side of the first display driver integrated circuit. The display module may include a plurality of driver circuits, and a correspondence between the plurality of driver circuits and ports in the first display driver integrated circuit may be set in a diversified manner.

[0035] In a possible implementation, the display module further includes a fourth driver circuit, the fourth driver circuit and the second driver circuit are located on a same side of the display module, the fourth driver circuit includes a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers, the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the second display driver integrated circuit is configured to: provide a seventh gate start signal for a 1 st< -stage seventh shift register, and provide an eighth gate start signal for a 1 st< -stage eighth shift register. A plurality of driver circuits that can implement partition control may be disposed in the display module, to further reduce power consumption of the display module.

[0036] In a possible implementation, the second display driver integrated circuit further includes a seventh gate start signal terminal and an eighth gate start signal terminal, the seventh gate start signal terminal is coupled to an input terminal of the 1 st< -stage seventh shift register, and the eighth gate start signal terminal is coupled to an input terminal of the 1 st< -stage eighth shift register; and at least one of the third gate start signal terminal, the fourth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal is located on a different side of the second display driver integrated circuit. The display module may include a plurality of driver circuits, and a correspondence between the plurality of driver circuits and ports in the first display driver integrated circuit may be set in a diversified manner.

[0037] In a possible implementation, the first driver circuit and the second driver circuit are configured to transmit gate scanning signals of a same type. The first driver circuit and the second driver circuit may be configured to control transistors of a same type in the pixel circuit, and are applicable to a plurality of application scenarios.

[0038] In a possible implementation, the first driver circuit and the second driver circuit are configured to transmit gate scanning signals of different types. The first driver circuit and the second driver circuit may alternatively be configured to control transistors of a same type in the pixel circuit, and are applicable to a plurality of application scenarios.

[0039] A third aspect of embodiments of this application provides an electronic device, where the electronic device includes a driver controller and a display module, where the driver controller is coupled to the display module. The display module includes the display module according to any implementation of the first aspect. Alternatively, the display module includes the display panel and the display driver integrated circuit according to the second aspect.

[0040] In a possible implementation, the driver controller is configured to output an image signal to the display driver integrated circuit, and the image signal includes coordinate information of a scanning start row and a scanning stop row and a data signal.

[0041] A fourth aspect of embodiments of this application provides a driving method of a display module, where the display module includes a first driver circuit and a first display driver integrated circuit, and the first driver circuit includes a plurality of cascaded first shift registers and a plurality of cascaded second shift registers. The driving method of the display module includes: in a first time period of an image frame, a 1 st< -stage first shift register receives a turn-on signal of a first gate start signal terminal, an N th< -stage first shift register receives a signal of an output terminal of an (N-1) th< -stage first shift register, each-stage first shift register receives a first clock signal of a first clock signal terminal, and each-stage first shift register outputs a scanning start signal, where N is an integer greater than 1, and a frequency of the first clock signal is a first frequency; and in a second time period of the image frame, a 1 st< -stage second shift register receives a turn-off signal of a second gate start signal terminal, and an M th< -stage second shift register receives a signal of an output terminal of an (M-1) th< -stage second shift register, each-stage second shift register receives a second clock signal or a fixed voltage signal of the first clock signal terminal, and each-stage second shift register outputs a scanning stop signal, where M is an integer greater than 1, a frequency of the second clock signal is a second frequency, and the second frequency is less than the first frequency.

[0042] According to the driving method of the display module provided in embodiments of this application, in a partial display scenario of the display module, driving power consumption of the display module is reduced by disabling a signal of a clock signal terminal or reducing a frequency of a signal of a clock signal terminal, so that a display power consumption optimization effect can be achieved.

[0043] In a possible implementation, the display module further includes a second driver circuit, and the second driver circuit includes a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers; in the first time period, a 1 st< -stage third shift register receives a turn-on signal of a third gate start signal terminal, an O th< -stage third shift register receives a signal of an output terminal of an (O-1) th< -stage third shift register, each-stage third shift register receives a third clock signal of a second clock signal terminal, each-stage third shift register outputs a scanning start signal, and O is an integer greater than 1; and in the second time period, a 1 st< -stage fourth shift register receives a turn-on signal of a fourth gate start signal terminal, a P th< -stage fourth shift register receives a signal of an output terminal of a (P-1) th< -stage fourth shift register, each-stage fourth shift register receives the third clock signal of the second clock signal terminal, each-stage fourth shift register outputs a scanning start signal, and P is an integer greater than 1. When the display module includes a plurality of driver circuits, during split-screen display, there may still be a driver circuit that keeps normal refreshing.BRIEF DESCRIPTION OF DRAWINGS

[0044] FIG. 1 is a diagram of a structure of an electronic device according to an embodiment of this application; FIG. 2 is a diagram of a topology structure of a pixel circuit according to an embodiment of this application; FIG. 3A is a diagram of a structure of a display module according to an embodiment of this application; FIG. 3B is a diagram of a structure of an EOA according to an embodiment of this application; FIG. 3C is a diagram of output waveforms of an EOA and a GOA according to an embodiment of this application; FIG. 4A is a diagram of a structure of a display module according to an embodiment of this application; FIG. 4B is a diagram of a structure of an EOA according to an embodiment of this application; FIG. 4C is a diagram of output waveforms of an EOA and a GOA according to an embodiment of this application; FIG. 5 is a diagram of a structure of a GOA according to an embodiment of this application; FIG. 6 is a diagram of a structure of a display module according to an embodiment of this application; FIG. 7 is a diagram of a structure of a display module according to an embodiment of this application; FIG. 8A and FIG. 8B each are a diagram of a structure of a display module according to an embodiment of this application; FIG. 9 is a section view in a direction A1-A2 in FIG. 8B according to an embodiment of this application; FIG. 10A to FIG. 10E each are a diagram of a structure of a display module according to an embodiment of this application; FIG. 11A to FIG. 11C each are a diagram of a structure of a display module according to an embodiment of this application; FIG. 12A and FIG. 12B each are a diagram of a structure of a display module according to an embodiment of this application; FIG. 13A and FIG. 13B each are a diagram of a structure of a display module according to an embodiment of this application; FIG. 14 is a diagram of a structure of a display module according to an embodiment of this application; FIG. 15A to FIG. 15D each are a diagram of a display scenario according to an embodiment of this application; FIG. 16A to FIG. 16E each are a diagram of a form of a display panel according to an embodiment of this application; FIG. 17A to FIG. 17D each are a diagram of a driving time sequence of a display panel according to an embodiment of this application; FIG. 18 is a diagram of signal transmission during partition display according to an embodiment of this application; and FIG. 19 is a diagram of driving logic during partition display according to an embodiment of this application. DESCRIPTION OF EMBODIMENTS

[0045] The following describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application. It is clear that the described embodiments are merely a part rather than all of embodiments of this application.

[0046] Terms such as "second" and "first" below are only for ease of description, and cannot be understood as indicating or implying relative importance or implicitly indicating a quantity of indicated technical features. Therefore, a feature limited by "second", "first", or the like may explicitly or implicitly include one or more features. In the descriptions of this application, unless otherwise stated, "a plurality of" means two or more.

[0047] In addition, in embodiments of this application, orientation terms such as "upper", "lower", "left", and "right" may include but are not limited to definitions based on illustrated orientations in which components in the accompanying drawings are placed. It should be understood that, these directional terms may be relative concepts. They are used for description and clarification of relative locations, and may vary accordingly depending on a change in the orientations in which the components in the accompanying drawings are placed in the accompanying drawings.

[0048] In embodiments of this application, unless otherwise clearly specified and limited, a term "connection" should be understood in a broad sense. For example, the "connection" may be a fixed connection, a detachable connection, or an integral connection, may be a direct connection, or may be an indirect connection through an intermediate medium. In addition, a term "coupling" may be a direct electrical connection, or may be an indirect electrical connection through an intermediate medium. A term "contact" may be direct contact or indirect contact through an intermediate medium.

[0049] In embodiments of this application, "and / or" describes an association relationship between associated objects, and indicates that three relationships may exist. For example, A and / or B may indicate the following cases: Only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects.

[0050] Embodiments of this application provide an electronic device. The electronic device may be, for example, a foldable electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. The consumer electronic product is, for example, a mobile phone (mobile phone), a tablet computer (pad), a notebook computer, an e-reader, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a desktop display, an intelligent wearable product (for example, a smartwatch or a smart band), a virtual reality (virtual reality, VR) electronic device, an augmented reality (augmented reality, AR) electronic device, or an uncrewed aerial vehicle. The home electronic product is, for example, a smart door lock, a television, a refrigerator, or a small charging home appliance (for example, a soy milk maker or a robot vacuum cleaner). The vehicle-mounted electronic product is, for example, a vehicle-mounted navigator, or a vehicle-mounted DVD. The financial electronic product is, for example, an ATM machine or an electronic device for self-service.

[0051] A specific form of the electronic device is not specially limited in embodiments of this application. For ease of description, an example in which the electronic device is a mobile phone is used for description in the following embodiments.

[0052] FIG. 1 is a diagram of a structure of an electronic device according to an embodiment of this application.

[0053] As shown in FIG. 1, an electronic device 1 includes a display module 40 and a driver controller 30. FIG. 1 shows an example in which the terminal 1 is a straight-screen mobile phone. This embodiment of this application is merely an example.

[0054] The driver controller 30 is coupled to the display module 40, and the driver controller 30 receives an image signal RGB and a control signal CTRL. The driver controller 30 outputs, based on the image signal RGB, an image data signal DATA that matches an interface specification of the display module 40. The driver controller 30 further outputs a data control signal DCS. The driver controller 30 includes, for example, a system on chip (system on chip, SOC).

[0055] The display module 40 includes, for example, a display panel 10 and a display driver integrated circuit 20. The display driver integrated circuit 20, for example, is coupled to the driver controller 30, receives a signal output by the driver controller 30, and provides a signal for display for the display panel 10.

[0056] For example, the display driver integrated circuit 20 receives the data control signal DCS and the image data signal DATA from the driver controller 30. The display driver integrated circuit 20 converts the image data signal DATA into a data signal, and outputs the data signal to a plurality of data signal lines DL1-DLm. The data signal is an analog voltage corresponding to a grayscale value of the image data signal DATA. The display driver integrated circuit (display driver integrated circuit, DDIC) 20 is further configured to output, to the display panel 10, a scanning control signal SCS (for example, a clock signal CLK, a gate start signal STV, or a reset signal RST) required for display.

[0057] In a possible embodiment, the display panel 10 is a liquid crystal display (liquid crystal display, LCD) panel. Based on this, the electronic device 1 further includes a back light unit (back light unit, BLU) located on a back surface of the liquid crystal display panel. The back light unit may provide a light source for the liquid crystal display panel, so that each sub pixel (sub pixel) in the liquid crystal display panel can emit light to display an image.

[0058] In another possible embodiment, the display panel 10 is a self light emitting display module 40 like an organic light emitting diode (organic light emitting diode, OLED) display module 40, an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display module 40, a mini organic light-emitting diode (mini organic light-emitting diode, Mini-OLED) display module 40, a micro light-emitting diode (micro light-emitting diode, Micro-LED) display module 40, a micro organic light-emitting diode (micro organic light-emitting diode, Micro-OLED) display module 40, or a quantum dot light emitting diode (quantum dot light emitting diode, QLED) display module 40. In this case, the display panel 10 may be a rigid display panel, or the display panel 10 may be a flexible display panel.

[0059] For any one of the foregoing display panels 10, the display panel 10 includes an active area (active area, AA) and a non-display area BB around the active area AA. The active display area AA is configured to display an image. The active display area AA includes a plurality of sub pixels (sub pixel, SP), a pixel circuit 11 is disposed in each sub pixel, and the pixel circuit 11 receives a data signal provided by the display driver integrated circuit 20. The non-display area BB includes a driver circuit 12, and the driver circuit 12 receives a scanning control signal SCS provided by the display driver integrated circuit 20.

[0060] In this application, an example in which pixel circuits 11 are arranged in a matrix form is used for description. Pixel circuits 11 arranged in a row in a horizontal direction X are referred to as a same row of pixel circuits 11, and pixel circuits 11 arranged in a row in a vertical direction Y are referred to as a same column of pixel circuits 11.

[0061] In some embodiments, the pixel circuit 11 usually includes a driver circuit including a plurality of transistors and a light emitting unit, and generates a driving current through the driver circuit to drive the light emitting unit to emit light, to implement light emission of the pixel circuit 11.

[0062] In some embodiments, the electronic device 1 further includes a middle frame, and the display panel 10 is disposed on the middle frame and carried by the middle frame.

[0063] With diversification of forms and use scenarios of the electronic device 1, a size of the display panel 10 is gradually increased. However, the larger display panel 10 results in relative increased display power consumption, affecting an overall battery life of the electronic device 1. Therefore, a requirement of the display panel 10 for low power consumption becomes a new focus of design improvement in the display field. For example, a "Picture in picture" function is used on a mobile phone product, that is, a video is floated at an upper part of the display panel 10, and a lower part is used for static reading. Alternatively, for example, "App Multiplier" is used on a tablet product, that is, in a use process of an application, a left part is mostly static, and a right part dynamically changes with browsing sliding.

[0064] To make the same display panel 10 support both a high refresh rate (for example, 120 Hz) and a low refresh rate (for example, 1 Hz), as well as to achieve smooth switching between the high refresh rate and the low refresh rate in any row of the display panel 10, a high mobility of a low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor, LTPS TFT) and a low leakage of an indium gallium zinc oxide thin-film transistor (indium gallium zinc oxide thin-film transistor, IGZO TFT) may be comprehensively utilized in a pixel circuit of the display panel 10, to perform related circuit design. In this way, both smoothness of the high refresh rate and power consumption reduction of the low refresh rate are implemented. The LTPS TFT and the IGZO TFT are combined (or referred to as a low temperature poly crystalline oxide (low temperature poly crystalline oxide, LTPO) technology) as a driver circuit of the pixel circuit 11, so that the high refresh rate, the low refresh rate, and seamless switching between different refresh rates can be implemented, to meet a requirement of a dynamic refresh rate. This shows great potential for wide application in an OLED display panel.

[0065] FIG. 2 is a diagram of a topology structure of a pixel circuit according to an embodiment of this application.

[0066] In some embodiments, as shown in FIG. 2, the pixel circuit 11 includes a first node initialization circuit 111, a programming and threshold compensation circuit 112, a light emitting control circuit 113, a light emitting unit 114, an anode reset circuit 115, and a second node initialization circuit 116. The pixel circuit 11 shown in FIG. 2 is merely an example, and constitutes no limitation.

[0067] In this embodiment of this application, an example in which a first power supply voltage terminal ELVDD is a high-level power supply voltage terminal and a second power supply voltage terminal ELVSS is a low-level power supply voltage terminal is used for illustration. However, this is not limited.

[0068] In some embodiments, as shown in FIG. 2, the first node initialization circuit 111 includes a fourth transistor M4 and a third transistor M3; the programming and threshold compensation circuit 112 includes a second transistor M2, a first transistor M1, a third transistor M3, and a storage capacitor Cst; the light emitting control circuit 113 includes a fifth transistor M5 and a sixth transistor M6; the anode reset circuit 115 includes a seventh transistor M7; and the second node initialization circuit 116 includes an eighth transistor M8. The first transistor M1 is a driving transistor, and other transistors are switch transistors. The first node initialization circuit 111 and the programming and threshold compensation circuit 112 share the third transistor M3. The light emitting unit 114 is, for example, an OLED.

[0069] In the following descriptions, a control electrode of a transistor may be, for example, a gate of the transistor, and a first electrode of the transistor and a second electrode of the transistor are respectively a source and a drain of the transistor. This is explained herein, and is not explained again below.

[0070] A control electrode of the fourth transistor M4 is coupled to an initialization scanning signal terminal SC, a first electrode of the fourth transistor M4 is coupled to a first initialization voltage terminal Vinit1, and a second electrode of the fourth transistor M4 is coupled to a fourth node N4.

[0071] A control electrode of the third transistor M3 is coupled to a compensation scanning signal terminal SB, a first electrode of the third transistor M3 is coupled to the fourth node N4, and a second electrode of the third transistor M3 is coupled to a node N.

[0072] A control electrode of the second transistor M2 is coupled to the programming scanning signal terminal SX, a first electrode of the second transistor M2 is coupled to a data voltage terminal Vdata, and a second electrode of the second transistor M2 is coupled to a third node N3.

[0073] A control electrode of the first transistor M1 is coupled to the node N, a first electrode of the first transistor M1 is coupled to the third node N3, and a second electrode of the first transistor M1 is coupled to a second node N2. The second node N2 is further coupled to the fourth node N4.

[0074] One end of the storage capacitor Cst is coupled to the node N, and the other end of the storage capacitor Cst is coupled to the first power supply voltage terminal ELVDD.

[0075] A control electrode of the fifth transistor M5 is coupled to a light emitting control signal terminal EM, a first electrode of the fifth transistor M5 is coupled to the first power supply voltage terminal ELVDD, and a second electrode of the fifth transistor M5 is coupled to the third node N3.

[0076] A control electrode of the sixth transistor M6 is coupled to the light emitting control signal terminal EM, a first electrode of the sixth transistor M6 is coupled to the second node N2, and a second electrode of the sixth transistor M6 is coupled to an anode of the light emitting unit 114. A cathode of the light emitting unit 114 is coupled to the second power supply voltage terminal ELVSS.

[0077] A control electrode of the seventh transistor M7 is coupled to a reset control signal terminal SF, a first electrode of the seventh transistor M7 is coupled to a second initialization voltage terminal Vinit2, and a second electrode of the seventh transistor M7 is coupled to the anode of the light emitting unit 114.

[0078] A control electrode of the eighth transistor M8 is coupled to the reset control signal terminal SF, a first electrode of the eighth transistor M8 is coupled to a third initialization voltage terminal Vinit3, and a second electrode of the eighth transistor M8 is coupled to the second node N2.

[0079] For example, in the pixel circuit 11, the third transistor M3 and the fourth transistor M4 are IGZO TFTs, are N-type transistors, and are turned on under control of a high-level signal. Alternatively, the third transistor M3 and the fourth transistor M4 may be transistors of other types. This is not limited in embodiments of this application. The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are LTPS TFTs, are P-type transistors, and are turned on under control of a low-level signal.

[0080] The initialization scanning signal terminal SC of the pixel circuit 11 is coupled to an initialization scanning signal line SCL, the compensation scanning signal terminal SB of the pixel circuit 11 is coupled to a compensation scanning signal line SBL, the programming scanning signal terminal SX of the pixel circuit 11 is coupled to a programming scanning signal line SXL, the light emitting control signal terminal EM of the pixel circuit 11 is coupled to a light emitting control scanning signal line EML, and the reset scanning signal terminal SF of the pixel circuit 11 is coupled to a reset scanning signal line SFL. The data voltage terminal Vdata of the pixel circuit 11 is coupled to a data signal line DL. Voltages of the first initialization voltage terminal Vinit1, the second initialization voltage terminal Vinit2, the third initialization voltage terminal Vinit3, the first power supply voltage terminal ELVDD, and the second power supply voltage terminal ELVSS may be provided by a voltage generator in an electronic device.

[0081] The compensation scanning signal line SBL in the scanning signal lines is used as an example. In FIG. 1, an example in which one row of pixel circuits 11 are coupled to a same compensation scanning signal line SBL is used for illustration. The same row of pixel circuits 11 may alternatively be correspondingly coupled to a plurality of compensation scanning signal lines SBL. For example, a left half part of one row of pixel circuits 11 are coupled to one compensation scanning signal line SBL, and a right half part of the row of pixel circuits 11 are coupled to another compensation scanning signal line SBL. Similarly, in FIG. 1, an example in which a same column of pixel circuits 11 are coupled to a same data signal line DL is used for illustration. The same column of the pixel circuits 11 may alternatively be correspondingly coupled to a plurality of data signal lines DL. For example, an upper half part of one column of pixel circuits 11 are coupled to one data signal line DL, and a lower half part of the column of pixel circuits 11 are coupled to another data signal line DL.

[0082] A driver circuit 12 receives a scanning control signal SCS from the driver controller 30. The driver circuit 12 may output a scanning signal to the scanning signal line in response to the scanning control signal SCS. The scanning signal line includes, for example, an initialization scanning signal lines SCL1 to SCLn, a compensation scanning signal lines SBL1 to SBLn, a programming scanning signal lines SXL1 to SXLn, a reset scanning signal lines SFL1 to SFLn, and a light emitting control scanning signal lines EML1 to EMLn. The driver circuit 12 may output an initialization scanning signal to the initialization scanning signal lines SCL1 to SCLn, output a compensation scanning signal to the compensation scanning signal lines SBL1 to SBLn, output a programming scanning signal to the programming scanning signal lines SXL1 to SXLn, output a reset scanning signal to the reset scanning signal lines SFL1 to SFLn, and output a light emitting control signal to the light emitting control scanning signal lines EML1 to EMLn in response to the scanning control signal SCS.

[0083] For example, the driver circuit 12 may be, for example, a gate driver on array (gate driver on array, GOA) and / or an emission circuit on array (emission circuit on array, EOA). The EOA is configured to output the light emitting control signal to the light emitting control scanning signal lines EML1 to EMLn; and the GOA is configured to output the initialization scanning signal to the initialization scanning signal lines SCL1 to SCLn, output the compensation scanning signal to the compensation scanning signal lines SBL1 to SBLn, output the programming scanning signal to the programming scanning signal lines SXL1 to SXLn, and output the reset scanning signal to the reset scanning signal lines SFL1 to SFLn. For example, a gate initialization driver circuit on array substrate GOA1 is configured to: output the initialization scanning signal to the initialization scanning signal lines SCL1 to SCLn, and control the fourth transistor M4 in the pixel circuit 11. The gate compensation driver circuit on array substrate GOA2 is configured to: output the compensation scanning signal to the compensation scanning signal lines SBL1 to SBLn, and control the third transistor M3 in the pixel circuit 11. The gate programming driver circuit on array substrate GOA3 is configured to: output the programming scanning signal to the programming scanning signal lines SXL1 to SXLn, and control the second transistor M2 in the pixel circuit 11. The gate reset driver circuit on array substrate GOA4 is configured to: output the reset scanning signal to the reset scanning signal lines SFL1 to SFLn, and control the seventh transistor M7 in the pixel circuit 11. When a gate of the eighth transistor M8 is also controlled by the reset scanning signal lines SFL1 to SFLn, the gate reset driver circuit on array substrate GOA4 further controls the eighth transistor M8 in the pixel circuit 11.

[0084] FIG. 3A is a diagram of a structure of a display module according to an embodiment of this application. FIG. 3B is a diagram of a structure of an EOA according to an embodiment of this application. FIG. 3C is a diagram of output waveforms of an EOA and a GOA according to an embodiment of this application.

[0085] In some embodiments, as shown in FIG. 3A, the display module 40 with a folding function is shown. The display panel 10 included in the display module 40 has a folding function, and includes a folding boundary. An EOA circuit in the display panel 10 is used as an example. EOAs may be disposed on two opposite sides of the active display area AA, and one row of pixel circuits 11 are driven by the two EOAs. Each EOA is correspondingly coupled to a DDIC, an edge pin of the DDIC is configured to provide a signal, a power supply, or the like for the EOA, and an internal pin of the DDIC is configured to provide a signal for a data signal line DL.

[0086] As shown in FIG. 3B, currently, for the display panel 10 with the folding function, an EOA included in the display panel 10 has a same structure as an EOA of the conventional unfoldable display panel 10, and partition control is not performed for different display areas.

[0087] The EOA includes at least two-stage cascaded shift registers RS(1) to RS(n). A signal input terminal STVI of a 1 st< -stage shift register RS(1) is configured to receive a gate start (start vertical, STV) signal. Except for the 1 st< -stage shift register RS(1), a signal input terminal STVI of each-stage shift register RS(m) is coupled to an output terminal GO of a previous-stage shift register RS(m-1) of the stage shift register RS(m). Except for a last-stage shift register, a reset signal terminal RST of each-stage shift register RS(m) is coupled to an output terminal GO of a next-stage shift register RS(m+1) of the shift register RS(m). A reset signal terminal RST of the last-stage shift register RSn receives an STV signal. When the STV signal is a turn-on signal, the 1 st< -stage shift register RS1 of the driver circuit 12 starts to work, and then the multi-stage shift registers start to work stage by stage.

[0088] Design of a GOA in the display panel 10 is the same as design of the EOA. A quantity of GOAs varies with different structures of the pixel circuit 11.

[0089] As shown in FIG. 3C, regardless of how an image is displayed in the active display area AA, the EOA and the GOA in the display panel 10 keeps outputting in a row-by-row manner.

[0090] In an inward folding use scenario, the display panel 10 is used as a whole, and there is no need to separately control different display areas. However, in an outward folding use scenario, some areas of the display panel 10 are used separately. If a conventional architecture is adopted, the EOA and the GOA do not perform separate control on different partition locations of a foldable screen, and a non-display area cannot be disabled during partition display. Actual driving power consumption during partition display is close to power consumption during full-screen display, and optimization cannot be performed on driving power consumption during partition display, affecting a battery life of the entire device.

[0091] With diversification of forms and use scenarios of the electronic device 1, a size of the display panel 10 is gradually increased. However, the larger display panel 10 results in relative increased display power consumption, affecting an overall battery life of the electronic device 1. Therefore, the requirement of the display panel 10 for low power consumption becomes a new focus of design improvement in the display field.

[0092] Currently, a person skilled in the art proposes to make a display panel have a partition display function, and refreshes the display panel by partition to reduce power consumption of the display panel. Partition display can be used to reduce power consumption of the electronic device 1 in an outward folding screen scenario, a multi-folding screen scenario, or another scenario in which partition display is applied.

[0093] In some embodiments, to implement partition display, the EOAs in the display panel 10 is divided into two or more parts, and different STV signals are used to drive different parts of the EOAs to work, so as to control display of different areas of the display panel 10.

[0094] FIG. 4A is a diagram of a structure of a display module according to an embodiment of this application. FIG. 4B is a diagram of a structure of an EOA according to an embodiment of this application. FIG. 4C is a diagram of output waveforms of an EOA and a GOA according to an embodiment of this application.

[0095] As shown in FIG. 4A, the EOA in the display panel 10 includes a first light emitting driver sub-circuit EOA1 and a second light emitting driver sub-circuit EOA2. A boundary between the first light emitting driver sub-circuit EOA1 and the second light emitting driver sub-circuit EOA2 corresponds to a folding boundary in the active display area AA. A first shift register RS1 is configured to send a scanning signal to the pixel circuit 11 in a first display partition, and a second shift register RS2 is configured to send a scanning signal to the pixel circuit 11 in a second display partition. However, a structure of the GOA is still the same as the structure of the EOA shown in FIG. 3B.

[0096] As shown in FIG. 4B, the first light emitting driver sub-circuit EOA1 includes a plurality of cascaded first shift registers RS1, and a 1 st< -stage first shift register RS1 receives a first gate start signal STV1. The second light emitting driver sub-circuit EOA2 includes a plurality of cascaded second shift registers RS2, and a 1 st< -stage second shift register RS2 receives a second gate start signal STV2. In other words, the first light emitting driver sub-circuit EOA1 is controlled by the first gate start signal STV1, and the second light emitting driver sub-circuit EOA2 is controlled by the second gate start signal STV2.

[0097] As shown in FIG. 4C, the first light emitting driver sub-circuit EOA1 and the second light emitting driver sub-circuit EOA2 independently output signals, and the EOA may separately drive the first display partition and the second display partition in the active display area AA. The first light emitting driver sub-circuit EOA1 may drive the first display partition to display an image, and the second light emitting driver sub-circuit EOA2 may drive the second display partition not to display an image. Alternatively, the first light emitting driver sub-circuit EOA1 may drive the first display partition not to display an image, and the second light emitting driver sub-circuit EOA2 may drive the second display partition to display an image. Alternatively, the first light emitting driver sub-circuit EOA1 may drive the first display partition not to display an image, and the second light emitting driver sub-circuit EOA2 may drive the second display partition not to display an image. Alternatively, the first light emitting driver sub-circuit EOA1 may drive the first display partition to display an image, and the second light emitting driver sub-circuit EOA2 may drive the second display partition to display an image. A plurality of display scenarios may be switched at random.

[0098] In the display panel 10, the EOA that provides a signal for a light emitting control signal terminal EM may implement independent partition control, but the GOA is still in full-screen control. With upgrade of an architecture of the current pixel circuit 11, a quantity of GOA signals that control work of the pixel circuit 11 increases, and a quantity of GOAs is significantly greater than a quantity of EOAs. In the foregoing solution, only power consumption of the EOA can be reduced, and power consumption of the GOA cannot be reduced. Therefore, a power consumption reduction degree of the display panel 10 is really limited.

[0099] Based on this, an embodiment of this application provides a GOA, to further reduce power consumption of the display panel 10.

[0100] FIG. 5 is a diagram of a structure of a GOA according to an embodiment of this application.

[0101] This embodiment of this application provides a GOA. As shown in FIG. 5, the GOA includes a first gate driver sub-circuit GOAI and a second gate driver sub-circuit GOAII.

[0102] The first gate driver sub-circuit GOAI includes a plurality of cascaded first shift registers RS1, an input terminal STVI of a 1 st< -stage first shift register RS1 receives a first gate start signal STV1, and an input terminal STVI of an N th< -stage first shift register RS1 is coupled to an output terminal GO of an (N-1) th< -stage first shift register RS1. N is an integer greater than 1.

[0103] The second gate driver sub-circuit GOAII includes a plurality of cascaded second shift registers RS2, an input terminal STVI of a 1 st< -stage second shift register RS2 receives a second gate start signal STV2, and an input terminal STVI of an M th< -stage second shift register RS2 is coupled to an output terminal GO of an (M-1) th< -stage second shift register RS2. M is an integer greater than 1.

[0104] The first gate driver sub-circuit GOAI is controlled by the first gate start signal STV1, and the second gate driver sub-circuit GOAII is controlled by the second gate start signal STV2. The first gate driver sub-circuit GOAI and the second gate driver sub-circuit GOAII independently output signals. The GOA may separately drive a first display partition and a second display partition in the active display area AA.

[0105] In the display panel 10, the GOA that provides a signal for a scanning signal terminal may implement independent partition control, to reduce power consumption of the GOA. However, one or more GOAs in the display panel 10 may be set to the foregoing structure of independent partition control, to greatly reduce power consumption of the display panel 10.

[0106] In some embodiments, the first shift register RS1 is further coupled to a high-voltage of gate driver (high-voltage of gate driver, VGH) of the display module 40, and the second shift register RS2 is also coupled to the high-voltage of gate driver. In this way, design of the GOA can be simplified.

[0107] Certainly, the first shift register RS1 and the second shift register RS2 may alternatively be coupled to different high-voltage of gate drivers.

[0108] In some embodiments, the first shift register RS1 is further coupled to a low-voltage of gate driver (low-voltage of gate driver, VGL) of the display module 40, and the second shift register RS2 is also coupled to the low-voltage of gate driver. In this way, design of the GOA can be simplified.

[0109] Certainly, the first shift register RS1 and the second shift register RS2 may alternatively be coupled to different low-voltage of gate drivers.

[0110] In some embodiments, the first shift register RS1 is further coupled to a first clock signal terminal CLK1 of the display driver integrated circuit 20, and the second shift register RS2 is also coupled to the first clock signal terminal CLK1. In this way, design of the GOA can be simplified.

[0111] Certainly, the first shift register RS1 and the second shift register RS2 may alternatively be coupled to different first clock signal terminals CLK1.

[0112] In some embodiments, the first shift register RS1 is further coupled to a second clock signal terminal CLK2 of the display driver integrated circuit 20, and the second shift register RS2 is also coupled to the second clock signal terminal CLK2. In this way, design of the GOA can be simplified.

[0113] Certainly, the first shift register RS1 and the second shift register RS2 may alternatively be coupled to different second clock signal terminals CLK2.

[0114] In some embodiments, the first shift register RS1 is further coupled to an identification signal terminal CX of the display driver integrated circuit 20, and the second shift register RS2 is also coupled to the identification signal terminal CX. In this way, design of the GOA can be simplified. The identification signal terminal CX is configured to transmit a signal for identifying a working status of the first driver circuit 121.

[0115] Certainly, the first shift register RS1 and the second shift register RS2 may alternatively be coupled to different identification signal terminals CX.

[0116] FIG. 6 and FIG. 7 each are a diagram of a structure of a display module according to an embodiment of this application.

[0117] This embodiment of this application further provides a display module 40. As shown in FIG. 6, the display module 40 includes the active display area AA, the first driver circuit 121, and a first display driver integrated circuit 21. The first driver circuit 121 and the first display driver integrated circuit 21 are disposed on a periphery of the active display area AA.

[0118] The first driver circuit 121 is disposed on a first side of the display module 40. The first driver circuit 121 includes a first driver sub-circuit 121I and a second driver sub-circuit 121II. The first driver sub-circuit 121I includes a plurality of cascaded first shift registers RS1, and an input terminal of a 1 st< -stage first shift register RS1 receives a first gate start signal STV 1 provided by the first display driver integrated circuit. The second driver sub-circuit 121II includes a plurality of cascaded second shift registers RS2, and an input terminal of a 1 st< -stage second shift register RS2 receives a second gate start signal STV2 provided by the first display driver integrated circuit. The first driver circuit 121 is configured to provide a scanning signal for the active display area AA. The first driver sub-circuit 121I in the first driver circuit 121 is configured to output a gate scanning signal for controlling a first display partition, and the second driver sub-circuit 121II in the first driver circuit 121 is configured to output a gate scanning signal for controlling a second display partition. The first driver sub-circuit 121I and the second driver sub-circuit 121II may implement independent driving.

[0119] For example, as shown in FIG. 6, the first driver circuit 121 is the GOA shown in FIG. 5, the first driver sub-circuit 121I is the first gate driver sub-circuit GOAI, and the second driver sub-circuit 121II is the second gate driver sub-circuit GOAII. Alternatively, the first driver circuit 121 is the EOA shown in FIG. 4B, the first driver sub-circuit 121I is the first light emitting driver sub-circuit EOA1, and the second driver sub-circuit 121II is the second light emitting driver sub-circuit EOA2.

[0120] The first display driver integrated circuit 21 includes a first gate start signal terminal 211 and a second gate start signal terminal 212. The first gate start signal terminal 211 is coupled to the input terminal of the 1 st< -stage first shift register RS1, and is configured to provide the first gate start signal STV 1 for the input terminal of the 1 st< -stage first shift register RS1. The second gate start signal terminal 212 is coupled to the input terminal of the 1 st< -stage second shift register RS2, and is configured to provide the second gate start signal STV2 for the input terminal of the 1 st< -stage second shift register RS2. In other words, the first gate start signal terminal 211 is configured to provide the first gate start signal STV 1, and the second gate start signal terminal 212 is configured to provide the second gate start signal STV2.

[0121] The first gate start signal terminal 211 and the second gate start signal terminal 212 are located on different sides of the first display driver integrated circuit 21. For example, the first display driver integrated circuit 21 is rectangular and has four sides. The first gate start signal terminal 211 is close to any one of the four sides of the first display driver integrated circuit 21 relative to the second gate start signal terminal 212, and the second gate start signal terminal 212 is close to any one of the remaining three sides of the first display driver integrated circuit 21 relative to the first gate start signal terminal 211. The first gate start signal terminal 211 and the second gate start signal terminal 212 may be disposed adjacently, and another signal terminal may alternatively be disposed between the first gate start signal terminal 211 and the second gate start signal terminal 212.

[0122] For example, in FIG. 6, a middle line of the first display driver integrated circuit 21 is used as a boundary, the first gate start signal terminal 211 and the second gate start signal terminal 212 are located on different sides of the middle line. Alternatively, for example, in FIG. 7, the first gate start signal terminal 211 and the second gate start signal terminal 212 are located on a same side of the middle line. The first gate start signal terminal 211 and the second gate start signal terminal 212 may be located at any location in the first display driver integrated circuit 21. FIG. 6 and FIG. 7 are merely examples.

[0123] The first display driver integrated circuit 21 and the first driver circuit 121 may be disposed on the same side, or may be disposed on different sides. For example, the first display driver integrated circuit 21 is disposed on a second side of the display module 40, and the second side intersects the first side.

[0124] The first driver sub-circuit 121I in the first driver circuit 121I is configured to output a gate scanning signal for controlling the first display partition, and the second driver sub-circuit 121II in the first driver circuit 121 is configured to output a gate scanning signal for controlling the second display partition. The first display partition may be disposed close to the first display driver integrated circuit 21. Alternatively, the second display partition may be disposed close to the first display driver integrated circuit 21.

[0125] According to the display module 40 provided in this embodiment of this application, the first driver circuit 121 includes a first driver sub-circuit 121I and a second driver sub-circuit 121II. The first driver sub-circuit 121I and the second driver sub-circuit 121II are controlled by a first gate start signal STV1 and a second gate start signal STV2 that are provided by the first display driver integrated circuit 21. In this way, the first driver sub-circuit 121I and the second driver sub-circuit 121II can implement independent partition control, and even each driver circuit in the display module 40 can implement independent partition control. Power consumption of a plurality of driver circuits in the display module 40 can be reduced, to greatly reduce power consumption of the display module 40.

[0126] FIG. 8A and FIG. 8B each are a diagram of a structure of a display module according to an embodiment of this application.

[0127] In some embodiments, as shown in FIG. 8A, the display module 40 further includes a data line DL, and the first display driver integrated circuit 21 further includes a first data signal terminal 215. A same column of pixel circuits 11 are coupled to a same data line DL, and the first data signal terminal 215 is coupled to the data line DL, and is configured to provide a data signal.

[0128] The first data signal terminal 215 is disposed between the first gate start signal terminal 211 and the second gate start signal terminal 212. For example, a part of the plurality of first data signal terminals 215 are disposed between the first gate start signal terminal 211 and the second gate start signal terminal 212. Alternatively, for example, all of the plurality of first data signal terminals 215 are disposed between the first gate start signal terminal 211 and the second gate start signal terminal 212. A specific disposition is not limited in embodiments of this application, provided that there is the first data signal terminal 215 disposed between the first gate start signal terminal 211 and the second gate start signal terminal 212.

[0129] Certainly, the first display driver integrated circuit 21 is not limited to including only the first gate start signal terminal 211, the second gate start signal terminal 212, and the first data signal terminal 215, but may further include a signal terminal for transmitting another signal (for example, a clock signal or a power supply signal).

[0130] In a driving process of the display module 40, signals of the first gate start signal terminal 211 and the second gate start signal terminal 212 are both provided by the first display driver integrated circuit 21. The first gate start signal terminal 211 and the second gate start signal terminal 212 that provide the first gate start signal STV1 and the second gate start signal STV2 are disposed on two sides of the first data signal terminal 215, so that signal terminals on the two sides of the first display driver integrated circuit 21 can be utilized, and existing layout design of the display module 40 is slightly modified, to reduce process implementation difficulty.

[0131] In some embodiments, as shown in FIG. 8A, the display module 40 further includes a plurality of connection lines 14, the first gate start signal terminal 211 is coupled to an input terminal of a 1 st< -stage first shift register RS1 through the connection line 14, and the second gate start signal terminal 212 is coupled to an input terminal of a 1 st< -stage second shift register RS2 through the connection line 14.

[0132] For example, as shown in FIG. 8A, the first gate start signal terminal 211 is disposed close to the first driver circuit 121 relative to the second gate start signal terminal 212, and the connection line 14 connecting the second gate start signal terminal 212 and the input terminal of the 1 st< -stage second shift register RS2 is wound from a side that is of the first display driver integrated circuit 21 and that is away from the active display area AA to be coupled to the input terminal of the 1 st< -stage second shift register RS2.

[0133] Alternatively, for example, as shown in FIG. 8B, the first gate start signal terminal 211 is disposed close to the first driver circuit 121 relative to the second gate start signal terminal 212, and the connection line 14 connecting the second gate start signal terminal 212 and the input terminal of the 1 st< -stage second shift register RS2 is wound from a side (away from an edge of the display module 40) that is of the first display driver integrated circuit 21 and that faces the active display area AA to be coupled to the input terminal of the 1 st< -stage second shift register RS2.

[0134] On the side that is of the first display driver integrated circuit 21 and that faces the active display area AA, a wiring structure above the data line DL is simple. Therefore, the connection line 14 is disposed in an area on the side that is of the first display driver integrated circuit 21 and that faces the active display area AA, so that process difficulty is low, and preparation costs are low.

[0135] For example, the connection line 14 coupled to the second gate start signal terminal 212 includes a first segment 141, a second segment 142, and a third segment 143. One end of the first segment 141 is coupled to the second gate start signal terminal 212, and the other end of the first segment 141 is coupled to the second segment 142. One end of the third segment 143 is coupled to the input terminal of the 1 st< -stage second shift register RS2, the other end of the third segment 143 is coupled to the second segment 142, and the second segment 142 is connected between the first segment 141 and the third segment 143. The second segment 142 is disposed between the first display driver integrated circuit 21 and a pixel array (the active display area AA), an extension direction of the second segment 142 intersects an extension direction of the data line DL, and a projection of the second segment 142 intersects the data line DL.

[0136] Certainly, this embodiment of this application is not limited to the connection line 14 only including the three segments, and a structure of the connection line 14 may be increased or reduced based on the three segments.

[0137] FIG. 9 is a section view in a direction A1-A2 in FIG. 8B according to an embodiment of this application.

[0138] In some embodiments, as shown in FIG. 9, the plurality of connection lines 14 and the data line DL are disposed on different layers. Different-layer disposition may be understood as that the plurality of connection lines 14 and the data line DL are not disposed on a surface of a same insulation layer. Alternatively, it is understood as that an insulation layer is disposed between the plurality of connection lines 14 and the data line DL. Alternatively, it is understood as that the plurality of connection lines 14 and the data line DL are not formed through a same time of a patterning process.

[0139] The plurality of connection lines 14 may be disposed on a same layer, or the plurality of connection lines 14 may be disposed on different layers. This is not limited in embodiments of this application, provided that the connection lines 14 and the data line DL are on different layers.

[0140] The connection line 14 and the data line DL are disposed on different layers, so that difficulty of jumper wiring at an intersection of the connection line 14 and the data line DL can be reduced, simplifying a preparation process.

[0141] In some embodiments, the display module 40 further includes a shield layer, and the shield layer is located between the data line DL and the plurality of connection lines 14.

[0142] For example, the shield layer is connected to a fixed voltage terminal, and the fixed voltage terminal is, for example, a reference ground voltage terminal, a first power supply voltage terminal ELVDD, or a second power supply voltage terminal ELVSS. An insulation layer may be disposed between the shield layer and the data line DL, and an insulation layer may further be disposed between the shield layer and the connection line 14.

[0143] The shield layer is disposed between the data line DL and the connection line 14, to shield a signal of the data line DL, so as to reduce a coupling effect between the data line DL and the connection line 14, so as to reduce noise on the connection line 14.

[0144] In some embodiments, in a thickness direction of the display module 40, the plurality of connection lines 14 are disposed on a side that is of the data line DL and that faces the first display driver integrated circuit 21. That is, as shown in FIG. 9, the plurality of connection lines 14 are disposed above the data line DL.

[0145] The data line DL is usually disposed on a same layer as a source and a drain of a transistor in the pixel circuit 11. The connection line 14 is disposed above the data line DL, so that a process modification can be reduced, and implementation difficulty can be reduced.

[0146] Certainly, the connection line 14 may alternatively be disposed below the data line DL. This is not limited in embodiments of this application.

[0147] FIG. 10A to FIG. 10E each are a diagram of a structure of a display module according to an embodiment of this application.

[0148] In some embodiments, as shown in FIG. 10A, the display module 40 further includes a second driver circuit 122, and the second driver circuit 122 and the first driver circuit 121 are located on a same side of the display module 40.

[0149] The second driver circuit 122 includes a third driver sub-circuit 122I and a fourth driver sub-circuit 122II. The third driver sub-circuit 122I includes a plurality of cascaded third shift registers RS3, and the fourth driver sub-circuit 122II includes a plurality of cascaded fourth shift registers RS3. A 1 st< -stage third shift register RS3 is configured to receive a third gate start signal STV3, and the third driver sub-circuit 122I is controlled by the third gate start signal STV3. A 1 st< -stage fourth shift register RS4 is configured to receive a fourth gate start signal STV4, and the fourth driver sub-circuit 122II is controlled by the fourth gate start signal STV4. The third driver sub-circuit 122I in the second driver circuit 122 is configured to output a gate scanning signal for controlling a first display partition, and the fourth driver sub-circuit 122II in the second driver circuit 122 is configured to output a gate scanning signal for controlling a second display partition.

[0150] For example, the second driver circuit 122 includes an EOA, a gate initialization driver circuit on array substrate GOA1, a gate compensation driver circuit on array substrate GOA2, a gate programming driver circuit on array substrate GOA3, or a gate reset driver circuit on array substrate GOA4.

[0151] The first display driver integrated circuit 21 further includes a third gate start signal terminal 213 and a fourth gate start signal terminal 214. The third gate start signal terminal 213 is coupled to an input terminal of the 1 st< -stage third shift register RS3, and the fourth gate start signal terminal 214 is coupled to an input terminal of the 1 st< -stage fourth shift register RS4.

[0152] At least one of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 is located on a different side of the first display driver integrated circuit 21. For example, the first display driver integrated circuit 21 has four sides, and at least one of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 is close to a first side, and other signal terminals are close to one or more of the remaining three sides.

[0153] For example, as shown in FIG. 10A, the first gate start signal terminal 211 and the third gate start signal terminal 213 may be located on one side of a first data signal terminal 215, and the second gate start signal terminal 212 and the fourth gate start signal terminal 214 are located on another side of the first data signal terminal 215.

[0154] Alternatively, as shown in FIG. 10B, the first gate start signal terminal 211, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 may be located on one side of the first data signal terminal 215, and the second gate start signal terminal 212 is located on another side of the first data signal terminal 215.

[0155] Certainly, there may be another distribution, provided that at least one of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 is located on a different side of the first display driver integrated circuit 21 from other signal terminals.

[0156] In some embodiments, as shown in FIG. 10C, the display module 40 includes an EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4. The EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 are all disposed on a first side of the active display area AA. Structures of the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 may be the same as a structure of the first driver circuit 121 in the display module 40.

[0157] For example, the EOA includes a first light emitting driver sub-circuit EOA1 and a second light emitting driver sub-circuit EOA2, the gate initialization driver circuit on array substrate GOA1 includes a first initialization driver sub-circuit GOA1I and a second initialization driver sub-circuit GOA1II, the gate compensation driver circuit on array substrate GOA2 includes a first compensation driver sub-circuit GOA2I and a second compensation driver sub-circuit GOA2II, the gate programming driver circuit on array substrate GOA3 includes a first programming driver sub-circuit GOA3I and a second programming driver sub-circuit GOA3II, and the gate reset driver circuit on array substrate GOA4 includes a first reset driver sub-circuit GOA4I and a second reset driver sub-circuit GOA4II.

[0158] A gate start signal STVA5 received by the first light emitting driver sub-circuit EOA1, a gate start signal STVA1 received by the first initialization driver sub-circuit GOA1I, a gate start signal STVA2 received by the first compensation driver sub-circuit GOA2I, a gate start signal STVA3 received by the first programming driver sub-circuit GOA3I, and a gate start signal STVA4 received by the first reset driver sub-circuit GOA4I are all provided by the first display driver integrated circuit 21.

[0159] A gate start signal STVB5 received by the second light emitting driver sub-circuit EOA2, a gate start signal STVB1 received by the second initialization driver sub-circuit GOA1II, a gate start signal STVB2 received by the second compensation driver sub-circuit GOA2II, a gate start signal STVB3 received by the second programming driver sub-circuit GOA3II, and a gate start signal STVB4 received by the second reset driver sub-circuit GOA4II are all provided by a second display driver integrated circuit 22.

[0160] For example, as shown in FIG. 10C, the first display driver integrated circuit 21 includes a plurality of first gate start signal terminals 211 and a plurality of second gate start signal terminals 212, and the plurality of first gate start signal terminals 211 and the plurality of second gate start signal terminals 212 are located on two opposite sides of the first data signal terminal 215.

[0161] The gate start signal STVA5, the gate start signal STVA1, the gate start signal STVA2, the gate start signal STVA3, and the gate start signal STVA4 are provided by the first gate start signal terminal 211, and the gate start signal STVB5, the gate start signal STVB1, the gate start signal STVB2, the gate start signal STVB3, and the gate start signal STVB4 are provided by the second gate start signal terminal 212.

[0162] The first light emitting driver sub-circuit EOA1, the first initialization driver sub-circuit GOA1I, the first compensation driver sub-circuit GOA2I, the first programming driver sub-circuit GOA3I, and the first reset driver sub-circuit GOA4I are coupled to different first gate start signal terminals 211. The second light emitting driver sub-circuit EOA2, the second initialization driver sub-circuit GOA1II, the second compensation driver sub-circuit GOA2II, the second programming driver sub-circuit GOA3II, and the second reset driver sub-circuit GOA4II are coupled to different second gate start signal terminals 212.

[0163] Alternatively, for example, as shown in FIG. 10D and FIG. 10E, provided that a part of the first light emitting driver sub-circuit EOA1, the second light emitting driver sub-circuit EOA2, the first initialization driver sub-circuit GOA1I, the second initialization driver sub-circuit GOA1II, the first compensation driver sub-circuit GOA2I, the second compensation driver sub-circuit GOA2II, the first programming driver sub-circuit GOA3I, the second programming driver sub-circuit GOA3II, the first reset driver sub-circuit GOA4I, and the second reset driver sub-circuit GOA4II are coupled to the first gate start signal terminal 211, and the other part is coupled to the second gate start signal terminal 212, a specific coupling relationship is not limited.

[0164] The specific coupling relationship is not limited in embodiments of this application, provided that two driver sub-circuits in one driver circuit are respectively coupled to the first gate start signal terminal 211 and the second gate start signal terminal 212. It is not limited to each driver circuit having two driver circuits respectively coupled to the first gate start signal terminal 211 and the second gate start signal terminal 212. For example, as shown in FIG. 10D, both the first light emitting driver sub-circuit EOA1 and the second light emitting driver sub-circuit EOA2 are coupled to the first gate start signal terminal 211. Alternatively, as shown in FIG. 10E, both the first reset driver sub-circuit GOA4I and the second reset driver sub-circuit GOA4II are coupled to the second gate start signal terminal 212.

[0165] Disposition locations of the driver circuits in the display module 40 and disposition locations of the corresponding first gate start signal terminal 211 and the corresponding second gate start signal terminal 212 are merely examples, and are not limited.

[0166] When the display module 40 includes a plurality of driver circuits, the display module 40 needs to include a plurality of connection lines 14. In some embodiments, a spacing between adjacent connection lines 14 is greater than or equal to ΔV / 0.5 µm, where ΔV is an electric potential difference of signals on the adjacent connection lines 14. In other words, the spacing between adjacent connection lines 14 depends on the electric potential difference of signals transmitted on the two connection lines 14, to meet a requirement for weakening signal interference.

[0167] For example, if the electric potential difference between the adjacent connection lines 14 is 10 V, a distance between the two connection lines 14 needs to be greater than or equal to 20 µm.

[0168] In some embodiments, the connection lines 14 used for low-level active signal transmission are disposed adjacently, and the connection lines 14 used for high-level active signal transmission are disposed adjacently.

[0169] Signals at some gate start signal terminals are high-level turn-on signals, and signals at some gate start signal terminals are low-level turn-on signals. Therefore, the connection lines 14 for low-level active signal transmission are disposed adjacently, and the connection lines 14 for high-level active signal transmission are disposed adjacently, to avoid cross disposition, so as to reduce a spacing between the connection lines 14, and reduce layout occupation.

[0170] FIG. 11A to FIG. 11C each are a diagram of a structure of a display module according to an embodiment of this application.

[0171] In some embodiments, as shown in FIG. 11A, the display module 40 further includes the second display driver integrated circuit 22, and the second display driver integrated circuit 22 and the first display driver integrated circuit 21 are disposed side by side. For example, the second display driver integrated circuit 22 is disposed on a side that is of the first display driver integrated circuit 21 and that is away from a first side. In this way, the display module 40 may be driven by two display driver integrated circuits.

[0172] In some embodiments, the display module 40 further includes a third driver circuit 123, and the third driver circuit 123 and the first driver circuit 121 are located on different sides of the display module 40.

[0173] For example, the third driver circuit 123 includes a fifth driver sub-circuit 123I and a sixth driver sub-circuit 123II, the fifth driver sub-circuit 123I includes a plurality of cascaded fifth shift registers RS5, and the sixth driver sub-circuit 123II includes a plurality of cascaded sixth shift registers RS6. The fifth driver sub-circuit 123I in the third driver circuit 123 is configured to output a gate scanning signal for controlling a first display partition, and the sixth driver sub-circuit 123II in the third driver circuit 123 is configured to output a gate scanning signal for controlling a second display partition.

[0174] In this way, the display module 40 may be provided with driver circuits on a plurality of sides, and this is favorable for the large-screen display module 40.

[0175] In some embodiments, the second display driver integrated circuit 22 includes a fifth gate start signal terminal 221 and a sixth gate start signal terminal 222. The fifth gate start signal terminal 221 is coupled to an input terminal of a 1 st< -stage fifth shift register RS5, and is configured to provide a fifth gate start signal STV5. The sixth gate start signal terminal 222 is coupled to an input terminal of a 1 st< -stage fourth shift register RS4, and is configured to provide a sixth gate start signal STV6.

[0176] For example, the fifth gate start signal terminal 221 and the sixth gate start signal terminal 222 are located on different sides of the second display driver integrated circuit 22. For a relative relationship between the fifth gate start signal terminal 221 and the sixth gate start signal terminal 222, refer to the foregoing related descriptions of the relative relationship between the first gate start signal terminal 211 and the second gate start signal terminal 212.

[0177] For example, the sixth gate start signal terminal 222 is disposed close to the first display driver integrated circuit 21 relative to the fifth gate start signal terminal 221. For a connection manner between the second display driver integrated circuit 22 and the second driver circuit 122, refer to the foregoing related descriptions of the connection manner between the first display driver integrated circuit 21 and the first driver circuit 121.

[0178] The first driver circuit 121 and the third driver circuit 123 may be configured to provide gate scanning signals of a same type for the display module 40. For example, both the first driver circuit 121 and the third driver circuit 123 are EOAs. The first driver circuit 121 and the third driver circuit 123 may alternatively be configured to provide gate scanning signals of different types for the display module 40. For example, the first driver circuit 121 is a GOA, and the third driver circuit 123 is an EOA.

[0179] In some embodiments, as shown in FIG. 11A, the second display driver integrated circuit 22 further includes a second data signal terminal 225, the second data signal terminal 225 is coupled to a data line DL, and one or more second data signal terminals 225 are disposed between the fifth gate start signal terminal 221 and the sixth gate start signal terminal 222. In this way, a plurality of signal ports of the second display driver integrated circuit 22 all can be utilized.

[0180] In some embodiments, as shown in FIG. 11B and FIG. 11C, the display module 40 further includes a fourth driver circuit 124, and the fourth driver circuit 124 and the third driver circuit 123 are located on a same side of the display module 40. The fourth driver circuit 124 includes a seventh driver sub-circuit 124I and an eighth driver sub-circuit 124II. The seventh driver sub-circuit 124I includes a plurality of cascaded seventh shift registers RS7, and the eighth driver sub-circuit 124II includes a plurality of cascaded eighth shift registers RS8. The seventh driver sub-circuit 124I in the fourth driver circuit 124 is configured to output a gate scanning signal for controlling the first display partition, and the eighth driver sub-circuit 124II in the fourth driver circuit 124 is configured to output a gate scanning signal for controlling the second display partition.

[0181] The fourth driver circuit 124 and the first driver circuit 121 (or the second driver circuit 122) may be configured to provide gate scanning signals of a same type, or provide gate scanning signals of different types for the display module 40.

[0182] In some embodiments, the second display driver integrated circuit 22 further includes a seventh gate start signal terminal 223 and an eighth gate start signal terminal 224. The seventh gate start signal terminal 223 is coupled to an input terminal of a 1 st< -stage seventh shift register RS7, and is configured to provide a seventh gate start signal STV7. The eighth gate start signal terminal 224 is coupled to an input terminal of a 1 st< -stage eighth shift register RS8, and is configured to provide an eighth gate start signal STV8.

[0183] At least one of the fifth gate start signal terminal 221, the sixth gate start signal terminal 222, the seventh gate start signal terminal 223, and the eighth gate start signal terminal 224 is located on a different side of the second display driver integrated circuit 22. For a connection relationship between the second display driver integrated circuit 22 and each of the third driver circuit 123 and the fourth driver circuit 124, refer to the foregoing related descriptions of the connection relationship between the first display driver integrated circuit 21 and each of the first driver circuit 121 and the second driver circuit 122. Details are not described herein again.

[0184] A location relationship between the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 in the first display driver integrated circuit 21 may be the same as or different from a location relationship between the fifth gate start signal terminal 221, the sixth gate start signal terminal 222, the seventh gate start signal terminal 223, and the eighth gate start signal terminal 224 in the second display driver integrated circuit 22.

[0185] FIG. 12A and FIG. 12B each are a diagram of a structure of a display module according to an embodiment of this application.

[0186] In some embodiments, as shown in FIG. 12A, a plurality of driver circuits are disposed on two opposite sides of the display module 40. For example, an EOA, a gate initialization driver circuit on array substrate GOA1, a gate compensation driver circuit on array substrate GOA2, a gate programming driver circuit on array substrate GOA3, and a gate reset driver circuit on array substrate GOA4 are disposed on a first side of the display module 40. An EOA, a gate initialization driver circuit on array substrate GOA1, a gate compensation driver circuit on array substrate GOA2, a gate programming driver circuit on array substrate GOA3, and a gate reset driver circuit on array substrate GOA4 are disposed on the opposite other side of the display module 40.

[0187] The first display driver integrated circuit 21 provides gate start signals for the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 that are disposed on the first side of the active display area AA. Both a signal port on an inner side and a signal port on an outer side of the first display driver integrated circuit 21 are configured to be coupled to gate start signal terminals, and signal ports in the middle are configured to be coupled to a data line DL and another signal terminal.

[0188] The second display driver integrated circuit 22 provides gate start signals for the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 that are disposed on the other side opposite to the first side. Both a signal port on an inner side and a signal port on an outer side of the second display driver integrated circuit 22 are configured to be coupled to gate start signal terminals, and signal ports in the middle are configured to be coupled to a data line DL and another signal terminal.

[0189] When the display module 40 provided in this embodiment of this application is used in the electronic device 1 provided in this embodiment of this application, the driver controller 30 in the electronic device is coupled to the display driver integrated circuit 20, and is configured to provide a signal for the display driver integrated circuit 20. For example, an application processor (application processor, AP) in the driver controller 30 provides a signal for the display driver integrated circuit 20.

[0190] For example, the driver controller 30 is used by the display driver integrated circuit 20 for outputting an image signal. The image signal includes coordinate information of a scanning start row and a scanning stop row and a data signal, so that the display module 40 implements partition display.

[0191] FIG. 13A and FIG. 13B each are a diagram of a structure of a display module according to an embodiment of this application.

[0192] This embodiment of this application further provides a display module 40. As shown in FIG. 13A, the display module 40 includes the active display area AA, the first driver circuit 121, the third driver circuit 123, the first display driver integrated circuit 21, and the second display driver integrated circuit 22 that are disposed on a periphery of the active display area AA.

[0193] The active display area AA includes a first display partition and a second display partition, and the first display partition and the second display partition are respectively arranged with a plurality of pixel circuits 11 in an array.

[0194] The first driver circuit 121 includes the first driver sub-circuit 121I and the second driver sub-circuit 121II. The first driver sub-circuit 121I includes a plurality of cascaded first shift registers RS1, and an input terminal of a 1 st< -stage first shift register RS1 receives a first gate start signal STV1 provided by the first display driver integrated circuit. The second driver sub-circuit 121II includes a plurality of cascaded second shift registers RS2, and an input terminal of a 1 st< -stage second shift register RS2 receives a second gate start signal STV2 provided by the first display driver integrated circuit. The first driver circuit 121 is configured to provide a scanning signal for the active display area AA. The first driver sub-circuit 121I in the first driver circuit 121 is configured to output a gate scanning signal for controlling the first display partition, and the second driver sub-circuit 121II in the first driver circuit 121 is configured to output a gate scanning signal for controlling the second display partition. The first driver sub-circuit 1211 and the second driver sub-circuit 121II may implement independent driving.

[0195] For example, as shown in FIG. 13A, the first driver circuit 121 is the GOA shown in FIG. 5, the first driver sub-circuit 121I is the first gate driver sub-circuit GOAI, and the second driver sub-circuit 121II is the second gate driver sub-circuit GOAII. Alternatively, the first driver circuit 121 is the EOA shown in FIG. 4B, the first driver sub-circuit 121I is the first light emitting driver sub-circuit EOA1, and the second driver sub-circuit 121II is the second light emitting driver sub-circuit EOA2.

[0196] The third driver circuit 123 includes the fifth driver sub-circuit 123I and the sixth driver sub-circuit 123II. The fifth driver sub-circuit 123I includes a plurality of cascaded fifth shift registers RS5. An input terminal of a 1 st< -stage fifth shift register RS5 is configured to receive a fifth gate start signal STV5 provided by the second display driver integrated circuit 22. The sixth driver sub-circuit 123II includes a plurality of cascaded sixth shift registers RS6, and an input terminal of a 1 st< -stage sixth shift register RS6 is configured to receive a sixth gate start signal STV6 provided by the second display driver integrated circuit 22. The third driver circuit 123 is configured to provide a scanning signal for the active display area AA. The fifth driver sub-circuit 123I in the third driver circuit 123 is configured to output a gate scanning signal for controlling the first display partition, and the sixth driver sub-circuit 123II in the third driver circuit 123 is configured to output a gate scanning signal for controlling the second display partition. The fifth driver sub-circuit 123I and the sixth driver sub-circuit 123II may implement independent driving.

[0197] The third driver circuit 123 may be any two of the EOA and the plurality of GOAs. For example, the first driver circuit 121 and the third driver circuit 123 each are any one of an EOA, a gate initialization driver circuit on array substrate GOA1 that is configured to output initialization scanning signals to initialization scanning signal lines SCL1 to SCLn, a gate compensation driver circuit on array substrate GOA2 that is configured to output compensation scanning signals to compensation scanning signal lines SBL1 to SBLn, a gate programming driver circuit on array substrate GOA3 that is configured to output programming scanning signals to programming scanning signal lines SXL1 to SXLn, or a gate reset driver circuit on array substrate GOA4 that is configured to output reset scanning signals to reset scanning signal lines SFL1 to SFLn.

[0198] As a structure of the pixel circuit 11 changes, types of the first driver circuit 121 and the third driver circuit 123 may also change accordingly, provided that the first driver circuit 121 and the third driver circuit 123 are configured to provide scanning signals for the pixel circuit 11.

[0199] The first driver circuit 121 and the third driver circuit 123 may be configured to output gate scanning signals of a same type, that is, the first driver circuit 121 and the third driver circuit 123 may be GOAs of a same type, and are configured to control transistors of a same type in the pixel circuit 11. The first driver circuit 121 and the third driver circuit 123 may alternatively be configured to output gate scanning signals of different types, that is, the first driver circuit 121 and the third driver circuit 123 may be GOAs of different types, and are configured to control different transistors in the pixel circuit 11.

[0200] For a connection relationship between the fifth shift register RS5 and the sixth shift register RS6 in the third driver circuit 123, and a voltage terminal and a signal terminal, refer to related descriptions of a connection relationship between the first shift register RS1 and the second shift register RS2 in the GOA, and the voltage terminal and the signal terminal. Details are not described herein again.

[0201] In some embodiments, the first driver circuit 121 and the third driver circuit 123 are located on different sides of the display module 40. For example, the first driver circuit 121 and the third driver circuit 123 are located on two opposite sides of the display module 40.

[0202] According to the display module 40 provided in this embodiment of this application, the first driver circuit 121 includes the first driver sub-circuit 121I and the second driver sub-circuit 121II. The first driver sub-circuit 121I and the second driver sub-circuit 121II are controlled by the first gate start signal STV1 and the second gate start signal STV2 that are provided by the first display driver integrated circuit 21. The third driver circuit 123 includes the fifth driver sub-circuit 123I and the sixth driver sub-circuit 123II. The fifth driver sub-circuit 123I and the sixth driver sub-circuit 123II are controlled by the fifth gate start signal STV5 and the sixth gate start signal STV6 that are provided by the second display driver integrated circuit 22. In this way, the first driver sub-circuit 1211 and the second driver sub-circuit 121II can implement independent partition control, the fifth driver sub-circuit 123I and the sixth driver sub-circuit 123II can implement independent partition control, and even each driver circuit in the display module 40 can implement independent partition control. Power consumption of a plurality of driver circuits in the display module 40 can be reduced, to greatly reduce power consumption of the display module 40.

[0203] In some embodiments, as shown in FIG. 13B, the display module 40 further includes the second driver circuit 122. The second driver circuit 122 and the first driver circuit 121 are located on a same side of the display module 40.

[0204] The second driver circuit 122 includes the third driver sub-circuit 122I and the fourth driver sub-circuit 122II. The third driver sub-circuit 122I includes a plurality of cascaded third shift registers RS3, and an input terminal of a 1 st< -stage third shift register RS3 is configured to receive a third gate start signal STV3 provided by the first display driver integrated circuit 21. The fourth driver sub-circuit 122II includes a plurality of cascaded fourth shift registers RS4, and an input terminal of a 1 st< -stage fourth shift register RS4 is configured to receive a fourth gate start signal STV4 provided by the first display driver integrated circuit 21. The second driver circuit 122 is configured to provide a scanning signal for the active display area AA. The third driver sub-circuit 122I in the second driver circuit 122 is configured to output a gate scanning signal for controlling the first display partition, and the fourth driver sub-circuit 122II in the second driver circuit 122 is configured to output a gate scanning signal for controlling the second display partition. The third driver sub-circuit 122I and the fourth driver sub-circuit 122II may implement independent driving.

[0205] In some embodiments, as shown in FIG. 13B, the display module 40 further includes the fourth driver circuit 124. The fourth driver circuit 124 and the third driver circuit 123 are located on a same side of the display module 40.

[0206] The fourth driver circuit 124 includes the seventh driver sub-circuit 124I and the eighth driver sub-circuit 124II. The seventh driver sub-circuit 124I includes a plurality of cascaded seventh shift registers RS7, and an input terminal of a 1 st< -stage seventh shift register RS7 is configured to receive a third gate start signal STV3 provided by the second display driver integrated circuit 22. The eighth driver sub-circuit 124II includes a plurality of cascaded eighth shift registers RS8, and an input terminal of a 1 st< -stage eighth shift register RS8 is configured to receive an eighth gate start signal STV8 provided by the second display driver integrated circuit 22. The fourth driver circuit 124 is configured to provide a scanning signal for the active display area AA. The seventh driver sub-circuit 124I in the fourth driver circuit 124 is configured to output a gate scanning signal for controlling the first display partition, and the eighth driver sub-circuit 124II in the fourth driver circuit 124 is configured to output a gate scanning signal for controlling the second display partition. The seventh driver sub-circuit 124I and the eighth driver sub-circuit 124II may implement independent driving.

[0207] The second driver circuit 122 and the fourth driver circuit 124 in the display module 40 may also implement independent partition control, to further reduce power consumption of the display module 40.

[0208] In some embodiments, the display module 40 further includes a third display partition, the first driver circuit 121 further includes a ninth driver sub-circuit, and the ninth driver sub-circuit is controlled by a ninth gate start signal provided by the first display driver integrated circuit 21. The third driver circuit 123 further includes a tenth driver sub-circuit, and the tenth driver sub-circuit is controlled by a tenth gate start signal provided by the second display driver integrated circuit 22.

[0209] In some embodiments, the display module 40 further includes one or more second driver circuits or fourth driver circuits.

[0210] FIG. 14 is a diagram of a structure of a display module according to an embodiment of this application.

[0211] In some embodiments, as shown in FIG. 14, the display module 40 includes an EOA, a gate initialization driver circuit on array substrate GOA1, a gate compensation driver circuit on array substrate GOA2, a gate programming driver circuit on array substrate GOA3, and a gate reset driver circuit on array substrate GOA4. A structure of the EOA may be shown in FIG. 4B. Structures of the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 may be shown in FIG. 5. A structure of the pixel circuit 11 in the active display area AA may be shown in FIG. 2.

[0212] For example, the EOA includes the first light emitting driver sub-circuit EOA1 and the second light emitting driver sub-circuit EOA2, the gate initialization driver circuit on array substrate GOA1 includes the first initialization driver sub-circuit GOA1I and the second initialization driver sub-circuit GOA1II, the gate compensation driver circuit on array substrate GOA2 includes the first compensation driver sub-circuit GOA2I and the second compensation driver sub-circuit GOA2II, the gate programming driver circuit on array substrate GOA3 includes the first programming driver sub-circuit GOA3I and the second programming driver sub-circuit GOA3II, and the gate reset driver circuit on array substrate GOA4 includes the first reset driver sub-circuit GOA4I and the second reset driver sub-circuit GOA4II.

[0213] The first light emitting driver sub-circuit EOA1, the first initialization driver sub-circuit GOA1I, the first compensation driver sub-circuit GOA2I, the first programming driver sub-circuit GOA3I, and the first reset driver sub-circuit GOA4I are configured to output a gate scanning signal for controlling a first display partition, and the second light emitting driver sub-circuit EOA2, the second initialization driver sub-circuit GOA1II, the second compensation driver sub-circuit GOA2II, the second programming driver sub-circuit GOA3II, and the second reset driver sub-circuit GOA4II are configured to output a gate scanning signal for controlling a second display partition.

[0214] A gate start signal STVA5 received by the first light emitting driver sub-circuit EOA1, a gate start signal STVA1 received by the first initialization driver sub-circuit GOA1I, a gate start signal STVA2 received by the first compensation driver sub-circuit GOA2I, a gate start signal STVA3 received by the first programming driver sub-circuit GOA3I, and a gate start signal STVA4 received by the first reset driver sub-circuit GOA4I are all provided by the first display driver integrated circuit 21.

[0215] A gate start signal STVB5 received by the second light emitting driver sub-circuit EOA2, a gate start signal STVB1 received by the second initialization driver sub-circuit GOA1II, a gate start signal STVB2 received by the second compensation driver sub-circuit GOA2II, a gate start signal STVB3 received by the second programming driver sub-circuit GOA3II, and a gate start signal STVB4 received by the second reset driver sub-circuit GOA4II are all provided by a second display driver integrated circuit 22.

[0216] In this embodiment of this application, the first driver circuit 121 and the second driver circuit 122 may be any two of the left EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4. The third driver circuit 123 and the fourth driver circuit 124 may be any two of the right EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4.

[0217] In embodiments of this application, a connection manner of the first display driver integrated circuit 21 and the first driver circuit 121 (or the second driver circuit 122) is not limited, and a connection manner of the second display driver integrated circuit 22 and the third driver circuit 123 (or the fourth driver circuit 124) is not limited. For details, refer to the foregoing related descriptions of the connection manner of the signal terminal in the first display driver integrated circuit 21 and the first driver circuit 121 (or the second driver circuit 122) and the connection manner of the signal terminal in the second display driver integrated circuit 22 and the third driver circuit 123 (or the fourth driver circuit 124). Details are not described herein again.

[0218] FIG. 15A to FIG. 15D each are a diagram of a display scenario according to an embodiment of this application.

[0219] Based on the foregoing two types of display modules 40 provided in embodiments of this application, the first driver circuit 121 and the third driver circuit 123 may implement partition control, and the display module 40 may implement a plurality of display scenarios.

[0220] For example, as shown in FIG. 15A, the display module 40 may implement that an image is displayed in a first display partition, and an image is not displayed in a second display partition. A driver sub-circuit for controlling the first display partition receives a start signal transmitted by a gate start signal terminal, and a driver sub-circuit for controlling the second display partition receives a non-start signal transmitted by the gate start signal terminal.

[0221] Alternatively, for example, as shown in FIG. 15B, the display module 40 may implement that an image is not displayed in a first display partition, and an image is displayed in a second display partition. A driver sub-circuit for controlling the first display partition receives a non-start signal transmitted by a gate start signal terminal, and a driver sub-circuit for controlling the second display partition receives a start signal transmitted by the gate start signal terminal.

[0222] Alternatively, for example, as shown in FIG. 15C, the display module 40 may implement that an image is displayed in a first display partition, and an image is displayed in a second display partition. A driver sub-circuit for controlling the first display partition receives a start signal transmitted by a gate start signal terminal, and a driver sub-circuit for controlling the second display partition receives a start signal transmitted by the gate start signal terminal.

[0223] Alternatively, for example, as shown in FIG. 15D, the display module 40 may implement that an image is not displayed in a first display partition, and an image is displayed in a second display partition. A driver sub-circuit for controlling the first display partition receives a non-start signal transmitted by a gate start signal terminal, and a driver sub-circuit for controlling the second display partition receives a non-start signal transmitted by the gate start signal terminal.

[0224] FIG. 16A to FIG. 16E each are a diagram of a form of a display module according to an embodiment of this application.

[0225] The form of the display module 40 for implementing the foregoing partition display effect is not limited in embodiments of this application. For example, the display module 40 is a display module having an outward folding function.

[0226] In a first state, the display module 40 may implement display effects shown in FIG. 15A, FIG. 15B, and FIG. 15D. For example, as shown in FIG. 16A, the display module 40 is an outward folding display module, and the display module 40 is in a folded form (or a hover form). A folded state of the display module may be defined by using a light-emitting side of the display module 40. Alternatively, as shown in FIG. 16B, the display module 40 is in an inward folding hover state. Alternatively, as shown in FIG. 16C, the display module 40 is an "S"-shaped or a "G"-shaped tri-fold display module, and the display module 40 is in a half-folded state. Alternatively, as shown in FIG. 16D, the display module 40 is a "G"-shaped tri-fold display module, and the display module 40 is in a folded state. In these cases, the display module 40 may implement the display effects shown in FIG. 15A, FIG. 15B, and FIG. 15D.

[0227] In a second state, the display module 40 of any structure is in an unfolded state, and the display module 40 may implement display effects shown in FIG. 15C and FIG. 15D.

[0228] In a third state, as shown in FIG. 16E, the display module 40 is an "S"-shaped tri-fold display module, the display module 40 is in a folded state, and the display module 40 may implement display effects shown in FIG. 15A and FIG. 15D.

[0229] After the display module 40 has a partition display function, the display effects shown in FIG. 15A to FIG. 15D can be implemented. Display images of the partitions can be dynamically adjusted, to match actual display areas of the images.

[0230] FIG. 17A to FIG. 17D each are a diagram of a driving time sequence of a display module according to an embodiment of this application.

[0231] This embodiment of this application further provides a driving method of the display module, to implement image display in the foregoing plurality of display scenarios. The display module 40 includes the first driver circuit 121. For example, a first display partition is normally displayed, and a second display partition is not displayed. The driving method of the display module includes the following content.

[0232] As shown in FIG. 17A, in a first time period t1 of an image frame, a 1 st< -stage first shift register RS1 receives a turn-on signal of the first gate start signal terminal 211, an N th< -stage first shift register RS1 receives a signal output by an (N-1) th< -stage first shift register RS1, and each-stage first shift register RS1 outputs a scanning start signal. N is an integer greater than 1. A value of N is not limited in embodiments of this application.

[0233] In some embodiments, simultaneously, each-stage first shift register RS1 receives a first clock signal of a first clock signal terminal CLK1, and a frequency of the first clock signal is a first frequency. The first frequency is, for example, a normal refresh frequency of the first clock signal.

[0234] In some other embodiments, simultaneously, each-stage first shift register RS1 receives a third clock signal of a third clock signal terminal CLK3, and a frequency of the third clock signal is a third frequency. The third frequency is, for example, a normal refresh frequency of the third clock signal.

[0235] In a second time period t2 of the image frame, a 1 st< -stage second shift register RS2 receives a turn-off signal of the second gate start signal terminal 212, an M th< -stage second shift register RS2 receives a signal output by an (M-1) th< -stage second shift register RS2, and each-stage second shift register RS2 outputs a scanning stop signal. M is an integer greater than 1. A value of M is not limited in embodiments of this application.

[0236] In FIG. 17A, only an example in which a first gate start signal STV1 of the first gate start signal terminal 211 is a turn-on signal when the first gate start signal STV1 is a low-level signal, and a second gate start signal STV2 of the second gate start signal terminal 212 is a turn-off signal when the second gate start signal STV2 is a high-level signal is used for description. This can also be the opposite. This is not limited in embodiments of this application.

[0237] For example, as shown in FIG. 17A, in some embodiments, simultaneously, the first clock signal terminal CLK1 coupled to the second shift register RS2 provides a fixed voltage signal. In other words, the signal of the first clock signal terminal CLK1 stops toggling.

[0238] In some other embodiments, simultaneously, the third clock signal terminal CLK3 coupled to the first shift register RS1 provides a fixed voltage signal. In other words, the signal of the third clock signal terminal CLK3 stops toggling.

[0239] In FIG. 17A, only that when signals of the first clock signal terminal CLK1 and the third clock signal terminal CLK3 stop toggling, a high-level signal may be fixedly provided is used as an example for illustration. When signals of the first clock signal terminal CLK1 and the third clock signal terminal CLK3 stop toggling, a low-level signal may also be continuously provided. This is not limited in embodiments of this application.

[0240] Alternatively, for example, as shown in FIG. 17B, in some embodiments, simultaneously, the first clock signal terminal CLK1 coupled to the second shift register RS2 provides a second clock signal, a frequency of the second clock signal is a second frequency, and the second frequency is less than the first frequency. In other words, a frequency of the clock signal provided by the first clock signal terminal CLK1 is reduced. For example, the second frequency is 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or the like of the first frequency.

[0241] In some other embodiments, simultaneously, the third clock signal terminal CLK3 coupled to the first shift register RS1 provides a fourth clock signal, a frequency of the fourth clock signal is a fourth frequency, and the fourth frequency is less than the third frequency. In other words, a frequency of the clock signal provided by the third clock signal terminal CLK3 is reduced. For example, the fourth frequency is 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or the like of the third frequency.

[0242] The first driver circuit 121 may be any one of an EOA, a gate initialization driver circuit on array substrate GOA1, a gate compensation driver circuit on array substrate GOA2, a gate programming driver circuit on array substrate GOA3, and a gate reset driver circuit on array substrate GOA4.

[0243] In some embodiments, the display module 40 further includes the second driver circuit 122. The driving method of the display module includes the following content.

[0244] As shown in FIG. 17C, in the first time period t1, a 1 st< -stage third shift register RS3 receives a turn-on signal of the third gate start signal terminal 213, an O th< -stage third shift register RS3 receives a signal output by an (O-1) th< -stage third shift register RS3, and each-stage third shift register RS3 outputs a scanning start signal. O is an integer greater than 1.

[0245] For example, simultaneously, a second clock signal terminal CLK2 coupled to the third shift register RS3 provides a third clock signal, and the third clock signal is normally toggled.

[0246] For example, simultaneously, a fourth clock signal terminal CLK4 coupled to the third shift register RS3 provides a fourth clock signal, and the fourth clock signal is normally toggled.

[0247] In the second time period t2, a 1 st< -stage fourth shift register RS4 receives a turn-on signal of the fourth gate start signal terminal 214, a P th< -stage fourth shift register receives a signal output by the (P-1) th< -stage fourth shift register RS4, and each-stage fourth shift register RS4 outputs a scanning start signal. P is an integer greater than 1.

[0248] For example, simultaneously, the second clock signal terminal CLK2 coupled to the fourth shift register RS4 provides a third clock signal, and the third clock signal is normally toggled.

[0249] For example, simultaneously, the fourth clock signal terminal CLK4 coupled to the fourth shift register RS4 provides a fourth clock signal, and the fourth clock signal is normally toggled.

[0250] In other words, in a scenario in which the display module 40 performs partial display, the display module 40 may still include the second driver circuit 122 that perform normal driving, but normal driving of the second driver circuit 122 does not affect partial display of the display module 40.

[0251] For example, the second driver circuit 122 is a gate reset driver circuit on array substrate GOA4, and is configured to provide a scanning signal for an anode reset circuit 115 that controls anode reset of the light emitting unit 114. When a partial area does not perform display, the light emitting unit 114 in the non-display area still performs normal reset, to improve a display effect.

[0252] When the display module 40 includes all of the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4, the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 all may implement driving according to the driving method of the first driver circuit 121.

[0253] Alternatively, a part of the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, the gate programming driver circuit on array substrate GOA3, and the gate reset driver circuit on array substrate GOA4 implement driving according to the driving method of the first driver circuit 121. For example, as shown in FIG. 17D, the EOA, the gate initialization driver circuit on array substrate GOA1, the gate compensation driver circuit on array substrate GOA2, and the gate programming driver circuit on array substrate GOA3 implement driving according to the driving method of the first driver circuit 121, and the gate reset driver circuit on array substrate GOA4 implements driving according to the driving method of the second driver circuit 122. In FIG. 17D, in each driver circuit, STVA is used for a gate start signal terminal for controlling a shift register of the first display partition, STVB is used for a gate start signal terminal for controlling a shift register of the second display partition, and CK and CB are a pair of complementary clock signal terminals coupled to the shift register.

[0254] If the first display partition shown in FIG. 15B does not perform display and the second display partition performs display normally, a driving time sequence in the first time period t1 and a driving time sequence in the second time period t2 are exchanged.

[0255] If the first display partition and the second display partition shown in FIG. 15C perform display normally, the driving time sequence in the second time period t2 does not perform processing of turn-off of a gate start signal and no toggling or frequency reducing of a clock signal. The second time period t2 is consistent with the first time period t1, and only normal start is required.

[0256] If the first display partition and the second display partition shown in FIG. 15D do not perform display, the driving time sequence in the first time period t1 also performs processing of turn-off of a gate start signal and no toggling or frequency reducing of a clock signal. The first time period t1 is consistent with the second time period t2, and only normal turn-off is required.

[0257] According to the driving method of the display module provided in embodiments of this application, in a partial display scenario of the display module 40, driving power consumption of the non-display area is reduced by disabling a signal of a clock signal terminal or reducing a frequency of a signal of a clock signal terminal, so that a display power consumption optimization effect can be achieved.

[0258] The foregoing is merely used as an example in which the first shift register RS1 controls display of the first display partition and the second shift register RS2 controls display of the second display partition for illustration. Alternatively, the first shift register RS1 controls display of the second display partition, and the second shift register RS2 controls display of the first display partition. In this case, display states of the first display partition and the second display partition are exchanged.

[0259] In this embodiment of this application, signals of the STVA, the STVB, the CK, and the CB are all provided by the display driver integrated circuit 20 in the display module 40.

[0260] FIG. 18 is a diagram of signal transmission during partition display according to an embodiment of this application.

[0261] In a display process, during partition display, as shown in FIG. 18, the driver controller 30 sends an image to a partition of the display driver integrated circuit 20, and an image register (graphics random access memory, GRAM) of the display driver integrated circuit 20 may support partition image signal refreshing. An image signal transmitted by the driver controller 30 to the display driver integrated circuit 20 includes coordinates related to partial refreshing and a data signal to be refreshed by the display driver integrated circuit 20. For example, the image signal includes coordinates of a scanning start row and a scanning stop row, coordinates of a data write start row and a data write stop row, and the like.

[0262] FIG. 19 is a diagram of driving logic during partition display according to an embodiment of this application.

[0263] For example, as shown in FIG. 19, the display module 40 may first display an image in a first display partition, and not display an image in a second display partition. Then, the driver controller 30 sends a new image signal to the display driver integrated circuit 20. The display driver integrated circuit 20 receives the image signal, outputs, based on the image signal, a gate start signal STV that matches a to-be-displayed image, and transmits the gate start signal STV to each driver circuit, to control whether the first display partition displays the image or the second display partition displays the image. The display driver integrated circuit 20 further outputs a clock signal, to control the driver circuit to output a scanning signal stage by stage. The display driver integrated circuit 20 outputs a data signal, to control a display gray scale of each row and implement image display.

[0264] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subjected to the protection scope of the claims.

Claims

1. A display module, wherein the display module comprises: a first driver circuit, comprising a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, wherein the plurality of cascaded first shift registers are configured to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are configured to output a gate scanning signal for controlling a second display partition; and a first display driver integrated circuit, comprising a first gate start signal terminal and a second gate start signal terminal, wherein the first gate start signal terminal is coupled to an input terminal of a 1st-stage first shift register, and the second gate start signal terminal is coupled to an input terminal of a 1st-stage second shift register; and the first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit.

2. The display module according to claim 1, wherein the first display driver integrated circuit further comprises a first data signal terminal, the first data signal terminal is coupled to a data line, and the first data signal terminal is disposed between the first gate start signal terminal and the second gate start signal terminal.

3. The display module according to claim 2, wherein the display module further comprises a plurality of connection lines, and the plurality of connection lines and the data line are disposed on different layers; and the first gate start signal terminal and the input terminal of the 1st-stage first shift register are coupled through the connection line, and the second gate start signal terminal and the input terminal of the 1st-stage second shift register are coupled through the connection line.

4. The display module according to claim 3, wherein the display module further comprises a shield layer, and the shield layer is located between the data line and the plurality of connection lines.

5. The display module according to claim 3 or 4, wherein in a thickness direction of the display module, the plurality of connection lines are disposed on a side that is of the data line and that faces the first display driver integrated circuit.

6. The display module according to any one of claims 3 to 5, wherein the first driver circuit is located on a first side of the display module, the first display driver integrated circuit is located on a second side of the display module, and the second side intersects the first side; the first gate start signal terminal is close to the first side relative to the second gate start signal terminal; and the connection line coupled to the second gate start signal terminal comprises a first segment, a second segment, and a third segment; and the first segment is coupled to the second gate start signal terminal, the third segment is coupled to the input terminal of the 1st-stage second shift register, the second segment is connected between the first segment and the third segment, the second segment is disposed on a side that is of the first display driver integrated circuit and that is away from an edge of the display module, and the second segment intersects the data line.

7. The display module according to any one of claims 3 to 6, wherein the connection lines used for low-level active signal transmission are disposed adjacently, and connection lines used for high-level active signal transmission are disposed adjacently.

8. The display module according to any one of claims 3 to 7, wherein a spacing between adjacent connection lines is greater than or equal to ΔV / 0.5 µm, and ΔV is an electric potential difference of signals on the adjacent connection lines.

9. The display module according to any one of claims 1 to 8, wherein the display module further comprises a second driver circuit, the second driver circuit and the first driver circuit are located on a same side of the display module, the second driver circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the first display driver integrated circuit further comprises a third gate start signal terminal and a fourth gate start signal terminal, the third gate start signal terminal is coupled to an input terminal of a 1st-stage third shift register, and the fourth gate start signal terminal is coupled to an input terminal of a 1st-stage fourth shift register.

10. The display module according to claim 9, wherein at least one of the first gate start signal terminal, the second gate start signal terminal, the third gate start signal terminal, and the fourth gate start signal terminal is located on a different side of the first display driver integrated circuit.

11. The display module according to any one of claims 1 to 10, wherein the display module further comprises a second display driver integrated circuit, and the second display driver integrated circuit and the first display driver integrated circuit are disposed side by side.

12. The display module according to claim 11, wherein the display module further comprises a third driver circuit, the third driver circuit and the first driver circuit are located on different sides of the display module, the third driver circuit comprises a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers, the plurality of cascaded fifth shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded sixth shift registers are configured to output a gate scanning signal for controlling the second display partition.

13. The display module according to claim 12, wherein the second display driver integrated circuit comprises a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled to an input terminal of a 1st-stage fifth shift register, and the sixth gate start signal terminal is coupled to an input terminal of a 1st-stage sixth shift register.

14. The display module according to claim 13, wherein the second display driver integrated circuit further comprises a second data signal terminal, the second data signal terminal is coupled to the data line, and the second data signal terminal is disposed between the fifth gate start signal terminal and the sixth gate start signal terminal.

15. The display module according to any one of claims 12 to 14, wherein the display module further comprises a fourth driver circuit, the fourth driver circuit and the third driver circuit are located on a same side of the display module, the fourth driver circuit comprises a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers, the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the second display driver integrated circuit further comprises a seventh gate start signal terminal and an eighth gate start signal terminal, the seventh gate start signal terminal is coupled to an input terminal of a 1st-stage seventh shift register, and the eighth gate start signal terminal is coupled to an input terminal of a 1st-stage eighth shift register.

16. The display module according to claim 15, wherein at least one of the fifth gate start signal terminal, the sixth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal is located on a different side of the second display driver integrated circuit.

17. The display module according to any one of claims 12 to 16, wherein the first driver circuit and the third driver circuit are configured to transmit gate scanning signals of a same type or gate scanning signals of different types.

18. The display module according to any one of claims 1 to 17, wherein the display module further comprises a power supply voltage terminal, and the first shift register and the second shift register are coupled to the power supply voltage terminal; or the first display driver integrated circuit further comprises a clock signal terminal, and the first shift register and the second shift register are coupled to the clock signal terminal.

19. A display module, wherein the display module comprises: a first driver circuit, comprising a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, wherein the plurality of cascaded first shift registers are configured to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are configured to output a gate scanning signal for controlling a second display partition; a second driver circuit, located on a different side of the display module from the first driver circuit, wherein the second driver circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers are configured to output a gate scanning signal for controlling the second display partition; a first display driver integrated circuit, configured to: provide a first gate start signal for a 1st-stage first shift register, and provide a second gate start signal for a 1st-stage second shift register; and a second display driver integrated circuit, configured to: provide a third gate start signal for a 1st-stage third shift register, and provide a fourth gate start signal for a 1 st-stage fourth shift register.

20. The display module according to claim 19, wherein the first display driver integrated circuit comprises a first gate start signal terminal and a second gate start signal terminal, the first gate start signal terminal is coupled to an input terminal of the 1st-stage first shift register, the second gate start signal terminal is coupled to an input terminal of the 1st-stage second shift register, and the first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driver integrated circuit.

21. The display module according to claim 19 or 20, wherein the second display driver integrated circuit comprises a third gate start signal terminal and a fourth gate start signal terminal, the third gate start signal terminal is coupled to an input terminal of the 1st-stage third shift register, the fourth gate start signal terminal is coupled to an input terminal of the 1st-stage fourth shift register, and the third gate start signal terminal and the fourth gate start signal terminal are located on different sides of the second display driver integrated circuit.

22. The display module according to any one of claims 19 to 21, wherein the display module further comprises a third driver circuit, the third driver circuit and the first driver circuit are located on a same side of the display module, the third driver circuit comprises a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers, the plurality of cascaded fifth shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded sixth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the first display driver integrated circuit is configured to: provide a fifth gate start signal for a 1st-stage fifth shift register, and provide a sixth gate start signal for a 1st-stage sixth shift register.

23. The display module according to claim 22, wherein the first display driver integrated circuit further comprises a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled to an input terminal of the 1st-stage fifth shift register, and the sixth gate start signal terminal is coupled to an input terminal of the 1st-stage sixth shift register; and at least one of the first gate start signal terminal, the second gate start signal terminal, the fifth gate start signal terminal, and the sixth gate start signal terminal is located on a different side of the first display driver integrated circuit.

24. The display module according to any one of claims 19 to 23, wherein the display module further comprises a fourth driver circuit, the fourth driver circuit and the second driver circuit are located on a same side of the display module, the fourth driver circuit comprises a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers, the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display partition; and the second display driver integrated circuit is configured to: provide a seventh gate start signal for a 1st-stage seventh shift register, and provide an eighth gate start signal for a 1st-stage eighth shift register.

25. The display module according to claim 24, wherein the second display driver integrated circuit further comprises a seventh gate start signal terminal and an eighth gate start signal terminal, the seventh gate start signal terminal is coupled to an input terminal of the 1st-stage seventh shift register, and the eighth gate start signal terminal is coupled to an input terminal of the 1st-stage eighth shift register; and at least one of the third gate start signal terminal, the fourth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal is located on a different side of the second display driver integrated circuit.

26. The display module according to any one of claims 19 to 25, wherein the first driver circuit and the second driver circuit are configured to transmit gate scanning signals of a same type or gate scanning signals of different types.

27. An electronic device, wherein the electronic device comprises a driver controller and a display module, the driver controller is coupled to the display module, and the display module comprises the display module according to any one of claims 1 to 26.

28. The electronic device according to claim 27, wherein the driver controller is configured to output an image signal to display driver integrated circuit, and the image signal comprises coordinate information of a scanning start row and a scanning stop row and a data signal.

29. A driving method of a display module, wherein the display module comprises a first driver circuit and a first display driver integrated circuit, and the first driver circuit comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers; and the driving method of the display module comprises: in a first time period of an image frame, receiving, by a 1st-stage first shift register, a turn-on signal of a first gate start signal terminal, receiving, by an Nth-stage first shift register, a signal of an output terminal of an (N-1)th-stage first shift register, receiving, by each-stage first shift register, a first clock signal of a first clock signal terminal, and outputting, by each-stage first shift register, a scanning start signal, wherein N is an integer greater than 1, and a frequency of the first clock signal is a first frequency; and in a second time period of the image frame, receiving, by a 1st-stage second shift register, a turn-off signal of a second gate start signal terminal, and receiving, by an Mth-stage second shift register, a signal of an output terminal of an (M-1)th-stage second shift register, receiving, by each-stage second shift register, a second clock signal or a fixed voltage signal of the first clock signal terminal, and outputting, by each-stage second shift register, a scanning stop signal, wherein M is an integer greater than 1, a frequency of the second clock signal is a second frequency, and the second frequency is less than the first frequency.

30. The driving method according to claim 29, wherein the display module further comprises a second driver circuit, and the second driver circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers; in the first time period, a 1st-stage third shift register receives a turn-on signal of a third gate start signal terminal, an Oth-stage third shift register receives a signal of an output terminal of an (O-1)th-stage third shift register, each-stage third shift register receives a third clock signal of a second clock signal terminal, each-stage third shift register outputs a scanning start signal, and O is an integer greater than 1; and in the second time period, a 1st-stage fourth shift register receives a turn-on signal of a fourth gate start signal terminal, a Pth-stage fourth shift register receives a signal of an output terminal of a (P-1)th-stage fourth shift register, each-stage fourth shift register receives the third clock signal of the second clock signal terminal, each-stage fourth shift register outputs a scanning start signal, and P is an integer greater than 1.

Images