Statistical channel analysis with feedback burst error

Abstract

This application discloses a computing system configured to measure a step response of a channel in an electronic device, determine a feedback voltage that a decision feedback equalizer adds to the channel in response to detecting inter-symbol interference in received symbols, and predict a signal integrity of the channel based, at least in part, on the step response of the channel and the feedback voltage. The computing system can utilize the predicted signal integrity to determine a probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous, and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

Description

2022P16141 STATISTICAL CHANNEL ANALYSIS WITH FEEDBACK BURST ERROR TECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to statistical analysis of transmission channels within an electronic circuits and systems including feedback burst error. BACKGROUND

[0002] Modern digital electronic circuits and systems can transmit or convey sequences of binary values, commonly referred to as bit sequences or digital signals. These bit sequences can be conveyed as voltage waveforms, wherein the voltage amplitude for a given time period or bit, corresponds to a binary logic value at that same time period. Accordingly, a digital signal can appear as a voltage waveform in the signal lines and transmission channels of electronic systems. As a digital signal is transmitted through a circuit, various effects may cause the signal to degrade, often to the point that errors occur. Errors within a digital signal may be quantified by a bit error rate. In many instances, the bit error rate of a circuit or signal pathway is defined as the ratio of incorrectly received bits to the total number of bits transmitted. An important consideration in digital electronic design is fidelity, or the quality with which a signal is conveyed. The fidelity of an electronic system is often referred to as signal integrity. As designers have increased the speed of operation and manufacturing has scaled the physical dimensions of today’s modern circuits, signal integrity has become increasingly more important. Currently, virtually all electronic circuits are designed with signal integrity in mind.2022P16141

[0003] One common type of link included in electronic systems—a SERDES (SERializer / DESerializer) link—often operates on a marginal speed considering channel loss and impairments and thus tends to use equalization schemes, such as a Decision Feedback Equalizer (DFE), to improve a signal to noise ratio at a receiver end. The DFE employed in the electronic system detects symbols received over the SERDES link and provides a feedback signal onto the SERDES link to eliminate inter-symbol interference associated with already detected symbols. If the DFE incorrectly detects a symbol, the resulting feedback signal introduced on the SERDES link would not eliminate the interference and increase a probability of future symbol detection error, often called a DFE burst error.

[0004] Electronic designers often employ techniques to predict link behavior in presence of DFE burst errors, for example, to find symbol error ratio (SER) or bit error ratio (BER), and also to select a Forward Error Correction (FEC) scheme for a given channel. For example, these designers can utilize simulation tools to perform time-domain simulation on the channel to identify link behavior problems before the device is manufactured. Time-domain simulation, however, tends to be complicated and computationally expensive, and sufficiently time intensive as to render it impractical. These complications and impracticalities often lead the designers to attempt to use statistical simulation methods instead of time-domain simulation, to determine probability distributions that describe eye- diagram, allowing predictions of the bit error rate BER as low as 1e-15 to 1e-20 bits and beyond, with minimal computational resources. Most conventional statistical simulations, however, cannot consider feedback from the DFE, tend to be super-linear in complexity with respect to a length of received symbol groups, and often incorporate many simplifications that can render their results unreliable.2022P16141 SUMMARY

[0005] This application discloses a computing system to include a channel analysis tool to perform statistical simulation on a channel capable of experiencing a burst errors stemming from a decision feedback equalizer. The computing system can measure a step response of a channel in an electronic device, determine a correct feedback voltage and an incorrect feedback voltage that a decision feedback equalizer can add to the channel in response to detecting inter-symbol interference in received symbols, and predict a signal integrity of the channel based, at least in part, on the step response of the channel and the correct feedback voltage. The computing system can utilize the predicted signal integrity to determine a probability that an incorrect feedback voltage added by the decision feedback equalizer to the channel, and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the correct feedback voltage, the incorrect feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous. The computing system can generate an eye diagram or a develop a bit error rate corresponding to the signal integrity of the channel capable of experiencing the burst error stemming from the decision feedback equalizer. Embodiments of statistical simulation on a channel capable of experiencing the burst error stemming from the decision feedback equalizer are described in greater detail below. DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments of the invention.2022P16141

[0007] Figures 3A and 3B illustrate example eye diagrams, showing signal integrity of a circuit pathway.

[0008] Figure 4 illustrates an example electrical system.

[0009] Figure 5 illustrates an example channel analysis tool to perform statistical simulation on a channel capable of experiencing decision feedback equalizer burst error according to various embodiments of the invention.

[0010] Figure 6 illustrates a flowchart showing an example process for implementing statistical simulation on the channel with decision feedback equalizer burst error in Figure 5.

[0011] Figure 7 illustrates an example step response of a channel being evaluated with statistical simulation according to various examples of the invention.

[0012] Figures 8A and 8B illustrate an example eye diagram and an example vertical cross- section of the eye diagram, which show signal integrity of a circuit pathway, built by statistical simulation of the channel according to various examples of the invention.

[0013] Figure 9 illustrates an example symbol state transition structure utilized with statistical simulation of the channel capable of experiencing burst error from a decision feedback equalizer according to various examples of the invention.

[0014] Figure 10 illustrates an example vertical cross-section of an eye diagram to identify symbol overlap error due to decision feedback equalization according to various examples of the invention. DETAILED DESCRIPTION2022P16141 Illustrative Operating Environment

[0015] The execution of various applications may be implemented using computer- executable software instructions executed by one or more programmable computing devices. Because these embodiments of the invention may be implemented using software instructions, the components and operation of a generic programmable computer system on which various embodiments of the invention may be employed will first be described.

[0016] Various examples of the invention may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0017] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 115, a removable magnetic disk drive 117, an optical disk drive 119, or a flash memory card 121. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more2022P16141 output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0018] With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0019] It should be appreciated that the computer 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments of the invention may be implemented using one or more computing devices that include the components of the computer 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments of the2022P16141 invention may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0020] With some implementations of the invention, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments of the invention. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those of ordinary skill in the art, a computing engine contains logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0021] Each processor core 201 is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 201. With some processor cores 201, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 communicate through the interconnect 207 with an input / output interface 209 and a memory controller 211. The input / output interface 209 provides a communication interface between the processor unit 201 and the2022P16141 bus 113. Similarly, the memory controller 211 controls the exchange of information between the processor unit 201 and the system memory 107. With some implementations of the invention, the processor units 201 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201.

[0022] It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments of the invention.

[0023] Detailed herein are methods, apparatuses, and systems for analyzing circuit channels, typically channels designed to carry high-speed signals. The disclosed methods, apparatus, and systems may be used, for example, in a printed circuit board or an integrated circuit design flow to analyze signal integrity. The disclosed methods, apparatus, and systems should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed methods, apparatus, systems, and equivalents thereof, alone and in various combinations and sub-combinations with one another. The present disclosure is not limited to any specific aspect or feature, or combination thereof, nor do the disclosed methods, apparatus, and systems require that any one or more specific advantages be present or problems be solved.

[0024] Although the operations of some of the disclosed methods, apparatus, and systems are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example,2022P16141 operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the figures may not show the various ways in which the disclosed methods, apparatus, and systems can be used in conjunction with other methods, apparatus, and systems. Additionally, the description sometimes uses terms like “generate” and “determine” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms may vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0025] Various implementations of the invention may be employed to analyze a channel to determine signal integrity. For example, traces, vias or other interconnects between a driver and a receiver in a printed circuit board layout may be evaluated. The signal integrity of a digital circuit may, in some examples, be presented as a bit error rate, which can correspond to a measure of degradation a bit sequence undergoes as a result of its being transmitted through the digital circuit. In addition to the bit error rate, the signal integrity of a channel is often analyzed by creating an “eye” diagram. Eye diagrams can be created through a variety of techniques, such as by repeatedly sampling a digital signal on the channel, for example, with signal measurement tools, such as an oscilloscope, and overlaying the various samples onto each other, by simulating transmission of the digital signals on the channel and overlaying simulated digital signals, or by performing statistical simulation of the channel.

[0026] Figure 3A illustrates an eye diagram 301, while Figure 3B illustrates an eye diagram 303. As can be seen in Figure 3A and Figure 3B, the eye diagram 301 is undistorted, while the eye diagram 303 contains distortions. An eye diagram may appear distorted, such as the eye diagram 303, due to various electronic effects. For example,2022P16141 noise, timing issues, overshoot or undershoot will often manifest themselves as amplitude and phase errors within an eye diagram. The amount of distortion is often quantified by an opening in the eye diagram. Figure 3A illustrates an opening 305 and Figure 3B illustrates an opening 307. With various implementations of the invention, a bit sequence will be selected to produce to the largest eye opening in an eye diagram. With other implementations of the invention, a bit sequence will be selected to produce the smallest opening in an eye diagram.

[0027] Various implementations of the invention analyze the signal integrity of a channel within an electronic device. For example, a printed circuit board, application-specific integrated circuits (ASICs), including mixed-signal application-specific integrated circuits, systems-on-a-chip (SoCs), programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), fiber-optic transmission networks, optical channels, such as an optical channel between two components of an integrated circuit. Furthermore, techniques can also be employed to evaluate the integrity of power carrying channels. As stated above, a physical electronic device may be employed in various implementations of the invention. However, with various other implementations of the invention, a simulated or statistically- simulated instance of the electronic device can be employed.

[0028] Any of the methods or techniques described herein can be performed using software that comprises computer executable instructions for causing a computer to perform the methods or techniques stored on one or more computer readable memory device. Such software can comprise, for example, an electronic design automation (EDA) tool, such as a signal integrity tool. The Hyperlynx tool available from Mentor Graphics Corporation of Wilsonville, Oregon is one example of a suitable software tool. With various implementations of the invention, the software may be executed on a single computer. With2022P16141 other implementations, the software may be executed upon a networked computer system. For example, via the Internet, a wide-area network, a local-area network, a client-server network, or other such network. For clarity, only certain selected aspects of the software based implementations are described. Other details that are well known in the art are omitted. For example, it should be understood that the disclosed technology is not limited to any specific computer language, program, or computer and that the disclosed technology can be implemented using any commercially available computer. An illustrative computing environment is described, but it is to be understood that this environment is not limiting and although all possible computing environments are not described, those of skill in the art are still capable of practicing the invention based upon the following disclosure.

[0029] Various implementations of the invention may use circuit design information. For example, printed circuit board layout information, such as a .HYP file, device models such as IBIS models, netlists, GDSII descriptions, or HDL descriptions such as Verilog or VHDL description, or other similar layout or device design description stored on one or more computer readable memory device. In certain implementations, the circuits to be simulated are instantiated as SPICE or Eldo models for simulation. For presentation purposes, the present disclosure sometimes refers to circuit components by their physical counterparts, such as drivers, channels, signals, and other such terms. It should be understood, however, that any such reference not only includes the physical components but also representations of such circuit components and signals on the components as may be used in a computer implemented signal integrity analysis environment. Electrical System Including a Channel2022P16141

[0030] Figure 4 illustrates an exemplary electrical system 401. As can be seen in Figure 4, the electrical system 401 includes a driver 403, a channel 405, and a buffer or receiver 407. With various implementations of the invention, the driver 403 can be a non-linear driver. In general, an electrical component can exhibit non-linear behavior when the sum of its responses does not equal the sum of its inputs. More particularly, in a linear system the response to the bit sequence ‘010’ summed with the response to the bit sequence ‘001’ would equal the response to the bit sequence ‘011’. The principle of linearity is often explained mathematically as follows. Given a function F whereinY 1 ^ F( X 1 )andY 2 ^ F( X 2 ), ifXs^ X1^ X2then Ys^ F( Xs) ^ Y1^ Y2. In a non-linear system, the response to the bit sequence ‘011’ may not equal the summed responses to the bit sequences ‘010’ and ‘001’. Employing the same function F, and Y1, Y2, and Xsdefined above, in a non-linear systemYs^ F( Xs) ^ Y1^ Y2.

[0031] As can be seen in Figure 4, the driver 403 includes an input 409 for receiving a digital signal, ord ( t ). Additionally, the driver 403 and the buffer 407 are connected by the channel 405. When a digital signal d ( t ) is placed on the driver 403 via the input 409, a response or voltage waveform, or V ( t ) is seen at the channel 405. The voltage waveformV ( t )is often referred to as the driver voltage, or the transmitter voltage. The response of the driver 403 is measurable at a point 411 in the electrical system 401. Additionally, the response of the channel, or W ( t ) , often referred to as the waveform at the receiver, or the receiver voltage, and is measurable at a point 413 in the electrical system 401. Furthermore, as can be seen in Figure 4, the driver 403, the channel 405, and the buffer 407 are typically connected to a plurality of ground terminals 415.2022P16141

[0032] As indicated above, the illustrative systems represented in Figure 4, as well as other electrical systems may be actual physical devices. Accordingly, the signals, voltages and currents present in the system may be measured for example, by an oscilloscope. However, more often, various implementations of the invention will be practiced in conjunction with a simulated instance of the electrical system. Accordingly, the signals, voltages, currents and other values present in the system may be simulated as well.

[0033] Additionally, those of skill in the art will appreciate that various tools exists for describing an electrical system mathematically. More particularly, various mathematical tools exist for describing the properties of an electrical system in the time domain and the frequency domain. The equations described herein may be further modified and converted using the available tools, for example, the Laplace or Fourier transforms. Such conversions and modification of the described methods and exemplary implementations of the invention are within the scope of this disclosure. Statistical Channel Analysis with Feedback Burst Error

[0034] Figure 5 illustrates an example channel analysis tool 500 to perform statistical simulation on a channel capable of experiencing decision feedback equalizer burst error according to various embodiments of the invention. Figure 6 illustrates a flowchart showing an example process for implementing statistical simulation on the channel with decision feedback equalizer burst error in Figure 5. Referring to Figures 5 and 6, in a block 601, a computing system implementing the channel analysis tool 500 can identify at least one step response or transition edge for the channel of an electronic device. The step response or transition edge can correspond to a reaction of the channel to a voltage signal transition, for example, from low-to-high or high-to-low edge through the channel, the step2022P16141 response or transition edge can electrically characterize the channel. Although the example channel analysis described below corresponds to two-level signaling, in some embodiments, the channel analysis tool 500 can implement similar channel analysis with any arbitrary signaling level, for example, Pulse Amplitude Modulation with Four Levels (PAM-4) signaling, or the like.

[0035] The channel analysis tool 500 can include a step response system 510 to identify the step response of the channel, in some embodiments, by performing a circuit simulation of the channel described in a circuit design 501, e.g., using analytical models of the channel, SPICE models, IBIS models, transistor-level models, ideal voltage source models, or other such models. In other implementations, the step response can measured from a test chip or other physical chip implementing the channel under consideration. In some embodiments, for example, when the channel is driven by a non-linear transmitter or driver, the channel may have multiple transition edges or step responses, the shape of which can be based on bits having been transmitted over the channel prior to the bit transition. The number of these previously transmitted bits that can affect the shape of the transition edges or step responses can be called a pre-history or history depth.

[0036] Figure 7 illustrates an example step response of a channel being evaluated with statistical simulation according to various examples of the invention. Referring to Figure 7, an x-y coordinate graph has a channel voltage 701 corresponding to the y-axis and time 702 corresponding to the x-axis. The graph shows a step response 711 of the channel over time 702, which, in this instance, corresponds to a channel voltage transition from a low-value to a high-value.2022P16141

[0037] As will be described below in greater detail, the statistical simulation process can identify sample points in the step response 711 of the channel. In some embodiments, these sample points can be periodic corresponding to a bit interval 713-1 to 713-3 of transmissions on the channel. The initial sample can be taken after an initial offset 712, for example, which can have a value set between zero to a duration of a bit interval. In some embodiments, a high-to-low step response can be the inverse or negative of the low-to- high step response 711 shown in Figure 7.

[0038] Referring back to Figures 5 and 6, the channel analysis tool 500 can include statistical simulation system 520 to predict a signal integrity of the channel, for example, by determining a bit error rate 503 or building a statistical eye diagram 504 through statistical simulation. In some embodiments, the statistical simulation system 520 can build the eye statistical diagram 504 by separately determining probability density functions for multiple different vertical cross-sections of the eye diagram. These probability density functions can represent a channel voltage transition from low-to-high and from high-to low. When implementing signaling with more than two levels, the probability density functions can represent channel voltage transitions between each of the voltage levels.

[0039] Figures 8A and 8B illustrate an example eye diagram 800 and an example vertical cross-section of the eye diagram 810, which show signal integrity of a circuit pathway, built by statistical simulation of the channel according to various examples of the invention. Referring to Figures 8A and 8B, an eye diagram 800 has a channel voltage 801 corresponding to the y-axis and a value interval 802 corresponding to the x-axis. The value interval 802 can correspond to a period of time that a value can be transmitted over the channel. The graph shows signals 804 received over the channel overlapped based on their2022P16141 corresponding value interval 802. The signals 804 in the eye diagram 800 can identify both their voltage at various times during the value interval 802, but, in some embodiments, also be presented as a density or frequency of their occurrence at a specific time-voltage intersection, for example, by their color in the eye diagram 800.

[0040] An offset 803 is also shown in Figure 8A to illustrate how the offset 803 corresponds to the vertical cross-section in the eye diagram 810. The vertical cross-section of the eye diagram 810 can have the channel voltage 801 corresponding to the x-axis and a density 811 corresponding to the y-axis. The density 811 can correspond to a frequency or probability signals 804 received over the channel at different channel voltages 801. A magnitude of the received signals 804 in the vertical cross-section of the eye diagram 810 along the y-axis can be represented in the eye diagram of Figure 8A as a color of the received signals 804. As will be discussed below in greater detail, the statistical simulation system 520 can determine probability density functions for the vertical cross-section 810 in the value interval 802 associated with the offset 803, which will identify signal voltages at the vertical cross-section 810 of the value interval 802 and a density or frequency of their occurrence in the different points in the vertical cross-section of the value interval 802.

[0041] Referring back to Figures 5 and 6, the statistical simulation system 520 can include a decision feedback equalizer error system 522 to receive decision feedback equalizer taps 502, which can identify a number of symbols received over a channel capable of being impacted by inter-symbol interference. As discussed above, the symbols received over the channel can have any number of signaling levels. In some examples, a symbol received over the channel can have a tail voltage level capable of altering a voltage value of one or more subsequently received symbols. A decision feedback equalizer at the receiving end of the channel can detect the reception of a symbol having the capability to cause inter-symbol2022P16141 interference, and introduce a voltage onto the channel that can eliminate or reduce the inter-symbol interference. In some cases, the decision feedback equalizer can correctly eliminate or reduce the inter-symbol interference, while in other cases the decision feedback equalizer can incorrectly add feedback voltage, which could exacerbate the inter- symbol interference. The decision feedback equalizer error system 522 can set a probability that the decision feedback equalizer in introduces correct or incorrect feedback voltage on the channel, or an error probability. For example, in a block 602, the computing system implementing the channel analysis tool 500 can set error probabilities for the decision feedback equalizer taps 502. In some embodiments, the decision feedback equalizer error system 522 can initially set the error probability to zero, meaning the statistical simulation system 520 assumes that the decision feedback equalizer makes no errors in introducing feedback voltage on the channel. In some implementations, the decision feedback equalizer error system 522 can build a symbol error probability matrix populated with the error probabilities. The symbol error probability matrix can be arranged in a row-column format, with the columns corresponding to a number of signal levels received and the rows corresponding to a number of signal levels transmitted. In these implementations, the decision feedback equalizer error system 522 can initially set the error probabilities in the symbol error probability matrix to one for the entries of the matrix having common signal levels and to zero for the other entries.

[0042] The statistical simulation system 520 can include an offset system 524 to set an offset for a unit interval on the channel. The offset for the unit interval can correspond to a vertical cross-section of the eye diagram for the channel. For example, in a block 603, the computing system implementing the channel analysis tool 500 can set the offset of the unit interval on the channel. The statistical simulation system 520 can utilize the offset to2022P16141 determine various sample points in the at least one step response identified by the step response system 510. In some embodiments, the sample points can be located in increments of one unit interval, such that each sample point corresponds to a same vertical cross-section of the unit interval for the channel.

[0043] The statistical simulation system 520 can identify sample points in the step response of the channel. In some embodiments, these sample points can be periodic corresponding to unit intervals of transmissions on the channel, which starts after the initial offset. In some embodiments, the statistical simulation system 520 can utilize transmit jitter distributions at each sample point of the step response to determine possible voltages at each sample point in the presence of transmit jitter, which can be called vertical distributions. These vertical distributions can be as probability density functions that identify potential voltages at each sample point as well as a probability or weight associated with each of the potential voltages of the step response at a corresponding sample point.

[0044] The statistical simulation system 520 can include a transition state system 526 to build a symbol state transition structure that describe symbol transitions received from the channel based, at least in part, on vertical voltage distributions associated with the symbol transitions and feedback voltages introduced by the decision feedback equalizer. In some examples, the symbol state transition structure can be implemented by the computing system or in a programmable hardware device.

[0045] Figure 9 illustrates an example symbol transition structure 900 utilized with statistical simulation of a channel capable of experiencing burst error from a decision feedback equalizer according to various examples of the invention. Referring to Figure 9,2022P16141 the symbol state transition structure 900 describes serially received symbols as a set including symbol cells 920-924. In this example implementation of the symbol state transition structure 900, the symbol cell 920 can correspond to a main cursor symbol and the symbol cells 921-924 can correspond to post-cursor symbols. Although not shown, the symbol transition structure 900 can include one or more symbol cells corresponding to pre- cursor symbols or previously received symbols (to the right of the main cursor), and can include one or more additional post-cursor symbol cells (to the left of the symbol cell 924). The main cursor symbol can correspond to the currently received symbol over the channel, while the post-cursor symbols can correspond to subsequently received symbols. The post- cursor symbols corresponding to the symbol cells 921-924 can correspond to symbols whose voltage level can be impacted by erroneous feedback voltage added to the channel by the decision feedback equalizer to eliminate or reduce a voltage tail associated with the main cursor symbol. The number of post-cursor symbols potentially impacted by the feedback voltage added to the channel by the decision feedback equalizer can correspond to a number decision feedback equalizer taps 905 associated with the channel.

[0046] Each symbol cell 920-924 in the symbol transition structure 900 can have a state- based structure, as shown with reference to symbol cell 921. The symbol cell 921 can include a first stage having multiple accumulators 911 and 912 to receive probability density functions 901 and 902, respectively, that correspond to a high-state and low-state of voltage levels on the channel. The symbol transition structure 900 includes a second stage having multiple accumulators 913 and 914 to accumulate versions of the probability density functions 901 and 902 from the first stage after having gone through one or more modifications 915-918.2022P16141

[0047] In some embodiments, the modification 915 performed in the probability density function output from the accumulator 911 can be a scaling of the probability density function based on the probability that a symbol transition from a high-state to another high-state on the channel along with a convolution of the probability density function with an incorrect feedback voltage weighted by the probability that the decision feedback voltage errored in the feedback voltage added to the channel. The modification 916 performed in the probability density function output from the accumulator 912 can be a scaling of the probability density function based on the probability that a symbol transition from a low- state to another low-state on the channel along with a convolution of the probability density function with an incorrect feedback voltage weighted by the probability that the decision feedback voltage errored in the feedback voltage added to the channel. In some embodiments, the modification 917 performed in the probability density function output from the accumulator 911 can be a scaling of the probability density function based on the probability that a symbol transition from a high-state to a low-state on the channel along with a convolution of the probability density function with both a correct feedback voltage and an incorrect feedback voltage complementarily weighted by the probability that the decision feedback voltage errored in the feedback voltage added to the channel. In some embodiments, the modification 918 performed in the probability density function output from the accumulator 912 can be a scaling of the probability density function based on the probability that a symbol transition from a low-state to a high-state on the channel along with a convolution of the probability density function with both a correct feedback voltage and an incorrect feedback voltage complementarily weighted by the probability that the decision feedback voltage errored in the feedback voltage added to the channel. The accumulator 913 can receive the probability density functions, as modified by 915 and 918, and aggregate them to output a probability density function 903. The accumulator 914 can2022P16141 receive the probability density functions, as modified by 916 and 917, and aggregate them to output a probability density function 904.

[0048] In some implementations, the accumulators 911 and 912 can utilize the error probabilities in the symbol error probability matrix to perform the convolutions of their respective probability density functions with incorrect feedback voltages weighted by the probability that the decision feedback voltage errored in the feedback voltages added to the channel. Since the error probability matrix can be arranged in a row-column format, the error probabilities at the respective intersections in the matrix can be applied to the accumulators associated with the corresponding rows and corresponding columns. After the convolutions the accumulators 911 and 912 can output the convolved probability density functions towards the accumulators 913 and 914 with the structure of the symbol cell 921 performing any other modifications during the transition to the accumulators 913 and 914. Although Figure 9 shows a symbol transition structure 900 utilized with statistical simulation of a channel with two-level signaling, in some embodiments, the symbol transition structure 900 can include additional accumulators and modifications to accommodate statistical simulation for any number of signal levels.

[0049] Referring back to Figures 5 and 6, the statistical simulation system 520 can include a signal integrity system 528 to build a statistical eye diagram 504 utilizing the symbol state transition structure generated by the transition state system 526. For example, in a block 604, the computing system implementing the channel analysis tool 500 can aggregate probability density functions and feedback voltages from a decision feedback equalizer for each of the points on the step response corresponding to the offset.2022P16141

[0050] The signal integrity system 528 can initially load the first stage of the bit state transition structure with a Dirac delta functions—having a voltage level corresponding to a high level in state containers associated with a ‘1’ symbol, and having a voltage level corresponding to a low level in state containers associated with a ‘0’ symbol. The signal integrity system 528 can transition the Dirac delta functions from the state containers in the first stage of the symbol state transition structure to the second stage of the symbol state transition structure, while performing modifications corresponding to the last sample point (for example, sample 710-Q in Figure 7) along the at least one step response. The signal integrity system 528 can move resulting probability density functions in the state containers in second stage into the corresponding state containers in the first stage and perform another transition between state containers, this time with the second to last sample point. The signal integrity system 526 can continue this process until all of the sample points (for example, sample 710-1 in Figure 7) have had their vertical distributions and added feedback voltages selectively convolved with probability density functions.

[0051] The signal integrity system 528 can aggregate the state containers for the low-state and the high-state for all of the state containers, which corresponds to a specific vertical cross-section of the statistical eye diagram 504. When the signaling includes more than two levels, the signal integrity system 528 can aggregate the state containers for each of the different state levels, which correspond to a specific vertical cross-section of the statistical eye diagram 504. In a block 605, the computing system implementing the channel analysis tool 500 can determine whether an additional offset of the unit interval on the channel can be evaluated, for example, by incrementing offset previously set in block 603. If so, execution returns to block 603, where the computing system implementing the channel analysis tool 500 can set a new offset of the unit interval on the channel. In some2022P16141 embodiments, the offset system 522 in the statistical simulation system 520 can select the new offset of the unit interval on the channel. Since each offset corresponds to a different vertical cross-section of the eye diagram shown in Figure 8A, in some embodiments, the statistical simulation system 520 can increment the offset, for example, by a preset value, across the unit interval in order to realize aggregate probability density functions for the entire eye diagram—one cross-section at a time. In other embodiments, the statistical simulation system 520 can analyze multiple offsets or cross-sections of the eye-diagram in parallel.

[0052] For example, if, in the block 605, the computing system implementing the channel analysis tool 500 determines to not evaluate an additional offset of the unit interval on the channel, execution continues to a block 606, where the computing system implementing the channel analysis tool 500 can determine error probabilities associated with feedback voltages added by a decision feedback equalizer using the aggregate probability density functions. In some embodiments, the channel analysis tool 500 can include a burst error system 530 to analyze a vertical cross-section of the aggregate probability density functions to determine a probability that the decision feedback equalizer errored in adding feedback voltage onto the channel for that symbol.

[0053] The burst error system 530 can include a symbol overlap system 532 to identify where the high-state and low-state of the aggregate probability density functions overlap and then determine the area of the overlap, which can correspond to the probability that the decision feedback equalizer errored in adding feedback voltage onto the channel for that symbol. When the channel has signaling with more than two levels, the symbol overlap system 532 can identify when the different signal levels overlap and determine the areas of the overlap for each of the signal levels. The burst error system 530 also can include an2022P16141 error probability system 534 to determine error probabilities associated with feedback voltages added by a decision feedback equalizer from the area of the overlap in the high- state and low-state of the aggregate probability density functions or form the multiple areas of overlap when analyzing more than two levels of signaling. In some embodiments, a ratio of the area of the overlap to the total density of the aggregate probability density functions can correspond to the error probabilities. In some implementations, the burst error system 530 can modify the symbol error probability matrix with the determined error probabilities.

[0054] Figure 10 illustrates an example vertical cross-section of an eye diagram 1000 to identify symbol overlap error due to decision feedback equalization according to various examples of the invention. Referring to Figure 10, the vertical cross-section of the eye diagram 1000 can have the channel voltage 1001 corresponding to the x-axis and a density 1011 corresponding to the y-axis. The density 1011 can correspond to a frequency or probability signals 1004 received over the channel at different channel voltages 1001. As discussed above, a statistical simulation system can determine probability density functions for the vertical cross-section 1000 in a value interval associated with an offset, which can identify signal voltages at the vertical cross-section 1000 of the value interval and a density or frequency of their occurrence in the different points in the vertical cross-section of the value interval. In this example, the received signals 1004 can at least partially overlap in their channel voltage 1001, which can indicate an erroneous feedback voltage was added to the channel by a decision feedback equalizer. The area associated with the overlap, or the symbol overlap error 1005 can be ascertained and a ratio of the symbol overlap error 1005 and the total density 1011 of the received signals 1004 can be used to identify one or more probabilities that the decision feedback equalizer added an erroneous feedback voltage to the channel.2022P16141

[0055] Referring back to Figures 5 and 6, in the block 607, the computing system implementing the channel analysis tool 500 can determine whether an error probability convergence has occurred. In some embodiments, the burst error system 530 can compare the determined error probabilities to the error probabilities set in the block 602 to determine whether convergence has occurred. When the burst error system 530 determines convergence has not occurred, for example, when the determined error probabilities to the error probabilities set in the block 602 differ by an amount above a predetermined threshold level, such as a level of machine precision of the computing system, execution returns to the block 602, where the channel analysis tool 500 sets the error probabilities of a DFE tap to the error probabilities determined by the burst error system 530. The blocks 602-606 can be iteratively performed with changing error probabilities in the symbol error probability matrix and in the DFE taps based on a prior run through the blocks until in the block 607, the burst error system 530 determines convergence has occurred, for example, when the determined error probabilities to the error probabilities set in the block 602 are the same or fall below the predetermined threshold level.

[0056] Execution can then proceed to a block 608, where the computing system implementing the channel analysis tool 500 can determine a signal integrity of the channel from the aggregate probability density functions for the different offsets. The signal integrity prediction system 528 also can generate a bit error rate 503 based on the statistical eye diagram 504, for example, by determining a ratio of signals in the statistical eye diagram 504 fall within a preset location towards the center of the eye in the statistical eye diagram 504 to those signals that fall outside of the preset location. This ratio can describe a number of transmission errors are predicted to occur given the capability of burst error due to erroneous feedback voltage from a decision feedback equalizer.2022P16141

[0057] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0058] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0059] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise2022P16141 moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.

[0060] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0061] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion2022P16141

[0062] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to certain processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of processes.

[0063] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0064] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

2022P16141 CLAIMS 1. A method comprising: measuring, by a computing system, a step response of a channel in an electronic device; determining, by the computing system, a feedback voltage that a decision feedback equalizer adds to the channel in response to detecting inter-symbol interference in received symbols; predicting, by the computing system, a signal integrity of the channel based, at least in part, on the step response of the channel and the feedback voltage; utilizing, by the computing system, the predicted signal integrity to determine a probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; and determining, by the computing system, the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

2. The method of claim 1, wherein determining the signal integrity of the channel further comprising at least one of generating a bit error rate for the channel or developing an eye diagram representing the signal integrity of the channel.

3. The method of claim 1, further comprising determining, by the computing system, an erroneous feedback voltage that the decision feedback equalizer adds to the channel, wherein determining the signal integrity of the channel is based, at least in part, on the2022P16141 step response of the channel, the feedback voltage, the erroneous feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

4. The method of claim 1, wherein utilizing the predicted signal integrity to determine the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous further comprises identifying symbols erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous corresponds to a ratio of the symbols erroneously received to a total number of symbols received.

5. The method of claim 1, further comprising: iteratively re-predicting, by the computing system, the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; iteratively utilizing, by the computing system, the re-predicted signal integrity to determine different probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous.

6. The method of claim 5, further comprising determining when there is a convergence of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous, wherein determining the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback2022P16141 voltage, and at least one of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

7. The method of claim 1, further comprising setting, by the computing system, an offset for a bit interval on the channel, wherein predicting the signal integrity of the channel further comprising aggregating probability density functions for multiple points in the step response of the channel corresponding to the offset.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: measure a step response of a channel in an electronic device; determine a feedback voltage that a decision feedback equalizer adds to the channel in response to detecting inter-symbol interference in received symbols; predict a signal integrity of the channel based, at least in part, on the step response of the channel and the feedback voltage; utilize the predicted signal integrity to determine a probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the signal2022P16141 integrity of the channel further comprising at least one of generating a bit error rate for the channel or developing an eye diagram representing the signal integrity of the channel.

10. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: determine an erroneous feedback voltage that the decision feedback equalizer adds to the channel; and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, the erroneous feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

11. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to utilize the predicted signal integrity by identifying symbols erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous corresponds to a ratio of the symbols erroneously received to a total number of symbols received.

12. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: iteratively re-predict the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; and2022P16141 iteratively utilize the re-predicted signal integrity to determine different probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous.

13. The system of claim 12, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: determine when there is a convergence of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous; and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and at least one of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: measuring a step response of a channel in an electronic device; determining a feedback voltage that a decision feedback equalizer adds to the channel in response to detecting inter-symbol interference in received symbols; predicting a signal integrity of the channel based, at least in part, on the step response of the channel and the feedback voltage; utilizing the predicted signal integrity to determine a probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; and2022P16141 determining the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

15. The apparatus of claim 14, wherein determining the signal integrity of the channel further comprising at least one of generating a bit error rate for the channel or developing an eye diagram representing the signal integrity of the channel.

16. The apparatus of claim 14, wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising determining an erroneous feedback voltage that the decision feedback equalizer adds to the channel, wherein determining the signal integrity of the channel is based, at least in part, on the step response of the channel, the feedback voltage, the erroneous feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

17. The apparatus of claim 14, wherein utilizing the predicted signal integrity to determine the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous further comprises identifying symbols erroneously received in the predicted signal integrity, wherein the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous corresponds to a ratio of the symbols erroneously received to a total number of symbols received.

18. The apparatus of claim 14, wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising:2022P16141 iteratively re-predicting the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous; iteratively utilizing the re-predicted signal integrity to determine different probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous.

19. The apparatus of claim 18, wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising determining when there is a convergence of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel were erroneous, wherein determining the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and at least one of the determined probabilities that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.

20. The apparatus of claim 14, wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising setting an offset for a bit interval on the channel, wherein predicting the signal integrity of the channel further comprising aggregating probability density functions for multiple points in the step response of the channel corresponding to the offset.

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