Phase-change memory

Abstract

Phase-Change Memory This description relates to a method for manufacturing a memory cell comprising: a) forming a stack (16, 18, 22, 24, 26) comprising a first layer (16) of a phase-change material and a second conductive layer (18); b) forming a first mask (20) on the stack covering only the location of the memory cell; c) etching the portions of the stack not covered by the first mask (20). Figure for the abstract: Fig. 5

Description

Title of the invention: Phase-change memory technical field

[0001] This description relates generally to electronic devices and more particularly to phase-change memories and their manufacturing process. Previous technique

[0002] Phase-change materials are materials that can switch, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electrical resistance of an amorphous material is significantly greater than the electrical resistance of a crystalline material, this phenomenon can be useful for defining two memory states, for example 0 and 1, differentiated by the resistance measured across the phase-change material.

[0003] Memory cells are preferably arranged in a memory in the form of a matrix comprising rows, associated for example with word rows, and columns, associated for example with bit rows. Summary of the invention

[0004] An embodiment provides a method for manufacturing a memory cell comprising: a) the formation of a stack comprising a first layer of a phase change material and a second conductive layer; b) the formation of a first mask on the stack covering only the location of the memory cell; c) the etching of the parts of the stack not covered by the first mask.

[0005] According to one embodiment, step a) includes the formation of at least one third electrically insulating layer between the second layer and the first mask.

[0006] According to one embodiment, step c) does not engrave the first layer and another layer of another material at the same time.

[0007] According to one embodiment, the process includes the formation of a resistive element in contact with the first layer.

[0008] According to one embodiment, step b) comprises: - depositing a fourth layer of the material of the first mask onto the stack; - forming a second mask extending in a first direction and covering the location of the memory cell; - etching the parts of the fourth layer not covered by the second mask; - forming a third mask extending in a second direction and covering the location of the memory cell; - the engraving of the parts of the fourth layer not covered by the third mask.

[0009] According to one embodiment, the etching process used for the engravings of the fourth layer etches the material of the fourth layer at least twenty times faster than the material of the layer located below the fourth layer.

[0010] According to one embodiment, the first mask is made of titanium nitride.

[0011] According to one embodiment, the first layer is made of a germanium alloy, of antimony and tellurium.

[0012] According to one embodiment, the process includes the manufacture of a memory cell matrix, each cell being manufactured by a process as defined above.

[0013] According to one embodiment, a first mask is formed on the location of each memory cell, and in which step c) is carried out simultaneously for all cells.

[0014] According to one embodiment, each first mask is common to a row of cells of the matrix, and in which each second mask is common to a column of cells of the matrix.

[0015] According to one embodiment, the process includes depositing at least one electrically insulating layer on the cells of the matrix.

[0016] According to one embodiment, the process includes the formation of electrically conductive vias traversing the insulating layer so as to reach the second layer.

[0017] According to one embodiment, the process includes the formation of a conductive band extending over the second layers of the cells of a row or column of the matrix. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1] illustrates a step in an embodiment of a process for manufacturing a phase-change memory cell;

[0020] [Fig.2] illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell;

[0021] [Fig.3] illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell;

[0022] [Fig.4] illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell;

[0023] [Fig.5] illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell;

[0024] [Fig.6] illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell;

[0025] [Fig.7] illustrates another step of an embodiment of a process for manufacturing a phase-change memory;

[0026] [Fig.8] illustrates another step of an embodiment of a process for manufacturing a phase-change memory;

[0027] [Fig.9] illustrates an alternative step to the step in [Fig.8]; and

[0028] [Fig. 10] illustrates an alternative step to the steps in Figures 8 and 9. Description of the implementation methods

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0034] Figures 1 to 8 illustrate steps, preferably successive, of an embodiment of a process for manufacturing a phase-change memory.

[0035] Fig. 1 illustrates a step in an embodiment of a process for manufacturing a phase-change memory cell.

[0036] This manufacturing step includes the formation of a conductive via 10. This step includes the fabrication of a resistive element 12, resting on the conductive via 10. The resistive element 12 preferably has an L-shape, a horizontal portion resting on the via 10 and a vertical portion extending substantially perpendicularly to the horizontal part. The via 10 and the resistive element 12 are surrounded by an electrically insulating layer 14. An upper face of the vertical part of the resistive element 12 is flush with an upper face of the layer 14. The layer 14 comprises, for example, a stack of several electrically insulating layers, for example, made of different electrically insulating materials.

[0037] Layer 14, and the upper face of the vertical part of the resistive element, are covered by a stack of layers comprising: - a layer 16 in a phase change material; - a conductive layer 18; - a hard mask for engraving 20.

[0038] Layer 16 is a flat layer covering the upper face of the vertical part of the resistive element 12 and preferably completely covering layer 14. Layer 16 is thus in contact with layer 14. Layer 16 is preferably made of a GST alloy of germanium, antimony, and tellurium. Layer 18 is, for example, made of titanium nitride.

[0039] The mask 20 is a layer preferably extending over the entire layer 18. The mask 20 is for example made of a metal or a metal alloy, for example titanium nitride.

[0040] The mask 20 and the layer 18 are, for example, separated by one or more layers, for example insulating layers, forming an etching mask. In the example of [Fig. 1], the mask 20 and the layer 18 are separated by: - an electrically insulating layer 22, for example made of silicon nitride; - a layer 24, for example made of an electrically insulating material, for example amorphous carbon; and - a layer 26 in an anti-reflective material for lithography, for example an electrically insulating material, for example silicon oxide.

[0041] Fig. 2 illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell.

[0042] During this step, a band 28 is formed on the mask 20. The band 28 corresponds for example to a photolithography mask.

[0043] The strip 28 covers the location of the memory cell. The strip 28 extends in a first direction, for example, along a row of the memory cell matrix. The strip 28 covers, for example, the locations of several cells, for example, all the cells in the row of the matrix. In a direction orthogonal to the direction of the row, corresponding, for example, to the direction of a column of the matrix, the strip 28 covers the location of only one memory cell.

[0044] Fig. 3 illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell.

[0045] During this step, the portions of the mask 20 not covered by the strip 28 are etched. The etching is preferably a selective etching of the material of the mask 20 with respect to the material of the layer located beneath the mask 20, for example, the material of layer 26. Preferably, the etching process etches the material of layer 20 at least 20 times faster than the material of layer 26. Preferably, only the mask 20 is etched during this step. Preferably, layers 18, 22, 24, and 26 are not etched during this step. Layer 16 is not etched during this step.

[0046] Strip 28 is then removed.

[0047] Figure 4 illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell.

[0048] During this step a band 30 is formed on the mask 20. The band 30 corresponds for example to a photolithography mask.

[0049] The strip 30 covers the location of the memory cell. The strip 30 extends in a second direction, for example substantially orthogonal to the first direction, for example along a column of the memory cell matrix. The strip 30 covers, for example, the locations of several cells, for example, all the cells in the column of the matrix. In a direction orthogonal to the column direction, corresponding, for example, to the direction of a row of the matrix, the strip 30 covers the location of only one memory cell.

[0050] Band 30 covers the portion of mask 20 located at the memory cell location. Preferably, band 30 covers only the portion of mask 20 located at the memory cell location. Band 30 covers, for example, a portion of layer 26.

[0051] Fig. 5 illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell.

[0052] During this step, the portions of the mask 20 not covered by the strip 30 are etched. The etching is preferably a selective etching of the material of the mask 20 as opposed to the material of the layer located beneath the mask 20, for example, the material of layer 26. Preferably, only the mask 20 is etched during this step. Preferably, layers 18, 22, 24, and 26 are not etched during this step. Layer 16 is not etched during this step.

[0053] Strip 30 is then removed.

[0054] The mask 20 obtained as a result of the step in [Fig.5] is preferably a rectangular parallelepiped.

[0055] The steps in Figures 2 to 5 allow the mask 20 to be formed, covering the location of the memory cell. The mask 20 is thus opposite the location of the memory cell, preferably only opposite the location of the memory cell.

[0056] As an alternative, the steps in Figures 2 to 5 can be replaced by the formation of a mask replacing masks 28 and 30, and covering only the location of the memory cell and the etching of the mask layer 20. The formation of mask 20 then comprises only a single etching of the mask layer 20.

[0057] Figure 6 illustrates another step of an embodiment of a process for manufacturing a phase-change memory cell.

[0058] This step includes etching around mask 20 layers 26, 18 and 16, as well as the layers separating layer 18 and mask 20, here layers 22, 24 and 26. This step may also include partial etching of layer 14 around the memory cell.

[0059] The stacking layers, i.e., layers 16, 18, 22, 24, and 26, are planar layers extending in a planar manner around the memory cell, for example, throughout the entire location of the memory cell array. In particular, layer 16, made of phase-change material, extends continuously between the different memory cells of the array. Thus, during the stacking etching step, i.e., the step in [Fig. 6], the materials of the different layers are not etched simultaneously. In particular, the material of layer 16 is not etched at the same time as the material of the other stacking layers.

[0060] At least some of the layers above layer 18 are also removed. In the example of [Fig. 6], layers 24, 26 and 20 are removed from the memory cell location.

[0061] One could have chosen to form a memory cell by a process comprising: - a first etching of the stack, including layer 16 in phase change material, so as to separate the rows of the matrix from each other; - a deposit of one or more electrically insulating layers, particularly between the matrix lines; and - a second etching of the stack, including layer 16 in phase-change material, so as to separate the matrix columns from each other. Layer 16 would then be etched simultaneously with the electrically insulating material formed at layer 16 between the rows. The simultaneous etching of the phase-change material and another material, in particular a material Electrically insulating, it can alter the phase change material and decrease the efficiency of the memory cell.

[0062] Fig. 7 illustrates another step of an embodiment of a process for manufacturing a phase-change memory.

[0063] This step includes the conformal deposition of a passivation layer 31. The layer 31 is, for example, made of an electrically insulating material, for example, silicon nitride. The passivation layer 31 covers the walls of layers 14, 16, 18, and 22 exposed by the etching in the step of [Fig. 6]. The layer 31 covers the upper surface of the memory cell, here the upper surface of layer 22.

[0064] This step further comprises the formation of a layer 32 represented, in transparency, by dotted lines. The layer 32 is made of an electrically insulating material, for example silicon oxide.

[0065] Figures 8 to 10 illustrate three distinct embodiments of a manufacturing step of an upper contact, or electrode, of the cell.

[0066] Figure 8 illustrates another step in an embodiment of a process for manufacturing a phase-change memory. More specifically, Figure 8 represents the formation of a conductive via 34. This step is preferably carried out after the step in Figure 7.

[0067] This step includes forming a cavity extending from the upper face of layer 32 to layer 18 and filling this cavity with a conductive material, for example, a metal. The cavity is etched through layer 32, the passivation layer 31, and layer 22 so as to reach the conductive layer 18. The vias 34 of the cells in the same row or column of the cell matrix are, for example, connected by a conductive strip (not shown), resting, for example, on the upper face of layer 32.

[0068] Figure 9 illustrates an alternative step to the step in Figure 8. In other words, this step is carried out instead of the step in Figure 8, following the step in Figure 7. More specifically, Figure 9 represents the formation of a conductive band 36 connecting the cells of the same row or column.

[0069] During this step, a cavity is etched in layer 32 and in layers 31 and 22 of the cells connected by the strip 36. The cavity therefore extends from the upper face of layer 32 to layer 18. The cavity thus passes through layer 22 and layer 31 in the memory cell. Between the memory cells, the cavity extends into layer 31. The cavity is then filled with a conductive material, for example a metal.

[0070] Figure 10 illustrates an alternative step to the steps in Figures 8 and 9. In other words, this step is performed instead of the step in Figure 8 or 9, following the step in the [Fig.7]. More specifically, [Fig. 10] represents the formation of a conductive band 38 connecting the cells of the same row or column of the memory matrix.

[0071] During this step, layers 32, 31, and 22 are etched in a planar manner until the upper surface of layer 18 is exposed. A planar layer of a conductive material, for example, a metal, is then formed on the structure obtained after etching. This layer thus covers the upper surface of layer 18 and the upper surfaces of layers 31 and 32 surrounding the memory cell. The conductive layer is then etched so as to maintain a band extending, in the first direction, over the layers 18 of several cells. In a second direction, the band 38 extends, for example, over the entire layer 18 and partially over the upper surface of layer 31.

[0072] Embodiments are described for the fabrication of a single memory cell. The methods can be used to simultaneously fabricate a plurality of cells, for example, a memory cell array. The method then comprises forming a mask 20 covering each location of a memory cell and simultaneously etching the stack of layers around the memory cell locations, i.e., etching the parts of the stack not covered by the masks 20.

[0073] One advantage of the described embodiments is that the phase change material layer is not etched at the same time as another material.

[0074] Another advantage of the described embodiments is that the described processes include an etching step and layer deposition steps compared to known processes.

[0075] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0076] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing a memory cell comprising: a) forming a stack (16, 18, 22, 24, 26) comprising a first layer (16) of a phase-change material and a second conductive layer (18); b) forming a first mask (20) on the stack covering only the location of the memory cell; c) etching the parts of the stack not covered by the first mask (20), wherein step b) comprises: - deposition of a fourth layer (20) of the material of the first mask on the stack; - formation of a second mask (28) extending in a first direction and covering the location of the memory cell; - etching the parts of the fourth layer (20) not covered by the second mask (28); - the formation of a third mask (30) extending in a second direction and covering the location of the memory cell;- the engraving of the parts of the fourth layer (20) not covered by the third mask..;

2. A method according to claim 1, wherein step a) comprises the formation of at least one third electrically insulating layer (22, 24, 26) between the second layer (18) and the first mask (20).

3. A method according to claim 1 or 2, wherein step c) does not simultaneously engrave the first layer (16) and another layer of another material.

4. A method according to any one of claims 1 to 3, comprising the formation of a resistive element (12) in contact with the first layer (16).

5. A method according to any one of claims 1 to 4, wherein the etching method used for the etchings of the fourth layer etches the material of the fourth layer at least twenty times faster than the material of the layer (28) located below the fourth layer (20).

6. A method according to any one of claims 1 to 5, wherein the first mask (20) is made of titanium nitride.

7. A method according to any one of claims 1 to 6, wherein the first layer (16) is made of an alloy of germanium, antimony and tellurium.

8. A method for manufacturing a memory, comprising manufacturing a memory cell array, each cell being manufactured by a method according to any one of claims 1 to 7.

9. A method according to claim 8, wherein a first mask (20) is formed on the location of each memory cell, and wherein step c) is performed simultaneously for all cells.

10. A method according to claim 8 or 9 in a connection with claim 5 or 6, wherein each first mask (28) is common to a row of cells of the matrix, and wherein each second mask (30) is common to a column of cells of the matrix.

11. A method according to any one of claims 8 to 10, comprising the deposition of at least one electrically insulating layer (31, 32) on the matrix cells.

12. A method according to any one of claims 8 to 11, comprising the formation of electrically conductive vias (34) traversing the insulating layer (31, 32) so as to reach the second layer.

13. A method according to any one of claims 8 to 11, comprising the formation of a conductive band (36, 38) extending over the second layers of the cells of a row or column of the matrix.