PWM CONTROL DEVICE AND METHOD FOR IMPROVING THE DYNAMIC FALSE CONTOUR OF A SCREEN

Abstract

The invention relates to a display device that is capable of improving a dynamic false contour. The display device can command a change of one order of a plurality of pulses whose widths are modulated during a defined transmission time in a frame, or a division of pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of image data among the pulses into two or more sub-pulses, and output the sub-pulses.

Description

Title of the invention: PWM control device and method for improving the dynamic false outline of a screen. (Referring to a related application)

[0001] This application claims priority over and the benefit of Korean patent applications No. 2021-0083174 filed on June 25, 2021, and 2021-0097558 filed on July 26, 2021, the descriptions of which are incorporated in full by reference below. Scope of the invention

[0002] The present invention relates to a display device and a method for controlling the display device. Description of prior art

[0003] The contents described below merely provide contextual information for embodiments described below and do not necessarily constitute the prior art.

[0004] An active matrix display maintains a light-emitting state while information from all other pixels is updated. In the case of a digital process associated with a display comprising memory in the pixel, data relating to the light to be exited from the pixel is stored for a row with a horizontal frequency (horizontal time), and the brightness is controlled by a pulse-width modulation (PWM) process. Generally, three or four light-emitting elements (for example, light-emitting diodes (LEDs)) are contained within a pixel, and each light-emitting element is called a sub-pixel.

[0005] PWM signals for controlling the brightness of subpixels are a combination of signals whose pulse widths are modulated, the difference between the pulse widths of each signal being equal to the power of two. Generally, the PWM signals enter the subpixels sequentially such that a signal corresponding to the most significant bit (MSB) of the image data exits first and a pulsed signal corresponding to the least significant bit (LSB) of the image data exits last. Furthermore, the number of pulsed signals (MSB, MSB-1, MSB-2, ..., LSB) is determined according to the number of bits in the image data.

[0006] For example, when the image data is 6 bits, a total of 6 PWM pulse signals PWM 5, PWM 4, PWM 3, PWM 2, PWM 1 and PWM 0 can be present. When a dimming level is 32, the LED emits light while the signal The LED emits no light during the remaining time (PWM 4 to PWM 0) when the pulses correspond to the MSB between PWM 5 and PWM 0. Conversely, in the case of a 31 dimming setting, the LED emits no light while the pulsed signal corresponding to the MSB between PWM 5 and PWM 0 causes the LED to emit light during the remaining time (PWM 4 to PWM 0).

[0007] When the subpixels corresponding to gradation 32 and gradation 31 are adjacent to each other, a problem arises because the difference in the light emission time of the LED relative to the gradations of the two subpixels is large, and consequently, a display distortion occurs, which is perceived by a viewer as a gradation corresponding to 0 or 64, rather than an intermediate gradation. In other words, a false dynamic contour can occur. Summary of the invention

[0008] This description relates to the supply of a display device capable of improving a dynamic false contour and a method for controlling it.

[0009] The present memorandum is not limited to the aforementioned problems, and other problems not mentioned will become clear to the person skilled in the art from the description that follows.

[0010] One aspect of this description provides a display device comprising: a display panel comprising a plurality of pixel drive circuits; a data drive circuit configured to output signals relating to the drive of a plurality of electroluminescent elements included in each pixel drive circuit through a plurality of data lines connected to each pixel drive circuit; a clock drive circuit configured to output a plurality of pulses whose widths are modulated for a defined transmission time in a frame to the pixel drive circuits through a plurality of clock lines connected to each pixel drive circuit;and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, wherein the control device includes a data output portion configured to change the order of image data outputs from the data drive circuit, and a scheduler configured to change the order of pulses outputs from the clock drive circuit.

[0011] According to one embodiment of the present document, the data output section can command the data attack circuit to output image data bits in order starting from the most significant bit in a first group of frames and output image data bits in order starting from the least significant bit in a second group of frames, and the scheduler can command the clock drive circuit to output pulses in order starting from a pulse with the longest width in the first group of frames and to output pulses in order starting from a pulse with the shortest width in the second group of frames.

[0012] According to another embodiment of the present document, the data output part can control the data attack circuit so that a pixel attack circuit included in a first row of groups outputs image data bits in order starting from the most significant bit in a first group of frames and outputs image data bits in order starting from the least significant bit in a second group of frames, and that a pixel attack circuit included in a second row of groups outputs image data bits in order starting from the least significant bit in the first group of frames and outputs image data bits in order starting from the most significant bit in the second group of frames,and the scheduler can control the clock drive circuit so that the pixel drive circuit in the first row of groups outputs pulses in order starting from the pulse with the longest width in the first group of frames and outputs pulses in order starting from the pulse with the shortest width in the second group of frames, and that the pixel drive circuit in the second row of groups outputs pulses in order starting from the pulse with the shortest width in the first group of frames and outputs pulses in order starting from the pulse with the longest width in the second group of frames.

[0013] Another aspect of the present description provides a method for controlling a display device comprising a data drive circuit configured to output signals relating to the drive of electroluminescent elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, wherein the control device repeatedly performs (a) the control of the data drive circuit to output bits of image data in an order starting from the most significant bit and the control of the clock drive circuit to output pulses in an order starting from a pulse having the longest width in the case of a first group of frames,and (b) the command of the data drive circuit to output bits of image data in order starting from the least significant bit and the command of the clock drive circuit to output pulses in order starting from a pulse with the shortest width in the case of a second group of frames.

[0014] Yet another aspect of the present description provides a method for controlling a display device comprising a data drive circuit configured to output signals relating to the drive of electroluminescent elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, wherein the control device repeatedly performs (a) the control of the data drive circuit so that a pixel drive circuit included in a first row of groups outputs bits of the image data in an order starting from the most significant bit,and that a pixel drive circuit included in a second row of groups outputs image data bits in order starting from the least significant bit, and the clock drive circuit is controlled such that the pixel drive circuit included in the first row of groups outputs pulses in order starting from the pulse with the longest width, and the pixel drive circuit included in the second row of groups outputs pulses in order starting from the pulse with the shortest width in the case of a first group of frames, and (b) the data drive circuit is controlled such that the pixel drive circuit included in the first row of groups outputs image data bits in order starting from the least significant bit, and the pixel drive circuit included in the second row of groups outputs image data bits in order starting from the most significant bit,and the control of the clock drive circuit such that the pixel drive circuit in the first row of groups outputs pulses in order starting from the pulse with the shortest width, and that the pixel drive circuit in the second row of groups outputs pulses in order starting from the pulse with the longest width in the case of a second group of frames.

[0015] Yet another aspect of the present description provides a display apparatus comprising: a display panel including a plurality of pixel drive circuits; a data drive circuit configured to output image data relating to the drive of a plurality of electroluminescent elements included in each pixel drive circuit via a plurality of data lines connected to each pixel drive circuit; a clock drive circuit configured to output a plurality of pulses whose widths corresponding to the image data are modulated for a defined transmission time in a frame to the pixel drive circuits via a plurality of clock lines connected to each pixel drive circuit; and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, wherein the control device commands the clock drive circuit to divide pulses corresponding to the most significant bit (MSB) and second significant bit (MSB-1) of the image data from the pulses output from the clock drive circuit into two or more sub-pulses and output the sub-pulses.

[0016] According to one embodiment of the present document, the control device can control the clock drive circuit to output alternately the sub-pulse corresponding to the most significant bit (MSB) of the image data and the sub-pulse corresponding to the second significant bit (MSB-1) of the image data.

[0017] According to one embodiment of the present memorandum, the number of sub-pulses corresponding to the most significant bit (MSB) of the image data can be the same as the number of sub-pulses corresponding to the second significant bit (MSB-1) of the image data.

[0018] According to another embodiment of the present memorandum, the number of sub-pulses corresponding to the most significant bit (MSB) of the image data can be one more than the number of sub-pulses corresponding to the second significant bit (MSB-1) of the image data.

[0019] In this case, the control device can command the clock drive circuit to output the sub-pulses corresponding to the second significant bit (MSB-1) of the image data between the sub-pulses corresponding to the most significant bit (MSB) of the image data.

[0020] Yet another aspect of the present description provides a method for controlling a display device comprising a data drive circuit configured to output image data relating to the drive of electroluminescent elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, wherein the control device repeatedly performs (a) the division of pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of the image data from the pulses output from the clock drive circuit into two or more sub-pulses,and (b) controlling the clock drive circuit to alternately output the subpulse corresponding to the most significant bit (MSB) of the image data and the subpulse corresponding to the second significant bit (MSB-1) of the image data.

[0021] According to one embodiment of the present document, operation (a) can be the division into the same number of sub-pulses corresponding to the most significant bit (MSB) of image data and subpulses corresponding to the second significant bit (MSB-1) of image data.

[0022] According to another embodiment of the present document, operation (a) may be the division which results in the number of sub-pulses corresponding to the most significant bit (MSB) of the image data being one more than the number of sub-pulses corresponding to the second significant bit (MSB-1) of the image data.

[0023] In this case, operation (b) can be the command of the clock drive circuit to output the sub-pulses corresponding to the second significant bit (MSB-1) of the image data between the sub-pulses corresponding to the most significant bit (MSB) of the image data.

[0024] The method for controlling a display device according to this document can be implemented in the form of a computer program recorded in a computer-readable recording medium written to carry out the operations of the control method in a computer.

[0025] Other specific details of this description are included in the detailed descriptions and drawings. Brief description of the drawings

[0026] The above-mentioned objects, features and advantages of this description and others will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof given by way of reference to the accompanying drawings, in which:

[0027] [Fig. 1] illustrates a display device comprising a plurality of pixel circuits according to the present memorandum;

[0028] [Fig.2] is an embodiment in which an output order is changed between frames;

[0029] [Fig.3] is an embodiment in which an output order is changed between arranged in the frame;

[0030] [Fig.4] is an output diagram of a conventional PWM signal, and

[0031] [Fig.5] is an output diagram of a PWM signal according to the present memory; and

[0032] [Fig.6] is a flowchart of a method for controlling a display device according to this memorandum.

[0033] DETAILED DESCRIPTION OF EMBODIMENTS GIVEN BY WAY OF EXAMPLE

[0034] Advantages and features of the present design, which are described in this document, and a method for achieving them, will appear by reference to embodiments which are described in detail later, together with the accompanying drawings. However, this document is not limited to these embodiments. of implementation which will be described later, but can be implemented in various different forms, and only the present embodiments allow the description of this document to be complete, and the embodiments are provided only in such a way that the description of this document is complete, and to fully inform the person skilled in the art to whom this document belongs (hereinafter referred to as "the person skilled in the art"), and the scope of this document is defined solely by the scope of the claims.

[0035] The terms used in this document are not intended to limit its scope but to describe embodiments. In this document, the singular form is intended to include the plural form unless the context clearly indicates otherwise. The terms "include" and / or "comprising" as used below do not preclude the presence or addition of one or more components other than those mentioned above.

[0036] The same reference numbers refer to identical or similar components throughout this document, and the term "and / or" encompasses each component and all combinations of one or more of the aforementioned components. Although "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, a first component mentioned below may be a second component for the purposes of this description.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in this document may be used with meanings that can be commonly understood by a person skilled in the art. Furthermore, terms defined in a commonly used dictionary should not be interpreted ideally or excessively, unless otherwise defined.

[0038] A case in which an element is indicated as being "connected to" or "coupled to" another element includes both a case in which the element is directly connected to or coupled to another element and a case in which the element is connected to or coupled to another element with yet another element between them. Furthermore, the case in which the element is "directly connected to" or "directly coupled to" another element indicates a case in which there is no other element between them.

[0039] Below, embodiments of this description will be described in detail with reference to the attached drawings.

[0040] Fig. 1 illustrates a display device comprising a plurality of pixel circuits according to the present memorandum.

[0041] With reference to [Fig. 1], a display device 100 according to this document may comprise a display panel 110, a scanning drive circuit 120, a data attack circuit 130, a clock attack circuit 140 and a control device 150.

[0042] The display panel 110 may comprise a plurality of pixels PX according to this document. The plurality of pixels PX, numbering M x N (where M and N are natural numbers), may be arranged in a matrix form. However, a pattern in which the plurality of pixels are arranged may be arranged in various patterns according to embodiments, such as a zigzag pattern and others.

[0043] The display panel 110 can be used as one of several liquid crystal displays (LCDs), light-emitting diode displays (LEDs), organic LED displays (OLEDs), active-matrix OLED displays (AMOLEDs), electrochromic displays (ECDs), digital micromirror devices (DMDs), actuated micromirror devices (AMDs), lattice light modulators (LLMs), plasma display panels (PDPs), electroluminescent displays (ELDs), and vacuum fluorescent displays (VFDs), and can be used as other types of flat panel or flexible displays. In this document, the LED display panel will be described as an example.

[0044] Each PX pixel can comprise a plurality of light-emitting elements. The light-emitting element can be a light-emitting diode (LED). The light-emitting diode can be a micro-LED with a size of 80 sq m or less. A PX pixel can output various colors through a plurality of light-emitting elements of different colors. For example, a PX pixel can comprise light-emitting elements composed of red, green, and blue. In another example, when a white light-emitting element can be further included, the white light-emitting element can replace any of the red, green, and blue light-emitting elements. Each light-emitting element included in a PX pixel is called a "sub-pixel."

[0045] Each pixel PX may include a pixel driver circuit that drives a plurality of sub-pixels. In the pixel driver circuit, the sub-pixel may be turned on or off by a signal output from the scan driver circuit 120 and / or the data driver circuit 130. The pixel driver circuit may include at least one thin-film transistor, at least one capacitor, etc. The pixel driver circuit may be implemented in a stacked structure on a semiconductor wafer.

[0046] The display panel 110 may include scan lines SLi to SLM arranged in a row direction, clock lines GCi to GCM arranged in the row direction, and data lines DLi to DLN arranged in a column direction. The PX pixels may be located at intersections of the lines SLi to SLM scan lines and DLi to DLN data lines. Each PX pixel can be connected to any SLK scan line and any DLK data line. SLi to SLM scan lines can be connected to the scan driver circuit 120, DLi to DLN data lines can be connected to the data driver circuit 130, and GCi to GCM clock lines can be connected to the clock driver circuit 140.

[0047] The scan driver circuit 120 can attack pixels connected to any of the scan lines S1 to SLM. Preferably, the scan driver circuit 120 can sequentially select the scan lines S1 to SLM. For example, pixels connected to a first scan line S1 can be attacked during a first scan attack period, and pixels connected to a second scan line SL2 can be attacked during a second scan attack period. The operation of the scan driver circuit 120 according to this specification will be described in more detail later.

[0048] The data attack circuit 130 can output image data to each pixel via the DLi to DLN data lines. The image data can be output in the form of a signal relating to a gradation to be expressed by the pixels during a frame. Although a data line is connected to a plurality of pixels in a vertical direction, a signal relating to the image data can only enter the pixels connected to the scan line selected by the scan attack circuit 120. The operation of the data attack circuit 130 according to this specification will be described in more detail later.

[0049] The clock driver circuit 140 can output a clock signal to the pixels via the GCi to GCM clock lines. The clock signal can be composed of a plurality of signals whose pulse widths are modulated (pulse width modulator, PWM), and the number of PWM signals (MSB, MSB-1, MSB-2, ..., LSB) can be determined according to the number of image data bits. The clock driver circuit 140 can output the clock signal for a defined transmission time within a frame.

[0050] The control device 150 can output control signals to perform the operations of the scan drive circuit 120, the data drive circuit 130 and the clock drive circuit 140. The control device 150 can output control signals corresponding to image data corresponding to an image frame to the scan drive circuit 120, the data drive circuit 130 and the clock drive circuit 140.

[0051] The control device 150 according to this memorandum may include a data output part 151 and a planner 152.

[0052] The data output portion 151 can change the order of the image data output from the data drive circuit 130. A change in the order of the image data relates to a change as to whether the output is in the order [MSB, MSB-1, MSB-2, LSB+1 and LSB], or in the order [LSB, LSB+1, LSB+2, MSB-1 and MSB] when the n-bit image data is output.

[0053] The planner 152 can change the order of the pulses output from the clock drive circuit 140. A change in the pulse order relates to a change in the output pulse widths corresponding respectively to the n bits of the image data in an order [2n, 2n l, 2"2,..., 21 and 2°], or in an order [2°, 21, 22,... 2"1 cl 2n],

[0054] According to one embodiment of the present document, an output order can be changed between frames.

[0055] In this case, the data output part 151 can command the data attack circuit 130 to output the image data bits in an order starting from the most significant bit in a first group of frames and output the image data bits in an order starting from the least significant bit in a second group of frames.

[0056] In addition, the planner 152 can command the clock drive circuit 140 to output pulses in order from a pulse having the longest width in the first group of frames and output pulses in order from a pulse having the shortest width in the second group of frames.

[0057] Figure [Fig.2] represents an embodiment in which the output order is changed between frames.

[0058] With reference to [Fig. 2], when the image data is 6 bits, the output order of PWM signals can be verified. In the embodiment shown in [Fig. 2], the first group of frames is represented as an odd frame, and the second group of frames is represented as an even frame. In the odd frame, a signal corresponding to the MSB is output first, and a signal corresponding to the LSB is output last. In the even frame, the signal corresponding to the LSB is output first, and the signal corresponding to the MSB is output last.

[0059] According to another embodiment of the present document, the output order is changed between frames, and an output order can also be changed between rows in the frame.

[0060] In this case, the data output part 151 can control the data drive circuit 130 so that a pixel drive circuit included in a first row of groups can output the image data bits in order from the most significant bit in the first group of frames and output the image data bits in order starting from the least significant bit in the second group of frames, and that a pixel attack circuit included in a second row of groups can output the image data bits in order starting from the least significant bit in the first group of frames and output the image data bits in order starting from the most significant bit in the second group of frames.

[0061] In addition, the planner 152 can control the clock drive circuit 140 so that the pixel drive circuit included in the first row of groups can output the pulses in order from the pulse having the longest width in the first group of frames and output the pulses in order from the pulse having the shortest width in the second group of frames, and the pixel drive circuit included in the second row of groups can output the pulses in order from the pulse having the shortest width in the first group of frames and output the pulses in order from the pulse having the longest width in the second group of frames.

[0062] The [Fig.3] is an embodiment in which the output order is changed between the rows in the frame.

[0063] With reference to [Fig. 3], in the odd-numbered frame, it can be seen that a signal corresponding to the MSB emerges first in an odd row, and a signal corresponding to the LSB emerges first in an even row. Furthermore, in the even-numbered frame, it can be seen that the signal corresponding to the LSB emerges first in an odd row, and the signal corresponding to the MSB emerges first in an even row.

[0064] Similarly, in [Fig. 2] and 3, an example is presented in which the relationship between the first group of frames and the second group of frames is defined as the even frame and the odd frame, but the present document is not limited to this. Each of the first and second groups of frames can be a group in which two, three, four, or other numbers of frames are grouped together. Furthermore, although an example is presented in which the relationship between the first and second groups is defined as the odd row and the even row, the present document is not limited to the example described above. The first and second groups can be a group in which two, three, four, or other numbers of rows are grouped together.

[0065] As described above, average values ​​of LED emission time differences in dimming levels 32 and 31 become the same by means of a change in the output order of the image data and the output order of the corresponding PWM signals. Consequently, a false dynamic contour due to a time difference between the LED emission times between Adjacent gradations can be improved. Similarly, although an embodiment in which the image data size is 6 bits has been presented for the sake of description, it appears that the image data size can vary.

[0066] The control device 150 according to this memory can control the clock drive circuit 140 to divide the pulses corresponding to the most significant bit MSB and the second significant bit MSB-1 of the image data among the pulses output from the clock drive circuit 140 into two or more sub-pulses and output the sub-pulses.

[0067] Fig. 4 is an output diagram of a conventional PWM signal, and Fig. 5 is an output diagram of a PWM signal according to the present memory.

[0068] With reference to [Fig. 4] and [Fig. 5], the PWM signal corresponding to an example in which the image data is 6 bits is shown. However, it should be understood that the display device and the control method according to this document are not limited to the examples described above, and are only examples for convenience of understanding.

[0069] In the output of a conventional PWM signal, when the output of the pulse signal corresponding to the MSB of the image data is complete, the output of the pulse signal corresponding to the MSB-1 of the next image data begins, then a one-period output is made after the output of the pulse signal corresponding to the MSB-2 of the image data, and so on, with the pulse signal corresponding to the LSB of the image data. However, in this case, since the false dynamic contour described above can occur, in order to improve this, the control device 150 according to this memory implements a control to output the signal by changing a shape of the pulse.

[0070] With reference to [Fig. 5], it can be seen that the pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of the image data are divided into four sub-pulses (1-1, 1-2, 1-3, and 1-4, and 2-1, 2-2, 2-3, and 2-4), respectively. In this case, the control device 150 can command the clock driver circuit 140 to alternately output the sub-pulse corresponding to the most significant bit (MSB) of the image data and the sub-pulse corresponding to the second significant bit (MSB-1) of the image data. As above, when the pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of the image data are output alternately via sub-pulses, since the PWM attack and non-attack times are uniformly distributed within a frame, the dynamic contour can be avoided.

[0071] Similarly, as shown in [Fig. 5], the number of subpulses corresponding to the most significant bit MSB of the image data can be the same as the number of subpulses corresponding to the second significant bit MSB-1 of the data of the image, but an example in which the number of sub-pulses corresponding to the most significant bit (MSB) of the image data and the number of sub-pulses corresponding to the second significant bit (MSB-1) of the image data are different is also possible. For example, the number of sub-pulses corresponding to the most significant bit (MSB) of the image data may be one more than the number of sub-pulses corresponding to the second significant bit (MSB-1) of the image data. In this case, the control device 150 can command the clock driver circuit 140 to output the sub-pulses corresponding to the second significant bit (MSB-1) of the image data between the sub-pulses corresponding to the most significant bit (MSB) of the image data.For example, when the number of subpulses corresponding to the most significant bit MSB of the image data is four (1-1, 1-2, 1-3 and 1-4) and the number of subpulses corresponding to the second significant bit MSB-1 of the image data is three (2-1, 2-2 and 2-3), an output order of the subpulses can be (1-1, 2-1, 1-2, 2-2, 1-3, 2-3 and 1-4).

[0072] A method for controlling the display device 100 according to this document will be described below. However, when describing the method for controlling the display device according to this document, the repetitive descriptions of the display device 100 described above are omitted.

[0073] Fig. 6 is a flowchart of the control method for the display device according to this document.

[0074] With reference to [Fig.6], in an S100 operation, the control device 150 can divide pulses corresponding to the most significant bit MSB and the second significant bit MSB-1 of the image data from the pulses output from the clock drive circuit 140 into two or more sub-pulses.

[0075] According to one embodiment of the present document, the operation S100 can be the division into the same number of sub-pulses corresponding to the most significant bit MSB of the image data and sub-pulses corresponding to the second significant bit MSB-1 of the image data.

[0076] According to another embodiment of the present document, the S100 operation can be the division which results in the number of sub-pulses corresponding to the most significant bit MSB of the image data being one more than, or one less than, the number of sub-pulses corresponding to the second significant bit MSB-1 of the image data.

[0077] In a subsequent operation S200, the control device 150 can command the clock drive circuit 140 to output alternately the sub-pulse corresponding to the most significant bit MSB of the image data and the sub-pulse corresponding to the second significant bit MSB-1 of the image data.

[0078] Previously, according to an example in which the number of sub-pulses is different, the operation S200 can be the command of the clock drive circuit 140 to output the sub-pulses corresponding to the second significant bit MSB-1 of the image data between the sub-pulses corresponding to the most significant bit MSB of the image data.

[0079] Subsequently, operations S100 and S200 can be performed repeatedly.

[0080] The control device 150 may include a processor, an integrated circuit A specific application (ASIC), another chipset, a logic circuit, a register, a communication modem, a data processing device, etc., known in the technical field to which this description belongs, can be used to perform calculations and various control logics. Furthermore, when the control logic described above is implemented in software, the control device 150 can be implemented as a set of program modules. In this case, the program modules can be stored in memory and executed by the processor.

[0081] The computer program described above may include code written in a computer language such as C / C++, C#, Java, Python, a machine language, or others, which can be read by a computer's processor (CPU) through a computer device interface so that the computer reads programs and executes processes implemented as programs. This code may include functional code relating to a function that defines functions necessary to execute the processes and other functions, and may include control code relating to an execution procedure necessary for the computer's processor to execute the functions according to a predetermined procedure.Furthermore, this code may also include code relating to a memory reference to which additional information or media necessary for the computer's processor to perform the functions described above should be referenced at any location (address) in the computer or in external memory. Moreover, when the computer's processor needs to communicate with any other computer, server, or other remote device to perform the functions described above, the code may also include code relating to communication with any other computer, server, or other remote device using the computer's communication module, and to transmit and receive any information or media during the communication.

[0082] The stored medium does not refer to a medium that stores data for a short time, such as a register, cache, memory, or the like, but refers to a medium that stores data semi-permanently and is readable by a device. Specifically, examples of storage media include read-only memory (ROM), random-access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage devices, and others, but this description is not limited to these. In other words, the program can be stored on various storage media on various servers that the computer can access, or on various storage media on the user's computer. Furthermore, the media can be distributed across a networked computer system, and machine-readable code can be stored on the media in a distributed manner.

[0083] According to the present memorandum, a dynamic false contour can be improved.

[0084] The effects of this description are not limited to the above-mentioned effect, and other effects not mentioned will be clearly understood by the person skilled in the art concerned by this description.

[0085] In the foregoing, although embodiments of this document have been described with reference to the accompanying drawings, those skilled in the art will understand that this description may take other specific forms without changing its technical spirit or essential characteristics. Accordingly, it should be understood that the embodiments described above are given by way of example in all respects and are not limiting.

Claims

Demands

1. Display device comprising: a display panel comprising a plurality of pixel attack circuits; a data attack circuit configured to output attack signals from a plurality of electroluminescent elements included in each pixel attack circuit via a plurality of data lines connected to each pixel attack circuit; a clock driver circuit configured to output a plurality of pulses whose widths are modulated for a defined transmission time in a frame to the pixel driver circuits via a plurality of clock lines connected to each pixel driver circuit; and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, the control device comprising a data output portion configured to change the order of image data outputs from the data drive circuit, and a scheduler configured to change the order of pulses outputs from the clock drive circuit, the display device being characterized in that: the data output portion commands the data drive circuit to output image data bits in order starting from the most significant bit in a first group of frames and to output image data bits in order starting from the least significant bit in a second group of frames; and The planner commands the clock drive circuit to output pulses in order starting from the pulse with the longest width in the first group of frames and to output pulses in order starting from the pulse with the shortest width in the second group of frames.

2. Display device comprising: a display panel comprising a plurality of pixel attack circuits; a data attack circuit configured to output signals related to the attack of a plurality of electroluminescent elements included in each pixel attack circuit through a plurality of data lines connected to each pixel attack circuit; a clock driver circuit configured to output a plurality of pulses whose widths are modulated for a defined transmission time in a frame to the pixel driver circuits via a plurality of clock lines connected to each pixel driver circuit; and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, the control device comprising a data output part configured to change the order of image data outputs from the data drive circuit, and a scheduler configured to change the order of pulses outputs from the clock drive circuit, the display device being characterized in that: the data output part controls the data drive circuit so that a pixel drive circuit included in a first row of groups outputs image data bits in an order starting from the most significant bit in a first group of frames and outputs image data bits in an order starting from the least significant bit in a second group of frames,and that a pixel attack circuit included in a second row of groups outputs bits of image data in order starting from the least significant bit in the first group of frames and outputs bits of image data in order starting from the most significant bit in the second group of frames; and, The planner commands the clock drive circuit so that the pixel drive circuit in the first row of groups outputs pulses in order from the pulse with the longest width in the first group of frames and outputs pulses in order from the pulse with the shortest width in the second group of frames, and that the pixel drive circuit in the second row of groups outputs pulses in order from the pulse with the shortest width in the first group of frames and outputs pulses in order from the pulse with the longest width in the second group of frames.

3.

4. A method for controlling a display device comprising a data drive circuit configured to output signals relating to the drive of electroluminescent elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, characterized in that the control device repeatedly performs (a) for a first group of frames, the command of the data drive circuit to output image data bits in an order starting from the most significant bit in the first group of frames and the command of the clock drive circuit to output pulses in an order starting from the pulse having the longest width in the first group of frames,and (b) for a second group of frames, the control of the data drive circuit to output image data bits in order starting from the least significant bit in the second group of frames and the control of the clock drive circuit to output pulses in order starting from the pulse having the shortest width in the second group of frames. A method for controlling a display device comprising a data drive circuit configured to output signals relating to the drive of light-emitting elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit.characterized in that the control device repeatedly performs (a) for a first group of frames, the control of the data attack circuit such that a pixel attack circuit included in a first row of groups outputs image data bits in order starting from the most significant bit in the first group of frames, and that a pixel attack circuit included in a second row of groups outputs image data bits in order starting from the least significant bit in the first group of frames, and the control of the circuit,

5.

6. (a) clock drive control such that the pixel drive circuit in the first row of groups outputs pulses in order starting from the pulse with the longest width in the first group of frames, and the pixel drive circuit in the second row of groups outputs pulses in order starting from the pulse with the shortest width in the first group of frames, and (b) for a second group of frames, the data drive control such that the pixel drive circuit in the first row of groups outputs image data bits in order starting from the least significant bit in the second group of frames, and the pixel drive circuit in the second row of groups outputs image data bits in order starting from the most significant bit in the second group of frames,and the control of the clock drive circuit such that the pixel drive circuit in the first row of groups outputs pulses in sequence starting from the shortest pulse in the second group of frames, and the pixel drive circuit in the second row of groups outputs pulses in sequence starting from the longest pulse in the second group of frames. A computer program recorded on a non-transient, computer-readable recording medium, the computer program in response to execution by a computer performing the method according to claim 3. Display device comprising: a display panel comprising a plurality of pixel attack circuits; a data attack circuit configured to output attack signals from a plurality of electroluminescent elements included in each pixel attack circuit via a plurality of data lines connected to each pixel attack circuit; a clock driver circuit configured to output a plurality of pulses whose widths correspond to the image data are modulated for a defined transmission time in a frame to the pixel driver circuits via a plurality of clock lines connected to each pixel driver circuit; and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, characterized in that the control device commands the clock drive circuit to divide pulses corresponding to a most significant bit (MSB) and a second significant bit (MSB-1) of the image data from among the pulses output from the clock drive circuit into two or more sub-pulses and output the sub-pulses.

7. Display device according to claim 6, characterized in that the control device controls the clock drive circuit to output alternately a sub-pulse corresponding to the most significant bit (MSB) of the image data and a sub-pulse corresponding to the second significant bit (MSB-1) of the image data.

8. A method for controlling a display device comprising a data drive circuit configured to output image data relating to the drive of electroluminescent elements to pixel drive circuits, a clock drive circuit configured to output pulses whose widths are modulated to the pixel drive circuits, and a control device configured to output control signals to perform operations of the data drive circuit and the clock drive circuit, characterized in that the control device repeatedly performs (a) the division of pulses corresponding to a most significant bit (MSB) and a second significant bit (MSB-1) of the image data from the pulses output from the clock drive circuit into two or more sub-pulses,and (b) controlling the clock drive circuit to alternately output a sub-pulse corresponding to the most significant bit (MSB) of the image data and a sub-pulse corresponding to the second significant bit (MSB-1) of the image data.

9. Computer program recorded in a non-transient, computer-readable recording medium, the computer program in response to execution by a computer performing the method according to claim 8.

10. A computer program recorded on a non-transient, machine-readable recording medium, the computer program in response to an execution by a computer carrying out the process according to claim 4.

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