Symbol time synchronization device and method with a parallel architecture

Abstract

The invention relates to a parallel architecture symbol time synchronization device comprising: a sample storage and reordering module (20) including a control unit (22) and 2 x P FIFOs (21) ordered cyclically, an interpolation module configured to provide at each clock stroke a time error indication (Err-Ind) taking a value from "nominal", "lower overshoot" or "upper overshoot", at a current clock stroke, the control unit (22) is configured to: write a sample into each of successive P FIFOs (21), read a sample into each of successive P, P - 1, or P + 1 FIFOs (21) depending on whether the time error indication (Err-Ind) is respectively "nominal", "lower overshoot" or "upper overshoot", reorder samples to be provided to the interpolation module using a permutation network (23). Figure for the abridged version: Fig. 3

Description

Description Title of the invention: Device and method for synchronizing symbol time with parallel architecture Field of invention

[0001] — The present invention belongs to the field of digital communications, in particular by satellite, and more particularly relates to a device and a method symbol time synchronization with a parallel architecture. The invention is particularly well suited for a high-speed communications system between a satellite and a ground station. State of the art

[0002] In digital communications systems, a transmitting device transmits a message to a receiving device in the form of a signal carrying a sequence of symbols. A symbol can correspond to a bit or a set of data bits. A symbol can, for example, correspond to a particular value phase, amplitude and / or frequency of the signal, depending on the modulation used. At the receiving device level, the received signal is sampled and the symbols must be synchronized from the samples obtained (one symbol corresponds to several samples).

[0003] = The symbol time at the transmitting device is clocked from a clock belonging to the transmitting device. The symbol time at the receiving device is clocked from a clock belonging to the receiving device. A bias However, a time difference may exist between the clock of the transmitting device and the clock of the receiving device due to the imperfection of the oscillators that form these clocks. Timing errors can also be introduced by the Doppler effect due to a variation in the relative speed of the transmitting device with respect to the receiving device (this is particularly true for communication between a low-orbit satellite and a ground station). These timing errors can lead to errors in determining the instants of symbols during sampling. This can lead to errors in symbol decoding and potentially to an inability to decode the received message.

[0004] There are different methods of symbol time synchronization. It is notably possible to use a method based on Gardner's algorithm, or a method based on the Oerder and Meyr algorithm. These algorithms are notably used in space communications based on SCPC technology (acronym for "Single Channel Per Carrier", in French "a single channel per carrier"), as in example for the DVB-S2X system (English acronym for “Digital Video Broadcasting — Second Generation Satellite Extensions”, it is a standard for broadcasting digital television by satellite). For these technologies, the symbol time synchronization device generally has a serial architecture. The CCSDS (Consultative Committee for Space Data Systems) is currently defining a communications standard offering a throughput of around 10 Gbits / s, thus enabling satellites to exchange data at very high speeds with ground stations via an optical link. To achieve such high throughputs, it becomes necessary to use a parallel architecture for the symbol time synchronization device, in order to meet the real-time requirements of FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) technologies. The parallel architecture, however, introduces a design challenge to resolve sample-level time drift without overly complexifying the receiving device. The paper "A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems" by Xin Hao et al describes a symbol time synchronization device with a parallel architecture based on the Gardner algorithm. It is mentioned in this paper that a frequency mismatch between the transmitting device and the receiving device results in a timing error that continuously increases or decreases. To correct this timing error, some samples should be discarded or retained when the error has accumulated to a certain level. It then becomes necessary to rearrange the samples into a correct order. However, this paper does not describe an example implementation for rearranging the samples in an efficient and effective manner. Statement of the invention The present invention aims to remedy all or part of the drawbacks of the prior art, in particular those set out above. To this end, and according to a first aspect, the present invention proposes, a symbol time synchronization device with parallel architecture. The symbol time synchronization device is configured to be clocked, and it comprises: a sample storage and reordering module comprising a control unit and 2 x P type buffer memories "first in, first out", also known as "FIFOs", P being an even integer greater than or equal to four, each FIFO being able to store multiple samples, with FIFOs ordered cyclically; an interpolation module configured to provide at each clock stroke a indication of time error determined from samples in originating from the storage and reordering module, said in- time error indication taking a value from “nominal”, “undershoot” or “overshoot”. At a current clock tick, the control unit is configured to: write a sample into each of P successive FIFOs that have not been used in writing at the previous clock stroke, read a sample from each of successive P, P - 1, or P + 1 FIFOs according to that the time error indication is respectively “nominal”, "underflow" or "overflow", the FIFOs in which a sample must be read being defined according to the FIFOs in which samples were read at the previous clock tick, reorder samples to be provided to the interpolation module using a permutation network and depending on a counter whose current value is defined according to the value of said counter at the previous clock stroke and depending on the time error indication at the previous clock tick. It should be noted that we are here in the generic case where the current clock tick and the previous clock tick present valid samples. As will be detailed later, it is possible to manage an indication which provides information on the validity of the samples at the clock tick considered, and to do (or not do) certain actions depending on this validity indication. The use of a permutation network and its management using a counter updated according to the time error indication makes it possible to dynamically rearrange the samples to be provided to the interpolation module using binary rotation operations that are relatively inexpensive in terms of hardware implementation and computation time. In particular embodiments, the invention may further comprise one or more of the following features, taken individually or in any technically possible combination. In particular embodiments, writing to the FIFOs is controlled by a binary write mask comprising 2 x P bits. Each bit is respectively associated with a FIFO and indicates whether or not said FIFO must be used for writing. The write mask can take two distinct possible values, each having exactly P bits indicating that the associated FIFOs must be used for writing, said values ​​having no bits in common, The control unit is configured to change the value of the write mask at each clock tick (if valid data is available for the clock tick considered). In particular embodiments, reading in the FIFOs is controlled by three binary read masks each comprising 2 x P cyclically ordered bits. Each bit is respectively associated with a FIFO and indicates whether or not said FIFO must be used for reading. Each read mask is respectively associated with one of the three possible values ​​of the timing error indication. Each read mask comprises exactly P, P - 1 or P + 1 successive bits indicating that the associated FIFOs must be used for reading depending on whether the read mask is respectively associated with the “nominal”, “underflow” or “overflow” indication. The control unit is configured, for said current clock tick, to identify the reading mask to use based on the error indication temporal, update each reading mask, for the next clock tick, by ef- performing a binary rotation of the current value of said reading mask of P,P-orP+ 1 bits depending on whether the time error indication is respect- tively "nominal", "undershoot" or "overshoot » In particular embodiments, to reorder the samples to be provided to the interpolation module, the control unit is configured to: command the permutation network to perform a binary rotation on said samples of a number of bits defined from the current value of the counter, update the counter, for the next clock tick, by performing a addition modulo 2 x P of the current value of the counter with the value P, P - l or P+ 1 depending on whether the time error indication is respectively “nominal”, “undershoot” or “overshoot”. According to a second aspect, the present invention relates to a receiving device of a communications system comprising a synchronization device according to any one of the preceding embodiments. According to a third aspect, the present invention relates to a satellite comprising such a receiving device. In particular embodiments, the communications system is a space communications system providing a data rate of at least 100 Mbps. According to a fourth aspect, the present invention relates to a method of func- operation of a symbol time synchronization device with parallel architecture. The synchronization device is clocked and comprises: a sample storage and reordering module including 2 x P first-in, first-out buffers, or FIFOs, P being an even integer greater than or equal to four, each FIFO able to store several samples, the FIFOs being ordered cy- click, an interpolation module configured to provide at each clock stroke a indication of time error determined from samples in originating from the storage and reordering module, said in- time error indication taking a value from “nominal”, “undershoot” or “overshoot”. The process involves, at a current clock stroke: a writing of a sample in each of P successive FIFOs which have not been used in writing at the previous clock stroke, a reading of a sample in each of P, P - 1, or P + 1 FIFOs suc- depending on whether the time error indication is respectively "nominal", "undershoot" or "overshoot", the FIFOs in which a sample must be read being defined according to the FIFOs from which samples were read at the clock tick previous, a reordering of samples to be provided to the interpolation module in function of a counter whose current value is defined as a function of the counter value at the previous clock stroke and according to the indication time error at the previous clock tick, a supply of the reordered samples to the interpolation module. In particular embodiments, the invention may further comprise one or more of the following characteristics, taken individually or in any technically possible combination. In particular embodiments, writing to the FIFOs is controlled by a binary write mask comprising 2 x P bits. Each bit is respectively associated with a FIFO and indicates whether or not said FIFO must be used for writing. The write mask can take two possible distinct values, each having exactly P bits indicating that the associated FIFOs must be used for writing, said values ​​having no bits in common. The value of the write mask is changed at each clock tick. In particular implementations, reading from the FIFOs is controlled by three binary read masks, each comprising 2 x P bits ordered cy- click. Each bit is respectively associated with a FIFO and indicates whether or not said FIFO must be used for reading. Each read mask is respectively associated with one of the three possible values ​​of the timing error indication. Each read mask comprises exactly P, P - 1 or P + 1 successive bits indicating that the associated FIFOs must be used for reading depending on whether the read mask is respectively associated with the "nominal", "underflow" or "overflow" indication. Reading comprises: an identification of the reading mask to be used depending on the indication of temporal error, an update of each reading mask, for the next clock tick, by performing a binary rotation of the current value of said mask of reading P, P- 1 or P + 1 bits depending on whether the timing error indication is respectively "nominal", "undershoot" or "overshoot superior ". In particular modes of implementation, the reordering of the samples to be provided to the interpolation module includes: a binary rotation operation, on said samples, of a number of bits set from the current value of the counter, an update of the counter, for the next clock tick, by performing a addition modulo 2 x P of the current value of the counter with the value P, P - l or P+ 1 depending on whether the time error indication is respectively “nominal”, “undershoot” or “overshoot”. In particular implementations, each FIFO is configured to activate an overflow risk indication when the number of samples stored in said FIFO is greater than or equal to a threshold, and writing to the FIFOs is authorized if and only if the overflow risk indication is not activated for any of the FIFOs. In particular implementations, each FIFO is configured to activate a shortage risk indication when the number of samples stored in said FIFO is less than or equal to a threshold, and reading from the FIFOs is authorized if and only if the shortage risk indication is not activated for any of the FIFOs. In particular modes of implementation, the frequency of the symbols at the output of the synchronization device is greater than or equal to 100 Mbits / s. Presentation of the figures The invention will be better understood by reading the following description, given as a non-limiting example, and made with reference to figures | to 8 which represent: [Fig.1] a schematic representation of a space communications system between a satellite orbiting the Earth and a ground station, [Fig.2] a schematic representation of a symbol time synchronization device according to the invention [Fig.3] a schematic representation of an embodiment of a sample storage and reordering module, [Fig.4] a schematic representation of an embodiment of an interpolation module, [Fig.5] a schematic representation of an example of implementation of the control of writing new samples in the FIFOs of the storage and reordering module, [Fig.6] a schematic representation of an example of implementation of the control of reading samples in the FIFOs of the storage and reordering module, [Fig.7] a schematic representation of an example implementation of the permutation network control of the storage and reordering module, [Fig.8] a schematic representation of the main steps of a method of operating a symbol time synchronization device according to the invention. In these figures, identical references from one figure to another designate identical or similar elements. For reasons of clarity, the elements represented are not necessarily to the same scale, unless otherwise indicated. Detailed description of an embodiment of the invention In the following description, we consider, in a non-limiting manner, the case of a space communications system. [Fig. 1] schematically represents a space communications system between a satellite 70 in orbit around the Earth 73 and a ground station 71. A signal 72 carrying data is transmitted by the ground station 71 to the satellite 70. To transmit the signal '72, the ground station 71 comprises a transmission chain. The transmission chain is clocked and generally comprises a channel encoder, an interleaver, a modulator, and other conventional elements involved in the transmission of a signal (filters, oscillators, amplifiers, digital / analog converter, etc.). After coding and interleaving, the data to be transmitted are modulated in the form of symbols. A symbol may correspond to a bit or a set of data bits. A symbol may, for example, correspond to a particular value of phase, amplitude and / or frequency of the signal, depending on the modulation used. To receive the signal 72, the satellite 70 has a reception chain. The chain reception is clocked and generally includes a sampler, a symbol time synchronization device, a demodulator, a deinterleaver, a channel decoder, and other conventional elements involved in signal reception (filters, oscillators, amplifiers, analog / digital converter, etc.). The role of the sampler is to take values ​​from the signal 72 at regular intervals to produce a series of discrete values ​​called samples. The role of the symbol time synchronization device is to detect and synchronize the symbols carried by the signal 72 from the samples thus obtained. The symbols are then transformed into binary data by the demodulator. The binary data is finally decoded. The signal 72 may be a radio signal or an optical signal. The data rates targeted for the space communications considered are relatively high, for example greater than 100 Mbit / s, or even greater than 1 Gbit / s, or even greater than 10 Gbit / s. Modulation can be of the PSK type (acronym for "Phase-Shift Keying") or NRZ-O3K type (acronym for "Non-Return-to-Zero Optical On-Off Keying"). In the example considered, the signal 72 is transmitted by the earth station 71 to the satellite 70. However, according to another example, nothing would prevent the satellite 70 from being the origin of the transmission of a signal to the earth station 71. In this case, it is the satellite 70 which would play the role of transmitting device with a transmission chain such as that previously described, and the earth station 71 would play the role of receiving device with a reception chain such as that previously described. Nor would anything prevent us from considering a transmitting device and a receiving device of another communications system, for example a cellular terrestrial communications system. To achieve high throughput, it becomes necessary to use a parallel architecture for the symbol time synchronization device to meet the real-time requirements of the FPGA or ASIC technologies used to design it. [Fig.2] schematically represents a symbol time synchronization device 10 according to the invention. As explained previously, the symbol time synchronization device 10 takes samples x, as input, and provides symbols X, as output. The symbol time synchronization device 10 is clocked by a clock (this is not shown in the figures for the sake of simplification). As illustrated in [Fig.2], the symbol time synchronization device 10 includes a module 20 for storing and reordering samples and a module 30 for interpolation. The role of the interpolation module 30 is to process the samples x; coming from the storage and reordering module 20 to detect and synchronize the symbols X, to be supplied to the demodulator. The interpolation module 30 is further configured to provide at each clock stroke an indication of time error Err-Ind (or synchronization error) estimated from the samples x; coming from the storage and reordering module 20. The time error indication Err-Ind takes a value from among “nominal”, “underrun”, or “overrun”. The time error may be due to a frequency bias between the clock of the transmitting device and that of the receiving device, or by the Doppler effect induced by a variation in the relative speed of the transmitting device with respect to the receiving device. The "undershoot" case corresponds to the situation where the sampling rate of the receiving device is too fast compared to the symbol rate. The "overshoot" case corresponds to the situation where the sampling rate of the receiving device is too slow compared to the symbol rate. The "nominal" case corresponds to the situation where the sampling rate of the receiving device is substantially synchronized with the symbol rate. The value of the timing error can vary over time, in particular due to the Doppler effect. To cancel the timing error, some samples must be kept (in the "underflow" case) or discarded (in the "overflow" case) when the error has accumulated to a certain level. In a parallel architecture, it is then necessary to reorder the sequence of samples to be processed when a sample is kept or skipped or deleted. The sample storage and reordering module 20 is configured to reorder (or rearrange) the samples provided by the sampler before making them available to the interpolation module 30. The reordering of the samples is done according to the time error indication Err-Ind. In other words, it is the sample storage and reordering module 20 which is responsible for keeping or deleting certain samples according to the observed time error, and for reordering the samples appropriately before making them available to the interpolation module 30. [Fig.3] schematically represents an embodiment of the sample storage and reordering module 20. This module 20 comprises a set of 2 x P buffer memories 21 of the "first in, first out" type, or FIFOs (English acronym for "First-In First-Out"). P corresponds to a parallelization factor. P is an even integer greater than or equal to four. Advantageously, the parallelization factor P can also be chosen to correspond to a power of two (this simplifies certain parts of the implementation). In the example considered and illustrated in [Fig.3], the parallelization factor is equal to four (P = 4). Each FIFO 21 can store several samples (for example eight samples per FIFO). In the example considered, a sample corresponds to a pair of values ​​each sampled respectively on channel I ("in phase" channel) and on channel Q ("quadrature" channel). According to another example, a sample could correspond to only one of the I and Q channels, and it is then sufficient to duplicate the solution to process each of the two I and Q channels. In the example considered, a sample is coded on eight bits with fixed-point quantization of type Q(2.6). However, nothing would prevent a sample from being encoded in a different way, for example on a different number of bits and / or with a different quantization method, for example in floating point. The different ways of defining and encoding a sample are only variants of the invention.The choice of an encoding or quantification method depends in particular on the modulations and the signal-to-noise ratios (SNR) considered. The FIFOs 21 are ordered cyclically. This means, for example, that the FIFOs can each be identified by an index varying between 0 and (2 x P - 1), and that they are ordered according to their index such that for an index i varying between | and (2 x P- 1), the FIFO with index (i - 1) precedes the FIFO with index i and the FIFO with index (2 x P - 1) precedes the FIFO with index 0. In the example considered and illustrated in [Fig.3], the FIFOs 21 are identified and ordered according to an index varying from 0 to 7 (in this case, the cyclic order of the FIFO indices is 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, … etc.). It should be noted that nothing would prevent the FIFOs from being ordered differently. For example, it would be possible to consider that the FIFOs are ordered as follows: first the FIFOs with even index, in ascending order, and then the FIFOs with odd index, in ascending order (in this case, the cyclic order of the FIFO indices is 0, 2, 4, 6, 1, 3, 5, 7, 0, 2, 4, etc.). At a current clock tick, a sample is written to each of P successive FIFOs 21 that have not been used for writing at the previous clock tick. In the example shown in [Fig.3], at the current clock tick, four samples xp, Xn+1, X n42s Xn43 are written respectively to the FIFOs of index 0 to 3 (the sample x, is written to the FIFO,, the sample x,+ is written to the FIFO,, the sample x,;2 is written to the FIFO,, the sample x,,3 is written to the FIFO;). At the next clock tick, the four samples X,44, Xn+5: Xn+6; Xn47 Will be written respectively to the FIFOs with index 4 to 7. And so on. At the current clock tick, a sample is read from each of P, (P - 1), or (P + 1) successive FIFOs 21 depending on whether the time error indication Err-Ind provided by the interpolation module 30 for the clock tick considered is respectively "nominal", "underflow" or "overflow". In other words, P samples are read when the time error indication Err-Ind is "nominal", (P- 1) samples are read when the time error indication Err-Ind is "underflow", and (P + 1) samples are read when the time error indication Err-Ind is "overflow". The FIFOs 21 from which a sample is to be read are defined based on the FIFOs 21 from which samples were read in the previous clock tick (samples are read in the FIFOs that follow the FIFOs from which samples were read in the previous clock tick). Conventionally, a FIFO 21 corresponds to a memory area associated with a write pointer and a read pointer. The write pointer indicates an address of the memory area to which the next sample must be stored. The read pointer indicates an address of the memory area to which the oldest sample that has not yet been read is stored (next sample to be read). The write pointer (respectively the read pointer) is incremented at each write operation of a sample (respectively at each read operation of a sample). It should be noted that there are different ways of managing a FIFO (pointer that traverses the memory in a circular fashion, binary pointer with Gray code that counts the read or write actions, etc.). The choice of a particular method to manage reading or writing in a FIFO is only a variant of the invention. Each FIFO 21 may be configured to activate an overflow risk indication when the number of samples stored in the FIFO 21 is greater than or equal to a threshold (the number of samples stored in a FIFO 21 corresponds to the number of samples that have been written to said FIFO 21 and that have not yet been read). Similarly, each FIFO 21 may be configured to activate a shortage risk indication when the number of samples stored in the FIFO 21 is less than or equal to a threshold. The write and / or read operations in the FIFOs 21 may then be controlled according to these overflow risk and / or shortage risk indications. These aspects will be described later with reference to FIGS. 5 and 6. For each FIFO 21, the next sample to be provided to the interpolation module 30 corresponds to the sample indicated by the read pointer of said FIFO 21. The sample storage and reordering module 20 comprises a permutation network 23 configured to reorder these samples to be provided to the interpolation module 30. The permutation network 23 corresponds, for example, to a computing unit capable of performing binary rotation operations ("barrel shifter" in English). A binary rotation is similar to a logical shift (shifting bits one or more places to the right or left), except that each outgoing bit is reinjected into the place freed by the shift. At the current clock tick, the permutation to be performed is defined as a function of a counter whose current value is defined as a function of the value of said counter at the previous clock tick and as a function of the time error indication Err-Ind provided by the interpolation module 30 at the previous clock tick. The permutation to be performed depends in fact on the history of the sample retention and / or deletion operations which have been successively performed at the previous clock ticks. Updating the counter at each clock tick as a function of the time error indication Err-Ind makes it possible to identify the FIFO 21 from which the next samples must be provided to the interpolation module 30. The sample storage and reordering module 20 comprises a control unit 22 configured to execute the reading and writing operations in the FIFOs 21 and the sample reordering operations with the permutation network 23. The control unit 22 is in particular configured to control the FIFOs in which a sample must be written, to control the FIFOs in which a sample must be read, and to control the permutation network 23. In the example illustrated in [Fig.3], the write control is represented by the WC indication (“Write Control”) which indicates in which FIFOs 21 a sample must be written, the read control is represented by the RC indication (“Read Control”) which indicates in which FIFOs 21 a sample must be read, and the control of the permutation network 23 is represented by the SC indication (“Shift Control”) which indicates in which order the available samples must be provided to the interpolation module 30. Figures 5 to 7, which will be described in detail later, illustrate particular modes of implementing the writing, reading, and reordering of the samples. [Fig.4] schematically represents an embodiment of the interpolation module 30. In the example considered, the Gardner algorithm is used (in its version for a parallel architecture). The interpolation module 30 comprises two parallel interpolation blocks 31. Similar to what is described in the document "Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems", Xin Hao et al, each block 31 comprises two interpolators 32 and a timing error detection unit 33. The timing error detection unit 33 is fed by the two interpolators 32 of the block 31 to which it belongs, as well as by one of the two interpolators 32 of the other block 31. At a clock stroke, each interpolator 32 takes as input four samples from the samples made available by the sample storage and reordering module 20: the first interpolator 32 of the first block 31 takes as input the samples x;, X;41, Xj42» X;;a 3 1st second interpolator 32 of the first block 31 takes as input the samples x;,1, X;42, X;43, Xp4 ; the first interpolator 32 of the second block 31 takes as input the samples x;,2, Xj+5s Xju4s Xjus ; the second interpolator 32 of the second block 31 takes as input the samples x;43, Xj4ss Xjass Xjss, Each block 31 provides as output a symbol: the first block 31 provides the symbol X, ; the second block 31 provides the symbol Xkar Thus, at each clock tick, four new samples (Xn, Xn+15 Xn+2s Xn+3) provided by the sampler are processed by the storage and reordering module 20 and two new symbols (X;, X1+1) are provided by the interpolation module 30. Generally speaking, the use of a parallelization factor of value P allows the symbol time synchronization device 10, at each clock tick, to process P new samples at the input and to provide P / 2 new symbols at the output. At each clock tick, P + 3 samples are processed by the interpolation module 30. The interpolation module 30 comprises a control unit 37 configured to estimate, in a conventional manner (Gardner algorithm), a time error from the time errors detected individually by each of the blocks 31. The control unit 37 can in particular rely on calculation units of the adder 34, multiplier / divider 35 and loop filter 36 type to estimate the time error. The control unit 37 is also configured to provide the time error indication Err-Ind to the storage and reordering module 20 as a function of the estimated time error. [Fig.5] schematically represents a particular mode of implementation of the control of writing in the FIFOs of P new samples. In this particular implementation mode, writing to the FIFOs is controlled by a write mask WM (Write Mask) comprising 2 x P bits. Each bit of the write mask is respectively associated with a FIFO 21 and indicates whether or not said FIFO 21 must be used for writing. The write mask WM can take two distinct possible values ​​WM, and WM: each having exactly P bits indicating that the associated FIFOs must be used for writing (these are successive FIFOs, i.e. they follow one another in the cyclic order of the FIFOs). The values ​​WM, and WM, have no bits in common. In the example considered and illustrated in [Fig.5], the parallelization factor P is equal to four (P = 4). The WM write mask therefore has eight bits (2 x P = 8). A bit at '1' indicates that the associated FIFO must be used for writing. A bit at '0° indicates that the associated FIFO must not be used for writing. The bits are ordered from left to right and the index of a bit corresponds to the index of the FIFO with which it is associated. The WM mask, whose binary value is Ob11110000, indicates that only the four FIFOs with indexes 0 to 3 must be used for writing. The WM mask, whose binary value is 0b00001111, indicates that only the four FIFOs with indexes 4 to 7 must be used for writing. It should be noted that nothing would prevent using different values ​​for WM, and WM:. For example, if the FIFOs are ordered by first considering the FIFOs with even index and then the FIFOs with odd index, then the WM mask, can take the binary value 0b10101010 and the WM mask, can take the binary value 0b01010101. It can also be noted that it is not essential that the index of a bit of a write mask correspond to the index of the FIFO with which it is associated: it would be possible for example to consider that the first four bits of the write mask correspond to the four FIFOs with even index, then that the following four bits of the write mask correspond to the four FIFOs with odd index. There would also be nothing to prevent the use of reverse logic where a bit at '0' indicates that the associated FIFO should be used for writing, and a bit at '1' indicates that the associated FIFO should not be used for writing. The control unit 22 is configured to change the value of the write mask WM at each clock tick. In the example considered and illustrated in [Fig. 5], the choice of the value to be used for the write mask WM among WMy; and WM, is carried out by a multiplexer 41 controlled by a binary value 42 updated at each clock tick using a gate 43 configured to carry out an “exclusive OR” (XOR) logic operation between said binary value 42 and the value '1'. Other implementation modes could however be envisaged, for example by using a register storing the value of the write mask WM and on which a one's complement operation (inversion of all the bits) is carried out at each clock tick. The table below gives an example of values ​​taken by the WM write mask at successive clock ticks. In the table below, the notation CK, represents a clock tick of index p. [Tables 1] |cx |WM CK,1 0b11110000 cK, 0b00001111 CK,: — |0b11110000 CK,. — |0b00001111 As indicated previously, each FIFO 21 can be configured to activate an overflow risk indication 44 when the number of samples stored in the FIFO 21 is greater than or equal to a threshold. In the example considered, each FIFO can have up to eight samples, the overflow risk indication 44 takes the value '1' when there are at least six samples present in the FIFO, otherwise the overflow risk indication 44 takes the value '0'. The gate 45 is configured to perform a logical "WHERE" (OR) operation between the overflow risk indications 44 of the different FIFOs 21. The "OR" gate 45 controls a multiplexer 46 to define the value of a write authorization bit mask WA ("Write Authorization"). The WA mask takes the value 0b00000000 when an overflow risk indication 44 is at '1' for at least one of the FIFOs (i.e. when the result of the "WHERE" gate 45 is '1').The WA mask takes the value 0b11111111 when the overflow risk indication 44 is '0' for all FIFOs (i.e. when the result of the "WHERE" gate 45 is '0'). Gate 47 is configured to perform a logical "AND" operation between the WM mask and the WA mask. The "AND" gate 47 provides as output the WC bit mask which controls the FIFOs to which a sample is to be written. Thus, writing to the FIFOs 21 is allowed if and only if the overflow risk indication 44 is not activated for any of the FIFOs 21. It should be noted that, in the above description of [Fig. 5], it is assumed that there are P valid samples at the clock tick considered. However, this is not necessarily always the case. For example, if the clock that regulates the symbol time synchronization device 10 is faster than the clock of the analog / digital converter, new samples might not be available at certain clock ticks. It is then possible to take into account an additional indication that provides information on the validity of the samples at the clock tick considered (for the sake of simplification, this indication of validity of the samples is not not shown in the figures). In such a case, writing to the FIFOs 21 as well as updating the WM write mask would be conditioned by this indication of validity of the samples. [Fig.6] schematically represents a particular mode of implementation of the reading control in the FIFOs of P, (P - 1) or (P + 1) samples depending on the Err-Ind indication. In this particular mode of implementation, the reading in the FIFOs 21 is controlled by a read mask RM (“Read Mask”) comprising 2 x P bits. This read mask RM corresponds to one of the read masks RM,, RM, and RM. The choice of the read mask to be used is made via the multiplexer 53 which is controlled by the time error indication Err-Ind. For example, the read mask RM, is used when the time error indication Err-Ind is equal to “nominal”, the read mask RM, is used when the time error indication Err-Ind is equal to “underflow” and the read mask RM; is used when the Err-Ind indication is equal to “overflow”. Each bit of a read mask is respectively associated with a FIFO 21 and indicates whether or not said FIFO 21 must be used for reading. As for the FIFOs 21, the bits of the read masks are ordered cyclically: for an index i varying between 1 and (2 x P - 1), the index bit (i - 1) precedes the index bit i and the index bit (2 x P - 1) precedes the index bit 0. In the example considered and illustrated in [Fig.6], the parallelization factor P is equal to four (P = 4) and the read masks each have eight bits. A bit at '1' indicates that the associated FIFO must be used for reading, a bit at '0' indicates that the associated FIFO must not be used for reading (again, nothing would prevent the use of inverse logic). The bits are ordered from left to right and the index of a bit corresponds to the index of the FIFO with which it is associated. The RM reading mask, which is associated with the "nominal" indication, comprises exactly P successive bits at '1'. The RM reading mask; which is associated with the "underflow" indication has exactly (P - 1) successive bits set to '1'. The read mask RM, which is associated with the "overflow" indication, has exactly (P + 1) successive bits set to '1'. For example, the read mask RMy£ is initialized to the binary value Ob11110000 (to indicate that only the four FIFOs with indexes O to 3 are to be used for reading); the read mask RMz is initialized to the binary value Ob11100000 (to indicate that only the three FIFOs with indexes O to 2 are to be used for reading); the read mask RMz is initialized to the binary value 0b11111000 (to indicate that only the five FIFOs with indexes 0 to 4 are to be used for reading). At a current clock tick, the control unit 22 is configured to update each of the three read masks RM,, RM; and RM;, for the following clock pulse, by performing a binary rotation of the current value of said read masks respectively by P, (P - 1) or (P + 1) bits depending on whether the time error indication Err-Ind provided by the interpolation module 30 is respectively “nominal”, “undershoot” or “overshoot”. In other words, if the indication is “nominal”, each of the three read masks RM,, RM, and RMz undergoes a rotation of P bits; if the indication is “undershoot”, each of the three read masks RM,, RM, and RM; undergoes a rotation of (P - 1) bits; if the indication is “overshoot”, each of the three read masks RM,, RM, and RM; undergoes a rotation of (P + 1) bits.Thus, the FIFOs 21 from which a sample must be read at the current clock tick are the FIFOs 21 which follow the FIFOs 21 from which samples were read at the previous clock tick: if the index of the last FIFO which was used for reading at the previous clock tick has a value i between 0 and (2 x P - 2), then the first FIFO to be used for reading at the current clock tick is the index (i + 1); if the index of the last FIFO which was used for reading at the previous clock tick has the value (2 x P - 1), then the first FIFO to be used for reading at the current clock tick is the one whose index is 0. In [Fig.6], the 51 "ROT" blocks each represent an electronic circuit capable of performing a binary rotation operation. In the example considered, this is a rotation to the right (because the bit with index O corresponding to the first FIFO is the leftmost bit, i.e. the most significant bit) but it is obvious that a rotation to the left could also be used if the bits were ordered in the other direction. The table below gives an example of values ​​taken by the read masks at successive clock ticks. In the table below, the notation CK, represents a clock tick with index p; the notation RM corresponds to the read mask used for the current clock tick; the notation "Next RM;" corresponds to the value of the read mask RM: updated for the next clock tick (with i = 1.20u3). [Tables 2] Err-Ind RM ex RM | [Next RM Next RM, |Next RM; _ 0b11110000 |ob11100000 |0b11111000: J0b11111000 |0b10000111 |0b00000111 [0b11000111 5 fs …. DOI LLIOMOU [VOL LUMOON" OLLLLIUUAT cs ma Nom CK… | |Overflow |0b11111000 |0b10000111 [0b00000111 |0b11000111 higher [exe Normal 0b10000111 [0b01111000 [obo1110000 [ob01 111100 As indicated previously, each FIFO 21 can be configured to activate a shortage risk indication 54 when the number of samples stored in the FIFO 21 is less than or equal to a threshold. In the example considered, each FIFO can have up to eight samples, the shortage risk indication 54 takes the value '1' when the number of samples in the FIFO 21 is less than or equal to two, otherwise the shortage risk indication 54 takes the value '0'. The gate 55 is configured to perform a logical "WHERE" (OR) operation between the shortage risk indications 54 of the different FIFOs 21. The "OR" gate 55 controls the multiplexer 56 to define the value of a read authorization bit mask RA ("Read Authorization"). The RA mask takes the value 0b00000000 when an indication 54 of risk of shortage is at '1' for at least one of the FIFOs (i.e. when the result of the gate 55 "WHERE" is '1').The RA mask takes the value 0b11111111 when the shortage risk indication 54 is '0' for all FIFOs (i.e., when the result of the "WHERE" gate 55 is '0"). Gate 57 is configured to perform a logical "AND" operation between the RM mask and the RA mask. The "AND" gate 57 outputs the RC bit mask that controls the FIFOs from which a sample is to be read. Thus, reading from the FIFOs 21 is allowed if and only if the shortage risk indication 54 is not activated for any of the FIFOs 21. Alternatively or in addition, a mechanism may be implemented to prohibit reading from the FIFOs 21 for a predetermined number of clock ticks after a reset of the synchronization device 10, in order to allow time for the FIFOs 21 to fill. When read control in FIFOs uses rotation operations on binary read masks, as described above with reference to [Fig.6], the bits are ordered from left to right (or right to left) in the same order cyclic than the FIFOs with which they are respectively associated. It can be noted, however, that it is not essential that the index of a bit of a read mask corresponds to the index of the FIFO with which it is associated. In accordance with what was previously described with reference to [Fig.5], it is possible to use an additional indication providing information on the validity of the samples at the clock tick considered. In such a case, the reading in the FIFOs 21 as well as the updating of the reading masks RM,, RM,, and RM; would be conditioned by this indication of validity of the samples. [Fig.7] schematically represents a particular mode of implementation of the control of the permutation network 23. In the example considered, the permutation network 23 is an electronic circuit capable of carrying out binary rotation operations. At the current clock tick, the rotation to be carried out is defined according to the SC indication (“Shift Control”). More particularly, the SC indication makes it possible to define the number of bits to be shifted according to the rotation operation. The indication SC corresponds to a counter 64 whose current value is defined as a function of the value of said counter 64 at the previous clock tick and as a function of the time error indication Err-Ind supplied by the interpolation module 30 at the previous clock tick. Updating the counter 64 at each clock tick as a function of the time error indication Err-Ind makes it possible to identify the FIFO 21 from which the next samples must be supplied to the interpolation module 30. The number of bits with which the value of counter 64 is encoded is equal to the ceiling (i.e. the nearest higher integer) of the binary logarithm of 2 x P Ge-[iog (@ x P)}> i.e. three bits in the example considered (P = 4 and A2 [tog-(8)} =3. At the current clock tick, the control unit 22 is configured to update the counter 64, for the next clock tick, by performing a modulo 2 x P addition of the current value of the counter 64 with the value P, P- 1 or P + 1 depending on whether the time error indication Err-Ind provided by the interpolation module 30 is respectively “nominal”, “underflow” or “overflow”. The choice of the value to be used depending on the time error indication Err-Ind is implemented by the multiplexer 62. The modulo 2 x P addition is implemented by the adder 63 (this is a 2 x P bit adder). It can be noted that choosing the value P as a power of two makes it possible to simplify the hardware implementation of the adder 63 (an N-bit adder directly returns a modulo 2N sum). As previously stated, at one clock tick, each interpolator 32 takes as input four samples made available by the storage and reordering module 20. In the example considered, there are four interpolators 32 (P = 4); seven samples are made available to the four interpolators 32 (P + 3 = 7). Each of these seven samples corresponds to the first sample available in a FIFO 21 (i.e. to the sample indicated by the read pointer of this FIFO, or in other words to the sample which will be read at the next reading of this FIFO). The value SC of the counter 64 indicates the order in which these samples must be made available to the interpolation module 30 (the counter 64 indicates the index of the FIFO 21 from which the next samples must be made available to the interpolation module 30).In other words, if we consider the concatenation of the binary values ​​of the samples available at a current clock stroke, the reordering of the samples to be supplied to the interpolation module 30 amounts to carrying out a binary rotation of a number of bits equal to the value SC of the counter 64 multiplied by the size in bits of a sample. The table below gives an example of the SC values ​​taken by the counter 64 at successive clock ticks as well as the FIFOs to be used to make samples available to the interpolation module 30. In the table below, the notation CK represents a clock tick of index p; the notation SC corresponds to the SC value of the counter 64 for the current clock tick; the notation “Next SC” corresponds to the SC value of the counter 64 after updating for the next clock tick. [Tables 3] |ex |Err-Ind |sc [Next SC FIFOs used to make samples available to the interpolation module = _f of o 4 FIFO, to FIFO, E o FIFO, to FIFO, then FIFO» to FIFO; : qe 5 |FIFO, to FIFO, CKpr Normal 5 1 FIFO; to FIFO, then FIFO, to FIFO; CK,s (Normal | 1 5 |FIFO, to FIFO, CK,4 Overflow |S 0 FIFOs to FIFO, then FIFO, to FIFO; | lower CKyss |Overflow 0 3 |FIFO, to FIFOs fr su 3 xs -|FrFOs to FIFO, then FIFO, to FIFO, If there has been no reading from the FIFOs at the current clock tick, for example due to a risk of shortage, following a reset, or if the samples are not valid, then counter 64 is not updated and the sample reordering step is not performed. [Fig. 8] schematically represents the main steps of a method 100 for operating a symbol time synchronization device according to the invention, in particular a symbol time synchronization device 10 such as that described above with reference to FIGS. 2 to 7. At a current clock tick, and in a nominal case (i.e. when the input samples are valid and there is no indication of a risk of shortage or overflow in the FIFOs), the method 100 comprises the following steps: a 101 write of a sample in each of P successive FIFOs 21 which were not used in writing at the previous clock tick, a 102 reading of a sample in each of P, P- 1, or P + 1 FIFOs 21 successive depending on whether the time error indication Err-Ind provided by the interpolation module 30 is respectively "nominal", "overshoot "lower" or "overflow"; FIFOs 21 in which a sample must be read being defined according to the FIFOs 21 in which samples were read at the previous clock tick, a reordering 103 of the samples to be provided to module 30 interpolation based on a counter 64 whose current value is set based on the value of counter 64 at the previous clock tick and depending on the time error indication Err-Ind provided by the interpolation module 30 at the previous clock stroke, a supply 104 of the reordered samples to the interpolation module 30. The solutions presented in the description above make it possible to implement in a relatively simple and particularly effective manner a symbol time synchronization device 10 with parallel architecture capable of supporting very high data rates. The particular embodiments described in particular with reference to FIGS. 5 to 7 are particularly advantageous since they make it possible to dynamically rearrange the samples to be supplied to the interpolation module 30 using binary rotation operations that are relatively inexpensive in terms of hardware implementation and calculation time. It should however be noted that these particular embodiments have been described as non-limiting examples, and that other variants are consequently conceivable. The invention has been described by considering optical or radio space communications systems with bit rates greater than 100 Mbits / s. However, nothing precludes, following other examples, considering other communications systems, in particular terrestrial communications, for example cellular communications.

Claims

Claims

1. Device (10) for symbol time synchronization with parallel architecture, configured to be clocked by a clock, and comprising: a storage and reordering module (20) of samples comprising a control unit (22) and 2 x P buffers (21) of the "first in, first out" type out”, or FIFOs (21), P being an even integer greater than or equal to to four, each FIFO (21) being able to memorize several samples, the FIFOs (21) being cyclically ordered, an interpolation module (30) configured to provide each clock tick an indication of time error (Err-Ind) determined from samples from the storage and reordering module (20), said time error indication (Err-Ind) taking a value among "nominal", "undershoot" or "de- "superior pass", at a current clock stroke, the control unit (22) is configured to write a sample into each of P FIFOs (21) suc- transfers that have not been used in writing at the time previous clock, read a sample from each of P, P-1, or P+1 FIFOs (21) successive depending on whether the time error indication (Err-Ind) is respectively “nominal”, “exceedance lower" or "overflow", the FIFOs (21) in which a sample must be read being defined according to FIFOs (21) in which samples were read at previous clock stroke, reorder samples to be provided to the module (30) interpolation using a permutation network (23) and in function of a counter (64) whose current value is defined depending on the value of said counter (64) at the clock stroke previous and depending on the time error indication (Err-Ind) provided by the interpolation module (30) at the stroke previous clock.

2. Synchronization device (10) according to claim 1 in which writing to FIFOs (21) is controlled by a write mask (WM) binary comprising 2 x P bits, each bit being respectively associated with a FIFO (21) and indicating whether or not said FIFO (21) should be used in writing, the write mask (WM) can take two distinct possible values ​​(WM,, WM) each presenting exactly P bits indicating that the associated FIFOs (21) must be used in writing, said values ​​(WM,, WM;) not presenting any bit in common, and the control unit (22) is configured to change the value of the write mask (WM) at each clock stroke.

3. Synchronization device (10) according to any one of the claims- dications ] to 2 in which the reading in the FIFOs (21) is controlled by three binary reading masks (RM,, RM;, RM;) comprising each 2 x P bits ordered cyclically, each bit being respec- tively associated with a FIFO (21) and indicating whether said FIFO (21) must or not be used in reading, each reading mask (RM,, RM,, RM:z) being associated respectively with one of the three possible values ​​of the time error indication (Err-Ind), each reading mask (RM,, RM,, RM;) having exactly P, P- 1 or P + | bits successive indicating that the associated FIFOs must be used in reading depending on whether the reading mask (RM,, RM,, RM:) is associated res- respectively to the indication "nominal", "undershoot" or " overshoot”, and the control unit (22) is configured, for said current clock stroke, for: identify the reading mask (RM,, RM, RM;3) to use in function of the time error indication (Err-Ind), update each read mask (RM,, RM;, RM:), for the next clock stroke, by rotating binary (51) of the current value of said reading mask (RM 1, RM3, RM;) of P, P- 1 or P + 1 bits depending on whether the indication of temporal error (Err-Ind) is respectively “nominal”, “undershoot” or “overshoot”.

4. Synchronization device (10) according to any one of the claims- indications 1 to 3 in which, to reorder the samples to be provided to the interpolation module (30), the control unit (22) is configured to control the permutation network (23) to perform a binary rotation on said samples by a number of bits set from the current value of the counter (64), update the counter (64), for the next clock tick, by performing an addition modulo 2 x P of the current value of the counter (64) with the value P, P - 1 or P+ | depending on whether the time error indication (Err-Ind) is respectively "nominal", "undershoot" or "overshoot" superior ".

5. A receiving device of a communications system comprising a synchronization device (10) according to any one of the re- dications | to 4.

6. Satellite (70) comprising a receiving device according to claim 5.

7. A satellite (70) according to claim 6 wherein the commu- nications is a space communications system offering a throughput of data at least equal to 100 Mbit / s.

8. Method (100) of operating a synchronization device (10) of symbol time with parallel architecture, said device (10) of syn- timing being regulated by a clock and comprising: a storage and reordering module (20) of samples including 2 x P buffer memories (21) of first in, first out type, or FIFOs (21), P being a even integer greater than or equal to four, each FIFO (21) able to store several samples, the FIFOs (21) being cyclically ordered, an interpolation module (30) configured to provide each clock tick an indication of time error (Err-Ind) determined from samples from the storage and reordering module (20), said time error indication (Err-Ind) taking a value among "nominal", "undershoot" or "de- "superior pass", said method (100) comprises, at a current clock stroke: a write (101) of a sample in each of P FIFOs (21) successive which were not used in writing at the time previous clock, a reading (102) of a sample in each of P, P- 1, or P + 1 successive FIFOs (21) depending on whether the error indication temporal (Err-Ind) is respectively “nominal”, "undershoot" or "overshoot", the FIFOs (21) in which a sample must be read being defined according to the FIFOs (21) in which samples were read at the previous clock tick, a reordering (103) of samples to be provided to the module (30) of interpolation according to a counter (64) whose current value is set based on the value of the counter (64) at the previous clock stroke and depending on the time error indication (Err-Ind) provided by the module (30) interpolation to the previous clock stroke, a supply (104) of the reordered samples to the module (30) interpolation.

9. The method (100) of claim 8 wherein the writing (101) in the FIFOs (21) is controlled by a binary write mask (WM) comprising 2 x P bits, each bit being associated respectively with a FIFO (21) and indicating whether or not said FIFO (21) should be used in writing, the write mask (WM) can take two values ​​(WM 1» WM;) distinct possible numbers each having exactly P bits indicating that the associated FIFOs (21) must be used for writing, said values ​​(WM,, WM:) having no bits in common, and the value of the write mask (WM) is changed at each clock tick.

10. Method (100) according to any one of claims 8 to 9 in which the reading (102) in the FIFOs (21) is controlled by three binary reading masks (RM,, RM, RMz) each comprising 2 x P cyclically ordered bits, each bit being associated respectively with a FIFO (21) and indicating whether or not said FIFO (21) should be used in reading, each reading mask (RM,, RM,, RM3) being associated respectively to one of the three possible values ​​of the error indication temporal (Err-Ind), each reading mask (RM,, RM,, RM3) comprising exactly P, P- 1 or P + 1 successive bits indicating that the associated FIFOs must be used in reading depending on whether the mask reading (RM,, RM,, RM;) is associated respectively with the indication “nominal”, “undershoot” or “overshoot”, and reading (102) includes: an identification of the reading mask (RM,, RM,, RM;) to use according to the time error indication (Err-Ind), an update of each reading mask (RM,, RM,, RM; ), for the next clock stroke, by rotating binary (51) of the current value of said reading mask (RM 1 RM, RM;) of P, P- 1 or P + | bits depending on whether the indication of temporal error (Err-Ind) is respectively “nominal”, “undershoot” or “overshoot”.

11. A method (100) according to any one of claims 8 to 10 in which reordering (103) of the samples to be provided to the module (30) interpolation in FIFOs (21) includes: a binary rotation operation, on said samples, of a number of bits defined from the current value of the counter (64), a counter update (64), for the clock tick following, by making an addition modulo 2 x P of the value current counter (64) with value PP, P-louP+1 depending on whether the time error indication (Err-Ind) is respect- tively “nominal”, “undershoot” or “de- "superior pass".

12. A method (100) according to any one of claims 8 to 11 in which each FIFO (21) is configured to activate an indication (44) risk of overflow when the number of stored samples in said FIFO (21) is greater than or equal to a threshold, and the writing (101) in the FIFOs (21) is authorized if and only if the indication (44) of overflow risk is not activated for any of the FIFOs (21).

13. Method (100) according to any one of claims 8 to 12 in which each FIFO (21) is configured to activate an indication (54) risk of shortage when the number of samples stored in said FIFO (21) is less than or equal to a threshold, and the reading (102) in FIFOs (21) is authorized if and only if the risk indication (44) shortage is not activated for any of the FIFOs (21).

14. A method (100) according to any one of claims 8 to 13 in which the frequency of the symbols at the output of the synchronization device (10) nization is greater than or equal to 100 Mbits / s.