A process for bonding two layers that reduces stress

Abstract

Title: Stress-Reducing Two-Layer Bonding Method The invention relates to a method for bonding a layer based on a first material and a layer based on a second material. The method comprises a step of supplying a stack (1) comprising a first layer (100) based on the first material, preferably silicon-based, and a second layer (200) based on the second material. The first and second materials are preferably distinct. The first layer has a first upper face (101). The method then provides a step of forming, from its first upper face through its entire thickness, a network of trenches (120) in the first layer. The stack is then subjected to a consolidation anneal. Figure for the abstract: Fig. 1C

Description

Title of the invention: Method for bonding two layers reducing stress technical field

[0001] The present invention relates to the bonding of two layers, preferably one silicon-based, involving consolidation annealing. It is particularly relevant to the manufacture of optoelectronic and microelectronic devices. For example, it finds a particularly advantageous application in the field of display technologies. STATE OF THE ART

[0002] Bonding, particularly direct bonding, is a technique commonly used in the fields of optoelectronic systems, microelectromechanical systems, and integrated circuits. Direct bonding consists of gluing two elements, typically two wafers, without an interlayer. For example, hydrophilic direct bonding typically takes place in three stages: pretreatment of the wafers, initial bonding at room temperature, and finally, high-temperature consolidation annealing, typically above 100°C. This consolidation annealing strengthens the molecular bonds between the two wafers (Van der Waals forces, hydrogen bonds, covalent bonds, etc.), as these bonds are very weak after simple bonding at room temperature. It is therefore necessary for satisfactory adhesion of the two wafers. However, this step has a major drawback.Indeed, it is common for the two plates to be composed of materials with very different coefficients of thermal expansion (CTE). Consequently, during consolidation annealing, the stress level at the interface between the two plates, and more generally in the stack formed by the two plates, is very high, leading to delamination of the stack, or even its failure. This drawback is all the more problematic when the materials involved have different coefficients of thermal expansion and their bonding requires a high consolidation annealing temperature.

[0003] A solution sometimes used consists of thinning at least one of the two layers in order to allow some relaxation of the stresses generated by consolidation annealing, but this technique does not allow one to overcome the problems of degradation in a satisfactory way.

[0004] The present invention therefore aims to provide a solution to limit the degradation of the stack during consolidation annealing. SUMMARY

[0005] To achieve this objective, according to one embodiment, a bonding process is provided for a layer based on a first material and a layer based on a second material comprising the following steps: a. Provide a stack comprising a layer based on a first material, preferably silicon-based, called the first layer, and a layer based on a second material, called the second layer, the first material preferably being different from the second material, the first layer having an initial thickness eioojni, the first layer having a first lower face opposite a face of the second layer, called the second upper face, and a first upper face opposite the first lower face, b. Form in the first layer, starting from the upper surface of the first layer and extending through its entire thickness, a network of trenches, and c. Subject the stack to a consolidation anneal.

[0006] The trenching step in the first layer allows for stress relaxation in the stack, these stresses being due to the difference between the coefficients of thermal expansion (CTE) of the first and second materials. The annealing step of the stack, which can, for example, be carried out at a temperature above 100°C, or even above 200°C, then allows for consolidation of the stack. The process thus makes it possible to obtain a solid stack while minimizing delamination and fracture phenomena. BRIEF DESCRIPTION OF THE FIGURES

[0007] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0008] [Fig. 1A] Figures IA to 1F illustrate the steps of the process according to one embodiment of the invention. [Fig. 1A] represents the supply of a stack comprising at least a first and a second layer.

[0009] [Fig. IB] Fig. IB illustrates a thinning step of the first layer.

[0010] [Fig.1C] [Fig.1C] illustrates a stage of trench formation in the first layer as well as in a first active layer that is part of the stacking.

[0011] [Fig. 1D] The [Fig. 1D] illustrates an annealing step of the stack.

[0012] [Fig.1E] Fig.1E illustrates a thinning step of the first layer.

[0013] [Fig.1F] [Fig.1F] illustrates a step of filling the trenches with a material filling.

[0014] [Fig. 2A] Fig. 2A represents an alternative embodiment of the process according to the invention and more specifically a trench formation step in the first layer without these trenches extending into the first active layer.

[0015] [Fig.2B] Figures 2B and 2C illustrate an embodiment of the process according to the invention in which the first active layer comprises buried electrical contact resumption zones.

[0016] [Fig.2C]

[0017] [Fig.3] Fig.3 illustrates a top view of the trench network.

[0018] [Fig.4] Fig.4 illustrates a cross-sectional view of the first and second layers and first and second active layers, in the case where the first active layer comprises a plurality of photo-elements and the second active layer includes photo-element control electronics.

[0019] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0020] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0021] According to one embodiment, the first material has a coefficient of thermal expansion ai and the second material has a coefficient of thermal expansion a2, ai and a2 being distinct, preferably with | (ara2) / ai | >k*ab with k>l,7.

[0022] According to one embodiment, the method further comprises, after the trench network formation step, a trench filling step with a filler layer. This allows the stack to be planarized so as to proceed with other conventional microelectronic steps.

[0023] According to one embodiment, the trench filling step is carried out after the annealing step.

[0024] According to one embodiment, the filling layer is based on a dielectric material. The dielectric material may be organic or mineral. Among the possible dielectric materials are polymers, for example polyimide. It is also possible to opt for SiO2, a mineral dielectric material.

[0025] According to an advantageous example, consolidation annealing is carried out at an annealing temperature Trecuitsorpérieuree of 100°C.

[0026] According to an advantageous example, the annealing temperature Trecuitest is greater than 200°C.

[0027] According to one embodiment, the method further comprises, before the stacking supply step, the following step: a. Perform a bonding of the first layer onto the second layer at a bonding temperature Tconage below 100°C, preferably below 40°C.

[0028] According to an advantageous example, the annealing temperature Trecuit is higher than the bonding temperature Tconage.

[0029] According to one embodiment, the bonding step includes the implementation of at least one technique among direct fusion bonding, direct hydrophilic bonding and eutectic bonding.

[0030] According to one embodiment, the method further comprises, after the stacking supply step and before the trench network formation step, the following step: a. Thin the first layer from the first top surface until it has an intermediate thickness e»»,inter-

[0031] According to one embodiment, the process further comprises, after the annealing step, a thinning step of the first layer until it has a final thickness eioo,finale- This makes it possible to reach stacking thickness levels that cannot be reached when thinning the entire plate.

[0032] According to one embodiment, the first material is based on at least one of sapphire and GaN.

[0033] According to one embodiment, the trench network comprises a set of parallel trenches extending along a second direction and having, along a first direction normal to the second direction, a dimension called trench width li2o,x, and in which the trenches extending along the second direction are separated two by two by islands, each having, along the first direction, a dimension called first island dimension ln0,x, the ratio lno,x / li2o,x being called first shape ratio.

[0034] According to one embodiment, the first aspect ratio is less than 10, preferably less than 4.

[0035] According to one embodiment, the first aspect ratio is greater than 0.1, preferably greater than 0.25.

[0036] According to one embodiment, the stack further comprises a first active layer and a second active layer in contact respectively with the lower face of the first layer and the upper face of the second layer.

[0037] According to one embodiment, the first active layer comprises a plurality of photo-elements, each photo-element being configured to be able to emit a beam of light.

[0038] According to one embodiment, the second active layer comprises an electronic ordering of the photo-elements of the first active layer.

[0039] According to one embodiment, the control electronics include CMOS transistors.

[0040] According to one embodiment, the process further comprises, before the stacking supply step, the following step: a. Perform a bonding of the first active layer onto the second active layer at a bonding temperature Tconage below 100°C, preferably below 40°C.

[0041] According to one embodiment, the first active layer includes metallic areas for electrical contact resumption and the island and trench network formation step is configured to update at least part of at least some of the electrical contact resumption areas.

[0042] According to one embodiment, the second active layer includes metallic areas for electrical contact resumption and the island and trench network formation step is configured to update at least part of at least some of the electrical contact resumption areas.

[0043] A film based on a material A is understood to be a film comprising that material A and possibly other materials.

[0044] A photo-element is defined as an element capable of emitting or receiving a beam of light. A photo-element can, for example, be an active 3D structure, such as an active wire or nanowire.

[0045] A 3D structure is said to be active when it includes an active region and is electrically connected, thus enabling it to emit light radiation.

[0046] A wire or nanowire is defined as a 3D structure elongated along its longitudinal axis. The longitudinal dimension of the 3D structure, along the Z axis in the figures, is greater, and preferably much greater, than the transverse dimensions of the 3D structure in the XY plane in the figures. For example, the longitudinal dimension is at least five times, and preferably at least ten times, greater than the transverse dimensions. A nanowire is a wire with transverse dimensions less than 1 pm (1 pm = 10⁶ m).

[0047] In this patent application, the terms "light-emitting diode," "LED," or simply "diode" are used synonymously. An "LED" may also be understood to mean a "micro-LED." A "micro-LED" is an LED whose dimensions do not exceed 100 µm.

[0048] The terms "approximately," "about," and "in the order of" mean, when referring to a value, "to the nearest 20%" or even "to the nearest 10%" of that value, or, when referring to an angular orientation, "to the nearest 20°" or even "to the nearest 10°" of that orientation. Thus, a direction substantially normal to a plane means a direction presenting an angle of 90+20° or even 90+10° with respect to the plane.

[0049] A frame of reference, preferably orthonormal, comprising the X, Y, Z axes is shown in the attached figures.

[0050] The process according to an embodiment of the invention will now be described with reference to figures IA to 1F.

[0051] As illustrated in [Fig. IA], a first step consists of providing a stack 1 comprising at least a first layer 100 and a second layer 200. The first layer 100 is based on a first material, preferably silicon-based. The first layer 100 can, for example, be based on one of the following materials: Si, SiC, SiGe.

[0052] The first layer 100 has a first upper face 101 and a first lower face 102, both extending mainly in planes parallel to the XY plane of the orthogonal coordinate system. It has an initial thickness ε₀.μ₀ along the Z direction. The initial thickness is typically greater than 500 pm, for example, approximately 750 pm, a classic value in the microelectronics industry. The second layer 200 also has an upper face 201 and a lower face 202, both extending mainly in planes parallel to the XY plane of the orthogonal coordinate system. The upper face 201 of the second layer 200 and the lower face 102 of the first layer 100 are opposite each other. The second layer 200 can, for example, be based on one of the following materials: Sa, GaN, glass...

[0053] Note that, although the proposed method shows its interest mainly when the first and second materials have different coefficients of thermal expansion between them, and therefore when the first and second materials are different from each other, it can nevertheless be carried out with first and second layers based on the same material.

[0054] The stacking may also include, as illustrated in [Fig.1A], a first active layer 150 and / or a second active layer 250. These two active layers 150, 250 are typically structured layers.

[0055] Advantageously, the first active layer 150 comprises a plurality of LEDs. Each of these LEDs can be formed by a plurality of photoelements 155, which can be three-dimensional (3D) structures such as nanowires. A "photoelement" is understood to be an active element, that is, one capable of emitting radiation, but it is understood that each of these elements can be electrically powered or not and thus be "on" or "off". An active photoelement or active nanowire comprises an active region and is typically electrically connected. This active region is the site of radiative recombination of electron-hole pairs, resulting in light radiation having a principal wavelength. The active region typically includes a plurality of quantum wells, for example formed by emissive layers based on GaN, InN, InGaN, AlGaN, AIN, AlInGaN, GaP, AlGaP, AlInGap, AlGaAs, GaAs, InGaAs, AlIlAs, or a combination of several of these materials.

[0056] Advantageously, the second active layer 250 comprises driver electronics 255 or control electronics 255 for the LEDs included in the first active layer 150. This driver electronics 255 is typically based on CMOS (Complementary Metal-Oxide-Semiconductor Transistors) 256 transistors. Alternatively, it may be based on TFT thin-film transistors. Advantageously, the control electronics 255 include connection pads opposite the photoelements 155 of the first active layer 150.

[0057] An optional step (not illustrated in the figures) consists, prior to the stacking supply step, of bonding the first layer 100 to the second layer 200. This may in particular be a full-plate bond: the first layer 100 and the second layer 200 may have the dimensions of microelectronic wafers (for example a diameter of 200 or 300 mm) and be bonded to each other on the entirety of one of its two faces.

[0058] This bonding step is typically carried out at a bonding temperature Tconage below 100°C. For example, a bonding temperature Tconage below 40°C is referred to as room temperature bonding. If the stack 1 comprises the first active layer 150 and the second active layer 250 described previously, a bonding step between these two active layers 150 and 250 is typically performed.

[0059] The bonding of these two layers—the first layer 100 and the second layer 200, or the first active layer 150 and the second active layer 250—can be direct bonding or indirect bonding. In the case of direct bonding, it is possible, for example, to implement a fusion bonding process. In the specific case of two layers with a silicon-based surface, this technique is classically based on the presence of water molecules on the surface of the two layers to be bonded. When the two layers are brought into contact, hydrophilic bonds form between the two surfaces. This is referred to as hydrophilic direct bonding. Fusion bonding can also be applied to a so-called hybrid bond between two layers, each having at least two distinct materials on its surface (for example, copper and SiO2).It is understood that any other bonding technique carried out at low temperature, that is to say typically at a temperature below 100°C, is also conceivable.

[0060] An optional step shown in [Fig. IB] consists of pre-thinning the first layer 100 is thinned from its upper face 101. This step reduces the thickness of the first layer 100 from an initial thickness eioo.ini to an intermediate thickness Gioo,inter. This pre-thinning can be achieved by grinding or chemical-mechanical polishing of the first layer 100 from its upper face 101. This optional pre-thinning step is performed before the trenching step described below. It allows for an initial relaxation of the stresses due to the difference in CTE between the first layer 100 and the second layer 200. It provides some flexibility to the first layer 100. It also facilitates trenching in the first layer 100 and improves its accuracy.

[0061] The intermediate thickness ei00,inter of the first layer 100 after pre-thinning is advantageously greater than 300 pm. This helps to limit the weakening of the interface between the first layer 100 and the second layer 200 (or the first active layer 150 and the second active layer 250). Indeed, at this stage of the process, these layers adhere to each other only through weak bonds (Van der Waals, hydrogen bonds, etc.) that are not yet consolidated. Excessive thinning of the first layer 100 could lead to delamination. Maintaining a first layer 100 thickness greater than 300 pm before the bond consolidation annealing (which will be described later below) helps to preserve the good structural quality of the different layers, and in particular of the first layer 100.

[0062] Figure IC illustrates a second step, consisting of the formation of a network of trenches 120 in the first layer 100. The trenches 120 are formed from the first upper face 101 of the first layer 100 and extend through its entire thickness. Thus, the depth of the trenches, taken along the Z direction, can be substantially equal to ei00,im, or to ei00,inter if the optional step of pre-thinning the first layer 100 prior to the formation of the trenches is implemented.

[0063] The network of trenches 120 may comprise trenches 120 that are substantially parallel to each other and extend mainly along the Y direction, as shown in [Fig. 1C]. It may also comprise a set of trenches 120 that are substantially parallel to each other and extend mainly along a direction distinct from the Y direction, typically the X direction, normal to the Y direction. This example is illustrated in [Fig. 3].

[0064] The trenches 120 extending primarily along the Y direction each have a trench width denoted li20,x, taken along dimension X. The trenches 120 extending primarily along the X direction each have a secondary trench width denoted 1i20.y, taken along dimension Y. The trench width li20,x and the secondary trench width 1i20,y are typically equal. For example, they are between 5 pm and 100 pm, preferably between 10 pm and 30 pm.

[0065] The trenches 120 are separated by islands 110 formed by the remaining parts of the first layer 100 after the formation of the trenches 120. The islands 110 therefore have, at this stage of the process and along the Z direction, a dimension equal to that of the trenches 120: eioojniOu ei00,inter, depending on whether or not the pre-thinning step of the first layer 100 has been implemented. Along the X direction, the islands 110 have a dimension called the first island dimension l110,x. By construction, this first dimension is equal to the spacing between two consecutive trenches 120 extending along the Y direction. If the network of trenches 120 also includes a set of trenches 120 extending along the X direction, the islands 110 are, in the XY plane, rectangular in shape and preferably square and have along the Y direction a dimension called second island dimension 111O,Y.This second dimension is by construction equal to the spacing between two consecutive trenches 120 extending along the Y direction. The first island dimension ln0>x and the second island dimension ln0.y are advantageously equal to each other. Such symmetry allows for uniformity in the mechanical relaxation of the first layer 100 resulting from the formation of trenches 120. In this case, the islands 110 have a square shape in the XY plane.

[0066] A first aspect ratio is further defined as the ratio between the first island dimension lno^ and the trench width li20jX. This first aspect ratio is advantageously greater than 1 and / or less than 100. A second aspect ratio is also defined as the ratio between the second island dimension 111O,Y and the secondary trench width li20>Y, also advantageously greater than 1 and / or less than 100. These aspect ratios are preferably substantially equal to each other.

[0067] The trenches 120 – and, by design, the islands 110 – can be formed in various ways. For example, the trenches 120 can be formed mechanically using a blade cutting tool. Laser cutting or plasma cutting can also be used to form these trenches 120.

[0068] In all cases, the formation of the trenches 120 can be followed by a step of removing potential residues due to this formation.

[0069] A third step, illustrated in [Fig. 1D], consists of subjecting the stack 1 to a consolidation anneal. This consolidation anneal is typically carried out at a temperature above 100°C, preferably above 200°C and advantageously above 400°C. It consolidates the bond between the first layer 100 and the second layer 200, or between the first active layer 150 and the second active layer 250. A simple bond of the two layers—the first layer 100 and the second layer 200, or the first active layer 150 and the second layer—is also achieved. Active 250 – without consolidation annealing – does not always allow for a sufficiently high level of adhesion between the layers for the intended applications or the technological steps to be followed. The adhesion energy between the two layers involved typically increases from a value of less than 1 J / m² before consolidation annealing to a value approximately equal to or greater than 5 J / m² after this annealing.

[0070] Figure 1E represents an optional post-thinning step of the first layer 100. This step reduces its thickness from the initial thickness ε00ji (or the intermediate thickness ε00,inter if pre-thinning of the first layer 100 was performed prior to trench formation 120) to a final thickness ε00,finale. The final thickness ε00,finale constitutes a target thickness, preferably chosen according to the intended applications. It is preferably less than 200 pm, typically approximately 150 pm. For applications in particularly thin electronic chips, the final thickness can be set at a value less than 20 pm, advantageously less than 15 pm. This post-thinning step makes it possible to achieve thickness levels that cannot be attained by conventional full-plate thinning.

[0071] Fig. 1F illustrates an optional step of filling trenches 120 with a filling layer 300.

[0072] The filling layer 300 is preferably based on one or more polymers, such as a polyimide.

[0073] Such filling makes it possible to flatten the stack 1 so that other conventional microelectronic steps can be carried out following the implementation of the process.

[0074] It should be noted that the trench filling step can be carried out after, but preferably before, the post-thinning step described above. If the filling is carried out before the thinning, the islands of the first layer 100 and the filling layer 300 can then be thinned simultaneously.

[0075] Advantageously, the filling step is carried out after consolidation annealing. However, if the filling layer 300 is made of materials whose melting temperature is higher than the annealing temperature Trecuit, the trench filling step 120 can also be carried out before consolidation annealing.

[0076] According to a particular embodiment of the invention, the step of forming the trenches 120 in the first layer 100 is immediately followed by, or carried out simultaneously with, a step of forming additional trenches 120' in the first active layer 150 and in the second active layer 250. It is possible for all the trenches 120 to be extended by an underlying additional trench 120', as illustrated in [Fig. 1C]. It is also possible to select the trenches 120 from which the additional trenches are formed. 120'. In all cases, the first active layer 150 and the second active layer 250 can thus be "diced" to form "smart pixels," each composed of a portion of the first active layer 150 and a portion of the second active layer 250, facing each other. The control element(s) included in the portion of the first active layer 150 then allow the control of the photo-elements 155 included in the portion of the second active layer 250 located opposite each other.

[0077] According to one embodiment of the invention, the first active layer 150 comprises buried electrical contacts electrically connected to metallic contact restoration zones 160, as illustrated in [Fig. 2B]. Advantageously, the trench formation step 120 is designed to expose these contact restoration zones 160. It should be noted that the presence of these contact restoration zones 160 is particularly advantageous during the formation of the trenches 120 in the first layer 100. Indeed, the presence of metal causes the etching process to stop ([Fig. 2C]). The etching is therefore physically limited by the contact restoration zones 160 and not by theoretical etching time calculations, which depend on numerous parameters and can be inaccurate. This improves the accuracy of the trench formation 120.

[0078] The buried electrical contacts and the 160 contact points allow electrical testing to be carried out in the stack 1. These 160 contact points can then be removed. Several methods are possible for this (laser, cutting blade, etc.).

[0079] The recovery areas 160 can for example be redistribution layers of an integrated circuit, commonly referred to by the English acronym "RDL" (for "Redistribution Layers").

[0080] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Demands

1. A method for bonding a layer based on a first material and a layer based on a second material comprising the following steps: • Providing a stack (1) comprising a layer based on a first material, preferably silicon-based, referred to as the first layer (100), and a layer based on a second material, referred to as the second layer (200), the first material preferably being different from the second material, the first layer (100) having an initial thickness ε₀μ₁, the first layer (100) having a first lower face (102) opposite a face of the second layer (200), referred to as the second upper face (201), and a first upper face (101) opposite the first lower face (102), • Forming in the first layer (100), from the first upper face (101) of the first layer (100) and throughout its thickness, a network of trenches (120),and • Subject the stack (1) to a consolidation annealing of said bonding of said first layer (100) and said second layer (200).

2. A method according to the preceding claim, wherein the first material has a coefficient of thermal expansion ai and the second material has a coefficient of thermal expansion a2, ai and a2 being distinct, preferably with (ara2) / ai >k*ab with k>l,7.

3. A method according to any one of the preceding claims further comprising, after the trench network formation step (120), the following step: • Filling the trenches (120) with a filling layer (300).

4. A method according to the preceding claim in which the trench filling step (120) is carried out after the annealing step.

5. A method according to any one of the two preceding claims, wherein the filling layer (300) is based on a di- material electrical, for example a polymer.

6. A method according to any one of the preceding claims wherein the consolidation annealing is carried out at an annealing temperature T greater than 100°C.

7. A process according to the preceding claim in which the annealing temperature Trecuit is greater than 200°C.

8. A method according to any one of the preceding claims comprising further, before the stacking supply step (1), the following step: • Bonding the first layer (100) to the second layer (200) at a bonding temperature Tcouage below 100°C, preferably below 40°C.

9. A method according to the preceding claim in which the annealing temperature Trecuit is greater than the bonding temperature Tcouage.

10. A method according to any one of the two preceding claims wherein the bonding step comprises the implementation of at least one technique among direct fusion bonding, direct hydrophilic bonding and eutectic bonding.

11. A method according to any one of the preceding claims comprising further, after the stacking step and before the trench network formation step (120), the following step: • Thinning the first layer (100) from the first upper face (101) until it has an intermediate thickness e loo,inter-

12. A method according to any one of the preceding claims comprising further, after the annealing step, the following step: • Thinning the first layer (100) until it has a final thickness e100,finaie-

13. A method according to any one of the preceding claims wherein the second material is based on at least one of sapphire and GaN.

14. A method according to any one of the preceding claims, in in which the network of trenches (120) comprises a set of parallel trenches extending along a second direction (Y) and having along a first direction (X) normal to the second direction (Y) a dimension called trench width l^x, and in which the trenches extending along the second direction (Y) are separated two by two by islands (110) each having along the first direction (X) a dimension called first island dimension lno.x, the ratio lno,x / li2o,x being called first shape ratio.

15. A method according to the preceding claim wherein the first aspect ratio is less than 10, preferably less than 4.

16. A method according to any one of the two preceding claims wherein the first aspect ratio is greater than 0.1, preferably greater than 0.

25.

17. A method according to any one of claims 1 to 7 and 11 to 16, wherein the stack (1) further comprises a first active layer (150) and a second active layer (250) in contact respectively with the lower face (102) of the first layer (100) and the upper face (201) of the second layer (200).

18. A method according to the preceding claim, wherein the first active layer (150) comprises a plurality of photo-elements (155), each photo-element (155) being configured to be able to emit a beam of light.

19. Method according to the preceding claim, wherein the second active layer (250) comprises control electronics (255) of the photo-elements of the first active layer (150).

20. Method according to the preceding claim wherein the control electronics comprise CMOS transistors (256).

21. A method according to any one of the four preceding claims comprising further, before the stack supply step (1), the following step: • Performing a bonding of the first active layer (150) onto the second active layer (250) at a bonding temperature Tcoiiage below 100°C, preferably below 40°C.

22. A method according to any one of the two preceding claims, wherein the first active layer (150) comprises metallic electrical contact re-establishment zones (160) and wherein the step of the formation of the island network (110) and trenches (120) is configured to update at least part of some at least of the electrical contact resumption zones (160).

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