Method of data communication between a slave device and a master device, and corresponding integrated system.

Abstract

One aspect concerns a method for communicating data between a slave device (SLV) and a master device (HST) according to a communication protocol (SDIO). The data is stored in a memory belonging to the slave device (SLV). The method includes the master device generating a command (CMD) as defined by the communication protocol, and using a field of the command (RegAdd) to select an indirection register (DMAi_BAdd; DMAi_Sz) belonging to the slave device and containing an address of a memory region (MEM) containing the data. Figure 2 for the abstract

Description

Title of the invention: Method for communicating data between a slave device and a master device, and corresponding integrated system.

[0001] Embodiments and implementations relate to methods of communicating data in an integrated system, in particular communications according to the “SDIO” standard for “Secure Digital Input Output” defined by the “SD Association” group.

[0002] Communication of the “SDIO” type between a master device and a slave device is conventionally carried out using standard-specific commands.

[0003] SDIO commands are defined by the standard and contain fixed fields, intended to contain useful information such as an indication of the type of command (a "command index"), a function number, the address of the read / write data to be transferred, etc.

[0004] The SDIO standard allows for a possibility of 8 functions. Function 0 is reserved to implement the standard. Functions 1 to 7 are free. Each function can be mapped into its own memory space.

[0005] The standard allows a 17-bit address field for direct and extended read / write commands (usually "IO_RW_DIRECT" and "IO_RW_EXTENDED" respectively).

[0006] This limits the address range to 128 kB (kilo Bytes).

[0007] Even using the 7 functions, the range of 128kB*7 = 896kB is not sufficient for cases of use of functionalities of the slave device, such as for example for sending and receiving data packets, placed in a memory of the slave device implementing a WiFi type communication.

[0008] In order to increase the size of the address range accessible in the memory with SDIO commands, it has been proposed to use a linked list of descriptors in the memory of the slave device. However, this prior solution has the disadvantages of not being able to program the linked list by the master device, nor to control the address range by the master device, and of being limited in volume per transmission, for example limited to 128kB per transmission.

[0009] There is thus a need to benefit from greater flexibility in SDIO communications, in particular in order to allow larger transfers.

[0010] Aspects and modes of implementation and embodiment defined below propose indirect addressing via an indirection register, allowing access of the direct memory access channel type, so that a single read or write command can reach any memory region (e.g. up to 1 MB) anywhere in memory (e.g. 4 GB).

[0011] Furthermore, the indirection register can be configured by the master device, so as to benefit from a functionality adapted to the needs and capacity of the master device on the one hand, or by the slave device, so as to be able to impose security measures, such as firewall-type filtering, in access to the memory on the other hand.

[0012] According to one aspect, there is provided in these respects a method of communicating data between a slave device and a master device according to a communication protocol, the data being recorded in a memory belonging to the slave device, the method comprising a generation by the master device of a command provided by said communication protocol, and a use of a field of the command in order to select an indirection register belonging to the slave device and containing an address of a region of the memory comprising the data.

[0013] According to one embodiment, the communication protocol provides that the field of the command is intended to contain an address of a memory location on a first number of bits; the indirection register comprising a second number of bits greater than the first number to contain the address of the region of the memory containing the data.

[0014] According to one embodiment, the indirection register contains a base address and the size of the memory region containing the data.

[0015] For example, with 32-bit registers for the base address and 20-bit registers for the memory region size, the communicated data may be 1 MB in size within the full extent of a 4 GB memory.

[0016] According to one embodiment, the use of the command field comprises: - a code, on the most significant bits of the field, to identify the indirection register which contains the address of the region of the memory containing said data, among several indirection registers of the slave device containing addresses of other respective regions of the memory; and - a quantization, on the least significant bits of the field, of an address offset positioning the start of the data location in the region.

[0017] According to one embodiment, said command further comprises the size of the data of said communication.

[0018] Thus, in these two modes of implementation, the master device can precisely define in the command the start and end addresses (by the size of the location) of the memory data.

[0019] According to one mode of implementation, the communication protocol follows the “Secure Digital Input Output - SDIO” communication standard defined by the group “SD Association”, and wherein the command is an extended block read / write command.

[0020] According to one embodiment, the method further comprises another use of the command field in order to address a register of a function according to said protocol, comprising a dedicated code on the most significant bits of the field to identify this other use.

[0021] According to another aspect, there is also provided an integrated system comprising a slave device and a master device capable of communicating data between them according to a communication protocol, the data being recorded in a memory belonging to the slave device, the master device being configured to generate a command provided by said communication protocol, and to use a field of the command in order to select an indirection register belonging to the slave device and capable of containing an address of a region of the memory comprising the data.

[0022] According to one embodiment, the communication protocol provides that the field of the command is intended to contain an address of a memory location on a first number of bits; the indirection register being capable of comprising a second number of bits greater than the first number to contain the address of the region of the memory comprising the data.

[0023] According to one embodiment, the indirection register is capable of containing a base address and the size of the memory region containing the data.

[0024] According to one embodiment, the master device is configured to use the command field by incorporating therein: - a code, on the most significant bits of the field, for identifying the indirection register containing the address of the region of the memory containing said data, among several indirection registers of the slave device containing addresses of other respective regions of the memory; and - a quantization, on the least significant bits of the field, of an address offset positioning the start of the data location in the region.

[0025] According to one embodiment, the master device is configured to further incorporate into said command the size of the data of said communication.

[0026] According to one embodiment, the slave device and the master device are able to communicate data between them according to the communication protocol following the “Secure Digital Input Output - SDIO” communication standard defined by the “SD Association” group.

[0027] According to one embodiment, the master device is further configured to otherwise use the field of the command in order to address a register of a function according to said protocol, by incorporating therein a respectively dedicated code, on the bits of strong weights of the field, to identify this other use.

[0028] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment, which is in no way limiting, and the appended drawings in which the figures:

[0029] [Fig.l] ;

[0030] [Fig.2] ;

[0031] [Fig.3] ;

[0032] [Fig.4] ;

[0033] [Fig.5] ;

[0034] [Fig.6] ;

[0035] [Fig.7] illustrate embodiments and implementations of the invention.

[0036] [Fig.l] illustrates an example of an integrated system SOC, such as a system on chip, comprising a master device HST, usually called "host" or "host" in English, and a slave device SLV capable of communicating data between them, according to a communication protocol on an SDIO channel.

[0037] The master device HST is for example the application processor of the integrated system, while the slave device SLV is for example a peripheral providing the resources to implement a given functionality, for example a wireless communication functionality of the Wifi type.

[0038] The master device HST and the slave device SLV are for example produced on the same fully integrated silicon chip of the system-on-chip type, or else according to separate chips connected to the same printed circuit board (usually "PCB" for "Printed Circuit Board" in English) in the integrated system.

[0039] The SLV slave device comprises in particular an SDIOS slave interface adapted to the “Secure Digital Input Output” communication protocol defined by the standard established by the “SD Association” group, a MEM memory and an internal central unit adapted for said functionality.

[0040] The SDIOS slave interface notably and advantageously comprises at least one DMAi indirection register ([Fig.2]), designed to contain an address of a region of the MEM memory, which can be selected by the master device in a suitable command CMD ([Fig.5]) of the communication protocol.

[0041] Indeed, the master device is advantageously configured to generate the CMD command ([Fig.5]) provided by said communication protocol, adapted by the use of a field of the RegAdd command ([Fig.5]) in order to select the DMAi indirection register of the slave device. Thus, the device can reach in the MEM memory the address contained in the DMAi indirection register, for example in the context of a data communication in reading or writing in MEM memory.

[0042] [Fig.2] illustrates an example of the implementation of the SDIOS slave interface.

[0043] On the one hand, the SDIOS interface comprises general purpose input / output terminals GPIO, an SD / SPI_INTF bus interface compatible with the SDIO protocol (or even with other protocols, such as the serial data bus protocol "SPI" for "Serial Peripheral Interface" in English), comprising for example a command and response interface CMD_RESP_INTF, an input data interface D_IN_INTF, an output data interface D_OUT_INTF.

[0044] The SD / SPI_INTF bus interface can be controlled by a control device which can include a state machine SDIO_FSM, a command decoder CMD_DEC, a response generator RESP_GEN, and communicate, via multiplexing circuits, with incoming buffers WDFIFO and outgoing buffers RDFIFO of a master bus controller AHB_MSTR_CONT and with register banks SDIO_F0_STDREG, SDIO_F1_REG.

[0045] The master bus controller AHB_MSTR_CONT, for example a bus of the type "AHB" (for "Advanced High-performance Bus" in English), can for example generate communications to the internal central unit of the slave device SLV on a respective master bus port AHB_MSTR_PRT and receive a clock signal from the master bus ahbm_clk. In addition, communications from the slave AHB bus can be received on a slave bus port AHB_SLV_PRT as well as a clock signal from the slave bus ahbs_clk.

[0046] Other incoming and outgoing sdios_sgnl_i / o signals, of general use and following the SDIO protocol, may be provided without being exhaustively detailed here.

[0047] On the other hand, a reserved bank of registers SDIO_F0_STDREG, and a first bank of registers SDIO_F1_REG are provided in the SDIOS slave interface.

[0048] The reserved register bank SDIO_F0_STDREG, as required by the respective SDIO standard, includes the instructions CCCRx, FIBRx, allowing the implementation of the SDIO protocol. The SDIO protocol also allows seven other distinct functions to exploit the resources of the SLV slave device.

[0049] The first register bank SDIO_F1_REG makes it possible to implement a first function of the SLV slave device. The first function may possibly be the only function of the SDIO protocol used by the SLV slave device. In other words, all the resources of the SLV slave device can be accessed by implementing a single function of the SDIO protocol. This may for example be the case of an SLV slave device implementing wireless communications of the Wifi type.

[0050] The first register bank SDIO_F1_REG may include, for example, a control register SDIOS_CTRL, an internal interrupt register INTRL_IT and event notification to the host HST_EVNT, an external interrupt register EXTRL_IT and event notification to the peripheral SLV_EVNT.

[0051] The first bank SDIO_F1_REG further advantageously comprises at least one indirection register DM Ai capable of containing an address of a region of the memory MEM comprising data to be read or written on command from the master device HST. An address, as such, typically makes it possible to locate in the memory a byte of bits, for example an 8-bit byte, depending on the granularity of the memory access. By "address of a region of the memory" is meant for example a start address of the region, as well as the size of the region, or alternatively an end address of the region. The indirection register DMAi is in this respect for example capable of containing a base address DMAi_BAdd and the size DMAi_Sz of the region of the memory containing the data.

[0052] [Fig.3] illustrates an example of a 32-bit DMAi_BAdd register belonging to one of the DMAi indirection registers to contain a base address of a region of the MEM memory.

[0053] Thus, on 32 bits, any address of a 4 GB (giga Byte) memory can be contained in the base address register DMAi_BAdd.

[0054] From the point of view of read and write accesses “rw”, the contents of the base address register DMAi_BAdd can for example: - be accessed in writing exclusively by the HST master device, and be accessed in reading by the HST master device and by the SVL slave device; or - be accessed in writing and reading exclusively by the SLV slave device.

[0055] [Fig.4] illustrates an example of a 32-bit DMAi_BAdd register belonging to one of the DMAi indirection registers, in which 20 bits are allocated to quantify the size of the MEM memory region.

[0056] Thus, on 20 bits, sizes from 1 bit to 1 MB (mega Byte) can be contained in the DMAi_Sz region size register.

[0057] From the point of view of read and write accesses “rw”, the contents of the region size register DMAi_Sz can for example be accessed in write mode exclusively by the master device HST, or exclusively by the slave device SLV; and, in both cases, be accessed in read mode by the master device HST and by the slave device SVL.

[0058] [Fig.5] illustrates a CMD command issued by the HST master device, and provided for by said communication protocol following the “Secure Digital Input Output” standard defined by the “SD Association” group, and which is for example and in particular an extended block read / write command.

[0059] A 6-bit CMD_INDX field is provided to communicate index or identifier of the command. In this example, the index 110101 in binary (53 in decimal) makes it possible to identify the extended command (as opposed to the “direct command” of said protocol), allowing in particular reading / writing by bytes or by blocks, depending on the BLC bit.

[0060] A field of the RegAdd command is used in a manner provided by the standard but nevertheless compatible with the standard, in order to select a DMAi indirection register belonging to the slave device and containing an address of a region of the MEM memory containing the data.

[0061] The RegAdd command field is intended, in the communication protocol according to the standard, to contain an address of a memory location on a first number of bits less than the second number of bits communicating the address of the memory region in the indirection registers DMAi, DMAi_BAdd, DMAi_Sz. In the SDIO standard protocol, the RegAdd field has 17 bits (first number), which is much less than the 32 bits (second number) of the base address register DMAi_BAdd.

[0062] The use of the RegAdd field of the CMD command can advantageously comprise a code on the most significant bits of the field, to identify the indirection register DMAi which contains the address of the region of the memory containing said data, among several indirection registers of the slave device containing addresses of other respective regions of the memory; and a quantification, on the least significant bits of the field, of an address offset AddOffst ([Fig.6]) positioning the start of the location RgAdd / CMD ([Fig.7]) of the data in the region RgAdd / DMAi ([Fig.7]). Reference will be made in particular to [Fig.6].

[0063] Furthermore, the CMD command includes in a 9-bit BYT / BLC CNT field provided for this purpose, the number of data to be communicated (or transferred) with this CMD command, counted over a number of bytes (BYT) or blocks (BLC) of size fixed in a register which may be larger than one byte.

[0064] The CMD command includes other classic fields S, D, E, #FCT, OPC, CRC7 which are not detailed here.

[0065] [Fig.6] illustrates an example of code on the most significant bits of the RegAdd field, making it possible to select a DMAi indirection register from among two indirection registers “DMA0”, “DMAI”, or from among eight indirection registers “DMAO-7”. Each indirection register contains the addressing of different memory regions.

[0066] On the one hand, firstly 61, the code "111" can be provided on the three most significant bits 16, 15, 14 to identify a standard use of the RegAdd field, i.e. addressing with the remaining fourteen least significant bits 13-0 of the SDIO_F1_REG registers of the first function, internal to the slave interface peripheral SDIOS.

[0067] On the other hand, in case 62, 64 of selection among two indirection registers, it is possible to provide on the two most significant bits 16, 15, the codes “Ox” (with x=0 or 1) to identify the respective indirection registers DMAi (i=[0;l]).

[0068] The quantification of the address offset AddOffst can be done on the remaining low-weight bits 14:0, or 14:1 if bit 0 is reserved "r", for example in order to communicate an end of session; that is to say up to 64 kB (kilo Byte) or respectively 32 kB. This corresponds in particular to a technique of alignment in the middle of the memory word (usually "half-word aligned offset" in English).

[0069] In case 63, 65 of selection from eight indirection registers, the codes “Ixxx” (with xxx=[000;001;010;011;100;101]) can be provided on the four most significant bits 16, 15, 14, 13 to identify the respective DMAi indirection registers (i=[2;3;4;5;6;7]). The registers DMA0, DMAI can be identified in the same way as previously described “Ox” in cases 62, 64.

[0070] The quantization of the address offset AddOffst can be done on the remaining low-weight bits 12:0, or 12:1 if bit 0 is reserved "r", for example in order to communicate an end of session; that is to say up to 16 kB (kilo Byte) or respectively 8 kB. This again corresponds to a technique of alignment in the middle of the memory word (usually "half-word aligned offset" in English).

[0071] [Fig.7] illustrates the MEM memory of the slave device SLV, and in particular the method of accessing data contained in the MEM memory according to the technique using the CMD command and the DMAi indirection register as described previously in relation to Figures 1 to 6.

[0072] The data of the RgAdd / CMD communication is located between a start address “start@” and an end address “end@”, in a RgAdd / DMAi memory region.

[0073] The contents of the DMAi indirection register define the address range of the memory region RgAdd / DMAi; in particular by a base address DMAi_BAdd in the base address register, and by a region size DMAi_Sz in the region size register.

[0074] The contents of the CMD command, in addition to the identification code of the DMAi indirection register to be used, define the address range of the data of the RgAdd / CMD communication, by positioning the start address start@ with the address offset AddOffst relative to the base address BMAi_BAdd of the region, and the end address with the CNT count of bytes or blocks of the respective 9-bit field of the CMD command.

[0075] Thus, in summary, embodiments and implementations have been described, in which function 1 of the SDIO protocol makes it possible to benefit from up to 8 channels "direct memory access" protocols configured with DMAi indirection registers, for example to provide a 32-bit base address and a 20-bit memory region size, providing 1 MB of data per channel over a 4 GB memory range. The SDIO protocol particularly allows such transfers in multiple block mode, such as the extended block read / write command. Access to memory regions is further advantageously configurable by the HST host or by the SLV peripheral, while the communication data is finely positioned in the region by information in the content of the CMD command.

Claims

Claims

1. Method for communicating data between a slave device (SLV) and a master device (HST) according to a communication protocol (SDIO), the data being recorded in a memory belonging to the slave device (SLV), the method comprising a generation by the master device of a command (CMD) provided for by said communication protocol, and a use of a field of the command (RegAdd) in order to select an indirection register (DMAi_BAdd; DMAi_Sz) belonging to the slave device and containing an address of a region of the memory (MEM) comprising the data.

2. The method of claim 1, wherein the communication protocol provides that the field of the command (RegAdd) is intended to contain an address of a memory location on a first number of bits; the indirection register (DMAi_BAdd; DMAi_Sz) comprising a second number of bits greater than the first number to contain the address of the region of the memory containing the data.

3. The method of claim 2, wherein the indirection register contains a base address (DMAi_BAdd) and the size (DMAi_Sz) of the region of memory containing the data.

4. Method according to one of claims 1 to 3, in which the use of the field (RegAdd) of the command (CMD) comprises: - a code (0 x), on the most significant bits of the field (16 15), to identify the indirection register which contains the address of the region of the memory containing said data, among several indirection registers of the slave device containing addresses of other respective regions of the memory; and - a quantification, on the least significant bits of the field (14:0), of an address offset (AddOffst) positioning the start of the location (RgAdd / CMD) of the data in the region (RgAdd / DMAi).

5. The method of claim 4, wherein said command further comprises the size (CNT) of the data of said communication.

6. Method according to one of claims 1 to 5, in which the communication protocol follows the “Secure Digital Input Output - SDIO” communication standard defined by the “SD Association” group, and in which the command (CMD) is an extended block read / write command.

7. Method according to one of claims 1 to 6, further comprising another use of the field of the command (RegAdd) in order to address a register (SDIO_F1_REG) of a function according to said protocol, comprising a respectively dedicated code (111) on the most significant bits of the field (16 15 14) to identify this other use.

8. Integrated system comprising a slave device (SLV) and a master device (HST) capable of communicating data between them according to a communication protocol (SDIO), the data being recorded in a memory (MEM) belonging to the slave device (SLV), the master device being configured to generate a command (CMD) provided by said communication protocol, and to use a field of the command (RegAdd) in order to select an indirection register (DMAi_BAdd; DMAi_Sz) belonging to the slave device and capable of containing an address of a region of the memory (MEM) comprising the data.

9. Integrated system according to claim 8, in which the communication protocol provides that the field of the command (RegAdd) is intended to contain an address of a memory location on a first number of bits; the indirection register (DMAi_BAdd; DMAi_Sz) being capable of comprising a second number of bits greater than the first number to contain the address of the region of the memory comprising the data.

10. An integrated system according to claim 9, wherein the indirection register is adapted to contain a base address (DMAi_BAdd) and the size (DMAi_Sz) of the region of memory containing the data.

11. Integrated system according to one of claims 8 to 10, in which the master device is configured to use the field (RegAdd) of the command (CMD) by incorporating therein: - a code (0 x), on the most significant bits of the field (16 15), to identify the indirection register containing the address of the region of the memory containing said data, among several indirection registers of the slave device containing addresses of other respective regions of the memory; and - a quantification, on the least significant bits of the field (14:0), of an address offset (AddOffst) positioning the start of the location (RgAdd / CMD) of the data in the region (RgAdd / DMAi).

12. An integrated system according to claim 11, wherein the master device is configured to further incorporate into said command the size (CNT) of the data of said communication.

13. Integrated system according to one of claims 8 to 12, in which the slave device (SLV) and the master device (HST) are capable of communicating data between them according to the communication protocol following the “Secure Digital Input Output -SDIO” communication standard defined by the “SD Association” group, the master device being configured to generate the command (CMD) of the extended block read / write command type.

14. Integrated system according to one of claims 8 to 13, in which the master device is further configured to otherwise use the field (RegAdd) of the command (CMD) in order to address a register (SDIO_F1_REG) of a function according to said protocol, by incorporating therein a respectively dedicated code (111), on the most significant bits of the field (16 15 14), to identify this other use.

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