Electronic device for X-ray capture and image display

Abstract

Electronic X-ray Capture and Image Display Device This description relates to an electronic image capture and display device (100) comprising a plurality of pixels (PIX) formed in and on a semiconductor substrate (101), each pixel comprising: – an X-ray detection element (103) (105), located on the side of a first face (101F) of the semiconductor substrate (101); – a visible light emission element (107) (109), located on the side of a second face (101R) of the semiconductor substrate opposite the first face; and – a circuit located in and on the semiconductor substrate and connecting the detection element to the emission element. Figure for the abstract: Fig. 1

Description

Title of the invention: Electronic device for X-ray capture and image display. Technical field

[0001] This description relates generally to electronic devices, and in particular to electronic devices for capturing and displaying images. Prior art

[0002] Electronic devices capable of implementing image capture and display functions have been proposed. Such devices typically include an image sensor, comprising an image capture pixel array, and an image display, comprising an image display pixel array distinct from the image capture pixels.Depending on the application, the image capture and display pixel arrays of the device may be located on one side of the same face of a semiconductor substrate, for example in the case of a mobile phone, smartwatch or tablet computer including a display screen incorporating an image sensor for acquiring a user's fingerprints, or may be located on opposite sides of the semiconductor substrate, for example in the case of a head-mounted display, head-up display or smart glasses including one or more display screens intended to be placed each in front of a user's eye and one or more image sensors facing outwards.

[0003] Existing electronic image capture and display devices, however, suffer from various drawbacks. In particular, in these devices, the pixels of the image sensor are typically connected to a control circuit and a readout circuit, and the pixels of the image display are connected to a control circuit different from the control and readout circuits for the pixels of the image sensor. These circuits, which are, for example, located on the periphery of the pixel arrays of the sensor and the image display, implement addressing functions for the pixel arrays to which they are respectively connected, and the images acquired by the sensor are, for example, stored in a memory circuit before being displayed, possibly after processing. This introduces an undesirable latency between the acquisition of an image by the sensor and the display of the corresponding image by the display.Furthermore, existing electronic image capture and display devices are complex, bulky, heavy, energy-intensive, and expensive to manufacture.

[0004] X-ray imaging devices have been proposed, in particular. Among the devices Among the known positives of X-ray imaging, there are more specifically indirect conversion devices and direct conversion devices.

[0005] Indirect conversion devices comprise a photodiode array adapted to capture light radiation, and a scintillator disposed above the photodiode array. During operation, the scintillator emits light following the absorption of X-rays. The light emitted by the scintillator is converted into electrical charges by the photodiodes. Thus, the photodiode array acquires an image representative of the light distribution emitted by the scintillator, this light distribution being itself representative of the X-ray distribution received by the scintillator.

[0006] Direct conversion devices comprise a layer of a conversion semiconductor material adapted to directly convert absorbed X-rays into electrical charges. The conversion layer is arranged above an array of elementary circuits adapted to read the electrical charges generated in the conversion material. During operation, the conversion layer generates electrical charges as a result of X-ray absorption. These charges are read by the readout circuit array. Thus, the readout circuit array directly acquires a representative image of the X-ray distribution received by the conversion material.

[0007] In any case, the sensor and the display are separate and require complex peripheral circuits to ensure their control. Summary of the invention

[0008] It would be desirable to overcome all or part of the drawbacks of existing electronic image capture and display devices. In particular, there is a need to reduce the weight, size, complexity, energy consumption, manufacturing costs and / or latency of these devices.

[0009] To this end, one embodiment provides an electronic image capture and display device comprising a plurality of pixels formed in and on a semiconductor substrate, each pixel comprising: - an X-ray detection element, located on the side of a first face of the semiconductor substrate; - a visible light-emitting element, located on the side of a second face of the semiconductor substrate opposite the first face; and - a circuit located in and on the semiconductor substrate and connecting the sensing element to the emitting element.

[0010] According to one embodiment, the circuit comprises: - an acquisition circuit located in and on the semiconductor substrate and adapted to to provide an acquisition signal representative of the intensity of the X-ray radiation received by the pixel's detection element; and - a control circuit located in and on the semiconductor substrate and adapted to apply a control signal to the emitting element of the pixel.

[0011] According to one embodiment, the acquisition circuit and the control circuit are analog circuits.

[0012] According to one embodiment: - each detection element includes a photodetector; - Each acquisition circuit includes a comparator with an inverting input connected to a conduction electrode of the photodetector; and - each control circuit includes an inverter having an input connected to an output of the comparator and an output connected to a gate of a MOS transistor, the MOS transistor having a conduction electrode connected to the emitting element.

[0013] According to one embodiment, each emission element comprises a single light-emitting diode.

[0014] According to one embodiment, the light-emitting diode is controlled by a control signal having pulses repeating at a frequency substantially proportional to an intensity of the X-ray radiation detected by the detection element.

[0015] According to one embodiment: - each detection element includes a photodetector; - Each acquisition circuit includes a signal conditioning circuit; and - each control circuit includes a multilevel comparator having one input connected to one output of the signal shaping circuit and at least two outputs each connected to a gate of a MOS transistor by an inverter, each MOS transistor including a conduction electrode connected to a light-emitting diode of the emitting element.

[0016] According to one embodiment, each emission element comprises exactly three light-emitting diodes.

[0017] According to one embodiment, the detection elements are located opposite the emission elements.

[0018] According to one embodiment, the detection elements and the emission elements are arranged respectively in first and second matrices, the first and second matrices having substantially identical steps.

[0019] According to one embodiment, the device comprises as many detection elements as emission elements.

[0020] According to one embodiment, the device further comprises a scintillator overcoming the detection elements.

[0021] According to one embodiment, the device further comprises a converter based on a perovskite material surmounting the detection elements.

[0022] One embodiment provides a method for manufacturing a device as described above, the method comprising a step of transferring, by molecular bonding, a structure comprising the detection elements and the circuits onto another structure comprising the emission elements. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1] is an isometric, schematic and partial view of an image capture and display device according to one embodiment;

[0025] [Fig.2] is an equivalent electrical diagram of a pixel of the device of [Fig.1] according to one embodiment;

[0026] [Fig.3] is an equivalent electrical diagram of a pixel of the device of [Fig.1] according to another embodiment;

[0027] [Fig.4] is a chronogram illustrating, schematically and partially, an example of the operation of the pixel of [Fig.3];

[0028] [Fig.5] is an equivalent electrical diagram of a pixel of the device of [Fig.1] according to yet another embodiment;

[0029] [Fig.6] is a chronogram illustrating, schematically and partially, an example of the operation of the pixel of [Fig.5];

[0030] Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D, Fig. 7E, Fig. 7F, Fig. 7G, Fig. 7H, Fig. 7I, Fig. 7J, Fig. 7K and Fig. 7L illustrate, by schematic and partial cross-sectional views, structures obtained at the end of steps in a manufacturing process of the device of Fig. 1 according to an embodiment;

[0031] [Fig. 8] is a schematic and partial top view of an interconnection network of the device in [Fig. 1]; and

[0032] [Fig.9A] and [Fig.9B] illustrate, by means of schematic and partial cross-sectional views, structures obtained at the end of successive stages of a manufacturing process of the device of [Fig.1] according to another embodiment. Description of the implementation methods

[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the various applications that the described X-ray imaging devices may have have have not been detailed, as the described embodiments are compatible with all or most known X-ray imaging applications, and especially applications that can benefit from large X-ray imaging devices, for example, devices with lateral dimensions greater than 10 cm, preferably greater than 20 cm. Furthermore, the implementation of the photosensitive diodes, the electronic control circuits, and the scintillator of the described devices has not been detailed, as the implementation of these elements is within the capabilities of a person skilled in the art based on the information provided in this description.

[0035] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 10%, preferably within 5%.

[0038] In the following description, the terms "insulating" and "conducting" mean, unless otherwise specified, electrically insulating and electrically conductive respectively.

[0039] The term "transmittance of a layer" refers to the ratio of the intensity of radiation exiting the layer to the intensity of radiation entering the layer. In the following description, a layer is said to be opaque to radiation when its transmittance for that radiation is strictly less than 40%, preferably less than or equal to 25%, and more preferably less than or equal to 10%. Conversely, a layer is said to be transparent to radiation when its transmittance for that radiation is greater than or equal to 40%, preferably greater than or equal to 75%, and more preferably greater than or equal to 90%. The preceding definitions of the terms opaque and transparent are not limited to the case of a layer, but apply more generally to any element likely to be exposed to radiation, for example, a substrate, a region, or a stack of several layers, etc.

[0040] In this description, the term "visible light" refers to electromagnetic radiation with a wavelength between 400 nm and 700 nm. Furthermore, the terms "X-rays" and "X-ray radiation" refer to radiation consisting of photons with energies, for example, between 1000 eV (electronvolts) and 20 MeV (megaelectronvolts).

[0041] The [Fig.1] is an isometric, schematic and partial view of an image capture and display device 100 according to one embodiment.

[0042] According to this embodiment, the image capture and display device 100 comprises a plurality of PIX pixels formed in and on a semiconductor substrate 101.

[0043] Each pixel PIX of the device 100 comprises a detection element 103 for radiation 105 and, associated with the detection element 103, an emission element 107 for radiation 109. The detection elements 103 and emission elements 107 are located on either side of the semiconductor substrate 101, respectively. More precisely, in the illustrated example, the detection elements 103 are located on the side of a face 101F of the substrate 101, and the emission elements 107 are located on the side of a face 101R of the substrate 101, opposite face 101F. For the sake of simplifying the drawing, each detection element 103 and each emission element 107 has been symbolized, in [Fig. 1], by a parallelepiped having, in top view, a perimeter of substantially square shape. This example is not limiting, however, as each detection element 103 or emission element 107 may, as a variant, have any shape, for example cylindrical.

[0044] In the illustrated example, the PIX pixels of the device 100 are arranged in a matrix of rows and columns. More precisely, in this example, the detection elements 103 are arranged in a matrix of rows and columns. Similarly, the emission elements 107 are, in this example, arranged in a matrix of rows and columns. In each of these matrices, the rows are, for example, substantially orthogonal to the columns. This example is not, however, limiting; the rows may, alternatively, not be orthogonal to the columns.

[0045] By way of example, the device 100 comprises as many detection elements 103 as emission elements 107.

[0046] In the example shown, the emission element matrix 107 has a pitch, that is, a center-to-center distance between two adjacent emission elements 107, substantially equal to the pitch of the detection element matrix 103, that is, substantially equal to a center-to-center distance between two adjacent detection elements 103. Furthermore, in this example, the emission elements 107 are located opposite the detection elements 103. In the illustrated example, the center of each The emitting element 107 is located approximately directly above the center of the opposite detection element 103. The emitting elements 107, viewed from above, have lateral dimensions that are, within manufacturing variations, approximately equal to those of the detection elements 103. This example is not limiting, however; the emitting elements 107 may, alternatively, have different lateral dimensions, for example, larger or smaller than those of the detection elements 103. The respective dimensions, for example, their respective surface areas, of the detection elements 103 and emitting elements 107 are chosen, for example, based on the desired sensitivity of the detection elements 103 and / or the intensity to be achieved on the side of the emitting elements 107.

[0047] For example, the radiation 105 captured by the detection elements 103 is X-ray radiation. Furthermore, the radiation 109 emitted by the emission elements 107 is, for example, visible light.

[0048] Figure 2 is an equivalent electrical diagram of a PIX pixel of device 100. [Fig.1] according to one embodiment.

[0049] In the example shown, the detection element 103 of the pixel PIX includes a photodetector 201 adapted to capture the radiation 105. The photodetector 201 is, for example, adapted to produce, under the effect of the incident radiation 105, a current Iph, also called photocurrent. The photocurrent Iph is, for example, substantially proportional to an intensity, or flux, of the radiation 105 captured by the photodetector 201. In the illustrated example, the photodetector 201 has a first conduction terminal, for example an anode electrode, connected to a node 203 for applying a reference potential, for example ground. The photodetector 201 further comprises, in this example, a second conduction terminal, for example a cathode electrode, connected to a circuit 205. By way of example, the photodetector 201 is a photosensitive diode, or photodiode.

[0050] In the illustrated example, the circuit 205 includes an acquisition circuit 207, also called a conditioner or conditioning circuit. The acquisition circuit 207 is, for example, adapted to provide an acquisition signal representative of the intensity of the radiation 105 captured by the photodetector 201. The acquisition signal produced by the acquisition circuit 207 is, for example, a function of the photocurrent Iph, for example, substantially proportional to the photocurrent Iph. Alternatively, the acquisition signal is a function of a voltage across the photodetector 201, for example, substantially proportional to this voltage.

[0051] The acquisition circuit 207 allows, for example, the amplification of the photocurrent Iph and the provision of a drive voltage for the emitting element 107. For these purposes, the acquisition circuit 207 includes, for example, an amplifier symbolized in [Fig. 2] by a transistor. As an example, the amplifier is of the CTIA type (from the English “Capacitive Trans-Impedance Amplifier” - capacitive transimpedance amplifier) ​​or of the RTIA type (from the English “Resistive Trans-Impedance Amplifier” - resistive transimpedance amplifier).

[0052] In the example shown, the PIX pixel circuit 205 further includes a control circuit 209, or driving circuit. The control circuit 209 is, for example, adapted to apply a control signal to the transmitting element 107. The control signal provided by the control circuit 209 is, for example, a function of the acquisition signal, for example, substantially proportional to the acquisition signal.

[0053] In the example shown, the acquisition circuit 207 and the control circuit 209 each receive a calibration signal cal. The calibration signal cal allows, for example, compensation for manufacturing variations between the pixels PIX of the image capture and display device 100, for example, manufacturing variations affecting the detection element 103 and / or the emission element 107 of the pixels PIX. In practice, the acquisition circuit 207 receives, for example, a calibration signal different from that received by the control circuit 209. The calibration signal cal has, for example, a determined value for each pixel PIX, following a calibration step subsequent to the manufacturing steps of the image capture and display device 100. Alternatively, the calibration signal cal can be omitted.

[0054] In the illustrated example, the emitting element 107 of the PIX pixel includes a light-emitting diode 211 adapted to emit the radiation 109. The light-emitting diode 211 is, for example, more precisely adapted to emit the radiation 109 when it is traversed by a lied current, corresponding, for example, to the control signal applied by the control circuit 209. The lied current has, for example, an intensity substantially proportional to that of the photocurrent Iph, for example substantially proportional to the intensity of the radiation 105 captured by the photodetector 201. In the example illustrated in [Fig. 2], the light-emitting diode 211 has a first conduction terminal, for example an anode electrode, connected to the circuit 205, for example to an output of the control circuit 209.The light-emitting diode 211 further comprises, in this example, a second conduction terminal, for example a cathode electrode, connected to a node 213 for applying a potential -Vk, for example a low potential. The light-emitting diode 211 can be an organic or inorganic LED. The diode 211 is, for example, of the micro-LED type, that is to say, it has micrometer dimensions.

[0055] In the case where the lied current has an intensity substantially proportional to that of the photocurrent Iph, the acquisition circuits 207 and control circuits 209 are, for example, analog circuits. In this case, the circuit 205 is notably devoid of analog-to-digital converter.

[0056] Figure 3 is an equivalent electrical circuit of a PIX pixel of the device 100 of Figure 1 according to another embodiment. The equivalent electrical circuit illustrated in Figure 3 corresponds more precisely to a case in which the circuit 205 of the PIX pixel is adapted to control the emitting element 107 by a pulsed signal.

[0057] The diagram in [Fig. 3] includes elements in common with the diagram in [Fig. 2]. These common elements will not be detailed again below. In particular, the detection element 103 and the emission element 107 of the diagram in [Fig. 3] are, for example, identical to those of the diagram in [Fig. 2].

[0058] In the example shown, the acquisition circuit 207 of the PIX pixel includes a comparator 301 having an inverting input (-) connected to a node 303 of the acquisition circuit 207, a non-inverting input (+) connected to a node 305 for applying a reference potential Vref, and an output connected to a node 307 of the acquisition circuit 207. In the illustrated example, the cathode of the photodetector 201 is connected to node 303. Nodes 303 and 307 of the acquisition circuit 207 constitute, for example, input and output terminals of the acquisition circuit 207, respectively. In the illustrated example, nodes 303 and 307 have potentials Vsn and Vo, respectively.

[0059] In the example shown, the acquisition circuit 207 further includes a capacitive element 309, for example a capacitor, connecting node 303 to another node 311 for applying a reference potential, for example ground. The capacitor can be replaced or supplemented by a parasitic capacitance of node 303. In the illustrated example, the acquisition circuit 207 further includes a transistor 313, for example a MOS (Metal-Oxide-Semiconductor) transistor. In this example, the transistor 313 is more precisely an N-type MOS transistor. In the example shown, transistor 313 includes a conduction terminal, for example a source electrode, connected to node 303, another conduction terminal, for example a drain electrode, connected to a node 315 for applying a supply potential Vdd, and a control terminal, for example a gate electrode, connected to node 307.The potential Vdd, for example, is strictly greater than the potential Vref.

[0060] In the illustrated example, the control circuit 209 comprises an inverter 317 and a transistor 319. The inverter 317 comprises, for example, an input connected to node 307 of the acquisition circuit 207 and an output connected to a control terminal, for example, a gate electrode, of the transistor 319. The transistor 319 is, for example, more precisely a P-type MOS transistor (PMOS transistor). In the example shown, the PMOS transistor 319 comprises a conduction terminal, by for example a drain electrode, connected to the anode of the light-emitting diode 211 and another conduction terminal, for example a source electrode, connected to a node 321 applying a supply potential Va.

[0061] By way of example, the light-emitting diode 211 is controlled by a control signal having an average value substantially proportional to the intensity of the radiation 105.

[0062] Figure 4 is a timing diagram illustrating, schematically and partially, an example of the operation of the PIX pixel of Figure 3. The timing diagram of Figure 4 includes curves 401 and 403 illustrating an example of the evolution, as a function of time (t), of the potentials Vsn and Vo, respectively.

[0063] Between a time t0 and a time t1, subsequent to time t0, the photodetector 201 is exposed to radiation 105 and produces the photocurrent Iph. During this period, the photocurrent Iph is integrated by the capacitive element 309. The charges photogenerated by the photodetector 201 accumulate at node 303, thus causing a decrease in the potential Vsn. In the illustrated example, the potential Vsn of node 303 has, between times t0 and t1, a value between that of the potential Vdd and that of the potential Vref. Between times t0 and t1, the potential Vo of node 307 connected to the output of comparator 301 is, for example, at a low level.

[0064] At time t1, the potential Vsn reaches a value approximately equal to that of the reference potential Vref. This causes the output of comparator 301 to switch, thus causing the potential Vo to transition from a low level to a high level. Transistor 313 is then switched on, which connects node 303 to node 315. The photogenerated charges accumulated at node 303 between times t0 and t1 are thus discharged to node 315. This tends to bring the potential Vsn back to a value approximately equal to that of the supply potential Vdd.

[0065] At a time t2, later than time t1, the potential Vsn again becomes greater than the potential Vref. This causes the output of comparator 301 to switch, resulting in a transition of the potential Vo from the high level to the low level. Curve 403 thus illustrates a pulse of the potential Vo between times t1 and t2.

[0066] Between time t2 and a time t3, subsequent to time t2, curve 403 illustrates several other pulses of the potential Vo similar to that present between times t1 and t2. These pulses result, as explained above, from successive charges and discharges of the capacitive element 309 when the photodetector 201 is subjected to radiation 105 and produces the photocurrent Iph. The pulses that make up curve 403 between times t0 and t3 are repeated, for example, periodically, for example at a frequency fh.

[0067] Between a time t4, subsequent to time t3, and a time t5, subsequent to time t4, Curve 403 illustrates further impulses of the potential Vo, for example analogous to the impulses present between times t0 and t3.

[0068] The potential pulses Vo between times t4 and t5 differ, for example, from the potential pulses Vo between times t0 and t3 in that they repeat periodically at a frequency fl strictly lower than the frequency fh. This arises, for example, from the fact that the photodetector 201 produces, during an LF phase between times t4 and t5, a weaker photocurrent Iph, for example resulting from a decrease in the intensity of the radiation 105, than during another HF phase between times t0 and t3.

[0069] In the example shown, the frequencies fh and fl are representative of the photocurrent Iph, for example, substantially proportional to the photocurrent Iph. The frequencies fh and fl are, for example, substantially proportional to the intensity, or flux, of the radiation 105 captured by the photodetector 201. The light-emitting diode 211 is, for example, thus controlled by a periodic signal with a frequency substantially proportional to the intensity of the radiation 105 captured by the photodetector 201.

[0070] By way of example, the sensitivity of the PIX pixel is adjusted by modifying the value of the reference potential Vref, which limits the range of variation of the potential Vsn. In the example shown, for the same radiation intensity value 105, the closer the value of the potential Vref is to that of the potential Vdd, the higher the frequency of variation of the potential Vo. Conversely, the further the value of the potential Vref is from that of the potential Vdd, the lower the frequency of variation of the potential Vo.

[0071] The embodiments of the PIX pixel circuit 205 are not limited to the examples of the detection circuit 207 and control circuit 209 shown, and a person skilled in the art can, based on the information in this description, provide detection and control circuits different from those shown in relation to Figures 3 and 4. By way of example, a counter or a frequency divider can be provided in the control circuit 209 to allow adjustment of the frequency of variation of the potential Vo for each PIX pixel independently of the other PIX pixels. The adjustment is then carried out, for example, at the factory, for example, after manufacturing steps of the device 100, and involves, for example, a step of storing calibration values ​​in memory circuits of the device 100, for example, ROM (Read-Only Memory) or flash memory circuits.This avoids the need for addressing circuits in device 100. Other types of circuits, for example logarithmic response circuits, could also be used.

[0072] Figure 5 is an equivalent electrical diagram of a PIX pixel of device 100. [Fig.1] according to yet another embodiment. The diagram in [Fig.5] illustrates more precisely a case in which the emission element 107 of the PIX pixel is capable of emitting radiation 109R, 109G and 109B in different wavelength ranges depending on the energy of the incident X-ray 105.

[0073] The diagram in [Fig. 5] includes elements in common with the diagram in [Fig. 2]. These common elements will not be detailed again below.

[0074] In the example illustrated in [Fig.5], the second conduction terminal of the photodetector 201, for example its cathode electrode, is connected to a node 501 of the sensing element 103. In this example, node 501 is connected to an input of the circuit 205, more precisely to an input of the acquisition circuit 207.

[0075] Furthermore, in the example shown, the sensing element 103 includes a capacitive element 503, for example a capacitor, connecting node 501 to another node 505 for applying a reference potential, for example ground. The capacitor can be replaced or supplemented by a parasitic capacitance of node 501.

[0076] In the example shown, the detection circuit 207 includes a signal shaping circuit 511, here a current shaping circuit Iph. In this example, the circuit 511 has an input connected to node 501 and an output connected to the input of the control circuit 209. The circuit 511 is adapted to provide, at its output, a signal substantially proportional to the energy of the incident X-rays 105 captured by the photodetector 201. By way of example, the circuit 511 is implemented by a structure identical or analogous to those described in the publication by B. Dierickx et al. entitled "X-ray Photon Counting and Two-Color X-Ray Imaging Using Indirect Detection", Sensors, 2016, 16, 764.

[0077] In the example illustrated in [Fig.5], potentials Vsn' and Vo' are respectively present at node 501 and at the output of the signal shaping circuit 511.

[0078] In the example shown, the control circuit 209 includes a multilevel comparator 521, one input of which is connected to the output of the signal-shaping circuit 511. The multilevel comparator 521 more specifically comprises, for example, as illustrated in [Fig. 5], three comparators 523R, 523G, and 523B. Each comparator 523R, 523G, and 523B includes an inverting input (-) connected to the input of the multilevel comparator 521, that is, connected to the output of the circuit 511. The connections of the inverting inputs of comparators 523R, 523G, and 523B to the input of the multilevel comparator 521 have not been shown in [Fig. 5] in order to avoid cluttering the drawing. Furthermore, comparators 523R, 523G and 523B include non-inverting inputs (+) connected to application nodes of a potential VR, VG and VB, respectively.For example, the VR potential is strictly greater than the VG potential and the VB potential is strictly less than the VG potential.

[0079] In the illustrated example, the control circuit 209 further comprises three transistors 319R, 319G and 319B identical or analogous to the transistor 319 previously described in relation to [Fig. 3]. In this example, the transistors 319R, 319G and 319B each comprise a conduction terminal, for example a drain electrode, connected to a first conduction terminal, for example an anode electrode, of a light-emitting diode 211R, 211G or 211B, and another conduction terminal, for example a source electrode, connected to the potential application node 321. Each transistor 319R, 319G, 319B further includes a control terminal, for example a gate electrode, connected to the output of comparator 523R, 523G, 523B by an inverter (not detailed in [Fig.5]), for example analogous to inverter 317 of [Fig.3].

[0080] In a manner analogous to the light-emitting diode 211 previously described in relation to [Fig.3], the light-emitting diodes 21 IR, 21 IG and 21 IB comprise another conduction terminal, for example a cathode electrode, connected to the potential application node 213 -Vk.

[0081] In the example shown in [Fig. 5], the light-emitting diodes 21 IR, 21 IG and 21 IB are respectively traversed by currents IledR, IledG and IledB, and emit respectively the radiations 109R, 109G and 109B. By way of example: - 109R radiation is included in a first range of wavelengths of visible light, corresponding for example to red light; - 109G radiation falls within a second range of visible light wavelengths, different from the first range and corresponding, for example, to green light; and - 109B radiation is included in a third range of wavelengths of visible light, different from the first and second ranges and corresponding for example to blue light.

[0082] Figure 5 illustrates a case in which the multilevel comparator 521 of the control circuit 209 comprises three comparators connected respectively to the control terminals of three transistors, and in which the transmitting element 107 comprises three LEDs. This example is not, however, limiting. Alternatively, the multilevel comparator 521 may comprise a number of comparators other than three, for example, two or more than three, each associated with a transistor similar or identical to transistors 319R, 319G, and 319B, and / or the transmitting element 107 may comprise a number of LEDs other than three, for example, two or more than three. Furthermore, the number of LEDs in the transmitting element 107 may differ from the number of comparators 523 and the number of transistors 319 in the control circuit 209.

[0083] Figure 6 is a timing diagram schematically and partially illustrating an example of the operation of the PIX pixel of Figure 5. The timing diagram of Figure 6 includes a curve 601 illustrating an example of the evolution, as a function of time (t), of the potential Vo' present at the output of the signal-shaping circuit 511. The timing diagram of Figure 6 further includes three curves 603R, 603G, and 603B illustrating an example of the evolution, as a function of time t, of the currents IledR, IledG, and IledB, respectively.

[0084] Between a time t0' and a time tl', subsequent to time t0', the potential Vo' present at the output of circuit 511 is equal to a minimum value Vmin. The currents IledR, IledG and IledB are, for example, at a low level, for example substantially zero, between times t0' and tl'. This corresponds, for example, to a period during which no X-rays are detected by the photodetector 201.

[0085] In the example shown, at time tl', the incident X-ray 105 is detected by the photodetector 201. Between time tl' and a time t2', later than time tl', a potential pulse Vo' with a maximum value greater than the potential VR is produced at the output of the circuit 511. The currents IledR, IledG and IledB then each switch, at time tl', from a low level to a high level and then, at time t2', from the high level to the low level.

[0086] Curves 603R, 603G, and 603B illustrate, between time t2' and a time t3' subsequent to time t2', several other pulses of the currents IledR, IledG, and IledB similar to those present between times t1' and t2'. These pulses of the currents IledR, IledG, and IledB result, as explained above, from pulses of the potential Vo' greater than the potential VR.

[0087] Between time t3' and a time t4', subsequent to time t3', curves 603G and 603B illustrate other pulses of the currents IledG and IledB, for example analogous to the pulses present between times t0' and t3'. Between times t3' and t4', the current IledR is, for example, substantially zero. The pulses of the currents IledG and IledB between times t3' and t4' differ, for example, from the pulses of the currents IledR, IledG, and IledB between times t0' and t3' in that they result from pulses of the potential Vo', each having a maximum value between the potential VG and the potential VR. This is due, for example, to the fact that photodetector 201 captures, during an ME phase between times t3' and t4', an incident X-ray of lower energy than during another HE phase between times t0' and t3'.

[0088] Similarly, between time t4' and a time t5', later than time t4', curve 603B illustrates further pulses of the current IledB, for example analogous to the pulses present between times t3' and t4'. Between times t4' and t5', the currents IledR and IledG are, for example, significantly degraded. The pulses of the The current IledB between times t4' and t5' differs, for example, from the pulses of the currents IledG and IledB between times t3' and t4' in that they result from pulses of the potential Vo', each with a maximum value between the potential VB and the potential VG. This arises, for example, from the fact that the photodetector 201 captures, during a LE phase between times t4' and t5', X-rays of lower energy than during the ME phase between times t3' and t4'.

[0089] To simplify the drawing, [Fig. 6] illustrates a case in which the pulses of the currents IledR, IledG, or IledB repeat substantially periodically, at a frequency f, between time t0' and time t3', t4', or t5'. However, in practice, the repetition frequency of the pulses of the currents IledR, IledG, and IledB can vary between time t0' and time t3', t4', or t5', for example, depending on the intensity, or flux, of the incident X-ray 10⁵ radiation. At constant energy, for example, between times t3' and t4', the repetition frequency of the pulses of the currents IledG and IledB is higher the greater the intensity of the X-ray 10⁵ radiation.

[0090] The PIX pixel shown above in relation to Figures 5 and 6 has the advantage of allowing X-rays, or X-ray photons, of different energies to be represented by means of three different colors. More precisely: - if the energy of the X-ray radiation is such that the potential Vo' is greater than the potential VR (HE phase), diodes 21 IR, 21 IG and 21 IB are lit; - if the energy of the X radiation is such that the potential Vo' is between VG and VR (ME phase), diodes 21 IG and 21 IB are lit and diode 21 IR is off; - if the energy of the X radiation is such that the potential Vo' is between VB and VG (LE phase), diode 21 IB is on and diodes 21 IR and 21 IG are off; and - if the energy of the X radiation is such that the potential Vo' is less than VB, diodes 211R, 211Get211B are off.

[0091] As an alternative, a person skilled in the art is able to foresee, from the indications in this description, an electronic circuit interposed for example between the multilevel comparator 521 and the transistors 319R, 319G and 319B and comprising logic enabling to light only one of the diodes 21 IR, 21 IG and 21 IB for each phase HE, ME and LE, respectively.

[0092] In the examples set out above, the image capture and display device 100 is devoid of addressing circuits for the detection element matrices 103 and emission elements 107. The device 100 is further devoid of circuits and components for storing, or memorizing, images acquired by the detection elements 103 or images to be displayed by the emission elements 107.

[0093] One advantage of device 100 is that it has a lower weight, size, complexity, energy consumption, manufacturing costs and / or latency than existing capture and display devices of images.

[0094] Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D, Fig. 7E, Fig. 7F, Fig. 7G, Fig. 7H, Fig. 7I, Fig. 7J, Fig. 7K and Fig. 7L illustrate, by schematic and partial cross-sectional views, structures obtained at the end of steps in a manufacturing process of device 100 of Fig. 1 according to an embodiment.

[0095] Figure 7A illustrates more precisely a structure obtained after a step of forming an active stack of light-emitting diodes 703, or active LED stack, on the side of a face 701T of a support substrate 701 (the upper face of the substrate 701, in the orientation of Figure 7A). By way of example, the support substrate 701 is a wafer or a piece of wafer made of a semiconductor material, for example silicon. Alternatively, the support substrate 701 may be made of sapphire or glass.

[0096] The support substrate 701 is coated, on one of its faces, with a semiconductor layer 705. In the example shown, the semiconductor layer 705 is located on and in contact with the face 701T of the support substrate 701. By way of example, the layer 705 is made of silicon.

[0097] The semiconductor layer 705 is, for example, coated with another semiconductor layer 707, for example, a layer made of the same material as the layer 705. In the example shown, the semiconductor layer 707 is located on and in contact with a face of the semiconductor layer 705 opposite the support substrate 701. By way of example, the semiconductor layer 707 is doped with a first type of conductivity, for example, type N (N+ doping). The semiconductor layer 705 acts, for example, as a buffer layer between the support substrate 701 and the semiconductor layer 707.

[0098] In the example shown, the semiconductor layer 707 is coated with an active layer 709. The active layer 709 is, in this example, located on and in contact with a face of the semiconductor layer 707 opposite the substrate 701 (the upper face of the layer 707, in the orientation of [Fig. 7A]). By way of example, the layer 709 includes quantum dots or wells.

[0099] In the illustrated example, the active layer 709 is coated with another semiconductor layer 711. In this example, the semiconductor layer 711 is located on and in contact with a face of the active layer 709 opposite the supporting substrate 701 (the upper face of the layer 709, in the orientation of [Fig. 7A]). The semiconductor layer 711 is, for example, doped with a type of conductivity opposite to that of the semiconductor layer 705 (type P, in this example).

[0100] In the illustrated example, the semiconductor layers 705 and 707, the active layer 709 and the semiconductor layer 711 form the stack of light-emitting diode 703.

[0101] By way of example, in the case where the substrate 701 is silicon, the semiconductor layer 705, the semiconductor layer 707, the active layer 709 and the semiconductor layer 711 are formed successively by epitaxial growth from the face 701T of the support substrate 701.

[0102] In the example shown, the semiconductor layer 711 is coated with a conductive layer 713. In this example, the conductive layer 713 is located on and in contact with a face of the semiconductor layer 711 opposite the supporting substrate 701 (the upper face of the layer 711, in the orientation of [Fig. 7A]). By way of example, the conductive layer 713 is made of a metal, for example aluminum or titanium, or of a metal alloy. The conductive layer 713 allows, for example, ohmic contact to be made with the semiconductor material of the layer 711. The conductive layer 713 may have a single-layer or multi-layer structure.

[0103] [Fig.7B] illustrates more precisely a structure obtained at the end of a step of forming the circuits 205 of the pixels PIX of the device 100. The step described in relation to [Fig.7B] can be carried out indifferently before, during or after the step previously described in relation to [Fig.7A].

[0104] In the example shown, the structure includes a support substrate 721. By way of example, the support substrate 721 is a wafer or a piece of wafer made of a semiconductor material, for example silicon.

[0105] The support substrate 721 is, for example, coated on one of its faces with an insulating layer 723. In the example shown, the insulating layer 723 is located on and in contact with a face 721T of the support substrate 721 (the upper face of the substrate 721, in the orientation of [Fig. 7B]). By way of example, the insulating layer 723 is made of an oxide, for example silicon dioxide.

[0106] The insulating layer 723 is, for example, coated with a semiconductor layer 725, for example a silicon layer. In the example shown, the semiconductor layer 725 is located on and in contact with a face of the insulating layer 723 opposite the support substrate 721.

[0107] By way of example, the support substrate 721, the insulating layer 723, and the semiconductor layer 725 are part of a SOI (Silicon On Insulator) type substrate. In this case, the insulating layer 723 corresponds to the buried oxide layer (BOX) of the SOL substrate.

[0108] In this example, the circuits 205 are located on the side of the face 721T of the semiconductor substrate 721. By way of example, the circuits 205 are formed in and on the semiconductor layer 725.

[0109] Although not detailed in [Fig. 7B] so as not to clutter the drawing, the structure further includes, for example, an interconnect stack or network located on the semiconductor layer 725. The interconnect stack includes, by An example is a stack of conductive layers, such as metallic layers or metallization levels, and alternating insulating layers. The interconnect stack includes, for example, conductive traces formed within the conductive layers and conductive vias, such as metallic vias, interconnecting conductive traces located in different conductive layers.

[0110] In the example shown, only one conductive layer 727 of the interconnect stack furthest from the support substrate 721, called the last metallization level, has been symbolized by disjoint hatched rectangles in [Fig.7B].

[0111] The semiconductor layer 725 of the structure illustrated in [Fig.7B] corresponds for example to the semiconductor substrate 101 of the device 100 of [Fig. 1].

[0112] Although [Fig. 7B] illustrates an example in which the circuits 205 are formed in and on a SOI-type substrate, this example is not limiting. As an alternative, the circuits 205 may be formed in and on a bulk semiconductor substrate, for example identical or analogous to the support substrate 721 of [Fig. 7B].

[0113] In the example shown, the conductive layer 727 is coated with another conductive layer 729. In this example, the conductive layer 729 is located on and in contact with a face of the conductive layer 727 opposite the substrate 721 (the upper face of the layer 727, in the orientation of [Fig. 7B]). By way of example, the conductive layer 729 is made of a metal, for example titanium, or of a metal alloy. The conductive layer 729 is, for example, made of the same material as the conductive layer 713.

[0114] [Fig.7C] illustrates more precisely a structure obtained at the end of a subsequent step of transferring the structure previously described in relation to [Fig.7A] onto the structure previously described in relation to [Fig.7B].

[0115] By way of example, the structure previously described in relation to [Fig. 7A] is inverted with respect to the orientation of [Fig. 7A] and then brought into contact, by the face of the conductive layer 713 opposite the support substrate 701 (the lower face of the layer 713, in the orientation of [Fig. 7C]), with the face of the conductive layer 729 opposite the substrate 721 (the upper face of the layer 729, in the orientation of [Fig. 7C]). During this step, the structure comprising the support substrate 701 and the active LED stack 703 is fixed to the interconnect stack coated with the conductive layer 729.

[0116] By way of example, the bonding is achieved by molecular bonding between the two surfaces brought into contact. The molecular bonding is, for example, more precisely of the metal-to-metal type, each surface comprising a metallic layer.

[0117] The support substrate 701 is then, for example, removed. The support substrate 701 is, for example, completely removed, for example by grinding the side of face 721T of the substrate 721.

[0118] Fig. 7D illustrates more precisely a structure obtained at the end of a further step of forming trenches 731, or openings, in the active stack of light-emitting diode 703.

[0119] The trenches 731 are, for example, formed by plasma etching through a mask (not shown) previously deposited on the upper face of the active stack 703. The trenches 731 extend from the upper face of the semiconductor layer 705 through the layers 705, 707, 709, and 711 of the active LED stack 703, the etching being, for example, interrupted on the upper face of the conductive layer 713. The formation of the trenches 731 through the active stack 703 results in the delimitation, within the active stack 703, of a plurality of LEDs 733. Each LED 733 corresponds to an island or mesa formed in the stack 703 and surrounded laterally by a trench 731.Each LED 733 thus comprises a vertical stack consisting, in order from the top face of the conductive layer 713, of a portion of the semiconductor layer 711, corresponding to the anode of the LED, a portion of the emissive layer 709, a portion of the semiconductor layer 707, corresponding to the cathode of the LED, and a portion of the semiconductor layer 707. The trenches 731 can be aligned with respect to marks previously formed on the underlying circuit 205. More specifically, after the etching mask has been deposited but before the trenches 731 are formed, marks previously formed on the substrate 721 can be exposed by etching the mask and the active stack 703 in peripheral areas of the assembly; these marks then serve as alignment marks for positioning the mask used to create the trenches 731.In the example shown, each LED 733 is located, in vertical projection, opposite a single contact element 735, for example a conductive pad, formed in the conductive layer 727.

[0120] Furthermore, [Fig. 7D] illustrates a subsequent step of removing, for example by plasma etching, portions of the metal layers 729 and 713 located at the bottom of the trenches 731, so as to extend the trenches 731 to the last conductive layer 727 of the interconnect stack. Following this step, the anodes of the individual LEDs 733 are electrically isolated from each other by the trenches 731, and each LED 733 has its anode connected to the portion of the underlying conductive layer 727 via the portions of the metal layers 729 and 713 remaining between the LED and a contact re-establishment element 735, for example a conductive pad formed in the conductive layer 727. This allows individual control of the LEDs by the circuits 205.Furthermore, at the end of this step, the upper face of other contact resumption elements 737, for example conductive pads, not coated with a portion of the active stack of light-emitting diodes. nescente 703, is discovered.

[0121] Furthermore, [Fig.7D] illustrates a subsequent step of depositing an insulating layer 741, for example a passivation layer of silicon oxide or nitride or aluminum oxide, on the side walls and on the bottom of the trenches 731. The layer 741 is, for example, further deposited on the upper faces of the portions of the active stack 703 of the LEDs 733. The layer 741 is, for example, deposited on the entire upper face of the structure by a conformal deposition method, for example by successive single-atom layer deposition (ALD).

[0122] The portions of layer 741 located at the bottom of the trenches 731 are, for example, subsequently removed. During this step, layer 741 is retained on the lateral walls, or sides, of the trenches 731. For this purpose, layer 741 is, for example, etched by vertical anisotropic etching, which also results in the removal of layer 741 from the upper faces of the portions of the active stack 703 above the LEDs 733.

[0123] Fig. 7E more precisely illustrates a structure obtained after a subsequent step of deposition of a conductive layer 751, for example a metallic layer, on the upper face side of the structure of Fig. 7D.

[0124] In the example shown, the conductive layer 751 fills the trenches 731. In other words, the layer 751 completely fills the spaces left free between the LEDs 733. In the illustrated example, the conductive layer 751 is flush with the top face of the active stack of light-emitting diodes 703. By way of example, a mechano-chemical polishing operation is carried out to remove portions of the conductive layer 751 coating the top faces of the LEDs 733.

[0125] Furthermore, another conductive layer 753 is deposited during this step on the upper surface of the structure. For example, the conductive layer 753 forms a common cathode electrode for the LEDs 733. The conductive layer 751 is then, for example, intended to form contact elements enabling the connections of the pads 737 to be made to the conductive layer 753. For example, the conductive layer 755 is a layer of a transparent and conductive oxide, for example indium tin oxide, or a thin metallic film, for example silver.

[0126] Figure 7F illustrates more precisely a structure obtained at the end of a step ul external transfer of the structure previously described in relation to [Fig.7E] on a temporary support substrate 755.

[0127] By way of example, the structure previously described in relation to [Fig.7E] is reversed with respect to the orientation of [Fig.7E] and then brought into contact, by the face of the conductive layer 753 opposite the support substrate 721 (the lower face of the layer 753, in the orientation of [Fig.7F]), with the upper face of the temporary support substrate 755. By way of example, the fixation is obtained by molecular bonding between the two surfaces brought into contact.

[0128] The support substrate 721 is then removed, for example. The support substrate 721 is completely removed, for example by grinding the upper face of the temporary support substrate 755. Using a SOI-type substrate has the advantage of facilitating the removal of the support substrate 721 during this step, for example by allowing it to stop on the insulating layer 723.

[0129] Furthermore, during this step, conductive vias 757 are formed from the face of the insulating layer 723 opposite the temporary support substrate 755 (the upper face of the insulating layer 723, in the orientation of [Fig. 7F]). In the example shown, the conductive vias 757 pass through the insulating layer 723 and penetrate the thickness of the semiconducting layer 725. Although not detailed in [Fig. 7F] to avoid cluttering the drawing, the conductive vias 757 are, for example, connected to the circuits 205. By way of example, the conductive vias 757 are formed by creating openings that pass through the insulating layer 723 and penetrate the semiconducting layer 725, the sides and bottom of the openings being, for example, subsequently passivated before the openings are completely filled with metallic regions.

[0130] Fig. 7G illustrates more precisely a structure obtained at the end of a subsequent step of transferring the structure previously described in relation to Fig. 7F onto another temporary support substrate 761.

[0131] By way of example, the structure previously described in relation to [Fig.7F] is reversed with respect to the orientation of [Fig.7F] and then brought into contact, by the face of the insulating layer 723 opposite the support substrate 755 (the lower face of the layer 723, in the orientation of [Fig.7G]), with the upper face of the temporary support substrate 761. By way of example, the fixing is obtained by gluing between the two surfaces brought into contact, for example by means of a layer of glue.

[0132] The support substrate 755 is then removed, for example. The support substrate 755 is completely removed, for example by grinding the upper face side of the temporary support substrate 761.

[0133] [Fig. 7H] illustrates more precisely a structure obtained at the end of a subsequent formation step, from the upper face of the structure of [Fig. 7G], of trenches 763 extending vertically, from the face of the conductive layer 753 opposite the temporary support substrate 761 (the upper face of the layer 753, in the orientation of [Fig. 7H]), to the upper face of the substrate 761. The trenches 763 laterally delimit a plurality of semiconductor chips corresponding to elementary chips 765 of the PIX pixels of the image capture and display device 100. The trenches 763 are formed, for example, by plasma etching, by sawing, or by any other suitable cutting method.

[0134] Figure 71 illustrates more precisely a structure obtained after a subsequent step of fixing the elementary chips 765 onto the upper face of the same Transfer substrate 767. Transfer substrate 767, for example, lacks contact elements. As an example, transfer substrate 767 is made of glass.

[0135] The structure of [Fig.7H] is for example reversed so as to place the elementary chips 765 opposite the transfer substrate 767. The elementary chips 765 are then fixed, for example by gluing, on the upper face of the transfer substrate 767.

[0136] Once attached to the transfer substrate 767, the individual chips 765 are detached from the temporary support substrate 761, and the latter is removed. By way of example, the chips 765 are detached by mechanical peeling or by peeling using a laser beam.

[0137] In the example shown, the pitch (i.e., the center-to-center distance, viewed from the front) of the elementary chips 765 on the transfer substrate 767 is a multiple of the pitch of the elementary chips 765 on the temporary support substrate 761. Thus, only some of the elementary chips 765 (one out of two, in the example shown) are transferred simultaneously from the temporary support substrate 761 to the transfer substrate 767. The other chips remain attached to the temporary support substrate 761. These remaining chips can then be transferred to another part of the transfer substrate 767. Alternatively, the transfer of these remaining elementary chips can be carried out on a different transfer substrate.

[0138] Fig. 7J illustrates more precisely a structure obtained after a subsequent step of depositing an insulating layer 769 on the upper face side of the transfer substrate 767.

[0139] In the example shown, the insulating layer 769 covers uncoated portions of the upper face of the transfer substrate 767 of the elementary chips 765, as well as the sides and upper faces of the elementary chips 765. In this example, the insulating layer 769 fills all the gaps extending laterally between the elementary chips 765. The insulating layer 769 acts, for example, as a planarization layer. By way of example, the insulating layer 769 is made of a polymer material.

[0140] Furthermore, during this step, the conductive vias 757 are extended to the upper face of the insulating layer 769. For example, openings are formed in the thickness of the insulating layer 769 directly above the conductive vias 757. These openings, which lead to the conductive vias 757, are then, for example, passivated and filled with a conductive material, for example the same material as that of the conductive vias 757.

[0141] Fig. 7K more precisely illustrates a structure obtained at the end of a further step of formation of an interconnection network 771, or interconnection stacking, on the upper face side of the structure of Fig. 7J.

[0142] The interconnection network 771 comprises, for example, a stack of conductive layers, for example metallic layers or levels of metallization, and alternating insulating layers. The interconnection network 771 comprises, for example, conductive tracks formed in the conductive layers and conductive vias, for example metallic vias, interconnecting conductive tracks located in different conductive layers. In [Fig. 7K], the metallic layers of the interconnection network 771 have been symbolized by hatched rectangles.

[0143] Furthermore, during this step, electrodes 773, for example the lower electrodes of the photodetectors 201 of the device 100, are formed on the upper face side of the structure. In the example shown, the electrodes 773 are located on and in contact with a face of the interconnection network 771 opposite the transfer substrate 767 (the upper face of the interconnection network 771, in the orientation of [Fig. 7K]).

[0144] By way of example, a conductive layer is deposited on the entire upper face of the structure, then trenches 775 are for example subsequently formed in the entire thickness of the conductive layer so as to delimit parts of the conductive layer isolated from each other and each forming one of the electrodes 773.

[0145] [Fig.7L] illustrates more precisely a structure obtained at the end of a further step of diode formation 781, for example PIN diodes (from the English "Positive Intrinsic Negative" - ​​intrinsically positive negative) on the upper face side of the structure of [Fig.7K].

[0146] By way of example, an active stack of PIN diodes is deposited on the entire upper surface of the structure of [Fig. 7K]. The active stack of PIN diodes is then structured, for example by photolithography and then etching, so as to retain only parts of the stack of PIN diodes located each above one of the electrodes 773. By way of example, the stack of PIN diodes is based on amorphous silicon, indium gallium zinc oxide (IGZO), or one or more organic materials.

[0147] Furthermore, during this step, an insulating layer 783 is then deposited on the upper face of the structure. In the example shown, the insulating layer 783 fills, that is, completely fills, all the free spaces extending laterally between the PIN 781 diodes and is flush with the upper face of the PIN 781 diodes.

[0148] Furthermore, during this step, a conductive layer 785 is deposited on the upper face of the structure. In the example shown, the conductive layer 785 is located on and in contact with the upper faces of the PIN diodes 781 and the insulating layer 783. The conductive layer 785 constitutes, for example, a common electrode for all the PIN diodes 781 of the device 100. By way of example, the conductive layer 785 is made of a transparent and conductive oxide, for example, oxide of indium-tin (ITO).

[0149] Furthermore, during this step, a scintillator 787 is then formed on the upper face of the structure. In the example shown, the scintillator 787 is located on and in contact with the upper face of the conductive layer 785. The scintillator 787 comprises a layer of a scintillation material, for example cesium iodide (Csl) in crystalline form, gadolinium oxide (GadOx), or any other suitable scintillation material, i.e., a material emitting light as a result of energy deposition by interaction with X-rays, extending continuously over the entire upper face of the conductive layer 785.

[0150] The scintillator 787 is for example formed separately on a growth substrate, then transferred to the upper face of the conductive layer 785. As an alternative, the scintillator 787 is formed directly on the upper face of the conductive layer 785.

[0151] In the structure of [Fig.7L], the detection elements 103 include, for example, the diodes 781, and the emission elements 107 include, for example, the light-emitting diodes 733 formed in the elementary chips 765.

[0152] The method described above in relation to Figures 7A to 7L can be used to produce a device 100 comprising a plurality of elementary chips (“smart pixels”) arranged, for example in a matrix arrangement, on the same substrate. By way of example, the substrate is a flexible substrate (“flex”), that is to say, a substrate capable of conforming to the shape of a rounded object.

[0153] The [Fig.8] is a schematic and partial top view of the interconnection network 771 of the device 100.

[0154] In the example shown, the interconnection network 771 comprises two metallization levels 801 and 803, symbolized in [Fig. 8] by hatched elements. In the orientation of [Fig. 8], the metallization level 801 consists mainly of vertical conductive tracks and the metallization level 803 consists mainly of horizontal conductive tracks.

[0155] In the illustrated example, each elementary chip 765 comprises: - a pad 811a connected to a conductive track 821a of the metallization level 801, for example an application track of the supply potential Va; - a pad 811b connected to a conductive track 821b of the metallization level 801, for example a reference potential application track; and - a pad 811c connected to a conductive track 821c of the metallization level 801, for example a track for applying the potential Vdd.

[0156] Furthermore, in this example, each elementary chip 765 comprises: - a pad 813a connected to a conductive track 823a of the metallization level 803, for example a potential application track Vref; and - a pad 813b connected to a conductive track 823b of the metallization level 803, for example a potential application track -Vk.

[0157] This example is not limiting, however, the interconnection network 771 can, more generally, have any structure allowing the application of signals adapted to allow the operation of each elementary chip 765.

[0158] Fig. 9A and Fig. 9B illustrate, by means of schematic and partial cross-sectional views, structures obtained at the end of successive stages of a manufacturing process of device 100 of Fig. 1 according to another embodiment.

[0159] Fig. 9A illustrates more precisely a structure obtained at the end of a step of forming a 900 converter based on a perovskite material.

[0160] In the example shown, the converter 900 more precisely comprises an active layer 901 made of a perovskite material. A perovskite material is, for example, a material having a crystal structure of the form ABX3, where A and B are two positively charged ions, or cations, and where X is a negatively charged ion, or anion. The anion X, typically an oxygen anion (O₂), is bonded to the cations A and B. The cations A and B may be of different sizes, for example, the A cations being larger than the B cations. However, this description is not limited to these examples. As an alternative, site A and / or site B of the perovskite material of the active layer 901 may exhibit a configuration of the type Alx_iA2x and / or B lv |B2V, and the anion X may deviate from the ideal coordination configuration, for example when the ions of sites A and B undergo changes in their respective oxidation states.As an alternative, the active layer can be based on amorphous selenium, gallium arsenide, mercury iodide, lead oxide or cadmium-zinc telluride.

[0161] In the orientation of [Fig.9A], the converter 900 includes, on the side of its lower face, electrodes 903 located under and in contact with the active layer 901. In the orientation of [Fig.9A], the converter 900 further includes, on the side of its upper face, a common electrode 905.

[0162] Fig. 9B illustrates more precisely a structure obtained at the end of a further step of transferring the converter 900 of Fig. 9A onto the structure previously described in relation to Fig. 7K.

[0163] By way of example, the converter 900 is brought into contact, by the faces of the electrodes 903 opposite the active layer 901 (the lower faces of the electrodes 903, in the orientation of [Fig. 9B]), with the upper faces of the electrodes 773 opposite the substrate 767 (the upper faces of the electrodes 773, in the orientation of [Fig. 9B]). During this step, the converter 900 is fixed to the interconnect stack 771.

[0164] By way of example, the bonding is achieved by molecular bonding between the two surfaces brought into contact. The molecular bonding is, for example, more precisely of the metal-to-metal type, each surface comprising a metallic layer.

[0165] In the example shown, the electrodes 773 have, in top view, lateral dimensions substantially equal to those of the electrodes 903. This example is not limiting, however, the electrodes 773 may, as an alternative, have lateral dimensions different from those of the electrodes 903, for example smaller than those of the electrodes 903.

[0166] The device in [Fig.9B] is used for example to reproduce color images characteristic of the captured X-rays, for example by means of direct conversion and photon counting.

[0167] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, although the described embodiments take as an example a case in which the arrays of sensing elements 103 and display elements 107 have a substantially identical pitch, those skilled in the art can predict, from the indications in this description, that the display element array 107 of the device 100 has a different, for example, larger, pitch than the sensing element array 103.

[0168] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this description.

Claims

Demands

1. An electronic image capture and display device (100) comprising a plurality of pixels (PIX) formed in and on a semiconductor substrate (101; 705), each pixel comprising: - an X-ray detection element (103) (105), located on the side of a first face (101F) of the semiconductor substrate (101); - a visible light emission element (107) (109), located on the side of a second face (101R) of the semiconductor substrate opposite the first face; and - a circuit (205) located in and on the semiconductor substrate and connecting the detection element to the emission element.

2. Device (100) according to claim 1, wherein the circuit (205) comprises: - an acquisition circuit (207) located in and on the semiconductor substrate (101; 705) and adapted to provide an acquisition signal representative of an intensity of the X-ray radiation (105) received by the detection element (103) of the pixel (PIX); and - a control circuit (209) located in and on the semiconductor substrate and adapted to apply a control signal to the emission element (107) of the pixel.

3. Device (100) according to claim 2, wherein the acquisition circuit (207) and the control circuit (209) are analog circuits.

4. Device (100) according to claim 2, wherein: - each detection element (103) comprises a photodetector (201); - each acquisition circuit (207) comprises a comparator (301) having an inverting input connected to a conduction electrode of the photodetector; and - each control circuit (209) comprises an inverter (317) having an input connected to an output of the comparator and an output connected to a gate of a MOS transistor (319), the MOS transistor comprising a conduction electrode connected to the emitting element (107).

5. Device (100) according to claim 4, wherein each emitting element (107) comprises a single light-emitting diode (211).

6. Device (100) according to claim 5, wherein the electrolu- diode minescente (211) is controlled by a control signal having pulses repeating at a frequency substantially proportional to an intensity of the X radiation (105) detected by the detection element (103).

7. Device (100) according to claim 2, wherein: - each detection element (103) comprises a photodetector (201); - each acquisition circuit (207) comprises a signal shaping circuit (511); and - each control circuit (209) comprises a multilevel comparator (521) having an input connected to an output of the signal shaping circuit and at least two outputs each connected to a gate of a MOS transistor (319R, 319G, 319B) by an inverter (317), each MOS transistor comprising a conduction electrode connected to a light-emitting diode (21IR, 21IG, 21IB) of the emitting element (107).

8. Device (100) according to claim 7, wherein each emitting element (107) comprises exactly three light-emitting diodes (21 IR, 21 IG, 21 IB).

9. Device (100) according to any one of claims 1 to 8, wherein the sensing elements (103) are located opposite the emitting elements (107).

10. Device (100) according to any one of claims 1 to 9, wherein the sensing elements (103) and the emitting elements (107) are arranged respectively in first and second matrices, the first and second matrices having substantially identical pitches.

11. Device (100) according to any one of claims 1 to 10, comprising as many detection elements (103) as emission elements (107).

12. Device (100) according to any one of claims 1 to 11, further comprising a scintillator (787) surmounting the detection elements (103).

13. Device (100) according to any one of claims 1 to 11, further comprising a converter (900) based on a perovskite material surmounting the sensing elements (103).

14. A method for manufacturing a device (100) according to any one of claims 1 to 13, comprising a transfer step, by bonding mo- ecular, of a structure comprising the detection elements (103) and the circuits (205) on another structure comprising the emission elements (107).

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